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Name Last modified Size Description
Parent Directory RC10-XX.pdf RC1117.pdf RC1584.pdf RC1585.pdf RC1587.pdf RC1616.pdf RC2207.pdf RC2211.pdf RC2211A.pdf RC2798.pdf RC2951.pdf RC3403A.pdf RC40-XX.pdf RC4136.pdf RC4152.pdf RC4153.pdf RC4156.pdf RC4157.pdf RC4190.pdf RC4191.pdf RC4192.pdf RC4193.pdf RC4194.pdf 11-Aug-98 15:45 17-Feb-00 00:01 17-Feb-00 00:01 17-Feb-00 00:01 22-Dec-99 00:14 22-Dec-99 00:14 22-Dec-99 00:14 11-Aug-98 15:45 22-Dec-99 00:14 22-Dec-99 00:14 22-Dec-99 00:14 22-Dec-99 00:14 11-Aug-98 15:45 22-Dec-99 00:14 22-Dec-99 00:14 22-Dec-99 00:14 22-Dec-99 00:14 22-Dec-99 00:14 22-Dec-99 00:14 12-Aug-98 00:00 06-Aug-98 00:00 06-Aug-98 00:00 22-Dec-99 00:14 23K 47K 67K 65K 59K 35K 73K 135K 83K 75K 102K 81K 22K 119K 76K 123K 91K 91K 164K 75K 75K 75K 108K
RC4195.pdf RC4200.pdf RC4207.pdf RC4227.pdf RC4277.pdf RC431A.pdf RC4391.pdf RC4558.pdf RC4559.pdf RC4560.pdf RC4741.pdf RC4861.pdf RC5010.pdf RC5011.pdf RC5011DB.pdf RC5031.pdf RC5031AP.pdf RC5032.pdf RC5033.pdf RC5034.pdf RC5035.pdf RC5035A.pdf RC5036.pdf RC5036AP.pdf RC5037.pdf RC5037A.pdf RC5039.pdf
22-Dec-99 00:14 22-Dec-99 00:14 22-Dec-99 00:14 22-Dec-99 00:14 22-Dec-99 00:14 22-Dec-99 00:14 22-Dec-99 00:14 22-Dec-99 00:14 22-Dec-99 00:14 22-Dec-99 00:14 22-Dec-99 00:14 22-Dec-99 00:14 11-Aug-98 15:46 11-Aug-98 15:46 11-Aug-98 15:46 22-Dec-99 00:14 11-Aug-98 15:46 22-Dec-99 00:14 22-Dec-99 00:14 22-Dec-99 00:14 11-Aug-98 15:47 11-Aug-98 15:47 02-Feb-00 00:00 11-Aug-98 15:47 02-Feb-00 00:00 11-Aug-98 15:47 22-Dec-99 00:14
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RC5040.pdf RC5041.pdf RC5042.pdf RC5043.pdf RC5050.pdf RC5051.pdf RC5052.pdf RC5053.pdf RC5054.pdf RC5054A.pdf RC5055.pdf RC5056.pdf RC5057.pdf RC5058.pdf RC5060.pdf RC5061.pdf RC5102.pdf RC5201.pdf RC5230.pdf RC5231.pdf RC5501.pdf RC5502.pdf RC5510.pdf RC5512.pdf RC5513.pdf RC5532.pdf RC5532A.pdf
22-Dec-99 00:14 22-Dec-99 00:14 22-Dec-99 00:14 11-Aug-98 15:47 22-Dec-99 00:14 22-Dec-99 00:14 22-Dec-99 00:14 22-Dec-99 00:14 29-Sep-98 00:00 22-Dec-99 00:14 22-Dec-99 00:14 22-Dec-99 00:14 22-Dec-99 00:14 22-Dec-99 00:14 22-Dec-99 00:14 22-Dec-99 00:14 22-Dec-99 00:14 22-Dec-99 00:14 22-Dec-99 00:14 22-Dec-99 00:14 22-Dec-99 00:14 11-Aug-98 15:48 11-Aug-98 15:48 22-Dec-99 00:14 22-Dec-99 00:14 22-Dec-99 00:14 22-Dec-99 00:14
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RC5534.pdf RC5534A.pdf RC5601.pdf RC5X01.pdf RC5X02.pdf RC6100.pdf RC6120.pdf RC6302.pdf RC6303.pdf RC6333.pdf RC6334.pdf RC6505.pdf RC6508.pdf RC6516.pdf RC6564.pdf RC6564A.pdf RC6601.pdf RC6702.pdf RC6704.pdf RC7100.pdf RC7101.pdf RC7102.pdf RC7104.pdf RC7105.pdf RC7106.pdf RC7108.pdf RC7144.pdf
22-Dec-99 00:14 22-Dec-99 00:14 11-Aug-98 15:48 11-Aug-98 15:48 11-Aug-98 15:48 22-Dec-99 00:14 11-Aug-98 15:48 22-Dec-99 00:14 22-Dec-99 00:14 22-Dec-99 00:14 22-Dec-99 00:14 22-Dec-99 00:14 22-Dec-99 00:14 11-Aug-98 15:49 11-Aug-98 15:49 11-Aug-98 15:49 22-Dec-99 00:14 22-Dec-99 00:14 11-Aug-98 15:49 22-Dec-99 00:14 22-Dec-99 00:14 22-Dec-99 00:14 22-Dec-99 00:14 22-Dec-99 00:14 22-Dec-99 00:14 22-Dec-99 00:14 22-Dec-99 00:14
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RC7310.pdf RC7311.pdf RC7315.pdf RC7316.pdf RC7321.pdf RC7352.pdf RC73687.pdf RC7B00.pdf RCB001.pdf RCB002.pdf RCB004.pdf RCB005-K.pdf RCB005.pdf RCB005K.pdf RCB006-K.pdf RCB006.pdf RCB006K.pdf RCB007.pdf RCB010.pdf RCC611.050A.pdf RCC611.053.pdf RCC613.pdf RCC615.pdf RCC700A.pdf RCXXXX.XXX.pdf
22-Dec-99 00:14 22-Dec-99 00:14 22-Dec-99 00:14 22-Dec-99 00:14 22-Dec-99 00:14 22-Dec-99 00:14 22-Dec-99 00:14 11-Aug-98 15:49 22-Dec-99 00:14 22-Dec-99 00:14 22-Dec-99 00:14 22-Dec-99 00:14 11-Aug-98 15:50 02-Mar-99 00:00 22-Dec-99 00:14 11-Aug-98 15:50 02-Mar-99 00:00 11-Aug-98 15:50 11-Aug-98 15:50 11-Aug-98 15:50 11-Aug-98 15:50 11-Aug-98 15:50 22-Dec-99 00:14 22-Dec-99 00:14 11-Aug-98 15:50
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www.fairchildsemi.com
RC10-XX
Sense Resistors for Fairchild Semiconductor DC-DC Controllers
Features
* Resistor typical tolerance 5% * Resistance wire TCR +20ppm/C * Wire alloy MnCu (0.624mW/mm)
Preliminary Information
Sense Resistor Selection
Fairchild Semiconductor Controller Fairchild Semiconductor Sense Resistor Part Number
CPU Type Socket 7: P54C, P55C, K6, M2
CPU IMAX 10A
RC5036 RC5041 RC5050 RC5051
RC10-58 RC10-73
13A
RC5036 RC5041 RC5050 RC5051
RC10-44 RC10-58
Pentium Pro Pentium II Klamath Pentium II Deschutes
13A 15A 18A
RC5050 RC5051 RC5050 RC5051 RC5050 RC5051
RC10-58 RC10-52 RC10-44
Resistor Dimensions
Type
H
R (mW) 5.8 7.3 5.2 4.4
D (mm) 1.0 1.0 1.0 1.0
L (mm) 9.3 11.7 8.3 7.1
H (mm) 5.0 5.0 5.0 5.0
RC10-58 RC10-73 RC10-52 RC10-44
D
L
Rev. 0.9.0
PRELIMINARY INFORMATION describes products that are not in full production at the time o f printing. Specifications are based on design goals and limited characterization. They may change without notice. Conta Fairchild Semiconductor for current information.
RC10-XX
PRODUCT SPECIFICATION
System Requirements
The design of the sense resistor is driven by the following system requirements: * Load current, (ILOAD). This is the full load DC current the converter is designed to support. * The controller short circuit current detect threshold voltage (VTH), which for Fairchild Semiconductor family of Controllers is specified at 120+/-20mV for the RC5040, RC5041, RC5042, RC5050, and RC5051, or 90 10mV for the RC5036. * The inductor current ripple (IR). A reasonable design guideline is to assume the current ripple is limited to 1.5A.
Wire Sense Resistors
There are several types of sense resitors available to the system designer in a wide range of cost and specifications. The resistors with higher precision (i.e. 1% SMT) demand the highest cost (i.e. $0.47); however a 10% to 15% tolerance is adequate for most DC-DC converters designs and wire resistors offer a very cost effective alternative. MnCu or CuNi alloy wire resistors have been used extensively in the manufacture of sense resistors used in the Fairchild Semiconductor's family of DC-DC converters. These resistive wires are available in all the most common gages and Table 1 and Table 2 describe the specifications of MnCu and CuNi alloys for various wire diameters. Wire with diameter of ~1 mm is best suited to make sense resistors for DC-DC converters used in motherboard applications. Refer to Figure 1 for the typical shape of a wire sense resistor and Figure 2 through Figure 5 for the dimensions of the resistor as function of the load current requirements of the converter. Table 1. MnCu Wire Resistor Specifications Diameter (mm) 1.40 1.30 1.10 1.00 0.90 0.80 W/m 0.31831 0.36916 0.51561 0.62389 0.77023 0.97482 mW/mm 0.318 0.369 0.516 0.624 0.770 0.975 Imax (Amp) 154 133 95 79 64 50
Preliminary Information
Design Equations
The design of the sense resistor must consider carefully the output requirements during normal operation and during a fault condition. If the sense resistor is too high, it may develop enough voltage drop accross it to trip the short circuit detect circuitry so that the DC-DC converter may not be able to deliver the maximum required load current. If the sense resistor is too low, the controller may not be disabled when a certain safe amount of load current is exceeded, thus the power dissipation within the MOSFET(s) may rise to destructive levels. The design equations used to calculate the sense resistor are as follows: I SC ( MIN ) = ( I LOAD + I R + 1 ) V TH ( MIN ) R SENSE ( MAX ) = --------------------------I SC ( MIN ) and, assuming a 10% tolerance, the nominal design value of the sense resistor is given by: R SENSE ( MAX ) RSENSE = --------------------------------------( 1 + 0.10 )
Note: 1. J = 104 A/cm2
Table 2. CiNi Wire Resistor Specifications AWG 15 16 17 18 19 20 Diameter (mm) 1.45 1.29 1.15 1.02 0.912 0.812 W/ft 0.09049 0.11300 0.14520 0.18370 0.22690 0.28710 mW/m 0.30 0.37 0.48 0.60 0.74 0.94 Imax (Amp) 165 131 104 82 65 52
Note: 1. J = 104 A/cm2
2
PRODUCT SPECIFICATION
RC10-XX
L
H = 5.0mm
D = 1.0mm
Figure 1. Wire Resistor
Preliminary Information
RSENSE L (mm) vs. ILOAD (A) CuNi (AWG 18) 24.0 22.0 20.0 18.0 16.0 14.0 12.0 10.0 8.0 6.0 4.0 2.0 0.0 6 8 10 16 18 20 22 24 ILOAD (A) RC5041/RC5042/RC5050/RC5051 12 14 26 28 30 24.0 22.0 20.0 18.0 16.0 14.0 12.0 10.0 8.0 6.0 4.0 2.0 0.0
RSENSE L (mm) vs. ILOAD (A) MnCu (diameter = 1mm)
RSENSE L (mm)
RSENSE L (mm)
6
8
10
16 18 20 22 24 ILOAD (A) RC5041/RC5042/RC5050/RC5051
12
14
26
28
30
Figure 2. Rsense vs. Imax (CuNi)
Rsense L (mm) vs. ILOAD (A) CuNi (AWG 18) 18.0 16.0 RSENSE L (mm) 12.0 10.0 8.0 6.0 4.0 2.0 0.0 6 8 10 12 14 16 18 20 ILOAD (A) RC5036 22 24 26 28 30 RSENSE L (mm) 14.0 16.0 14.0 12.0 10.0 8.0 6.0 4.0 2.0 0.0 6
Figure 3. Rsense vs. Imax (MnCu)
RSENSE L (mm) vs. ILOAD (A) MnCu (diameter = 1mm)
8
10
12
14
16 18 20 ILOAD (A) RC5036
22
24
26
28
30
Figure 4. Rsense vs. Imax (CuNi)
Figure 5. Rsense vs. Imax (MnCu)
3
RC10-XX
PRODUCT SPECIFICATION
Preliminary Information
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonable expected to result in a significant injury of the user.
Fairchild Semiconductor Corporation Americas Customer Response Center Tel:1-888-522-5372 Fairchild Semiconductor Europe Fax: Email: Deutsch Tel: English Tel: Italy Tel: +49 (0) 1 80-530 85 86 europe.support@nsc.com +49 (0) 8 141-35-0 +44 (0) 1 793-85-68-56 +39 (0) 2 57 5631
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
Fairchild Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Center, 5 Canto Rd. Tsimshatsui, Kowloon Hong Kong Tel:+852 2737-7200 Fax:+852 2314-0061
National Semiconductor Japan Ltd. Tel:81-3-5620-6175 Fax:81-3-5620-6179
www.fairchildsemi.com 2/98 0.0m Stock#DS300010-XX O 1998 Fairchild Semiconductor Corporation
www.fairchildsemi.com
RC1117
1A Adjustable/Fixed Low Dropout Linear Regulator
Features
* * * * * * Low dropout voltage Load regulation: 0.05% typical Trimmed current limit On-chip thermal limiting Standard SOT-223 and TO-263 packages Three-terminal adjustable or fixed 2.5V, 2.85V, 3.3V, 5V
Description
The RC1117 and RC1117-2.5, -2.85, -3.3 and -5 are low dropout three-terminal regulators with 1A output current capability. These devices have been optimized for low voltage where transient response and minimum input voltage are critical. The 2.85V version is designed specifically to be used in Active Terminators for SCSI bus. Current limit is trimmed to ensure specified output current and controlled short-circuit current. On-chip thermal limiting provides protection against any combination of overload and ambient temperatures that would create excessive junction temperatures. Unlike PNP type regulators where up to 10% of the output current is wasted as quiescent current, the quiescent current of the RC1117 flows into the load, increasing efficiency. The RC1117 series regulators are available in the industrystandard SOT-223 and TO-263 power packages.
Applications
* * * * * * Active SCSI terminators High efficiency linear regulators Post regulators for switching supplies Battery chargers 5V to 3.3V linear regulators Motherboard clock supplies
Typical Applications
RC1117 VIN = 3.3V 10F ADJ 124 + VIN VOUT + 22F 1.5V at 1A
24.9
RC1117-2.85 VIN = 5V 10F GND + VIN VOUT + 22F 2.85V at 1A
REV. 1.1.0 10/29/99
PRODUCT SPECIFICATION
RC1117
Pin Assignments
Front View 3 Tab is VOUT 2 1 IN OUT ADJ/GND Tab is VOUT
4-Lead Plastic SOT-223 JC = 15C/W*
1
2
3
ADJ/ GND
OUT
IN
3-Lead Plastic TO-263 JC = 10C/W*
*With package soldered to 0.5 square inch copper area over backside ground plane or internal power plane., JA can vary from 30C/W to more than 50C/W. Other mounting techniques may provide better thermal resistance than 30C/W.
Absolute Maximum Ratings
Parameter VIN Operating Junction Temperature Range Storage Temperature Range Lead Temperature (Soldering, 10 sec.) 0 -65 Min. Max. 7.5 125 150 300 Unit V C C C
2
REV. 1.1.0 10/29/99
RC1117
PRODUCT SPECIFICATION
Electrical Characteristics
Operating Conditions: VIN 7V, TJ = 25C unless otherwise specified. The * denotes specifications which apply over the specified operating temperature range. Parameter Reference Voltage3 Conditions 1.5V (VIN - VOUT) 5.75V, 10mA IOUT 1A 10mA IOUT 1A RC1117-2.5, 4V VIN 7V RC1117-2.85, 4.35V VIN 7V RC1117-3.3, 4.8V VIN 7V RC1117-5, 6.5V VIN 7V (VOUT + 1.5V) VIN 7V, IOUT = 10mA (VIN - VOUT) = 2V, 10mA IOUT 1A VREF = 1%, IOUT = 1A (VIN - VOUT) = 2V 1.5V (VIN - VOUT) 5.75, 10mA IOUT 1A 1.5V (VIN - VOUT) 5.75 VIN = VOUT + 1.25V f = 120Hz, COUT = 22F Tantalum, (VIN - VOUT) = 3V, IOUT = 1A TA = 25C, 30ms pulse * TA = 125C, 1000hrs. TA = 25C, 10Hz f 10kHz SOT-223 TO-263 Junction Temperature
1,2
Min. * 1.225 (-2%) 2.450 2.793 3.234 4.900
Typ. 1.250
Max. 1.275 (+2%) 2.550 2.907 3.366 5.100 0.2 0.5 1.200 120 5
Units V
Output Voltage
* * * * * * * * * * * *
2.5 2.85 3.3 5.0 0.005 0.05 1.100
V V V V % % V A A A mA
Line Regulation1,2 Load Regulation Dropout Voltage Current Limit Adjust Pin Current3 Adjust Pin Current Change3 Minimum Load Current Quiescent Current Ripple Rejection Thermal Regulation Temperature Stability Long-Term Stability RMS Output Noise (% of VOUT) Thermal Resistance, Juncation to Case Thermal Shutdown Thermal Shutdown Hysteresis
1.1
1.5 35 0.2
10 4 60 72 0.004 0.5 0.03 0.003 15 10 155 10 1.0 0.02 13
mA dB %/W % % % C/W C/W C C
Notes: 1. See thermal regulation specifications for changes in output voltage due to heating effects. Load and line regulation are measured at a constant junction temperature by low duty cycle pulse testing. 2. Line and load regulation are guaranteed up to the maximum power dissipation (18W). Power dissipation is determined by input/output differential and the output current. Guaranteed maximum output power will not be available over the full input/ output voltage range. 3. RC1117 only.
REV. 1.1.0 10/29/99
3
PRODUCT SPECIFICATION
RC1117
Typical Performance Characteristics
DROPOUT VOLTAGE DEVIATION (%) 1.5 1.4 DROPOUT VOLTAGE (V) 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0 0 0.2 0.4 0.6 0.8 1.0 TJ = 25C TJ = 125C TJ = 0C 0.10 0.05 0 -0.05 -0.10 -0.15 -0.20 -75 -50 -25 0 I = 1A
25 50 75 100 125 150 175
OUTPUT CURRENT (A)
JUNCTION TEMPERATURE (C)
Figure 1. Dropout Voltage vs. Output Current
1.250 1.245 REFERENCE VOLTAGE (V) 1.240 1.235 1.230 1.225 1.220 1.215 1.210 1.205 1.200 -75 -50 -25 0 25 50 75 100 125 150 175
Figure 2. Load Regulation vs. Temperature
3.70 3.65 REFERENCE VOLTAGE (V) 3.60 3.55 3.50 3.45 3.40 3.35 3.30 3.25 3.20 -75 -50 -25 0 VOUT = 3.3V Note: 1. RC1117 Only 25 50 75 100 125 150 175
VOUT SET WITH 1% RESISTORS VOUT = 3.6V1
JUNCTION TEMPERATURE (C)
JUNCTION TEMPERATURE (C)
Figure 3. Reference Voltage vs. Temperature
5 MINIMUM LOAD CURRENT (mA)
Figure 4. Output Voltage vs. Temperature
100 90 ADJUST PIN CURRENT (A) Note: 1. RC1117 Only
4
80 70 60 50 40 30 20 10
3
2
1
0 -75 -50 -25 0
25 50 75 100 125 150 175
0 -75 -50 -25 0
25 50 75 100 125 150 175
JUNCTION TEMPERATURE (C)
JUNCTION TEMPERATURE (C)
Figure 5. Minimum Load Current vs. Temperature
Figure 6. Adjust Pin Current vs. Temperature
4
REV. 1.1.0 10/29/99
RC1117
PRODUCT SPECIFICATION
Typical Performance Characteristics (continued)
2.0 SHORT-CIRCUIT CURRENT (A) 90 80 RIPPLE REJECTION (dB) 1.75 70 60 50 40 30 20 10 1.0 -75 -50 -25 0 25 50 75 100 125 150 175 0 10 (VIN - VOUT) = 3V 0.5 < VRIPPLE < 2V IOUT = 1A 100 1K 10K 100K
1.5
1.25
JUNCTION TEMPERATURE (C)
FREQUENCY (Hz)
Figure 7. Short-Circuit Current vs. Temperature
Figure 8. Ripple Rejection vs. Frequency
10
7.5 POWER (W) TO-263 5
2.5
SOT-223
0 25
45
65
85
105
125
CASE TEMPERATURE (C)
Figure 9. Maximum Power Dissipation
REV. 1.1.0 10/29/99
5
PRODUCT SPECIFICATION
RC1117
Mechanical Dimensions
3-Lead TO-263 Package
Symbol A b b2 c2 D E e L L1 L2 R Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. 2. 3. 4. 5. Dimensions are exclusive of mold flash and metal burrs. Stand off-height is measured from lead tip with ref. to Datum -B-. Foot length is measured with ref. to Datum -A- with lead surface (at inner R). Dimension exclusive of dambar protrusion or intrusion. Formed leads to be planar with respect to one another at seating place -C-.
.160 .190 .020 .039 .049 .051 .045 .055 .340 .380 .380 .405 .100 BSC .575 .625 .090 .100 -- .055 .017 .019 0 8
4.06 4.83 0.51 0.99 1.25 1.30 1.14 1.40 8.64 9.65 9.65 10.29 2.54 BSC 14.61 10.88 2.29 2.79 -- 1.40 0.43 0.48 0 8
E @PKG/ @HEATSINK
L2 c2
D L b2 E-PIN R (2 PLCS) L1 b e
-B-
-A-
A -C-
6
REV. 1.1.0 10/29/99
RC1117
PRODUCT SPECIFICATION
Mechanical Dimensions
4-Lead SOT-223 Package
Inches Min. A A1 B c D E e F H I J K L M N -- -- .025 -- .248 .130 .115 .033 .264 .012 -- 10 .0008 10 .010 Max. .071 .181 .033 .090 .264 .148 .124 .041 .287 -- 10 16 .0040 16 .014 Millimeters Min. -- -- .640 -- 6.30 3.30 2.95 .840 6.71 .310 -- 10 .0203 10 .250 Max. 1.80 4.80 .840 2.29 6.71 3.71 3.15 1.04 7.29 -- 10 16 .1018 16 .360
Symbol
Notes
D e K
A H E B A1 c F J M I L N
REV. 1.1.0 10/29/99
7
PRODUCT SPECIFICATION
RC1117
Ordering Information
Product Number RC1117M RC1117S RC1117M-2.5 RC1117S-2.5 RC1117M-2.85 RC1117S-2.85 RC1117M-3.3 RC1117S-3.3 RC1117M-5 RC1117S-5 Package TO-263 SOT-223 TO-263 SOT-223 TO-263 SOT-223 TO-263 SOT-223 TO-263 SOT-223
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. www.fairchildsemi.com
10/29/99 0.0m 004 Stock#DS30001117 (c) 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
ACExTM CoolFETTM CROSSVOLTTM E2CMOSTM FACTTM FACT Quiet SeriesTM FAST(R) FASTrTM GTOTM HiSeCTM
DISCLAIMER
ISOPLANARTM MICROWIRETM POPTM PowerTrench QFETTM QSTM Quiet SeriesTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8
SyncFETTM TinyLogicTM UHCTM VCXTM
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Rev. D
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RC1584
7A Adjustable/Fixed Low Dropout Linear Regulator
Features * Fast transient response * Low dropout voltage at up to 7A * Load regulation: 0.05% typical * Trimmed current limit * On-chip thermal limiting * Standard TO-220, TO-263 and TO-263 center cut packages
Description
The RC1584 and RC1584-1.5 are low dropout three-terminal regulators with 7A output current capability. These devices have been optimized for low voltage applications including VTT bus termination, where transient response and minimum input voltage are critical. The RC1584 is ideal for low voltage microprocessor applications requiring a regulated output from 1.5V to 3.6V with an input supply of 5V or less. The RC1584-1.5 offers fixed 1.5V with 7A current capability for GTL+ bus VTT termination. Current limit is trimmed to ensure specified output current and controlled short-circuit current. On-chip thermal limiting provides protection against any combination of overload and ambient temperature that would create excessive junction temperatures. The RC1584 and RC1584-1.5 are available in the industrystandard TO-220, TO-263 and TO-263 center cut power packages.
Applications
* Pentium(R) Class GTL+ bus supply * Low voltage logic supply * Post regulator for switching supply
Typical Applications
VIN = 3.3V 10F + VIN RC1584 VOUT ADJ 124 + 1.5V at 7A 22F
24.9
RC1584-1.5 VIN = 3.3V + 10F VIN VOUT GND + 1.5V at 7A 22F
65-1584-16
Pentium is a registered trademark of Intel Corporation.
REV. 1.0.3 11/11/99
RC1584
PRODUCT SPECIFICATION
Pin Assignments
RC1584T FRONT VIEW RC1584T-1.5 FRONT VIEW
RC1584M-1.5 FRONT VIEW
RC1584M FRONT VIEW
1
2
3
1
2
3
1
2
3
1
2
3
GND OUT IN
ADJ OUT IN
ADJ OUT IN
GND OUT IN
3-Lead Plastic TO-263 JC = 3C/W* RC1584MC-1.5 FRONT VIEW RC1584MC FRONT VIEW
3-Lead Plastic TO-220 JC = 3C/W
Tab is Out. 1 2 3 1 2 3
GND
IN
ADJ
IN
65-1584-02
3-Lead Plastic TO-263 Center Cut JC = 3C/W* * JA can vary from 20C/W to >40C/W with various mounting techniques.
Absolute Maximum Ratings
Parameter VIN Operating Junction Temperature Range Storage Temperature Range Lead Temperature (Soldering, 10 sec.) 0 -65 Min. Max. 7 125 150 300 Unit V C C C
2
REV. 1.0.3 11/11/99
PRODUCT SPECIFICATION
RC1584
Electrical Characteristics
Tj = 25C unless otherwise specified. The * denotes specifications which apply over the specified operating temperature range. Parameter Reference Voltage Output Voltage4 Line Regulation1, 2 Load Regulation1, 2 Dropout Voltage Current Limit Adjust Pin Current3 Adjust Pin Current Change3 1.5V (VIN - VOUT) 5.75V, 10mA IOUT 7A Minimum Load Current Quiescent Current Ripple Rejection Thermal Regulation Temperature Stability Long-Term Stability RMS Output Noise (% of VOUT) Thermal Resistance, Junction to Case Thermal Shutdown TA = 125C, 1000 hrs. TA = 25C, 10Hz f 10kHz TO-220 TO-263 1.5V (VIN - VOUT) 5.75V VIN = 5V f = 120Hz, COUT = 22F Tantalum, (VIN - VOUT) = 3V, IOUT = 7A TA = 25C, 30ms pulse *
3
Conditions 1.5V (VIN - VOUT) 5.75V, 10mA IOUT 7A 3.3V VIN 7V 10mA IOUT 7A (VOUT + 1.5V) VIN 7V, IOUT = 10mA (VIN - VOUT) = 3V 10mA IOUT 7A VREF = 1%, IOUT = 7A (VIN - VOUT) = 2V * * * * * * * * * *
Min. 1.225 (-2%) 1.47
Typ. 1.250 1.5 0.005 0.05 1.150
Max 1.275 (+2%) 1.53 0.2 0.5 1.300 120 5
Units V V % % V A A A mA
7.1
8 35 0.2
10 4 60 72 0.004 0.5 0.03 0.003 3 3 150 1.0 0.02 13
mA dB %/W % % % C/W C/W C
Notes: 1. See thermal regulation specifications for changes in output voltage due to heating effects. Load and line regulation are measured at a constant junction temperature by low duty cycle pulse testing. 2. Line and load regulation are guaranteed up to the maximum power dissipation (18W). Power dissipation is determined by input/output differential and the output currrent. Guaranteed maximum output power will not be available over the full input/ output voltage range. 3. RC1584 only. 4. RC1584-1.5 only.
REV. 1.0.3 11/11/99
3
RC1584
PRODUCT SPECIFICATION
Typical Performance Characteristics
1.5 OUTPUT VOLTAGE DEVIATION (%) 1.4 DROPOUT VOLTAGE (V) 1.3 1.2 1.1 1.0 0.9 T=25C 0.8
65-1584-03
0.10
I = 7A
0.05
0
T=0C T=125C
-0.05
-0.10
65-1584-04
0.7 0.6 0.5 0 1 2 3 4 5 6 7 OUTPUT CURRENT (A)
-0.15
-0.20 -75 -50 -25
0
25 50 75 100 125 150 175
JUNCTION TEMPERATURE (C)
Figure 1. Dropout Voltage vs. Output Current
Figure 2. Load Regulation vs. Temperature
1.275 1.270 REFERENCE VOLTAGE (V) REFERENCE VOLTAGE (V) 1.265 1.260 1.255 1.250 1.245 1.240
65-1584-05
3.70 3.65 3.60 3.55 3.50 3.45 3.40 3.35
65-1584-06
VOUT SET WITH 1% RESISTORS VOUT = 3.6V1
1.235 1.230 1.225 -75 -50 -25 0
3.30 3.25 3.20 -75 -50 -25 0
Note: 1. RC1584 Only
25 50 75 100 125 150 175
25 50 75 100 125 150 175
JUNCTION TEMPERATURE (C)
JUNCTION TEMPERATURE (C)
Figure 3. Reference Voltage vs. Temperature
Figure 4. Output Voltage vs. Temperature
5 MINIMUM LOAD CURRENT (mA)
100 90
Note: 1. RC1584 Only
4
ADJUST PIN CURRENT (A)
80 70 60 50 40 30
65-1584-08
3
2
65-1584-07
1
20 10 0 -75 -50 -25 0
0 -75 -50 -25
0
25 50 75 100 125 150 175
25 50 75 100 125 150 175
JUNCTION TEMPERATURE (C)
JUNCTION TEMPERATURE (C)
Figure 5. Minimum Load Current vs. Temperature
Figure 6. Adjust Pin Current vs. Temperature
4
REV. 1.0.3 11/11/99
PRODUCT SPECIFICATION
RC1584
Typical Performance Characteristics (continued)
10 SHORT-CIRCUIT CURRENT (A) 90 80 RIPPLE REJECTIONS (dB) 9 70 60 50 40 30 20 10 0 10
65-1584-10
8
7
65-1584-09
(VIN - VOUT) 3V 0.5V VRIPPLE 2V IOUT = 7A 100 1K FREQUENCY (Hz) 10K
6 -75 -50 -25
0
25 50 75 100 125 150 175
100K
JUNCTION TEMPERATURE (C)
Figure 7. Short-Circuit Current vs. Temperature
Figure 8. Ripple Rejection vs. Frequency
20
POWER (W)
15 10
65-1584-11
5
0 50 60 70 80 90 100 110 120 130 140 150 CASE TEMPERATURE (C)
Figure 9. Maximum Power Dissipation
REV. 1.0.3 11/11/99
5
RC1584
PRODUCT SPECIFICATION
Applications Information
General
The RC1584 and RC1584-1.5 are three-terminal regulators optimized for GTL+ VTT termination applications. These devices are short-circuit protected, and offer thermal shutdown to turn off the regulator when the junction temperature exceeds about 150C. The RC1584 series provides low dropout voltage and fast transient response. Frequency compensation uses capacitors with low ESR while still maintaining stability. This is critical in addressing the needs of low voltage high speed microprocessor buses like GTL+.
D1 1N4002 (OPTIONAL)
RC1584 RC1587 VIN C1 10F + IN ADJ + CADJ R2 OUT R1 + VOUT C2 22F
Stability
The RC1584 series require an output capacitor as a part of the frequency compensation. It is recommended to use a 22F solid tantalum or a 100F aluminum electrolytic on the output to ensure stability. The frequency compensation of these devices optimizes the frequency response with low ESR capacitors. In general, it is suggested to use capacitors with an ESR of <1. It is also recommended to use bypass capacitors such as a 22F tantalum or a 100F aluminum on the adjust pin of the RC1584 for low ripple and fast transient response. When these bypassing capacitors are not used at the adjust pin, larger values of output capacitors provide equally good results.
D1 1N4002 (OPTIONAL)
RC1587-1.5, -3.3 RC1584-1.5 VIN C1 10F + IN GND OUT + VOUT C2 22F
65-1584-13 65-1587-13
Figure 10. Optional Protection
Protection Diodes
In normal operation, the RC1584 series does not require any protection diodes. For the RC1584, internal resistors limit internal current paths on the adjust pin. Therefore, even with bypass capacitors on the adjust pin, no protection diode is needed to ensure device safety under shortcircuit conditions. A protection diode between the input and output pins is usually not needed. An internal diode between the input and output pins on the RC1584 series can handle microsecond surge currents of 50A to 100A. Even with large value output capacitors it is difficult to obtain those values of surge currents in normal operation. Only with large values of output capacitance, such as 1000F to 5000F, and with the input pin instantaneously shorted to ground can damage occur. A crowbar circuit at the input can generate those levels of current; a diode from output to input is then recommended, as shown in Figure 10. Usually, normal power supply cycling or system "hot plugging and unplugging" will not generate current large enough to do any damage. The adjust pin can be driven on a transient basis 7V with respect to the output, without any device degradation. As with any IC regulator, exceeding the maximum input-tooutput voltage differential causes the internal transistors to break down and none of the protection circuitry is then functional.
Ripple Rejection
In applications that require improved ripple rejection, a bypass capacitor from the adjust pin of the RC1584 to ground reduces the output ripple by the ratio of VOUT/1.25V. The impedance of the adjust pin capacitor at the ripple frequency should be less than the value of R1 (typically in the range of 100 to 120) in the feedback divider network in Figure 10. Therefore, the value of the required adjust pin capacitor is a function of the input ripple frequency. For example, if R1 equals 100 and the ripple frequency equals 120Hz, the adjust pin capacitor should be 22F. At 10kHz, only 0.22F is needed.
Output Voltage
The RC1584 regulator develops a 1.25V reference voltage between the output pin and the adjust pin (see Figure 11). Placing a resistor R1 between these two terminals causes a constant current to flow through R1 and down through R2 to set the overall output voltage. Normally, this current is the specified minimum load current of 10mA. The current out of the adjust pin adds to the current from R1 and is typically 35A. Its output voltage contribution is small and only needs consideration when very precise output voltage setting is required.
6
REV. 1.0.3 11/11/99
PRODUCT SPECIFICATION
RC1584
RC1584 VIN + IN C1 10F ADJ IADJ 35A VOUT = VREF (1 + R2/R1) + IADJ (R2) OUT VREF R1 + VOUT C2 22F VIN IN ADJ RC1584 OUT
RP PARASITIC LINE RESISTANCE
R2
65-1584-14
R1* RL * CONNECT R1 TO CASE CONNECT R2 TO LOAD R2*
Figure 11. Basic Regulator Circuit
Load Regulation
It is not possible to provide true remote load sensing because the RC1584 series are three-terminal devices. Load regulation is limited by the resistance of the wire connecting the regulators to the load. Load regulation per the data sheet specification is measured at the bottom of the package. For fixed voltage devices, negative side sensing is a true Kelvin connection with the ground pin of the device returned to the negative side of the load. This is illustrated in Figure 12.
RC1584-1.5 VIN IN GND OUT RL RP PARASITIC LINE RESISTANCE
65-1584-15
Figure 13. Connection for Best Load Regulation
Thermal Considerations
The RC1584 series protect themselves under overload conditions with internal power and thermal limiting circuitry. However, for normal continuous load conditions, do not exceed maximum junction temperature ratings. It is important to consider all sources of thermal resistance from junction-to-ambient. These sources include the junction-to-case resistance, the case-to-heat sink interface resistance, and the heat sink resistance. Thermal resistance specifications have been developed to more accurately reflect device temperature and ensure safe operating temperatures. For example, look at using an RC1584T to generate 7A @ 1.5V 2% from a 1.8V source (1.71V to 1.89V). Assumptions: * * * * * VIN = 1.89V worst case VOUT = 1.46V worst case IOUT = 7A continuous TA = 70C Case-to-Ambient = 3C/W (assuming both a heatsink and a thermally conductive material) The power dissipation in this application is: PD = (VIN - VOUT) * (IOUT) = (1.89 - 1.46) * (3) = 3.01W From the specification table: TJ = TA + (PD) * (Case-to-Ambient + JC) = 70 + (3.01) * (3 + 3) = 88C The junction temperature is below the maximum rating.
65-1584-17
Figure 12. Connection for Best Load Regulation
For adjustable voltage devices, negative side sensing is a true Kelvin connection with the bottom of the output divider returned to the negative side of the load. The best load regulation is obtained when the top of resistor divider R1 connects directly to the regulator output and not to the load. Figure 13 illustrates this point. If R1 connects to the load, then the effective resistance between the regulator and the load would be: RP x (1 + R2/R1), RP = Parasitic Line Resistance The connection shown in Figure 13 does not multiply RP by the divider ratio. As an example, RP is about four milliohms per foot with 16-gauge wire. This translates to 4mV per foot at 1A load current. At higher load currents, this drop represents a significant percentage of the overall regulation. It is important to keep the positive lead between the regulator and the load as short as possible and to use large wire or PC board traces.
REV. 1.0.3 11/11/99
7
RC1584
PRODUCT SPECIFICATION
Junction-to-case thermal resistance is specified from the IC junction to the bottom of the case directly below the die. This is the lowest resistance path for heat flow. Proper mounting ensures the best thermal flow from this area of the package to the heat sink. Use of a thermally conductive material at the
case-to-heat sink interface is recommended. Use a thermally conductive spacer if the case of the device must be electrically isolated and include its contribution to the total thermal resistance. The cases of the RC1584 series are directly connected to the output of the device.
VIN 3.3V C1 10F
U1 RC1584 VIN + ADJ + C2 100F VOUT R1 124 R2 24.9 +
VOUT 1.5V C3 100F
65-1584-18
Figure 14. Application Circuit (RC1584)
Table 1. Bill of Materials for Application Circuit for the RC1584
Item C1 C2, C3 R1 R2 U1 Quantity 1 2 1 1 1 Manufacturer Xicon Xicon Generic Generic Fairchild RC1584T Part Number L10V10 L10V100 Description 10F, 10V Aluminum 100F, 10V Aluminum 124, 1% 24.9, 1% 7A Regulator
VIN 3.3V C1 10F
U1 RC1584-1.5 VIN + VOUT GND +
VOUT 1.5V C3 100F
65-1584-19
Figure 15. Application Circuit (RC1584-1.5)
Table 2. Bill of Materials for Application Circuit for the RC1584-1.5
Item C1 C3 U1 Quantity 1 1 1 Manufacturer Xicon Xicon Fairchild Part Number L10V10 L10V100 RC1584T-1.5 Description 10F, 10V Aluminum 100F, 10V Aluminum 7A Regulator
8
REV. 1.0.3 11/11/99
PRODUCT SPECIFICATION
RC1584
Mechanical Dimensions
3-Lead TO-263 Package
Inches Min. A b b2 c2 D E e L L1 L2 R .160 .020 Max. .190 .039 Millimeters Min. 4.06 0.51 Max. 4.83 0.99 Notes: 1. Dimensions are exclusive of mold flash and metal burrs. 2. Standoff-height is measured from lead tip with ref. to Datum -B-. 3. Foot length is measured with ref. to Datum -A- with lead surface (at inner R). 4. Dimensiuon exclusive of dambar protrusion or intrusion. 5. Formed leads to be planar with respect to one another at seating place -C-.
Symbol
Notes
.049 .051 .045 .055 .340 .380 .380 .405 .100 BSC .575 .090 -- .017 0 .625 .110 .055 .019 8
1.25 1.30 1.14 1.40 8.64 9.65 9.65 10.29 2.54 BSC 14.61 2.29 -- 0.43 0 15.88 2.79 1.40 0.78 8
E @PKG/ @HEATSINK
L2 c2
D L b2 E-PIN R (2 PLCS) L1 b e
-B-
-A-
A -C-
REV. 1.0.3 11/11/99
9
RC1584
PRODUCT SPECIFICATION
Mechanical Dimensions (continued)
3-Lead TO-263 Center Cut Package
Inches Min. A b b2 c2 D E e L L1 L2 R .160 .020 Max. .190 .039 Millimeters Min. 4.06 0.51 Max. 4.83 0.99 Notes: 1. Dimensions are exclusive of mold flash and metal burrs. 2. Standoff-height is measured from lead tip with ref. to Datum -B-. 3. Foot length is measured with ref. to Datum -A- with lead surface (at inner R). 4. Dimensiuon exclusive of dambar protrusion or intrusion. 5. Formed leads to be planar with respect to one another at seating place -C-.
Symbol
Notes
.049 .051 .045 .055 .340 .380 .380 .405 .100 BSC .575 .090 -- .017 0 .625 .110 .055 .019 8
1.25 1.30 1.14 1.40 8.64 9.65 9.65 10.29 2.54 BSC 14.61 2.29 -- 0.43 0 15.88 2.79 1.40 0.78 8
E @PKG/ @HEATSINK
L2 c2
D L b2 E-PIN R (2 PLCS) L1 b e
-B-
-A-
A -C-
10
REV. 1.0.3 11/11/99
PRODUCT SPECIFICATION
RC1584
Mechanical Dimensions (continued)
3-Lead TO-220 Package
Inches Min. A b b1 c1 oP D E e e1 e3 F H1 J1 L L1 Q Max. Millimeters Min. Max.
Symbol
Notes
.140 .190 .015 .040 .045 .070 .014 .022 .139 .161 .560 .650 .380 .420 .090 .110 .190 .210 .045 -- .020 .055 .230 .270 .080 .115 .500 .580 .250 BSC .100 .135 3 7
3.56 4.83 .38 1.02 1.14 1.78 .36 .56 3.53 4.09 14.22 16.51 9.65 10.67 2.29 2.79 4.83 5.33 1.14 -- .51 1.40 5.94 6.87 2.04 2.92 12.70 14.73 6.35 BSC 2.54 3.43 3 7
Notes: 1. Dimension c1 apply for lead finish.
H1 L e3 e e1 E b1 Q
b L1 E-PIN oP
(5X) c1 J1 D A F
REV. 1.0.3 11/11/99
11
RC1584
PRODUCT SPECIFICATION
Ordering Information
Product Number RC1584M RC1584MC RC1584T RC1584M-1.5 RC1584MC-1.5 RC1584T-1.5 Package TO-263 TO-263 center cut TO-220 TO-263 TO-263 center cut TO-220
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2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
TRADEMARKS
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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Rev. D
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RC1585
5A Adjustable/Fixed Low Dropout Linear Regulator
Features
* * * * * * Fast transient response Low dropout voltage at up to 5A Load regulation: 0.05% typical Trimmed current limit On-chip thermal limiting Standard TO-220, TO-263 and TO-263 center cut packages
Description
The RC1585 and RC1585-1.5 are low dropout three-terminal regulators with 5A output current capability. These devices have been optimized for low voltage applications including VTT bus termination, where transient response and minimum input voltage are critical. The RC1585 is ideal for low voltage microprocessor applications requiring a regulated output from 1.5V to 3.6V with an input supply of 5V or less. The RC1585-1.5 offers fixed 1.5V with 5A current capabilities for GTL+ bus VTT termination. Current limit is trimmed to ensure specified output current and controlled short-circuit current. On-chip thermal limiting provides protection against any combination of overload and ambient temperature that would create excessive junction temperatures. The RC1585 series regulators are available in the industrystandard TO-220, TO-263 and TO-263 center cut power packages.
Applications
* Pentium(R) class GTL+ bus supply * Low voltage logic supply * Post regulator for switching supply
Typical Applications
RC1585 VOUT ADJ 124 +
VIN = 3.3V 10F +
VIN
1.5V at 5A 22F
24.9
RC1585-1.5 VIN = 3.3V + 10F VIN VOUT GND + 1.5V at 5A 22F
65-1585-01a
Pentium is a registered trademark of Intel Corporation.
Rev. 1.0.4
RC1585
PRODUCT SPECIFICATION
Pin Assignments
RC1585T FRONT VIEW RC1585T-1.5 FRONT VIEW
RC1585M-1.5 FRONT VIEW
RC1585M FRONT VIEW
1
2
3
1
2
3
1
2
3
1
2
3
GND OUT IN
ADJ OUT IN
ADJ OUT IN
GND OUT IN
3-Lead Plastic TO-263 JC = 3C/W* RC1585MC-1.5 FRONT VIEW RC1585MC FRONT VIEW
3-Lead Plastic TO-220 JC = 3C/W
Tab is Out. 1 2 3 1 2 3
GND
IN
ADJ
IN
3-Lead Plastic TO-263 Center Cut JA = 3C/W* * JA can vary from 20C/W to >40C/W with various mounting techniques.
65-1585-02
Absolute Maximum Ratings
Parameter VIN Operating Junction Temperature Range Storage Temperature Range Lead Temperature (Soldering, 10 sec.) 0 -65 Min. Max. 7 125 150 300 Unit V C C C
2
PRODUCT SPECIFICATION
RC1585
Electrical Characteristics
Tj = 25C unless otherwise specified. The * denotes specifications which apply over the specified operating temperature range. Parameter Reference Voltage Output Voltage4 Line Regulation1, 2 Load Regulation1, 2, 3 Dropout Voltage Current Limit Adjust Pin Current3 Adjust Pin Current Change3 1.5V (VIN - VOUT) 5.75V, 10mA IOUT 5A Minimum Load Current Quiescent Current Ripple Rejection Thermal Regulation Temperature Stability Long-Term Stability RMS Output Noise (% of VOUT) Thermal Resistance, Junction to Case Thermal Shutdown TA = 125C, 1000 hrs. TA = 25C, 10Hz f 10kHz TO-220 TO-263 1.5V (VIN - VOUT) 5.75V VIN = 5V f = 120Hz, COUT = 22F Tantalum, (VIN - VOUT) = 3V, IOUT = 5A TA = 25C, 30ms pulse *
3
Conditions 1.5V (VIN - VOUT) 5.75V, 10mA IOUT 5A 3V VIN 7V 10mA IOUT 5A (VOUT + 1.5V) VIN 7V, IOUT = 10mA (VIN - VOUT) = 3V, 10mA IOUT 5A VREF = 1%, IOUT = 5A (VIN - VOUT) = 2V * * * * * * * * * *
Min. 1.225 (-2%) 1.47
Typ. 1.250 1.5 0.005 0.05 1.150
Max 1.275 (+2%) 1.53 0.2 0.5 1.300 120 5
Units V V % % V A A A mA
5.1
5.5 35 0.2
10 4 60 72 0.004 0.5 0.03 0.003 3 3 150 1.0 0.02 13
mA dB %/W % % % C/W C/W C
Notes: 1. See thermal regulation specifications for changes in output voltage due to heating effects. Load and line regulation are measured at a constant junction temperature by low duty cycle pulse testing. 2. Line and load regulation are guaranteed up to the maximum power dissipation (18W). Power dissipation is determined by input/output differential and the output currrent. Guaranteed maximum output power will not be available over the full input/ output voltage range. 3. RC1585 only. 4. RC1585-1.5 only.
3
RC1585
PRODUCT SPECIFICATION
Typical Performance Characteristics
1.5 OUTPUT VOLTAGE DEVIATION (%) 1.4 DROPOUT VOLTAGE (V) 1.3 1.2 1.1 1.0 0.9 T=25C 0.8
65-1585-03
0.10
I = 5A
0.05
0
T=0C T=125C
-0.05
-0.10
65-1585-04
0.7 0.6 0.5 0 1 2 3 4 5 OUTPUT CURRENT (A)
-0.15
-0.20 -75 -50 -25
0
25 50 75 100 125 150 175
JUNCTION TEMPERATURE (C)
Figure 1. Dropout Voltage vs. Output Current
Figure 2. Load Regulation vs. Temperature
1.250 1.245 REFERENCE VOLTAGE (V) REFERENCE VOLTAGE (V) 1.240 1.235 1.230 1.225 1.220 1.215
65-1585-05
3.70 VOUT SET WITH 1% RESISTORS 3.65 3.60 3.55 3.50 3.45 3.40 3.35 VOUT = 3.3V
65-1585-06 65-1585-08
VOUT = 3.6V
1
1.210 1.205 1.200 -75 -50 -25 0 25 50 75 100 125 150 175
3.30 3.25 3.20 -75 -50 -25
1
Note: 1. RC1585 Only
0
25 50 75 100 125 150 175
JUNCTION TEMPERATURE (C)
JUNCTION TEMPERATURE (C)
Figure 3. Reference Voltage vs. Temperature
Figure 4. Output Voltage vs. Temperature
5 MINIMUM LOAD CURRENT (mA)
100 90 ADJUST PIN CURRENT (A)
Note: 1. RC1585 Only
4
80 70 60 50 40 30 20 10 0 -75 -50 -25 0
3
2
0 -75 -50 -25
0
25 50 75 100 125 150 175
65-1585-07
1
25 50 75 100 125 150 175
JUNCTION TEMPERATURE (C)
JUNCTION TEMPERATURE (C)
Figure 5. Minimum Load Current vs. Temperature
Figure 6. Adjust Pin Current vs. Temperature
4
PRODUCT SPECIFICATION
RC1585
Typical Performance Characteristics (continued)
8.0 SHORT-CIRCUIT CURRENT (A) 90 80 RIPPLE REJECTIONS (dB) 7.0 70 60 50 40 30 20 10 0 10
65-1585-10
6.0
5.0
65-1585-09
(VIN - VOUT) 3V 0.5V VRIPPLE 2V IOUT = 5A 100 1K FREQUENCY (Hz) 10K
4.0 -75 -50 -25
0
25 50 75 100 125 150 175
100K
JUNCTION TEMPERATURE (C)
Figure 7. Short-Circuit Current vs. Temperature
Figure 8. Ripple Rejection vs. Frequency
20 15
POWER (W)
10 5
65-1585-11
0 50 60 70 80 90 100 110 120 130 140 150 CASE TEMPERATURE (C)
Figure 9. Maximum Power Dissipation
5
RC1585
PRODUCT SPECIFICATION
Applications Information
General
The RC1585 and RC1585-1.5 are three-terminal regulators optimized for GTL+ VTT termination and logic applications. These devices are short-circuit protected and offer thermal shutdown to turn off the regulator when the junction temperature exceeds about 150C. The RC1585 series provides low dropout voltage and fast transient response. Frequency compensation uses capacitors with low ESR while still maintaining stability. This is critical in addressing the needs of low voltage high speed microprocessor buses like GTL+.
D1 1N4002 (OPTIONAL)
RC1585 VIN C1 10F + IN ADJ + CADJ R2 OUT R1 + VOUT C2 22F
Stability
The RC1585 series requires an output capacitor as a part of the frequency compensation. It is recommended to use a 22F solid tantalum or a 100 F aluminum electrolytic on the output to ensure stability. The frequency compensation of these devices optimizes the frequency response with low ESR capacitors. In general, it is suggested to use capacitors with an ESR of <1. It is also recommended to use bypass capacitors such as a 22F tantalum or a 100F aluminum on the adjust pin of the RC1585 for low ripple and fast transient response. When these bypassing capacitors are not used at the adjust pin, larger values of output capacitors provide equally good results.
D1 1N4002 (OPTIONAL)
RC1585-1.5 VIN C1 10F + IN GND OUT + VOUT C2 22F
65-1585-12
Figure 10. Optional Protection
Protection Diodes
In normal operation, the RC1585 series does not require any protection diodes. For the RC1585, internal resistors limit internal current paths on the adjust pin. Therefore, even with bypass capacitors on the adjust pin, no protection diode is needed to ensure device safety under short-circuit conditions. A protection diode between the input and output pins is usually not needed. An internal diode between the input and the output pins on the RC1585 series can handle microsecond surge currents of 50A to 100A. Even with large value output capacitors it is difficult to obtain those values of surge currents in normal operation. Only with large values of output capacitance, such as 1000F to 5000F, and with the input pin instantaneously shorted to ground can damage occur. A crowbar circuit at the input can generate those levels of current; a diode from output to input is then recommended, as shown in Figure 10. Usually, normal power supply cycling or system "hot plugging and unplugging" will not generate current large enough to do any damage. The adjust pin can be driven on a transient basis 7V with respect to the output, without any device degradation. As with any IC regulator, exceeding the maximum input-tooutput voltage differential causes the internal transistors to break down and none of the protection circuitry is then functional.
Ripple Rejection
In applications that require improved ripple rejection, a bypass capacitor from the adjust pin of the RC1585 to ground reduces the output ripple by the ratio of VOUT/1.25V. The impedance of the adjust pin capacitor at the ripple frequency should be less than the value of R1 (typically in the range of 100 to 120) in the feedback divider network in Figure 10. Therefore, the value of the required adjust pin capacitor is a function of the input ripple frequency. For example, if R1 equals 100 and the ripple frequency equals 120Hz, the adjust pin capacitor should be 22F. At 10kHz, only 0.22F is needed.
Output Voltage
The RC1585 regulator develops a 1.25V reference voltage between the output pin and the adjust pin (see Figure 11). Placing a resistor R1 between these two terminals causes a constant current to flow through R1 and down through R2 to set the overall output voltage. Normally, this current is the specified minimum load current of 10mA. The current out of the adjust pin adds to the current from R1 and is typically 35A. Its output voltage contribution is small and only needs consideration when a very precise output voltage setting is required.
6
PRODUCT SPECIFICATION
RC1585
RC1585 VIN + IN C1 10F ADJ IADJ 35A VOUT = VREF (1 + R2/R1) + IADJ (R2) OUT VREF R1 + VOUT C2 22F RC1585 VIN IN ADJ OUT
RP PARASITIC LINE RESISTANCE
R2
65-1585-13
R1* RL * CONNECT R1 TO CASE CONNECT R2 TO LOAD R2*
Figure 11. Basic Regulator Circuit
Load Regulation
It is not possible to provide true remote load sensing because the RC1585 series are three-terminal devices. Load regulation is limited by the resistance of the wire connecting the regulators to the load. Load regulation per the data sheet specification is measured at the bottom of the package. For fixed voltage devices, negative side sensing is a true Kelvin connection with the ground pin of the device returned to the negative side of the load. This is illustrated in Figure 12.
RC1585-1.5 VIN IN GND RL OUT RP PARASITIC LINE RESISTANCE
65-1585-15
Figure 13. Connection for Best Load Regulation
Thermal Considerations
The RC1585 series protect themselves under overload conditions with internal power and thermal limiting circuitry. However, for normal continuous load conditions, do not exceed maximum junction temperature ratings. It is important to consider all sources of thermal resistance from junction-to-ambient. These sources include the junction-to-case resistance, the case-to-heat sink interface resistance, and the heat sink resistance. Thermal resistance specifications have been developed to more accurately reflect device temperature and ensure safe operating temperatures. For example, look at using an RC1585T to generate 5A @ 1.5V 2% from a 3.3V source (3.2V to 3.6V). Assumptions: * * * * * VIN = 3.6V worst case VOUT = 1.46V worst case IOUT = 5A continuous TA = 60C Case-to-Ambient = 3C/W (assuming both a heatsink and a thermally conductive material)
65-1585-14
Figure 12. Connection for Best Load Regulation
For adjustable voltage devices, negative side sensing is a true Kelvin connection with the bottom of the output divider returned to the negative side of the load. The best load regulation is obtained when the top of the resistor divider R1 connects directly to the regulator output and not to the load. Figure 13 illustrates this point. If R1 connects to the load, then the effective resistance between the regulator and the load would be: RP x (1 + R2/R1), RP = Parasitic Line Resistance The connection shown in Figure 13 does not multiply RP by the divider ratio. As an example, RP is about four milliohms per foot with 16-gauge wire. This translates to 4mV per foot at 1A load current. At higher load currents, this drop represents a significant percentage of the overall regulation. It is important to keep the positive lead between the regulator and the load as short as possible and to use large wire or PC board traces.
The power dissipation in this application is: PD = (VIN - VOUT) * (IOUT) = (3.6 - 1.46) * (5) = 10.7W From the specification table: TJ = TA + (PD) * (Case-to-Ambient + JC) = 60 + (10.7) * (3 + 3) = 120C The junction temperature is below the maximum rating.
7
RC1585
PRODUCT SPECIFICATION
Junction-to-case thermal resistance is specified from the IC junction to the bottom of the case directly below the die. This is the lowest resistance path for heat flow. Proper mounting ensures the best thermal flow from this area of the package to the heat sink. Use of a thermally conductive material at the
case-to-heat sink interface is recommended. Use a thermally conductive spacer if the case of the device must be electrically isolated and include its contribution to the total thermal resistance. The cases of the RC1585 series are directly connected to the output of the device.
VIN 3.3V C1 10F
U1 RC1585 VIN + ADJ + C2 100F VOUT R1 124 R2 24.9 +
VOUT 1.5V C3 100F
65-1586-16
Figure 14. Application Circuit (RC1585)
Table 1. Bill of Materials for Application Circuit for the RC1585
Item C1 C2, C3 R1 R2 U1 Quantity 1 2 1 1 1 Manufacturer Xicon Xicon Generic Generic Fairchild RC1585T Part Number L10V10 L10V100 Description 10F, 10V Aluminum 100F, 10V Aluminum 124, 1% 24.9, 1% 5A Regulator
VIN 3.3V C1 10F
U1 RC1585-1.5 VIN + VOUT GND +
VOUT 1.5V C3 100F
65-1585-17
Figure 15. Application Circuit (RC1585-1.5)
Table 2. Bill of Materials for Application Circuit for the RC1585-1.5
Item C1 C3 U1 Quantity 1 1 1 Manufacturer Xicon Xicon Fairchild Part Number L10V10 L10V100 RC1585T-1.5 Description 10F, 10V Aluminum 100F, 10V Aluminum 5A Regulator
8
PRODUCT SPECIFICATION
RC1585
Mechanical Dimensions
3-Lead TO-263 Package
Notes: 1. Dimensions are exclusive of mold flash and metal burrs. 2. Standoff-height is measured from lead tip with ref. to Datum -B-. 3. Foot length is measured with ref. to Datum -A- with lead surface (at inner R). 4. Dimensiuon exclusive of dambar protrusion or intrusion. 5. Formed leads to be planar with respect to one another at seating place -C-.
Symbol A b b2 c2 D E e L L1 L2 R
Inches Min. .160 .020 Max. .190 .039
Millimeters Min. 4.06 0.51 Max. 4.83 0.99
Notes
.049 .051 .045 .055 .340 .380 .380 .405 .100 BSC .575 .090 -- .017 0 .625 .110 .055 .019 8
1.25 1.30 1.14 1.40 8.64 9.65 9.65 10.29 2.54 BSC 14.61 2.29 -- 0.43 0 15.88 2.79 1.40 0.78 8
E @PKG/ @HEATSINK
L2 c2
D L b2 E-PIN R (2 PLCS) L1 b e
-B-
-A-
A -C-
9
RC1585
PRODUCT SPECIFICATION
Mechanical Dimensions (continued)
3-Lead TO-263 Center Cut Package
Inches Min. A b b2 c2 D E e L L1 L2 R .160 .020 Max. .190 .039 Millimeters Min. 4.06 0.51 Max. 4.83 0.99 Notes: 1. Dimensions are exclusive of mold flash and metal burrs. 2. Standoff-height is measured from lead tip with ref. to Datum -B-. 3. Foot length is measured with ref. to Datum -A- with lead surface (at inner R). 4. Dimensiuon exclusive of dambar protrusion or intrusion. 5. Formed leads to be planar with respect to one another at seating place -C-.
Symbol
Notes
.049 .051 .045 .055 .340 .380 .380 .405 .100 BSC .575 .090 -- .017 0 .625 .110 .055 .019 8
1.25 1.30 1.14 1.40 8.64 9.65 9.65 10.29 2.54 BSC 14.61 2.29 -- 0.43 0 15.88 2.79 1.40 0.78 8
E @PKG/ @HEATSINK
L2 c2
D L b2 E-PIN R (2 PLCS) L1 b e
-B-
-A-
A -C-
10
PRODUCT SPECIFICATION
RC1585
Mechanical Dimensions (continued)
3-Lead TO-220 Package
Symbol A b b1 c1 oP D E e e1 e3 F H1 J1 L L1 Q Inches Min. Max. Millimeters Min. Max. Notes
.140 .190 .015 .040 .045 .070 .014 .022 .139 .161 .560 .650 .380 .420 .090 .110 .190 .210 .045 -- .020 .055 .230 .270 .060 .115 .500 .580 .250 BSC .100 .135 3 7
3.56 4.83 .38 1.02 1.14 1.78 .36 .56 3.53 4.09 14.22 16.51 9.65 10.67 2.29 2.79 4.83 5.33 1.14 -- .51 1.40 5.94 6.87 2.04 2.92 12.70 14.73 6.35 BSC 2.54 3.43 3 7
Notes: 1. Dimension c1 apply for lead finish.
H1 L e3 e e1 E b1 Q
b L1 E-PIN oP
(5X) c1 J1 D A F
11
RC1585
PRODUCT SPECIFICATION
Ordering Information
Product Number RC1585M RC1585MC RC1585T RC1585M-1.5 RC1585MC-1.5 RC1585T-1.5 Package TO-263 TO-263 Center Cut TO-220 TO-263 TO-263 Center Cut TO-220
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
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TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
ACExTM CoolFETTM CROSSVOLTTM E2CMOSTM FACTTM FACT Quiet SeriesTM FAST(R) FASTrTM GTOTM HiSeCTM
DISCLAIMER
ISOPLANARTM MICROWIRETM POPTM PowerTrench QFETTM QSTM Quiet SeriesTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8
SyncFETTM TinyLogicTM UHCTM VCXTM
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Rev. D
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RC1587
3A Adjustable/Fixed Low Dropout Linear Regulator
Features * Fast transient response * Low dropout voltage at up to 3A * Load regulation: 0.05% typical * Trimmed current limit * On-chip thermal limiting * Standard TO-220, TO-263 and TO-263 center cut packages
Description
The RC1587, RC1587-1.5, and RC1587-3.3 are low dropout three-terminal regulators with 3A output current capability. These devices have been optimized for low voltage applications including VTT bus termination, where transient response and minimum input voltage are critical. The RC1587 is ideal for low voltage microprocessor applications requiring a regulated output from 1.5V to 3.6V with an input supply of 5V or less. The RC1587-1.5 offers fixed 1.5V with 3A current capability for GTL+ bus VTT termination. The RC1587-3.3 offers fixed 3.3V current capability for logic IC operation. Current limit is trimmed to ensure specified output current and controlled short-circuit current. On-chip thermal limiting provides protection against any combination of overload and ambient temperature that would create excessive junction temperatures. The RC1587, RC1587-1.5, and RC1587-3.3 are available in the industry-standard TO-220, TO-263 and TO-263 center cut power packages.
Applications
* Pentium(R) Class GTL+ bus supply * Low voltage logic supply * Post regulator for switching supply
Typical Applications
VIN = 3.3V 10F + VIN RC1587 VOUT ADJ 124 + 1.5V at 3A 22F
24.9
VIN = 3.3V + 10F
RC1587-1.5 VIN VOUT GND +
1.5V at 3A 22F
VIN = 5V + 10F
RC1587-3.3 VIN VOUT GND +
3.3V at 3A 22F
65-1587-16
Pentium is a registered trademark of Intel Corporation.
Rev. 1.3.4
RC1587
PRODUCT SPECIFICATION
Pin Assignments
RC1587T FRONT VIEW RC1587T-1.5, -3.3V FRONT VIEW
RC1587M-1.5 FRONT VIEW
RC1587M FRONT VIEW
1
2
3
1
2
3
1
2
3
1
2
3
GND OUT IN
ADJ OUT IN
ADJ OUT IN
GND OUT IN
3-Lead Plastic TO-263 JC = 3C/W* RC1587MC-1.5, 3.3 FRONT VIEW RC1587MC FRONT VIEW
3-Lead Plastic TO-220 JC = 3C/W
Tab is Out. 1 2 3 1 2 3
GND
IN
ADJ
IN
65-1587-02
3-Lead Plastic TO-263 Center Cut JC = 3C/W* * JA can vary from 20C/W to >40C/W with various mounting techniques.
Absolute Maximum Ratings
Parameter VIN Operating Junction Temperature Range Storage Temperature Range Lead Temperature (Soldering, 10 sec.) 0 -65 Min. Max. 7 125 150 300 Unit V C C C
2
PRODUCT SPECIFICATION
RC1587
Electrical Characteristics
Tj = 25C unless otherwise specified. The * denotes specifications which apply over the specified operating temperature range. Parameter Reference Voltage Output Voltage4 Output Voltage5 Line Regulation1, 2 Load Regulation1, 2 Dropout Voltage Current Limit Adjust Pin Current3 Adjust Pin Current Change3 1.5V (VIN - VOUT) 5.75V, 10mA IOUT 3A 1.5V (VIN - VOUT) 5.75V VIN = 5V f = 120Hz, COUT = 22F Tantalum, (VIN - VOUT) = 3V, IOUT = 3A TA = 25C, 30ms pulse * TA = 125C, 1000 hrs. TA = 25C, 10Hz f 10kHz TO-220 TO-263
3
Conditions 1.5V (VIN - VOUT) 5.75V, 10mA IOUT 3A 3.3V VIN 7V 10mA IOUT 3A 5.1V VIN 7V 10mA IOUT 3A (VOUT + 1.5V) VIN 7V, IOUT = 10mA (VIN - VOUT) = 3V 10mA IOUT 3A VREF = 1%, IOUT = 3A (VIN - VOUT) = 2V * * * * * * * * * * *
Min. 1.225 (-2%) 1.47 3.234
Typ. 1.250 1.5 3.3 0.005 0.05 1.150
Max 1.275 (+2%) 1.53 3.366 0.2 0.5 1.300 120 5
Units V V V % % V A A A mA
3.1
4 35 0.2
Minimum Load Current Quiescent Current Ripple Rejection Thermal Regulation Temperature Stability Long-Term Stability RMS Output Noise (% of VOUT) Thermal Resistance, Junction to Case Thermal Shutdown
10 4 60 72 0.004 0.5 0.03 0.003 3 3 150 1.0 0.02 13
mA dB %/W % % % C/W C/W C
Notes: 1. See thermal regulation specifications for changes in output voltage due to heating effects. Load and line regulation are measured at a constant junction temperature by low duty cycle pulse testing. 2. Line and load regulation are guaranteed up to the maximum power dissipation (18W). Power dissipation is determined by input/output differential and the output currrent. Guaranteed maximum output power will not be available over the full input/ output voltage range. 3. RC1587 only. 4. RC1587-1.5 only. 5. RC1587-3.3 only.
3
RC1587
PRODUCT SPECIFICATION
Typical Performance Characteristics
1.5
OUTPUT VOLTAGE DEVIATION (%) 0.10 I = 3A
1.4 DROPOUT VOLTAGE (V) 1.3 1.2 1.1 1.0 0.9 T=25C 0.8
65-1587-03
0.05
0
T=0C T=125C
-0.05
-0.10
65-1587-04
0.7 0.6 0.5 0 0.5 1 1.5 2 2.5 OUTPUT CURRENT (A)
-0.15
3.0
-0.20 -75 -50 -25
0
25 50 75 100 125 150 175
JUNCTION TEMPERATURE (C)
Figure 1. Dropout Voltage vs. Output Current
Figure 2. Load Regulation vs. Temperature
1.275 1.270 REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
3.70 3.65 3.60 3.55 3.50 3.45 3.40 3.35 3.30 3.25 3.20 -75 -50 -25 0
Note: 1. RC1587 Only 2. RC1587, -3.3
VOUT SET WITH 1% RESISTORS VOUT = 3.6V1
1.265 1.260 1.255 1.250 1.245 1.240
65-1587-05
VOUT = 3.3V2
1.230 1.225 -75 -50 -25 0
25 50 75 100 125 150 175
25 50 75 100 125 150 175
JUNCTION TEMPERATURE (C)
JUNCTION TEMPERATURE (C)
Figure 3. Reference Voltage vs. Temperature
Figure 4. Output Voltage vs. Temperature
5 MINIMUM LOAD CURRENT (mA)
100 90
Note: 1. RC1587 Only
4
ADJUST PIN CURRENT (A)
80 70 60 50 40 30
65-1587-08
3
2
65-1587-07
1
20 10 0 -75 -50 -25 0
0 -75 -50 -25
0
25 50 75 100 125 150 175
25 50 75 100 125 150 175
JUNCTION TEMPERATURE (C)
JUNCTION TEMPERATURE (C)
Figure 5. Minimum Load Current vs. Temperature
Figure 6. Adjust Pin Current vs. Temperature
4
65-1587-06
1.235
PRODUCT SPECIFICATION
RC1587
Typical Performance Characteristics (continued)
5.0 SHORT-CIRCUIT CURRENT (A)
90 80 RIPPLE REJECTIONS (dB)
4.5
70 60 50 40 30 20 10 0 10
65-1587-10
4.0
3.5
65-1587-09
(VIN - VOUT) 3V 0.5V VRIPPLE 2V IOUT = 3A 100 1K FREQUENCY (Hz) 10K
3.0 -75 -50 -25
0
25 50 75 100 125 150 175
100K
JUNCTION TEMPERATURE (C)
Figure 7. Short-Circuit Current vs. Temperature
Figure 8. Ripple Rejection vs. Frequency
20 15
POWER (W)
10 5
65-1587-11
0 50 60 70 80 90 100 110 120 130 140 150 CASE TEMPERATURE (C)
Figure 9. Maximum Power Dissipation
5
RC1587
PRODUCT SPECIFICATION
Applications Information
General
The RC1587, RC1587-1.5, and RC1587-3.3 are three-terminal regulators optimized for GTL+ VTT termination applications. These devices are short-circuit protected, and offer thermal shutdown to turn off the regulator when the junction temperature exceeds about 150C. The RC1587 series provides low dropout voltage and fast transient response. Frequency compensation uses capacitors with low ESR while still maintaining stability. This is critical in addressing the needs of low voltage high speed microprocessor buses like GTL+.
D1 1N4002 (OPTIONAL)
RC1587 VIN C1 10F + IN ADJ + CADJ R2 OUT R1 + VOUT C2 22F
Stability
The RC1587 series require an output capacitor as a part of the frequency compensation. It is recommended to use a 22F solid tantalum or a 100F aluminum electrolytic on the output to ensure stability. The frequency compensation of these devices optimizes the frequency response with low ESR capacitors. In general, it is suggested to use capacitors with an ESR of <1. It is also recommended to use bypass capacitors such as a 22F tantalum or a 100F aluminum on the adjust pin of the RC1587 for low ripple and fast transient response. When these bypassing capacitors are not used at the adjust pin, larger values of output capacitors provide equally good results.
D1 1N4002 (OPTIONAL)
RC1587-1.5, -3.3 VIN C1 10F + IN GND OUT + VOUT C2 22F
65-1587-13
Figure 10. Optional Protection
Protection Diodes
In normal operation, the RC1587 series does not require any protection diodes. For the RC1587, internal resistors limit internal current paths on the adjust pin. Therefore, even with bypass capacitors on the adjust pin, no protection diode is needed to ensure device safety under shortcircuit conditions. A protection diode between the input and output pins is usually not needed. An internal diode between the input and output pins on the RC1587 series can handle microsecond surge currents of 50A to 100A. Even with large value output capacitors it is difficult to obtain those values of surge currents in normal operation. Only with large values of output capacitance, such as 1000F to 5000F, and with the input pin instantaneously shorted to ground can damage occur. A crowbar circuit at the input can generate those levels of current; a diode from output to input is then recommended, as shown in Figure 10. Usually, normal power supply cycling or system "hot plugging and unplugging" will not generate current large enough to do any damage. The adjust pin can be driven on a transient basis 7V with respect to the output, without any device degradation. As with any IC regulator, exceeding the maximum input-tooutput voltage differential causes the internal transistors to break down and none of the protection circuitry is then functional.
Ripple Rejection
In applications that require improved ripple rejection, a bypass capacitor from the adjust pin of the RC1587 to ground reduces the output ripple by the ratio of VOUT/1.25V. The impedance of the adjust pin capacitor at the ripple frequency should be less than the value of R1 (typically in the range of 100 to 120) in the feedback divider network in Figure 10. Therefore, the value of the required adjust pin capacitor is a function of the input ripple frequency. For example, if R1 equals 100 and the ripple frequency equals 120Hz, the adjust pin capacitor should be 22F. At 10kHz, only 0.22F is needed.
Output Voltage
The RC1587 regulator develops a 1.25V reference voltage between the output pin and the adjust pin (see Figure 11). Placing a resistor R1 between these two terminals causes a constant current to flow through R1 and down through R2 to set the overall output voltage. Normally, this current is the specified minimum load current of 10mA. The current out of the adjust pin adds to the current from R1 and is typically 35A. Its output voltage contribution is small and only needs consideration when very precise output voltage setting is required.
6
PRODUCT SPECIFICATION
RC1587
RC1587 VIN + IN C1 10F ADJ IADJ 35A VOUT = VREF (1 + R2/R1) + IADJ (R2) OUT VREF R1 + VOUT C2 22F RC1587 VIN IN ADJ OUT
RP PARASITIC LINE RESISTANCE
R2
65-1587-14
R1* RL * CONNECT R1 TO CASE CONNECT R2 TO LOAD R2*
Figure 11. Basic Regulator Circuit
Load Regulation
It is not possible to provide true remote load sensing because the RC1587 series are three-terminal devices. Load regulation is limited by the resistance of the wire connecting the regulators to the load. Load regulation per the data sheet specification is measured at the bottom of the package. For fixed voltage devices, negative side sensing is a true Kelvin connection with the ground pin of the device returned to the negative side of the load. This is illustrated in Figure 12.
RC1587-1.5, -3.3 VIN IN GND OUT RL RP PARASITIC LINE RESISTANCE
65-1587-15
Figure 13. Connection for Best Load Regulation
Thermal Considerations
The RC1587 series protect themselves under overload conditions with internal power and thermal limiting circuitry. However, for normal continuous load conditions, do not exceed maximum junction temperature ratings. It is important to consider all sources of thermal resistance from junction-to-ambient. These sources include the junction-to-case resistance, the case-to-heat sink interface resistance, and the heat sink resistance. Thermal resistance specifications have been developed to more accurately reflect device temperature and ensure safe operating temperatures. For example, look at using an RC1587T to generate 3A @ 1.5V 2% from a 3.3V source (3.2V to 3.6V). Assumptions: * * * * * VIN = 3.6V worst case VOUT = 1.46V worst case IOUT = 3A continuous TA = 70C Case-to-Ambient = 3C/W (assuming both a heatsink and a thermally conductive material) The power dissipation in this application is: PD = (VIN - VOUT) * (IOUT) = (3.6 - 1.46) * (3) = 6.42W From the specification table: TJ = TA + (PD) * (Case-to-Ambient + JC) = 70 + (6.42) * (3 + 3) = 109C The junction temperature is below the maximum rating.
65-1587-17
Figure 12. Connection for Best Load Regulation
For adjustable voltage devices, negative side sensing is a true Kelvin connection with the bottom of the output divider returned to the negative side of the load. The best load regulation is obtained when the top of resistor divider R1 connects directly to the regulator output and not to the load. Figure 13 illustrates this point. If R1 connects to the load, then the effective resistance between the regulator and the load would be: RP x (1 + R2/R1), RP = Parasitic Line Resistance The connection shown in Figure 13 does not multiply RP by the divider ratio. As an example, RP is about four milliohms per foot with 16-gauge wire. This translates to 4mV per foot at 1A load current. At higher load currents, this drop represents a significant percentage of the overall regulation. It is important to keep the positive lead between the regulator and the load as short as possible and to use large wire or PC board traces.
7
RC1587
PRODUCT SPECIFICATION
Junction-to-case thermal resistance is specified from the IC junction to the bottom of the case directly below the die. This is the lowest resistance path for heat flow. Proper mounting ensures the best thermal flow from this area of the package to the heat sink. Use of a thermally conductive material at the
case-to-heat sink interface is recommended. Use a thermally conductive spacer if the case of the device must be electrically isolated and include its contribution to the total thermal resistance. The cases of the RC1587 series are directly connected to the output of the device.
VIN 3.3V C1 10F
U1 RC1587 VIN + ADJ + C2 100F VOUT R1 124 R2 24.9 +
VOUT 1.5V C3 100F
65-1587-18
Figure 14. Application Circuit (RC1587)
Table 1. Bill of Materials for Application Circuit for the RC1587
Item C1 C2, C3 R1 R2 U1 Quantity 1 2 1 1 1 Manufacturer Xicon Xicon Generic Generic Fairchild RC1587T Part Number L10V10 L10V100 Description 10F, 10V Aluminum 100F, 10V Aluminum 124, 1% 24.9, 1% 3A Regulator
VIN 3.3V C1 10F
U1 RC1587-1.5 VIN + VOUT GND +
VOUT 1.5V C3 100F
65-1587-19
Figure 15. Application Circuit (RC1587-1.5)
Table 2. Bill of Materials for Application Circuit for the RC1587-1.5
Item C1 C3 U1 Quantity 1 1 1 Manufacturer Xicon Xicon Fairchild Part Number L10V10 L10V100 RC1587T-1.5 Description 10F, 10V Aluminum 100F, 10V Aluminum 3A Regulator
8
PRODUCT SPECIFICATION
RC1587
VIN 3.3V C1 10F
U1 RC1587-3.3 VIN + VOUT GND +
VOUT 3.3V C3 100F
65-1587-20
Figure 16. Application Circuit (RC1587-3.3)
Table 3. Bill of Materials for Application Circuit for the RC1587-1.5
Item C1 C3 U1 Quantity 1 1 1 Manufacturer Xicon Xicon Fairchild Part Number L10V10 L10V100 RC1587T-3.3 Description 10F, 10V Aluminum 100F, 10V Aluminum 3A Regulator
9
RC1587
PRODUCT SPECIFICATION
Notes
10
PRODUCT SPECIFICATION
RC1587
Mechanical Dimensions
3-Lead TO-263 Package
Inches Min. A b b2 c2 D E e L L1 L2 R .160 .020 Max. .190 .039 Millimeters Min. 4.06 0.51 Max. 4.83 0.99 Notes: 1. Dimensions are exclusive of mold flash and metal burrs. 2. Standoff-height is measured from lead tip with ref. to Datum -B-. 3. Foot length is measured with ref. to Datum -A- with lead surface (at inner R). 4. Dimensiuon exclusive of dambar protrusion or intrusion. 5. Formed leads to be planar with respect to one another at seating place -C-.
Symbol
Notes
.049 .051 .045 .055 .340 .380 .380 .405 .100 BSC .575 .090 -- .017 0 .625 .110 .055 .019 8
1.25 1.30 1.14 1.40 8.64 9.65 9.65 10.29 2.54 BSC 14.61 2.29 -- 0.43 0 15.88 2.79 1.40 0.78 8
E @PKG/ @HEATSINK
L2 c2
D L b2 E-PIN R (2 PLCS) L1 b e
-B-
-A-
A -C-
11
RC1587
PRODUCT SPECIFICATION
Mechanical Dimensions (continued)
3-Lead TO-263 Center Cut Package
Inches Min. A b b2 c2 D E e L L1 L2 R .160 .020 Max. .190 .039 Millimeters Min. 4.06 0.51 Max. 4.83 0.99 Notes: 1. Dimensions are exclusive of mold flash and metal burrs. 2. Standoff-height is measured from lead tip with ref. to Datum -B-. 3. Foot length is measured with ref. to Datum -A- with lead surface (at inner R). 4. Dimensiuon exclusive of dambar protrusion or intrusion. 5. Formed leads to be planar with respect to one another at seating place -C-.
Symbol
Notes
.049 .051 .045 .055 .340 .380 .380 .405 .100 BSC .575 .090 -- .017 0 .625 .110 .055 .019 8
1.25 1.30 1.14 1.40 8.64 9.65 9.65 10.29 2.54 BSC 14.61 2.29 -- 0.43 0 15.88 2.79 1.40 0.78 8
E @PKG/ @HEATSINK
L2 c2
D L b2 E-PIN R (2 PLCS) L1 b e
-B-
-A-
A -C-
12
PRODUCT SPECIFICATION
RC1587
Mechanical Dimensions (continued)
3-Lead TO-220 Package
Inches Min. A b b1 c1 oP D E e e1 e3 F H1 J1 L L1 Q Max. Millimeters Min. Max.
Symbol
Notes
.140 .190 .015 .040 .045 .070 .014 .022 .139 .161 .560 .650 .380 .420 .090 .110 .190 .210 .045 -- .020 .055 .230 .270 .080 .115 .500 .580 .250 BSC .100 .135 3 7
3.56 4.83 .38 1.02 1.14 1.78 .36 .56 3.53 4.09 14.22 16.51 9.65 10.67 2.29 2.79 4.83 5.33 1.14 -- .51 1.40 5.94 6.87 2.04 2.92 12.70 14.73 6.35 BSC 2.54 3.43 3 7
Notes: 1. Dimension c1 apply for lead finish.
H1 L e3 e e1 E b1 Q
b L1 E-PIN oP
(5X) c1 J1 D A F
13
RC1587
PRODUCT SPECIFICATION
Ordering Information
Product Number RC1587M RC1587MC RC1587T RC1587M-1.5 RC1587MC-1.5 RC1587T-1.5 RC1587M-3.3 RC1587MC-3.3 RC1587T-3.3 Package TO-263 TO-263 center cut TO-220 TO-263 TO-263 center cut TO-220 TO-263 TO-263 center cut TO-220
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 8/20/99 0.0m 001 Stock#DS30001587 (c) 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC1616
0.5A Adjustable/Fixed Low Dropout Linear Regulator
Features
* * * * * * Low dropout voltage Load regulation: 0.05% typical Current limit On-chip thermal limiting Standard SOT-223 and TO-263 packages Three-terminal adjustable or fixed 2.5V, 3.3V or 5V
Description
The RC1616 and RC1616-2.5, -3.3 and -5 are low dropout three-terminal regulators with 0.5A output current capability. These devices have been optimized for low voltage where transient response and minimum input voltage are critical. The 5V version is designed also to be used in USB Hub and Motherboard applications. On-chip thermal limiting provides protection against any combination of overload and ambient temperature that would create excessive junction temperatures. Unlike PNP type regulators where up to 10% of the output current is wasted as quiescent current, the bias current of the RC1616 flows into the load, increasing efficiency. The RC1616 series regulators are available in the industrystandard SOT-223 and TO-263 power packages.
Applications
* USB Controlled Power Supply * High efficiency linear regulators for Mixed Voltage Logic, ASIC, FPGA based systems * Post regulators for switching supplies * Battery chargers * 5V to 3.3V, or 2.5V, 1.8V, 1.5V linear regulators * Motherboard clock supplies * SDRAM Module supplies
Typical Applications
RC1616 VIN = 3.3V 10F ADJ 124 + VIN VOUT + 22F 1.5V at 0.5A
24.9
RC1616-3.3 VIN = 5V 10F GND + VIN VOUT + 22F 3.3V at 0.5A
Rev. 1.0.4
PRODUCT SPECIFICATION
RC1616
Pin Assignments
RC1616S (Variable) RC1616S-X (Fixed) Front View 3 Tab is VOUT 2 1 IN OUT ADJ/GND RC1616S (Variable) RC1616S-X (Fixed) Front View
4-Lead Plastic SOT-223 JC = 15C/W*
1
2
3
ADJ/ GND
OUT
IN
3-Lead Plastic TO-263 JC = 10C/W*
*With package soldered to 0.5 square inch copper area over backside ground plane or internal power plane, JA can vary from 30C/W to >50C/W. Other mounting techniques may provide better power dissipation than 30C/W.
Absolute Maximum Ratings
Parameter VIN Operating Junction Temperature Range Storage Temperature Range Lead Temperature (Soldering, 10 sec.) 0 -65 Min. Max. 7.5 125 150 300 Unit V C C C
2
RC1616
PRODUCT SPECIFICATION
Electrical Characteristics
Operating Conditions: VIN 7V, TJ = 25C unless otherwise specified. The * denotes specifications which apply over the specified operating temperature range. Parameter Reference Voltage3 Conditions 1.5V (VIN - VOUT) 5.75V, 10mA IOUT 0.5A 10mA IOUT 0.5A RC1616-2.5, 4.0V VIN 7V RC1616-3.3, 4.5V VIN 7V RC1616-5, 6.2V VIN 7V (VOUT + 1.5V) VIN 7V, IOUT = 10mA (VIN - VOUT) = 2V, 10mA IOUT 0.5A VREF = 1%, IOUT = 0.5A 1.5V (VIN - VOUT) 5.75, 10mA IOUT 0.5A 1.5V (VIN - VOUT) 5.75 VIN = VOUT + 1.25V f = 120Hz, COUT = 22F Tantalum, (VIN - VOUT) = 3V, IOUT = 0.5A TA = 25C, 30ms pulse * TA = 125C, 1000hrs. TA = 25C, 10Hz f 10kHz SOT-223 TO-263 * Min. 1.225 (-2%) 2.450 3.234 4.900 Typ. 1.250 Max. 1.275 (+2%) 2.550 3.366 5.100 0.2 0.5 1.200 120 5 Units V
Output Voltage
* * * * * * * * * *
2.500 3.300 5.000 0.005 0.05 1.000 35 0.2
V V V % % V A A mA
Line Regulation1,2 Load Regulation1,2,3 Current3 Dropout Voltage Adjust Pin Adjust Pin Current Change3 Minimum Load Current Quiescent Current Ripple Rejection Thermal Regulation Temperature Stability Long-Term Stability RMS Output Noise (% of VOUT) Thermal Resistance, Juncation to Case Thermal Shutdown
10 4 60 72 0.004 0.5 0.03 0.003 15 10 150 1.0 0.02 13
mA dB %/W % % % C/W C/W C
Notes: 1. See thermal regulation specifications for changes in output voltage due to heating effects. Load and line regulation are measured at a constant junction temperature by low duty cycle pulse testing. 2. Line and load regulation are guaranteed up to the maximum power dissipation. Power dissipation is determined by input/ output differential and the output current. Guaranteed maximum output power will not be available over the full input/output voltage range. 3. RC1616 only.
3
PRODUCT SPECIFICATION
RC1616
Typical Performance Characteristics
OUTPUT VOLTAGE DEVIATION (%) 1.5 1.4 DROPOUT VOLTAGE (V) 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0 0 0.2 0.4 0.6 0.8 1.0 TJ = 0C TJ = 25C TJ = 125C 0.10 0.05 0 -0.05 -0.10 -0.15 -0.20 -75 -50 -25 0 I = 0.5A
25 50 75 100 125 150 175
OUTPUT CURRENT (A)
JUNCTION TEMPERATURE (C)
Figure 1. Dropout Voltage vs. Output Current
1.250 1.245 REFERENCE VOLTAGE (V) 1.240 1.235 1.230 1.225 1.220 1.215 1.210 1.205 1.200 -75 -50 -25 0 25 50 75 100 125 150 175
Figure 2. Load Regulation vs. Temperature
3.70 3.65 REFERENCE VOLTAGE (V) 3.60 3.55 3.50 3.45 3.40 3.35 3.30 3.25 Note: 1. RC1616 Only 3.20 -75 -50 -25 0 25 50 75 100 125 150 175 JUNCTION TEMPERATURE (C) VOUT = 3.3V
VOUT SET WITH 1% RESISTORS VOUT = 3.6V1
JUNCTION TEMPERATURE (C)
Figure 3. Reference Voltage vs. Temperature
5 MINIMUM LOAD CURRENT (mA)
Figure 4. Output Voltage vs. Temperature
100 90 ADJUST PIN CURRENT (A) Note: 1. RC1616 Only
4
80 70 60 50 40 30 20 10
3
2
1
0 -75 -50 -25 0
25 50 75 100 125 150 175
0 -75 -50 -25 0
25 50 75 100 125 150 175
JUNCTION TEMPERATURE (C)
JUNCTION TEMPERATURE (C)
Figure 5. Minimum Load Current vs. Temperature
Figure 6. Adjust Pin Current vs. Temperature
4
RC1616
PRODUCT SPECIFICATION
Typical Performance Characteristics (continued)
1.50 SHORT-CIRCUIT CURRENT (A) 90 80 RIPPLE REJECTION (dB) 1.25 70 60 50 40 30 20 10 0.50 -75 -50 -25 0 25 50 75 100 125 150 175 0 10 (VIN - VOUT) 3V 0.5 VRIPPLE 2V IOUT = 0.5A 100 1K 10K 100K
1.00
0.75
TEMPERATURE (C)
FREQUENCY (Hz)
Figure 7. Short-Circuit Current vs. Temperature
Figure 8. Ripple Rejection vs. Frequency
4 TO-263 3 POWER (W)
2 SOT-223 1
0 50
60 70 80 90 100 110 120 130 140 150 CASE TEMPERATURE (C)
Figure 9. Maximum Power Dissipation
5
PRODUCT SPECIFICATION
RC1616
Mechanical Dimensions
3-Lead TO-263 Package
Symbol A b b2 c2 D E e L L1 L2 R Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. Dimensions are exclusive of mold flash and metal burrs. 2. Standoff-height is measured from lead tip with ref. to Datum -B-. 3. Foot length is measured with ref. to Datum -A- with lead surface (at inner R). 4. Dimension exclusive of dambar protrusion or intrusion. 5. Formed leads to be planar with respect to one another at seating place -C-.
.160 .190 .020 .039 .049 .051 .045 .055 .340 .380 .380 .405 .100 BSC .575 .625 .090 .100 -- .055 .017 .019 0 8
4.06 4.83 0.51 0.99 1.25 1.30 1.14 1.40 8.64 9.65 9.65 10.29 2.54 BSC 14.61 10.88 2.29 2.79 -- 1.40 0.43 0.48 0 8
E @PKG/ @HEATSINK
L2 c2
D L b2 E-PIN R (2 PLCS) L1 b e
-B-
-A-
A -C-
6
RC1616
PRODUCT SPECIFICATION
Mechanical Dimensions
4-Lead SOT-223 Package
Inches Min. A A1 B c D E e F H I J K L M N -- -- .025 -- .248 .130 .115 .033 .264 .012 -- 10 .0008 10 .010 Max. .071 .181 .033 .090 .264 .148 .124 .041 .287 -- 10 16 .0040 16 .014 Millimeters Min. -- -- .640 -- 6.30 3.30 2.95 .840 6.71 .310 -- 10 .0203 10 .250 Max. 1.80 4.80 .840 2.29 6.71 3.71 3.15 1.04 7.29 -- 10 16 .1018 16 .360
Symbol
Notes
D e K
A H E B A1 c F J M I L N
7
PRODUCT SPECIFICATION
RC1616
Ordering Information
Product Number RC1616M RC1616S RC1616M-2.5 RC1616S-2.5 RC1616M-3.3 RC1616S-3.3 RC1616M-5 RC1616S-5 Package TO-263 SOT-223 TO-263 SOT-223 TO-263 SOT-223 TO-263 SOT-223
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. www.fairchildsemi.com
6/16/99 0.0m 003 Stock#DS30001616 (c) 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC2207
Voltage Controlled Oscillator
Features
* * * * * * * * * * Excellent temperature stability -- 20 ppm/C Linear frequency sweep Adjustable duty cycle -- 0.1% to 99.9% Two or four level FSK capability Wide sweep range -- 1000:1 min. Logic compatible input and output levels Wide supply voltage range -- 4V to 13V Low supply sensitivity 0.15%/V Wide frequency range -- 0.01 Hz to 1 MHz Simultaneous triangle and squarewave outputs
Description
The RC2207 is a monolithic voltage-controlled oscillator (VCO) integrated circuit featuring excellent frequency stability and a wide tuning range. The circuit provides simultaneous triangle and squarewave outputs over a frequency range of 0.01 Hz to 1 MHz. It is ideally suited for FM, FSK and sweep or tone generation as well as for phase-locked loop applications. As shown in the Block Diagram, the circuit is comprised of four functional blocks: a variable-frequency oscillator which generates the basic periodic waveforms; four current switches actuated by binary keying inputs; and buffer amplifiers for both the triangle and squarewave outputs. The internal switches transfer the oscillator current to any of four external timing resistors to produce four discrete frequencies which are selected according to the binary logic levels at the keying terminals (pins 8 and 9). The RC2207 has a typical drift specification of 20 ppm/C. The oscillator frequency can be linearly swept over a 1000:1 range with an external control voltage; and the duty cycle of both the triangle and the squarewave outputs can be varied from 0.1% to 99.9% to generate stable pulse and sawtooth waveforms.
Applications
FSK generation Voltage and current-to-frequency conversion Stable phase-locked loop Waveform generation triangle, sawtooth, pulse, squarewave * FM and sweep generation * * * *
Block Diagram
A1 TIMING CAPACITOR VCO A2 -VS TRIANGLE WAVE OUTPUT SQUARE WAVE OUTPUT
TIMING RESISTORS R1-R4
CURRENT SWITCH
BINARY KEY INPUTS
65-2207-01
Rev. 1.0.0
RC2207
PRODUCT SPECIFICATION
Pin Assignments
+VS Timing Capacitor R1 Timing Resistors R2 R3 R4 1 2 3 4 5 6 7 14 13 12 11 10 9 8
65-2207-02
Trianglewave Output Squarewave Output +VS Bias GND Binary Keying Inputs
Pin Descriptions
Pin Name Bias for Single Supply Binary Keying Inputs Ground Pin Number 11 Pin Function Description For single supply operations, pin 11 should be externally biased to a potential between +VS/3 and +VS/2 (see Figure 8). The bias current at pin 11 is nominally 5% of the total oscillation timing current IT. The internal impedance at these pins is approximately 5 kW. Keying levels are <1.4V for zero and > 3V for one logic levels referenced to the DC voltage at pin 10. For split supply operation, this pin serves as circuit ground. For single supply operation, pin 10 should be AC grounded through a 1 mF bypass capacitor. During split supply operation, a ground current of 2 IT flows out of this terminal, where IT is the total timing current. The squarewave output at pin 13 is an open-collector stage capable of sinking up to 20 mA of load current. RL serves as a pull-up load resistor for this output. Recommended values for RL range from 1 kW to 10 kW The RC2207 is designed to operate over a power supply range of +4V to 13V for split supplies, or 8V to 26V for single supplies. At high supply voltages, the frequency sweep range is reduced. Performance is optimum for 6V, or 12V single supply operation. The oscillator frequency is inversely proportional to the timing capacitor, C. The minimum capacitance value is limited by stray capacitances and the maximum value by physical size and leakage current considerations. Recommended values range from 100 pF to 100 mF. The capacitor should be non-polarized. The timing resistors determine the total timing current, IT, available to charge the timing capacitor. Values for timing resistors can range from 1.5 kW to 2 MW; however, for optimum temperature and power supply stability, recommended values are 4 kW to 200 kW. To avoid parasitic pick up, timing resistor leads should be kept as short as possible. For noise environments, unused or deactivated timing terminals should be bypassed to ground through 0.1 mF capacitors. Otherwise, they may be left open. The output at pin 14 is a trianglewave with a peak swing of approximately one-half of the total supply voltage. Pin 14 has a very low output impedance of 10W and is internally protected against short circuits. Notice that the triangle waveform linearity is sensitive to parasite coupling between the square and the trianglewave outputs (pins 13 and 14). In board layout or circuit wiring, care should be taken to minimize stray wiring capacitance between those pins.
8, 9
10
Squarewave Output Supply Voltage (+VS, -VS)
13
1, 12
Timing Capacitor
2, 3
Timing Resistors (R1-R4)
4-7
Trianglewave Output
14
2
PRODUCT SPECIFICATION
RC2207
Absolute Maximum Ratings
Parameter Supply Voltage Storage Temperature Range Operating Temperature Range Lead Soldering Temperature (60 seconds) -65 -55 Min. Max. +26 +150 +125 +300 Units V V C C
Thermal Characteristics
Ceramic DIP Maximum Juncton Temperature Maximum PD TA < 50C Thermal Resistance, qJC Thermal Resistance, qJA For TA > 50C Derate at +175C 1042 mW 60C/W 120C/W 8.33 mW/C SOIC +125C 300 mW 60C/W 200C/W 5.0 mW/C Plastic DIP +125C 468 mW 60C/W 160C/W 6.25 mW/C
3
RC2207
PRODUCT SPECIFICATION
(Test Circuit of Figure 1, VS = 6V, TA = +25C, C = 5000 pF, R1= R2 = R3 = R4 = 20 kW, RL = 4.7W binary inputs grounded, S1 and S2 closed unless otherwise specified) Parameters General Characteristics Supply Voltage Single Supply Split Supplies Supply Current Single Supply Split Supplies Positive Negative Binary Keying Inputs Switching Threshold Input Resistance Oscillator Section--Frequency Characteristics Upper Frequency Limit Lower Practical Frequency Frequency Accuracy Frequency Matching Frequency Stability Sweep Range Sweep Linearity 10:1 FM Distortion Recommended Range of Timing Resistors Impedance at Timing Pins DC Level at Timing Terminals Output Characteristics Triangle output Amplitude Impedance DC Level Linearity Squarewave Output Amplitude Saturation Voltage Rise Time Fall Time
Note: 1. Guaranteed by design.
Electrical Characteristics
Test Conditions See Typical Performance Characteristics Measured at pin 1, S1 open (See Fig. 8) Measured at pin 1, S1 open (See Fig. 7) Measured at pin 12, S1, S2 open RC2207 RM2207 RC2207 RM2207
Min. +8.0 4
Typ. +12 6 5.0 5.0
Max. +26 13 7.0 7.0 8.0 7.0
Units V V mA mA mA
4.0 1.4 2.2 5.0
6.0 2.8 V kW MHz Hz 3.0 % of f0 % of f0 50 ppm/C %/V fH/fL
Measured at pins 8 and 9. Refer to pin 10.
C = 500 pF, R3 = 2 kW C = 50 mF, R3 = 2 kW
0.5
1.0 0.01 1.0 0.5 20 0.15
vs. Temperature (Note 1) 0C < TA < +70C vs. Supply Voltage R3 = 1.5 kW for fH R3 = 2 MW for fL C = 5000 pF Sweep1 fH = 10 kHz, fL = 1 kHz fH = 100 kHz, fL = 100 Hz 10% FM Deviation See Characteristic Curves Measured at pins 4, 5, 6, or 7 1.5
1000:1 3000:1
1.0 5.0 0.1
2.0
% % %
1000:1 Sweep
2000 75 10
kW W mV VP-P W mV % VP-P
Measured at pin 14 Referenced to pin 10 from 10% to 90% of swing Measured at pin 13, S2 Closed Referenced to pin 12 CL 10 pF CL 10 pF
4
6 10 +100 0.1
11
12 0.2 200 20 0.4
V ns ns
4
PRODUCT SPECIFICATION
RC2207
Typical Performance Characteristics
+25 +20 Positive Supply (V) +15 +10 +5 0
65-2207-03
,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,,
Typical Operating Range 0 -5 -10 Negative Supply (V) -15
7 6 5 4 3 2 1 0 -1 -2 -3 -4 -5 -6 -7 1K
Frequency Accuracy (% Error)
VS = +6V C = 5000 pF
-20
10K
100K Timing Resistance (W)
1M
10M
Figure 1. Typical Operating Range for Split Supply Voltage
Figure 2. Frequency Accuracy vs. Timing Resistance
10M Total Timing Resistor (W)
1M
100K
10K
1K 0
,,,,,,,, ,,,,,,,, ,,,,,,,, ,,,,,,,, ,,,,,,,, ,,,,,,,, ,,,,,,,, ,,,,,,,, ,,,,,,,, ,,,,,,,,
Timing Resistor Range 4 8 12 Split Supply Voltage (V) 0 8 16 24 Single Supply Voltage (V)
1.04 Normalized Frequency Drift RT = 2 MW 1.02 1.00 0.98 0.96 0.94 0.92 2 4 6 8
65-2207-06
TA = +25C
RT = 20 kW RT = 200 kW
65-2207-05
TA = +20C RT = Total Timing Resistance C = 5000 pF
RT = 2 kW 10 12
16
14
Split Supply Voltage (V) 32 4 8 12 14 18 Single Supply Voltage (V) 20 22
1R = Parallel Combination of Activated Timing Resistors T
Figure 3. Recommended Timing Resistor Value vs. Power Supply Voltage
Figure 4. Normalized Frequency Drift vs. Supply Voltage
+2 Normalized Frequency Drift (%) +1 0 VS = +6V C = 5000 pF 2 MWY 200 kW
65-2207-07
-3 -75
-50
-25
0
+25
+50
+75
+100 +125
Temperature (C)
Figure 5. Pulse and Sawtooth Outputs
Figure 6. Normalized Frequency Drift vs. Temperature
65-2207-08
4 kWY 2 kWY 20 kWY -1 200 kWY Y 2 MW -2
2 kWY 4 kW R = 2 kW
65-2207-04
5
RC2207
PRODUCT SPECIFICATION
Applications Information
Precautions
The following precautions should be observed when operating the RC2207 family of integrated circuits: * Pulling excessive current from the timing terminals will adversely affect the temperature stability of the circuit. To minimize this disturbance, it is recommended that the total current drawn from pins 4, 5, 6 and 7 be limited to <6 mA. In addition, permanent damage to the device may occur if the total timing current exceeds 10 mA. * Terminals 2, 3, 4, 5, 6 and 7 have very low internal impedance and should, therefore, be protected from accidental shorting to ground or the supply voltages. * The keying logic pulse amplitude should not exceed the supply voltage.
Table 1. Logic Table for Binary Keying Controls
Logic Level 8 0 0 1 9 6 1 0 Selected Timing Pins Frequency f1 6&7 5 f1 = 1/R3C f1 + Df1 f2
Definitions Df1 = 1/R4C f2 = 1/R2C, Df2 = 1/R1C Logic levels: 0 = Ground
14 &5
f2 + fD2 Logic levels: 1 = 3V
Note: 1. For single supply operation, logic levels are referenced to voltage at pin 10.
Split Supply Operation
Figure 7 is the recommended circuit connection for split supply operation. The frequency of operation is determined by the timing capacitor (C) and the activated timing resistors (R1 through R4). The timing resistors are activated by the logic signals at the binary keying inputs (pins 8 and 9), as shown in Table 1. If a single timing resistor activated, the frequency is 1/RC. Otherwise, the frequency is either 1/(R1| |R2)C or 1/(R1| |R4)C.
The squarewave output is obtained at pin 13 and has a peak-to-peak voltage swing equal to the supply voltages. This output is an open-collector type and requires an external pull-up load resistor (nominally 5 kW) to the positive supply. The triangle waveform obtained at pin 14 is centered about ground and has a peak amplitude of +VS/2. The circuit operates with supply voltages ranging from 4V to it 13V. Minimum drift occurs with 6V supplies.
Single Supply Operation
The circuit should be interconnected as shown in Figure 8 for single supply operation. Pin 12 should be grounded, and pin 11 biased from +VS through a resistive divider to a value of bias voltage between +VS/3 and +VS/2. Pin 10 is bypassed to ground through a 0.1mF capacitor.
0.1 F +VS Binary Keying Inputs 9 10 11 0.1 F 12 IS-VS S1 6 R3 RC2207 Device Under Test 7 R4 4 5 R1 R2 8 1 IS+ 2 C S2 +VS 3 13 14 RL Squarewave Output Trianglewave Output
65-2207-09
Note: This circuit is for Bench Tests only. DC testing is normally performed with automated test equipment using an equivalent circuit.
Figure 7. Test Circuit for Split Supply Operation
6
PRODUCT SPECIFICATION
RC2207
0.1 F +VS Binary Keying Inputs 0.1 F 3.9K 9 10 11 5.1K 12 6 R3 +VS S1
65-2207-10
IS 1 2
C
S2 +VS 3 13 14 5 RL Squarewave Output Trianglewave Output
8
RC2207 Device Under Test 7 R4 4
R1
R2
Figure 8. Test Circuit for Single Supply Operation
For single supply operation, the DC voltage at pin 10 and the timing terminals (pins 4 through 7) are equal and approximately 0.6V above VB, the bias voltage at pin 11 . The logic levels at the binary keying terminals are referenced to the voltage at pin 10.
Pulse and Sawtooth Operation
The duty cycle of the output waveforms can be controlled by frequency shift keying at the end of every half cycle of oscillator output. This is accomplished by connecting one or both of the binary keying inputs (pin 8 or 9) to the squarewave output at pin 13. The output waveforms can then be converted to positive or negative pulses and sawtooth waveform. Figure 10 is the recommended circuit connection for duty cycle control. Pin 8 is shorted to pin 13 so that the circuit switches between the 0 0 and the 1 0 logic states given in Table 1. Timing pin 5 is activated when the output is high, and pin 6 is activated when the squarewave output goes to a low state. The duty cycle of the output waveforms given as:
R2 Duty Cycle = -------------------R2 + R3
On-Off Keying
The RC2207 can be keyed on and off by simply activating an open circuited timing pin. Under certain conditions, the circuit may exhibit very low frequency (<1 Hz) residual oscillation in the off state due to internal bias current. If this effect is undesirable, it can be eliminated by connecting a 10 MW resistor from pin 3 to + VS.
Frequency Control (Sweep and FM)
The frequency of operation is controlled by varying the total timing current, IT, drawn from the activated timing pin 4, 5, 6 or 7. The timing current can be modulated by applying a control voltage, VC, to the activated timing pin through a series resistor RC as shown in Figure 9. For split supply operation, a negative control voltage, VC, applied to the circuit of Figure 9 causes the total timing current, IT, and the frequency, to increase. As an example, in the circuit of Figure 9, the binary keying inputs are grounded. Therefore, only timing pin 6 is activated. The frequency of operation determined by:
V C R3 1 f = -------------- 1 - --------------------------- Hz R3C B ( RC ) ( -VC )
and can be varied from 0.1% to 99.9% by proper choice of timing resistors. The frequency of oscillation, f, is given as:
2 1 f = --- -------------------C R2 + R3
The frequency can be modulated or swept without changing the duty cycle by connecting R2 and R3 to a common control voltage VC instead of to -VS. The sawtooth and the pulse output waveforms are shown in the Typical Performance Characteristics Graphs.
7
RC2207
PRODUCT SPECIFICATION
9 10 12 IC VC RC R3 -VS CB
65-2207-11
RC2207
IT
5
6 R3
8
13
14 Sawtooth Output 4.7K
RC2207
R2 IO 12 8 9 -VS CO Pulse Output +VS
65-2207-12
Figure 9. Frequency Sweep Operation
Figure 10. Pulse and Sawtooth Generation
8
PRODUCT SPECIFICATION
RC2207
Mechanical Dimensions
14-Lead SOIC
Inches Min. A A1 B C D E e H h L N a ccc Max. Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
Symbol
.053 .069 .004 .010 .013 .020 .008 .010 .336 .345 .150 .158 .050 BSC .228 .244 .010 .016 14 0 -- 8 .004 .020 .050
1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 8.54 8.76 3.81 4.01 1.27 BSC 5.79 6.20 0.25 0.40 14 0 -- 8 0.10 0.50 1.27
3 6
14
8
E
H
1
7
D A1 A SEATING PLANE -C- LEAD COPLANARITY ccc C a
h x 45 C
e
B
L
9
RC2207
PRODUCT SPECIFICATION
Mechanical Dimensions (continued)
14-Lead Plastic DIP
Inches Min. A A1 A2 B B1 C D D1 E E1 e eB L N -- .015 .115 Max. .210 -- .195 Millimeters Min. -- .38 2.93 Max. 5.33 -- 4.95 Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E1" do not include mold flashing. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. Terminal numbers are shown for reference only. 4. "C" dimension does not include solder finish thickness. 5. Symbol "N" is the maximum number of terminals. 4 2
Symbol
.014 .022 .045 .070 .008 .015 .725 .795 .005 -- .300 .325 .240 .280 .100 BSC -- .430 .115 .200 14
.36 .56 1.14 1.78 .20 .38 18.42 20.19 .13 -- 7.62 8.26 6.10 7.11 2.54 BSC -- 10.92 2.92 5.08 14
2
5
D 7 1
E1
D1
8
14
E e A A1 L B1 B eB C
10
PRODUCT SPECIFICATION
RC2207
Mechanical Dimensions (continued)
14-Lead Ceramic DIP
Inches Min. A b1 b2 c1 D E e eA L Q s1 a Max. Millimeters Min. Max. 8 2 8 4 4 5, 9 7 3 6 Notes: Notes 1. Index area: a notch or a pin one identification mark shall be located adjacent to pin one. The manufacturer's identification shall not be used as pin one identification mark. 2. The minimum limit for dimension "b2" may be .023 (.58mm) for leads number 1, 7, 8 and 14 only. 3. Dimension "Q" shall be measured from the seating plane to the base plane. 4. This dimension allows for off-center lid, meniscus and glass overrun. 5. The basic pin spacing is .100 (2.54mm) between centerlines. Each pin centerline shall be located within .010 (.25mm) of its exact longitudinal position relative to pins 1 and 14. 6. Applies to all four corners (leads number 1, 7, 8, and 14). 7. "eA" shall be measured at the center of the lead bends or at the centerline of the leads when "a" is 90. 8. All leads - Increase maximum limit by .003 (.08mm) measured at the center of the flat, when lead finish applied. 9. Twelve spaces. D
7 1
Symbol
-- .200 .014 .023 .045 .065 .008 .015 -- .785 .220 .310 .100 BSC .300 BSC .125 .200 .015 .060 .005 -- 90 105
-- 5.08 .36 .58 1.14 1.65 .20 .38 -- 19.94 5.59 7.87 2.54 BSC 7.62 BSC 3.18 5.08 .38 1.52 .13 -- 90 105
NOTE 1
E
8
14
s1 eA
e
A Q L b2 b1 a c1
11
PRODUCT SPECIFICATION
RC2207
Ordering Information
Part Number RC2207M RC2207N RV2207M RV2207N RM2207D RM2207D/883B Package 14 Lead SOIC 14 Lead Plastic DIP 14 Lead SOIC 14 Lead Plastic DIP 14 Lead Ceramic DIP 14 Lead Ceramic DIP Operating Temperature Range 0C to +70C 0C to +70C -25C to +85C -25C to +85C -55C to +125C -55C to +125C
Note: 1. /883B suffix denotes MIL-STD-883, Level B processing
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS30002207 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
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RC2211A
FSK Demodulator/Tone Decoder
Features
* * * * * * * Wide frequency range - 0.01 Hz to 300 kHz Wide supply voltage range - 4.5V to 20V DTL/TTL/ECL logic compatibility FSK demodulation with carrier-detector Wide dynamic range - 2 mV to 3 VRMS Adjustable tracking range - 1% to 80% Excellent temperature stability - 20 ppm/C typical
Description
The RC2211A is a monolithic phase-locked loop (PLL) system especially designed for data communications. It is particularly well-suited for FSK modem applications, and operates over a wide frequency range of 0.01 Hz to 300 kHz. It can accommodate analog signals between 2 mV and 3V, and can interface with conventional DTL, TTL and ECL logic families. The circuit consists of a basic PLL for tracking an input signal frequency within the passband, a quadrature phase detector which provides carrier detection, and an FSK voltage comparator which provides FSK demodulation. External components are used to independently set carrier frequency, bandwidth and output delay.
Applications
* * * * * FSK demodulation Data synchronization Tone decoding FM detection Carrier detection
Block Diagram
Loop Filter f-Detector FSK Comparator VCO f Preamp Lock Detector Outputs Lock Detector Filter Lock Detector Comparator
65-2211-01
Data Filter FSK Data Output
f FSK Input
f-Detector
Rev. 1.3.1
RC2211A
PRODUCT SPECIFICATION
Functional Description
Signal Input (Pin 2)
The input signal is AC coupled to this terminal. The internal impedance at pin 2 is 20 kW. Recommended input signal level is in the range of 10 mVRMS to 3 VRMS.
FSK Data Output (Pin 7)
This output is an open collector stage which requires a pull-up resistor, RL, to +VS for proper operation. It can sink 5 mA of load current. When decoding FSK signals the FSK data output will switch to a "high" or off state for low input frequency, and will switch to a "low" or on state for high input frequency. If no input signal is present, the logic state at pin 7 is indeterminate.
Quadrature Phase Detector Output, Q (Pin 3)
This is the high impedance output of the quadrature phase detector, and is internally connected to the input of lock detector voltage comparator. In tone detection applications, pin 3 is connected to ground through a parallel combination of RD and CD (see Figure 1) to eliminate chatter at the lock detector outputs. If this tone detector section is not used, pin 3 can be left open circuited.
FSK Comparator Input (Pin 8)
This is the high impedance input to the FSK voltage comparator. Normally, an FSK post detection or data filter is connected between this terminal and the PLL phase detector output (pin 11). This data filter is formed by RF and CF of Figure 1. The threshold voltage of the comparator is set by the internal reference voltage, VR, available at pin 10.
Lock Detector Output, Q (Pin 5)
The output at pin 5 is at a "high" state when the PLL is out of lock and goes to a "low" or conducting state when the PLL is locked. It is an open collector output and requires a pull-up resistor, RL, to +VS for proper operation. In the "low" state it can sink up to 5 mA of load current.
Reference Bypass (Pin 9)
This pin can have an optional 0.1 mF capacitor connected to the ground.
Reference Voltage, VR (Pin 10)
This pin is internally biased at the reference voltage level, VR; VR = +VS/2 - 650 mV. The DC voltage level at this pin forms an internal reference for the voltage levels at pin 3, 8, 11 and 12. Pin 10 must be bypassed to ground with a 0.1 mF capacitor.
Lock Detector Complement, Q (Pin 6)
The output at pin 6 is the logic complement of the lock detector output at pin 5. This output is also an open collector type stage which can sink 5 mA of load current in the low or "on" state.
RB 510K (11) C1 Input Preamp (2) VCO 0.1 F Input Signal Quad f-Detector (3) RD 100K to 470K Lock Detector Comparator f (14) C0 (13) R0 0.1 F f (12) (10) Internal Reference RF 100K (8)
RL
(1) +VS (7)
Loop f-Detector
R1
CF
FSK Comparator
FSK Output
Q (6) Lock Detector Outputs (5) Q
CD
65-2211-02
Figure 1. Generalized Circuit Connection for FSK and Tone Detection
2
PRODUCT SPECIFICATION
RC2211A
Loop Phase Detector Output (Pin 11)
This terminal provides a high impedance output for the loop phase detector. The PLL loop filter is formed by R1 and C1 connected to pin 11 (see Figure 1). With no input signal, or with no phase error within the PLL, the DC level at pin 11 is very nearly equal to VR. The peak voltage swing available at the phase detector output is equal to VR.
2.
Internal Reference Voltage, VR (measured at pin 10) +V S V R = ae ----------o -650 mV e2o
3.
Loop Lowpass Filter Time Constant, t t = R1C1
VCO Control Input (Pin 12)
VCO free running frequency is determined by external timing resistor, R0, connected from this terminal to ground. The VCO free running frequency, F0 is given by: 1 F 0 ( Hz ) = -----------R0 C0 where C0 is the timing capacitor across pins 13 and 14. For optimum temperature stability R0 must be in the range of 10 kW to 100 kW (see Typical Performance Characteristics). This terminal is a low impedance point, and is internally biased at a DC level equal to VR. The maximum timing current drawn from pin 12 must be limited to 3 mA for proper operation of the circuit.
4.
Loop Dampening, z: ae C 0o 1 z = c ----- / ae --o -e C 1o e 4o
5.
Loop Tracking Bandwidth, DF/F0:
Df/FO = R0/R1 Tracking Bandwidth Df Df
FLL
F1
F0
F2
FLH
65-2211-03
VCO Timing Capacitor (Pins 13 and 14)
VCO frequency is inversely proportional to the external timing capacitor, C0, connected across these terminals. C0 must be non-polarized, and in the range of 200 pF to 10 mF.
6.
FSK Data Filter Time Constant, tF: tF = RFCF
7.
VCO Frequency Adjustment
VCO can be fine tuned by connecting a potentiometer, Rx, in series with R0 at pin 12 (see Figure 2).
Loop Phase Detector Conversion Gain, Kf (Kf is the differential DC voltage across pins 10 and 11, per unit of phase error at phase-detector input): ( -2 ) ( VR ) kf ( in volts per radian ) = ----------------------p
VCO Free-Running Frequency, F0
The RC2211A does not have a separate VCO output terminal. Instead, the VCO outputs are internally connected to the phase detector sections of the circuit. However, for set-up or adjustment purposes, the VCO freerunning frequency can be measured at pin 3 (with CD disconnected) with no input and with pin 2 shorted to pin 10. 8.
VCO Conversion Gain, K0 is the amount of change in VCO frequency per unit of DC voltage change at pin 11: -1 K0 ( in Hertz per volt ) = -------------------C0 R1 VR
9.
Total Loop Gain, KT: KT (in radians per second per volt)= 2 pKfK0 = 4 -----------C0 R1
Design Equations
See Figure 1 for Definitions of Components. 1. VCO Center Frequency, F0: 1 F 0 ( Hz ) = -----------R0 C0
10. Peak Phase Detector Current, IA: VR I A ( mA ) = -----25
3
RC2211A
PRODUCT SPECIFICATION
Pin Assignments
+VS Input Lock Detector Filter GND Q Q FSK Data Output 1 2 3 4 5 6 7 14 13 12 11 10 9 8 Timing Capacitor Timing Capacitor Timing Resistor Loop f-Detector Reference Voltage Output Reference Bypass FSK Comparator Input
65-2211-04
Absolute Maximum Ratings
Parameter Supply Voltage Input Signal Level Storage Temperature Range Operating Temperature Range Junction Temperature Lead Soldering Temperature (60 sec.) Max. PD TA<50C RV2211A RC2211A -65 -25 0 Conditions Min. Max. +20 3 +150 +85 +70 +125 +300 468 Unit V VRMS C C C C C mW
Thermal Characteristics
Parameter Therm. Res. qJA 14 Lead Plastic DIP 92C/W 14 Lead SOIC 150C/W
4
PRODUCT SPECIFICATION
RC2211A
Electrical Characteristics
(Test Conditions +VS = +12V, TA +25C, R0 = 30 kW, C0 = 0.033 mF. See Figure 1 for component designations.) RV2211A Parameters General Supply Voltage2 Supply Current Oscillator Frequency Accuracy Frequency Stability1 R1 = +VS = 12 1V +VS = 5 0.5V R0 = 8.2 kW, C0 = 400 pF R0 = 2 MW, C0 = 50 mF 100 20 0.05 0.2 300 0.01 0.5 0.2 300 0.01 20 0.05 0.5 ppm/C %/V %/V kHz Hz Temperature Coefficient Power Supply Rejection Upper Frequency Limit Lowest Practical Operating Frequency1 Timing Resistor, R0 Operating Range Recommended Range Loop Phase Detector Peak Output Current Output Offset Current Output Impedance Maximum Swing Quadrature Phase Detector Peak Output Current3 Output Impedance Maximum Swing Input Preamp Input Impedance Measured at pin 2 2.0 18 1.0 2.0 18 1.0 kW mVRMS Input Signal Voltage VS = +6V Required to Cause Limiting3 f = 1.7 kHz Voltage Comparator Input Impedance Input Bias Current Voltage Gain
1
RC2211A Min. 4.5 5.0 1.0 Typ . Max. 20 11 5 Units V mA %
Test Conditlons
Min. 4.5
Typ.
Max. 20
R0 10 kW Deviation from f0 = 1/R0C0
5.0 1.0
11.0 3.0
5.0 15 Measured at pin 11 150 200 1.0 1.0 Ref. to pin 10 Measured at pin 3 4.0 100 5.0 150 1.0 11
2000 100 300
5.0 15 100 200 2.0 1.0 4.0 5.0 150 1.0 11
2000 100 300
kW kW mA mA MW V mA MW VP-P
Measured at pins 3 & 8 RL = 5.1 kW IC = 3mA V0 = 12V Measured at pin 10 4.9 55
2.0 100 70 300 0.01 5.3 100 5.7 4.75 55
2.0 100 70 300 0.01 5.3 100 5.85
MW nA dB mV mA V W
Output Voltage Low Output Leakage Current Internal Reference Voltage Level Output Impedance
Notes: 1. Guaranteed by design. 2. Individual applications may need special circuitry to function at <12V. 3. Sample tested.
5
RC2211A
PRODUCT SPECIFICATION
Typical Performance Characteristics
20 10
15 R0 = 5 kW IS (mA) 10 R0 = 10 kW C0 (F) 1.0
R0 = 5 kWY R0 = 10 kWY R0 = 20 kWY R0 = 40 kWY R0 = 80 kWY R0 = 160 kW
0
4
6
8
10 12 14 16 +VS (V)
18
20 22
24
0.1 100 1K FO (Hz) Figure 7. Timing Resistor with Timing Capacitor vs. VCO Frequency
10K
Figure 6. Supply Current vs. Supply Voltage (Logic Outputs Open Circuited)
1K
1.0
100
65-2211-11
10 0 1 FO (Hz) 10
-1.0 -50
-25
0
+25
+50
+75
+100
+125
Temperature (C)
Figure 8. Timing Capacitor with Timing Resistor vs. VCO Frequency
Figure 9. Center Frequency Drift vs. Temperature
1.02 Normalized Frequency 1.01 1.00 0.99
65-2211-13
Curve 1 2 3 4 5 FO = 1 kHz R 10 R0 4 6 8 10 12 14 -VS (V) Figure 10. VCO Frequency vs. Supply Voltage 16 18 20 22
R0 5K 10K 30K 100K 300K
0.98 0.97
24
6
65-2211-12
C 0= 0.0 01 C 0= F 0.0 03 C 3 0= F 0.0 1 C 0= F C 0.0 0= 33 0.1 C F F 0= 0.3 3 F
Normalized Center Frequency Drift (% of FO)
0.5
R0 = 10 kWY YR = 50 kWY 0 Y
1 MW
R0 (kW)
500 kW
0
50 kW
-0.5
R0 = 1 MWY Y R0 = 500 kWY Y
10 kW
65-2211-10
R0 > 100 kW
65-2211-09
5
PRODUCT SPECIFICATION
RC2211A
Applications Discussion
FSK Decoding
Figure 2 shows the basic circuit connection for FSK decoding. With reference to Figures 1 and 2, the functions of external components are defined as follows: R0 and C0 set the PLL center frequency, R1 sets the system bandwidth, and C1 sets the loop filter time constant and the loop damping factor. CF and RF form a one pole post-detection filter for the FSK data output. The resistor RB (510 kW) from pin 7 to pin 8 introduces positive feedback across FSK comparator to facilitate rapid transition between output logic states. Recommended component values for some of the most commonly used FSK bauds are given in Table 1.
+VS 0.1 F C0 FSK Input 0.1 F 1 2 3 RL +VS 5.1K FSK Data Output 4 5 6 7 14 13 12 11 0.1 F RC2211A 10 9 8 RB 510K RF 100K
65-2211-05
1.
Calculate PLL center frequency, F0
F1 + F2 fF 0 = ----------------2
2.
Choose a value of timing resistor R0 to be in the range of 10 kW to 100 kW. This choice is arbitrary. The recommended value is R0 = 20 kW. The final value of R0 ios normally finetuned with the series potentiometer, RX. Calculate value of C0 from Design Equation No. 1 or from Typical Performance Characteristics: C0 = 1/R0F0
3.
4.
Calculate R1 to give a Df equal to the markspace deviation: R1 = R0 [F0/(F1 - F2)]
VCO Fine Tune R0 R1 C1 RX 5K
5.
Calculate C1 to set loop damping. (See Design Equation No. 4) Normally, z 1/2 is recommended Then: C1 = C0/4 for z = 1/2
6.
Calculate Data Filter Capacitance, CF: For RF = 100 kW, RB = 510 kW, the recommended value of CF is: 3 C F ( in mF ) = -----------------------Baud Rate
CF
Figure 2. Circuit Connection for FSK Decoding
Table 1. Recommended Component Values for Commonly Used FSK Bands (see Circuit of Figure 2)
FSK Band 300 Baud F1 = 1070 Hz F2 = 1270 Hz 300 Baud F1 = 2025 Hz F2 = 2225 Hz 1200 Baud F1 = 1200 Hz F2 = 2200 Hz Component Values C0 = 0.039 mF, CF = 0.005 mF C1 = 0.01 mF, R0 = 18 kW R1 = 100 kW C0 = 0.022 mF, CF = 0.005 mF C1 = 0.0047 mF, R0 = 18 kW R1 = 200 kW C0 = 0.027 mF, CF = 0.0022 mF C1 = 0.01 mF, R0 = 18 kW R1 = 30 kW
Note: All calculated component values except R0 can be rounded off to the nearest standard value, and R0 can be varied to fine-tune center frequency through a series potentiometer, RX (see Figure 2).
Design Example
75 Baud FSK demodulator with mark space frequencies of 1110/1170 Hz: Step 1: Calculate F0: F0=(1110+1170)(1/2)= 1140Hz Step 2: Choose R0 = 20 kW (18 kW fixed resistor in series with 5 kW potentiometer) Step 3: Calculate C0 from VCO Frequency vs. Timing Capacitor: C9 = 0.044mF Step 4: Calculate R1: R1 = R0 (1140/60) = 380 kW Step 5: Calculate C1: C1 = C0/4 = 0.011 mF
Design Instructions
The circuit of Figure 2 can be tailored for any FSK decoding application by the choice of five key circuit components: R0, R1, C0, C1 and CF. For a given set of FSK mark and space frequencies, F1 and F2, these parameters can be calculated as follows:
Note: All values except R0 can be rounded off to nearest standard value.
7
RC2211A
PRODUCT SPECIFICATION
FSK Decoding with Carrier Detector
The lock detector section of the RC2211A can be used as a carrier detector option for FSK decoding. The recommended circuit connection for this application is shown in Figure 3. The open-collector lock detector output, pin 6, is shorted to the data output (pin 7). Thus, the data output will be disabled at "low" state, until there is a carrier within the detection band of the PLL, and the pin 6 output goes "high" to enable the data output.
+VS 0.1 F C0 FSK Inputs CO 0.1 F 1 2 3 470K 4 14 13 12 R0 R1 C1 RF 100K 510K CF
65-2211-06
+VS 0.1 F C0 FSK Inputs CO 0.1 F 1 2 3 470K 4 14 13 12 R0 R1 C1 +VS RL2 Logic Output Q Q Logic Outputs
65-2211-07
VCO Fine Tune
11 0.1 F RC2211A 5 10 6 9 8
RX 5K
+VS VCO Fine Tune
RL1
7
11 0.1 F RC2211A 5 10 6 9 8
RX 5K
Figure 4. Circuit Connection for Tone Detection
+VS
5.1K Data Output
7
Both logic outputs at pins 5 and 6 are open-collector type stages, and require external pull-up resistors RL1 and RL2 as shown in Figure 4. With reference to Figures 1 and 4, the function of the external circuit components can be explained as follows: R0 and C0 set VCO center frequency, R1 sets the detection bandwidth, C1 sets the lowpass-loop filter time constant and the loop dampening factor, and RL1 and RL2 are the respective pull-up resistors for the Q and Q logic outputs.
Note: Data output is "low" when no carrier is present.
Figure 3. External Connections for FSK Demodulation with Carrier Detector Capability
The minimum value of the lock detector filter capacitance CD is inversely proportional to the capture range, DfC. This is the range of incoming frequencies over which the loop can acquire lock and is always less than the tracking range. It is further limited by C1. For most applications, DFC< DF/2. For RD = 470 kW, the approximate minimum value of CD can be determined by: CD(mF) 16/capture range in Hz With values of CD that are too small, chatter can be observed on the lock detector output as an incoming signal frequency approaches the capture bandwidth. Excessively large values of CD will slow the response time of the lock detector output.
Design Instructions
The circuit of Figure 4 can be optimized for any tone-detection application by the choice of five key circuit components: R0, R1, C0, C1 and CD. For a given input tone frequency, FS, these parameters are calculated as follows: 1. 2. 3. Choose R0 to be in the range of 15 kW to 100 kW. This choice is arbitrary. Calculate C0 to set center frequency, f0 equal to FS: C0 = 1/R0FS. Calculate R1 to set bandwidth DF (see Design Equation No. 5): R1 = R0(F0/DF). Note: The total detection bandwidth covers the frequency range of F0 DF. Calculate value of C1 for a given loop damping factor: C1 =C0/16z2 Normally z = 1/2 is optimum for most tone detector applications, giving C1 = 0.25 C0. Increasing C1 improves the out-of-band signal rejection, but increases the PLL capture time. 5. Calculate value of filter capacitor CD. To avoid chatter at the logic output, with RD = 470W, CD must be: CD(mF) (16/capture range in Hz) Increasing CD slows the logic output response time.
4.
Tone Detection
Figure 4 shows the generalized circuit connection for tone detection. The logic outputs, Q and Q at pins 5 and 6 are normally at "high" and "low" logic states, respectively. When a tone is present within the detection band of the PLL, the logic state at these outputs becomes reversed to the duration of the input tone. Each logic output can sink 5 mA of load current.
8
PRODUCT SPECIFICATION
RC2211A
Design Examples
Tone detector with a detection band of 1 kHz 20 Hz: Step 1: Choose R0 = 20 kW (18 kW in series with 5 kW potentiometer) . Step 2: Choose C0 for F0 = 1 kHz: C0 = 0.05 mF. Step 3: Calculate R1: R1 = (R0) (1000/20) = 1 MW. Step 4: Calculate C1: for z = 1/2, C1 = 0.25 mF, C0 = 0.013 mF. Step 5: Calculate CD: CD = 16/38 = 0.42 mF. Step 6: Fine tune the center frequency with the 5 kW potentiometer. RX.
Linear FM Detection
The RC2211A can be used as a linear FM detector for a wide range of analog communications and telemetry applications. The recommended circuit connection for the application is shown in Figure 5. The demodulated output is taken from the loop phase detector output (pin 11), through a post detection filter made up of RF and CF, and an external buffer amplifier. This buffer amplifier is necessary because of the high impedance output at pin 11. Normally, a non-inverting unity gain op amp can be used as a buffer amplifier, as shown in Figure 5. The FM detector gain, i.e., the output voltage change per unit of FM deviation, can be given as: VOUT = R1 VR/100 R0 Volts/% deviation where VR is the internal reference voltage. For the choice of external components R1, R0, C0, C1 and CF, see the section on Design Instructions.
0.1 F (2) (13) CO CK (14) (12) R0 RF 100K CF +VS (11) (8) (1) (10) 0.1 F +VS
FM Input
RC2211A
(4)
0.1 F
R1 C1
Demodulated Ouput
65-2211-08
Figure 5. Linear FM Detector Using RC2211A and an External Op Amp
9
RC2211A
PRODUCT SPECIFICATION
Mechanical Dimensions
14-Pin SOIC Package
Inches Min. A A1 B C D E e H h L N a ccc .053 .004 .013 .008 .336 Max. .069 .010 .020 .010 .345 Millimeters Min. 1.35 0.10 0.33 0.19 8.54 Max. 1.75 0.25 0.51 0.25 8.76 5 2 2 Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
Symbol
.150 .158 .050 BSC .228 .244 .010 .016 14 0 -- 8 .004 .020 .050
3.81 4.01 1.27 BSC 5.79 6.20 0.25 0.40 14 0 -- 8 0.10 0.50 1.27
3 6
14
8
E
H
1
7
D A1 A SEATING PLANE -C- LEAD COPLANARITY ccc C a
h x 45 C
e
B
L
10
PRODUCT SPECIFICATION
RC2211A
Mechanical Dimensions (continued)
14-Lead Plastic DIP Package
Inches Min. A A1 A2 B B1 C D D1 E E1 e eB L N -- .015 .115 Max. .210 -- .195 Millimeters Min. -- .38 2.93 Max. 5.33 -- 4.95 Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E1" do not include mold flashing. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. Terminal numbers are shown for reference only. 4. "C" dimension does not include solder finish thickness. 5. Symbol "N" is the maximum number of terminals. 4 2
Symbol
.014 .022 .045 .070 .008 .015 .725 .795 .005 -- .300 .325 .240 .280 .100 BSC -- .430 .115 .200 14
.36 .56 1.14 1.78 .20 .38 18.42 20.19 .13 -- 7.62 8.26 6.10 7.11 2.54 BSC -- 10.92 2.92 5.08 14
2
5
D 7 1
E1
D1
8
14
E e A A1 L B1 B eB C
11
RC2211A
PRODUCT SPECIFICATION
Ordering Information
Part Number RC2211AN RC2211AM RV2211AN RV2211AM Package 14-Lead Plastic DIP 14-Lead Plastic SOIC 14-Lead Plastic DIP 14-Lead Plastic SOIC Operating Temperature Range 0C to +70C 0C to +70C -25C to +85C -25C to +85C
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS30002211A O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC2798
Integrated QAM IF Downconverter
Features
* * * * * * * * RF input frequency range 30 to 250MHz On chip VCO with LO frequency range 30 to 250MHz IF amplifier with AGC setting High dynamic range -9dBm IIP3 On chip Video Amplifier Built in ESD protection Supply voltage range 5 to 10 V Space saving 20-Lead TSSOP package
Description
The RC2798 is an integrated solution for the downconversion of QAM IF signals in the front-end design of cable modem and set-top receivers. It is intended for use in 64QAM and 256QAM IF downconversion applications. The RC2798 integrates IF amplifier with AGC , mixer, VCO, and a video amplifier on a single chip. It accepts the QAM IF signals via SAW filter and downconverts it to 5MHz baseband signal. The baseband signal can be digitized using Fairchild Semiconductor's 8 bit A/D (TMC1175 series) or 10bit A/D (TMC1185 series) and decoded further with a QAM demodulator. The IF, Oscillator and Mixer section work at 5V. The video amplifier works at 5V to 10V. The RC2798 is available in a 20 Lead TSSOP package.
Applications
* * * * * Digital Set-top receivers Cable modems Internet surfboards Network Interface Modules Multimedia PCs
Block Diagram
AGC_IN1 AGC_IN2 VAGC VCC MIX OSC_OUT GND B2 C1 C2 1 2 3 4 5 6
LO
RC2798
20 GND 19 MIX_OUT2 18 MIX_OUT1 17 G1A 16 G1B 15 VampIn1 14 VampIn2 13 VccAmp 12 OUT1
VideoAmp
AGC + MIX
7 8 9
B1 10
11 OUT2
Rev 1.0.0
PRELIMINARY INFORMATION describes products that are not in full production at the time of printing. Specifications are based on design goals and limited characterization. They may change without notice. Contact Fairchild Semiconductor for current information.
RC2798
PRODUCT SPECIFICATION
Absolute Maximum Ratings (TA = 25C unless otherwise specified)
Parameter Video Amplifier 5V Operation Vcc_Mix Supply voltage 1 (for AGC amplifier, oscillator, and mixer) AGC amplifier, oscillator, and mixer block Video amplifier block TA = 85C1 -40 -55 AGC amplifier, oscillator, and mixer block Video amplifier block TA = 75C1 -40 -55 6 6 430 +85 +150 6 11 500 +75 +150 V V mW C C V V mW C C Test conditions Min. Typ. Max. Unit
VccVamp Supply voltage 2 ( for video amplifier) PD TA Tstg Vcc_Mix Power dissipation Operation temperature range Storage temperature range Supply voltage 1 (for AGC amplifier, oscillator, and mixer)
Video Amplifier 9V Operation
VccVamp Supply voltage 2 ( for video amplifier) PD TA Tstg Power dissipation Operation temperature range Storage temperature range
Notes: 1. Mounted on 50 X 50 X 1.6mm double epoxy glasss board.
Recommended Operating Range
Parameter Vcc_Mix VccVamp Ta1 Ta2 Supply voltage 1 (for AGC amplifier, oscillator, and mixer) Supply voltage 2 ( for video amplifier) Operation temperature range Operation temperature range 11 22 Min. 4.5 4.5 -40 -40 Typ. 5.0 5.0 +25 +25 Max. 5.5 10.0 +85 +75 Unit V V C C
Notes: 1. @ Vcc_Mix = VccVamp = 4.5 to 5.5V 2. @ Vcc_Mix = 4.5 to 5.5V, VccVamp = 4.5 to 10.0V
2
PRODUCT SPECIFICATION
RC2798
Electrical Characteristics (TA = 25C )
Parameter Icc1 fRF fOSC fIF CGMAX CGMIN GCR NF VAGC H VAGC L Icc2 VOUT G1 G2 Supply current 1 RF input frequency range OSC frequency range IF output frequency range Maximum conversion gain Minimum conversion gain AGC dynamic range Noise figure AGC voltage high level AGC voltage low level Supply current 2 Output voltage Differential gain 1 Differential gain 2 VAGC = 4.0V VAGC = 1.0V VAGC = 1.0 to 4.0V SSB, VAGC = 4.0V At maximum gain At maximum gain At minimum gain No input signal RL = 1KW, differential G1A-G1B pins: short, VOUT = 3Vp-p G1A-G1B pins: open, VOUT = 3Vp-p no input signal RL = 1KW, differential G1A-G1B pins: short, RL = 2KW G1A-G1B pins: open, RL = 2KW G1 G2 G1 G2 300 25.0 150 22.0 7.0 12.5 3.0 200 26.0 250 30.0 4.0 1.0 17.0 24 Test conditions no input signal Min. 17.0 30 30 DC 25 -7 32 9 40 Typ. 23.0 Max. 31.0 250 250 150 Unit mA MHz MHz MHz dB dB dB dB V V mA Vp-p V/V V/V AGC Amplifier, Oscillator, and Mixer Blocks (Vcc = 5V)
Video Amplifier Block (Vcc = 5V)
Video Amplifier Block (Vcc = 9V) Icc2 VOUT G1 G2 Supply current 2 Output voltage Differential gain 1 Differential gain 2 18.0 24.0 3.0 385 28.5 470 32.0 32.0 mA Vp-p V/V V/V
Video Amplifier Block (Vcc = 5V or 9V) BWG1 BWG2 Rin1 Rin2 Cin Bandwidth 1 Bandwidth 2 Input resistance 1 Input resistance 2 Input capacitance 50 50 3.5 7.5 1.6 MHz MHz KW KW pF
Standard Characteristics (VCC = 5V, TA = 25C)
Parameter AGC Amplifier Block (Vcc = 5V) AGC IIP3 AGC input intercept point At minimum gain (AGC amplifier + mixer) -9 dBm Test conditions Min. Typ. Max. Unit
Video Amplifier Block (Vcc = 5V or 9V) CMRR PSRR tr tPD Common mode rejection ratio Power supply rejection ratio Rise time Propagation delay time 80 70 2.6 4.4 dB dB nS nS 3
RC2798
PRODUCT SPECIFICATION
Typical Characteristics
30 Conversion gain - dB 25 20 15 10 5 0 -5 -10 0 5.00 E-01 1 1.5 2 2.5 3 3.5 4 4.5 5 conv. gain Series1
AGC control - Volts
Figure 1. AGC Control Characteristics
4.50E-02 4.00E-02 3.50E-02 3.00E-02 Supply current - A 2.50E-02 2.00E-02 1.50E-02 1.00E-02 5.00E-03 0.00E+00 -5.00E-03 0 4.00 8.00 E-01 E-01 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2 5.6 6 Video Amp AGC amp + Mixer + LO Total
Supply voltage - Volts
Figure 2. Supply Current vs. Supply Voltage
4
PRODUCT SPECIFICATION
RC2798
10nF RF input 51 10K VAGC (1.0-4.0V) Vcc_Mix(+5V) + 10F 0.22F FB 0.1F 10F + 10K
AGC_IN1 1 AGC_IN2 2
RC2798
GND 20 MIX_OUT2 10nF 19 MIX OUT 1K MIX_OUT1 18 10nF 1K
10nF VAGC 3
AGC + MIX
0.1F
VCC MIX 4
G1A 17
Oscillator O/P
OSC_OUT 5 10nF GND 6 LO B2 7 10nF C1 8 C2 9
G1B 16 VampIn1 15
VampIn2 14 VccAmp 13 OUT1 12 VideoAmp OUT2 11
Ext. LO I/P 51 10nF
B1 10
Figure 3. Measurement Circuit 1--AGC + MIX Block
5
RC2798
PRODUCT SPECIFICATION
AGC_IN1 1 AGC_IN2 2
RC2798
GND 20
MIX_OUT2 19 AGC + MIX
VAGC 3
MIX_OUT1 18
VCC MIX 4
G1A 17
OSC_OUT 5 GND 6 LO B2 7 C1 8 C2 9 B1 10 VideoAmp
G1B 16 VampIn1 15
0.01F VampIn1
VampIn2 14 VccAmp 13 OUT1 12 OUT2 11 10F
0.01F VampIn2 FB + 0.1F 10F + 0.1F OUT1 10nF OUT2 10nF
VccVamp (+5 or +9V)
Figure 4. Measurement Circuit 2--Video Amplifier Block
6
IF INPUT OUT+ R5 29 200 1% GND R6 200 1% R7 1K1% 5.6H C14 56pF L2 C19 1 C17 0.01F 0.01F C13 56pF 18 17 16 15 14 13 12 11 C26 15pF C16 82pF GND C18 0.01F C15 82pF 5.6H C11 0.1F C12 0.1F L1 GND OUT3 VAGC MIX_OUT1 G1A G1B VampIn1 VampIn2 VccAmp OUT1 OUT2 C25 0.01F VCC MIX OSC_OUT GND C3 R3 10K 4 5 GND FB1 6 + C6 10F GND C24 0.01F GND C7 0.1F GND FB + C5 10F GND 0.22F 4 MIX_OUT2 5 GND 20 GND
F1 SAWFILTER RC2798
PRODUCT SPECIFICATION
J1
1
1
IN+
2 x6964
R1 51
2
IN-
C1 GND 1 AGC_IN1 10nF C2 2 AGC_IN2 10nF
GND
3
GND
IN_GAIN
J3 VAMPIN2_TP R9 2 51 GND
Applications Discussion
GND
R2
GAIN CONTROL INPUT (1.0 - 4.0V) +5 P1
10K
+5V IN
C4 0.1F
R8 1K1% FB2 FB +
GND
OSC_OUT
GND
+9
P2 +9V IN + C20 0.1F C21 10F GND GND R10 C22 10F GND J4 1 1.0K BB_OUT R12 49.9 2 GND C23 0.1F GND
C8 0.01F C30 D1 MMBV809 R15 20K L3 1.2H C10 100pF C9 J2 1 EXT. LO I/P 2 1000pF GND GND GND GND R4 51 GND C29 1000pF 1000pF
OSCILLATOR OUTPUT
7 B2 C31 15pF 8 C1 C33 10pF 9 C2 C32 15pF 10 B1
VCOC D2 MMBV809
R18
R17
Figure 5. Application Circuit
R16 20K
TP_VCOC
20K
C28 0.1F
20K
GND
GND R11 OUT2_TP 1.0K R13 49.9 GND
Notes: 1. For self oscillation, do not load C9, and C10. 2. Fro external injection (VCO), do not load C28, C29, C30, C31, C32, C33, L3, D1, D2, R15, R16, R17, and R18. 3. For down convesion with video amplifier, do not load C19. 4. For using video amplifier only, do not load C17, C18, C16, C26, and change C15 to 0.1F.
RC2798
7
RC2798
PRODUCT SPECIFICATION
Crystal Oscillator Implementation
AGC_IN1 1 AGC_IN2 2 RC2798 GND 20
MIX_OUT2 19
VAGC 3
MIX_OUT1 18
+5V + 10F Oscillator O/P
FB + .1F 10F .1F
VCC MIX 4
G1A 17
OSC_OUT 5 GND 6
G1B 16 VampIn1 15
220pF
B2 7 C1 8 C2 9 B1 10
VampIn2 14 VccAmp 13 OUT1 12 OUT2 11
XTL 38.886 MHz Fundamental mode Series Resonant
Figure 6. Fundamental Mode--Series Resonant XTL
AGC_IN1 1 AGC_IN2 2
RC2798
GND 20
MIX_OUT2 19
VAGC 3
MIX_OUT1 18
+5V + 10F Oscillator O/P
FB + .1F 10F .1F
VCC MIX 4
G1A 17
OSC_OUT 5 GND 6
G1B 16 VampIn1 15
B2 7 220pF C1 8 C2 9 B1 10 Lo 180nH
VampIn2 14 VccAmp 13 OUT1 12 OUT2 11
XTL 38.886 MHz
10nF Co 93pF
Figure 7. Overtone Mode--Series Resonant XTL
8
PRODUCT SPECIFICATION
RC2798
Overtone Mode--Series Resonant XTL
If it is desired to operate a XTL at non-fundamental or overtone frequency, an AC coupled parallel resonant network should be connected to feedback input pin, B1. The typical impedance looking into B1 with B2 AC grounded is approximately Rin =1KW @ 38MHz. It is recommended to design the value of Qo at approximately 15 to 25. The Lo and Co values can be calculated from the following equations:
Qo = wo Co Rin wo = 2 p fo = (1/LoCo)1/2 The XTL is a series resonant type and it is operated at third overtone frequency.
AGC_IN1 1 AGC_IN2 2
RC2798
GND 20
MIX_OUT2 19
VAGC 3
MIX_OUT1 18
+5V + 10F Oscillator O/P
FB .1F 10F + .1F
VCC MIX 4
G1A 17
OSC_OUT 5 GND 6
G1B 16 VampIn1 15
B2 7 220pF C1 8 C2 9 B1 10
VampIn2 14 VccAmp 13 OUT1 12 OUT2 11
Cc 15pF for Fundamental 2pF for Overtone XTL 38.886 MHz Parallel Resonant
Figure 8. Fundamental or Overtone Mode--Parallel Resonant XTL
Fundamental or Overtone Mode- Parallel Resonant XTL
Figure 8 shows the implemenation of parallel resonant XTL at fundamental or overtone frequency. The XTL is a parallel resonant type and can be operated at either fundamental or third overtone frequency depending upon the feedback capacitor, Cc. When used with Cal Crystal Lab's XTL, P/N#CCL-6-38.8860G153, for Cc = 15pF it operates at fundamental mode and for Cc = 2pF, it operates at third overtone mode (38.886MHz).
For symmetrical reasons, the following design is recommended for better duty cycle (50 to 50%) output from VCO (see Figure 9).
9
RC2798
PRODUCT SPECIFICATION
AGC_IN1 1 AGC_IN2 2
RC2798
GND 20
MIX_OUT2 19
VAGC 3
MIX_OUT1 18
+5V + 10F Oscillator O/P
FB .1F 10F + .1F
VCC MIX 4
G1A 17
OSC_OUT 5 GND 6
G1B 16 VampIn1 15
B2 7 Cc XTL 38.886 MHz Parallel Resonant Cc Cc: 15pF for Fundamental 2pF for Overtone C1 8 C2 9 B1 10
VampIn2 14 VccAmp 13 OUT1 12 OUT2 11
Figure 9. Fundamental or Overtone Mode with Improved Duty Cycle--Parallel Resonant XTL
10
PRODUCT SPECIFICATION
RC2798
Package Dimensions
20-pin TSSOP package
Inches Min. A A1 A2 B C D E E1 e L N a ccc -- .002 .031 .007 .004 .250 .240 .168 Max. .047 .006 .041 .012 .008 .257 .264 .176 Millimeters Min. -- 0.05 0.80 0.19 0.09 6.40 6.10 4.30 Max. 1.20 0.15 1.05 0.30 0.20 6.60 6.70 4.50 5 5 2, 4 Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E1" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5. "B" & "C" dimensions include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
Symbol
.026 BSC .018 .029 20 0 -- 10 .004
0.65 BSC 0.45 0.75 20 0 -- 10 0.10
3 6
D
E1 E
A2 A1 SEATING PLANE -C- LEAD COPLANARITY ccc C a L C
A B e
11
RC2798
PRODUCT SPECIFICATION
Ordering Information
Product Number RC2798G Package 20 pin TSSOP
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS30002798 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC2951
Adjustable Micropower Voltage Regulator
Features
* * * * * * * * * * * High accuracy output voltage Guaranteed 100 mA output current Extremely low quiescent current Extremely tight load and line regulation Requires only a 1.0mF output capacitor for stability Internal Current and Thermal Limiting Error flag warns of output dropout Logic-controlled electronic shutdown Output programmable from 1.24 to 29V Fixed 3.3V version available 8 lead SOIC package
Description
The RC2951 is a voltage regulator specifically designed to maintain proper regulation with a very low dropout voltage (Typ. 40mV at light loads and 380 mV at 100mA). It has a low quiescent bias current of 75mA and is capable of supplying output currents in excess of 100mA. It has internal current and thermal limiting protection. The output can be programmed from 1.24V to 29V with two external resistors. A fixed output voltage (3.3V) is also available. The error flag output can be used as power-on reset for warning of a low output voltage. The Shutdown input feature allows a logic level signal to turn on and off the regulator output. The RC2951 is ideally suited for battery powered computer, consumer, and industrial equipment where an extension of useful battery life is desirable. The RC2951 is available in an 8-pin SOIC package.
Preliminary Information
Block Diagram
Unregulated DC 7 + FeedBack 8 Input 1 Output 2 + - From CMOS or TTL 3 Shut Down + + 60 mV + 1.23V Reference - Error 4 Ground Error Detection Comparator To CMOS or TTL Error Amplifier 6 VTAP 5 330k1/2 + See Application Discussion Sense VOUT IL 100 mA
Rev. 0.9.3
PRELIMINARY INFORMATION describes products that are not in full production at the time of printing. Specifications are based on design goals full production at the time of printing. Specifications are based on design goals and limited characterization. They may change without notice. Contact Raytheon for current information. information. Fairchild Semiconductor for current
RC2951
PRODUCT SPECIFICATION
Pin Assignments
8 Lead SOIC Package
Output Sense Shutdown Ground 1 2 3 4 8 7 6 5 Input Feedback VTAP Error
Top View
Absolute Maximum Ratings
Preliminary Information
Power Dissipation Lead Temp. (Soldering, 5 seconds) Storage Temperature Range Operating Junction Temperature Range Input Supply/Voltage Feedback Input Voltage2,3 Shutdown Input Voltage2 Error Comparator Output Voltage2
1
Internally Limited 260C -65 to +150C -55 to +150C -0.3 to +30V -1.5 to +30V -0.3 to +30V -0.3 to +30V
Notes: 1. Junction to ambient thermal resistance for the S.O. (M) package is 160C/W. 2 May exceed input supply voltage. 3. When used in dual-supply systems where the output terminal sees loads returned to a negative supply, the output voltage should be diode-clamped to ground.
Electrical Characteristics
The * denotes that the limits apply at temperature extremes. Parameter Output Voltage (RC2951M) Conditions1 TJ = 25C -25C TJ 85C Full Operating Temperature Range Output Voltage (RC2951M) Output Voltage (RC2951M-3.3) 100mA IL 100mA TJ TJMAX TJ = 25C -25C TJ 85C Full Operating Temperature Range Output Voltage (RC2951M-3.3) Output Voltage Temperature Coefficient7 100mA IL 100mA TJ TJMAX * * * * * * * * * Typ. 5.0 5.0 5.0 5.0 3.3 3.3 3.3 3.3 20 3.340 3.260 3.346 3.254 120 5.06 4.94 5.075 4.925 3.317 3.284 Tested Limit2 5.025 4.975 Units V max V min V max V min V max V min V max V min V max V min V max V min V max V min V max V min ppm/C
2
PRODUCT SPECIFICATION
RC2951
Electrical Characteristics (continued)
The * denotes that the limits apply at temperature extremes. Parameter Line Regulation9, 10 Regulation9 Conditions1 (VONOM + 1)V Vin 20V 100 mA IL 100 mA IL = 100 mA IL = 100 mA Ground Current IL = 100 mA IL = 100 mA Dropout Ground Current Current Limit Thermal Regulation8 Output Noise, 10 Hz to 100 KHz CL = 1 mF (5V Only) CL = 200 mF CL = 3.3 mF (Bypass = 0.01 mF Pins 7 to 1 (RC2951) * * Reference Voltage5 Feedback Pin Bias Current Reference Voltage Temperature Coefficient7 Feedback Pin Bias Current Temperature Coefficient Error Comparator Output Leakage Current Output Low Voltage Upper Threshold Voltage4 Lower Threshold Voltage4 Hysteresis4 VOH = 30V Vin = (VONOM - 0.5)V IOL = 400 mA * * * * 0.01 150 60 75 15 1 2 250 400 40 25 95 140 mA max mA max mV max mV max mV min mV min mV max mV max mV * * * 20 20 0.1 Vin = (VONOM - 0.5)V IL = 100 mA Vout = 0 * * * * * * * * Typ. 0.03 0.08 50 380 75 8 110 160 0.05 430 160 100 Tested Limit2 0.1 0.5 0.2 0.4 80 150 500 700 120 140 14 15 250 300 200 220 0.2 Units % max % max % max % max mV max mV max mV max mV max mA max mA max mA max mA max mA max mA max mA max mA max %/W max mV rms mV rms mV rms
Load
Dropout Voltage3
Preliminary Information
Reference Voltage
1.235
1.25 1.26 1.22 1.2 1.27 1.19 40 60
V max V max V min V min V max V min nA max nA max ppm/C nA/C
3
RC2951
PRODUCT SPECIFICATION
Electrical Characteristics (continued)
The * denotes that the limits apply at temperature extremes. Parameter Shutdown Input Input Logic Voltage Low (Regulator ON) High (Regulator OFF) Shutdown Pin Input Current Vshutdown = 2.4V Vshutdown = 30V * * * * * 1.3 0.6 2.0 30 450 3 50 100 600 750 10 20 V V max V min mA max mA max mA max mA max mA max mA max Conditions1 Typ. Tested Limit2 Units
Preliminary Information
Regulator Output Current in Shutdown6
Notes: 1. Unless otherwise specified all limits guaranteed for TJ - 25C, Vin = (VONOM + 1)V, IL = 100mA and CL = 1 mF for 5V versions, and 2.2 mF for 3V and 3.3V versions. Additional conditions for the 8-pin versions are Feedback tied to VTAP, Output tied to Output Sense and Vshutdown < 0.8V. 2. Guaranteed and 100% production tested. 3. Dropout Voltage is defined as the input to output differential at which the output voltage drops 100 mV below its nominal value measured at 1V differential. At very low values of programmed output voltage, the minimum input supply voltage of 2V (2.3V over temperature) must be taken into account. 4. Comparator thresholds are expressed in terms of a voltage differential at the Feedback terminal below the nominal reference voltage measured at Vin = (VONOM + 1)V. To express these thresholds in terms of output voltage change, multiply by the error amplifier gain = Vout/Vref = (R1 + R2)/R2. For example, at a programmed output voltage of 5V, the Error output is guaranteed to go low when the output drops by 95 mV x 5V/1.235V = 384 mV. Thresholds remain constant as a percent of Vout as Vout is varied, with the dropout warning occurring at typically 5% below nominal, 7.5% guaranteed. 5. Vref < Vout (Vin - 1V), 2.3V Vin 30V, 100mA IL 100 mA, TJ TJMAX. 6. Vshutdown 2V, Vin 30V, Vout = 0, Feedback pin tied to VTAP. 7. Output or reference voltage temperature coefficient is defined as the worst case voltage change divided by the total temperature range. 8. Thermal regulation is defined as the change in output voltage at a time T after a change in power dissipation is applied, excluding load or line regulation effects. Specifications are for a 50 mA load pulse at VIN = 30V (1.25W pulse) for T = 10 ms. 9. Regulation is measured at constant junction temperature, using pulse testing with a low duty cycle. Changes in output voltage due to heating effects are covered under the specification for thermal regulation. 10. Line regulation for the RC2951 is tested at 150C for IL = 1 mA. For IL = 100 mA and TJ = 125C, line regulation is guaranteed by design to 0.2%. See Typical Performance Characteristics for line regulation versus temperature and load current.
4
PRODUCT SPECIFICATION
RC2951
Applications Discussion
The RC2951 regulator is designed with internal current limiting and thermal shutdown. It is not internally compensated and requires a 1.0mF (or greater) capacitor between the output terminal and ground for stability. At lower output voltages, more capacitance is required (2.2mF or more is recommended for 3V and 3.3V versions) for stability. Most types of aluminum, tantalum or multilayer ceramic capacitors will perform adequately. Solid tantalums or appropriate multilayer ceramic capacitors are suggested for operation below 25C. At lower values of output current, less capacitance is needed to maintain stability at output. The capacitor at the output can be reduced to 0.33mF for currents less that 10mA, or 0.1mF for currents below 1.0mA. Using the adjustable versions at voltages below 5V runs the error amplifier at lower gains so that more output capacitance is needed. For the worst-case situation of a 100 mA load at 1.23V output (Output shorted to Feedback) a 3.3 mF (or greater) capacitor should be used. When setting the output voltage of the RC2951 versions with external resistors, a minimum load of 1 mA is recommended. A 1 mF tantalum or aluminum electrolytic capacitor should be placed from the RC2951 input to ground if there is more than 10 inches of wire between the input and the AC filter capacitor or if a battery is used as the input. Stray capacitance to the RC2951 Feedback terminal can cause instability. This may especially be a problem when using high value external resistors to set the output voltage. Adding a 100 pF capacitor between Output and Feedback and increasing the output capacitor to at least 3.3 mF will fix this problem. Figure 1 is a timing diagram showing the ERROR signal and the regulated output voltage as the RC2951 input is ramped up and down. For 5V versions, the ERROR signal becomes valid (low) at about 1.3V input. It goes high at about 5V input (the input voltage at which VOUT = 4.75.) Since the RC2951's dropout voltage is load-dependent (see curve in typical performance characteristics), the input voltage trip point (about 5V) will vary with the load current. The output voltage trip point (approx. 4.75V) does not vary with load.
4.75V Output Voltage
Preliminary Information
Error*
Input Voltage 1.3V
5V
2950-10
Figure 1. ERROR Output Timing
The error comparator has an open-collector output which requires an external pullup resistor. This resistor may be returned to the output or some other supply voltage depending on system requirements. In determining a value for this resistor, note that while the output is rated to sink 400 mA, this sink current adds to battery drain in a low battery condition. Suggested values range from 100k to 1MW. The resistor is not required if this output is unused.
Programming the Output Voltage (RC2951)
The RC2951 may be pin-strapped for the nominal fixed output voltage using its internal voltage divider by tying the output and sense pins together, and also tying the feedback and VTAP pins together. Alternatively, it may be programmed for any output voltage between its 1.235V reference and its 30V maximum rating. As seen in Figure 2 an external pair of resistors is required.
Error Detection Comparator Output
The comparator switches to a logic low whenever the RC2951 output falls out of regulation by more than approximately 5%. This value is the comparator's built-in offset of about 60 mV divided by the 1.235 internal reference voltage. This trip level remains "5% below normal" regardless of the value of the output voltage. For example, the error flag trip level is typically 4.75V for a 5V output or 11.4V for a 12V output. The out of regulation condition may be due either to low input voltage, current limiting, or thermal limiting.
5
RC2951
PRODUCT SPECIFICATION
.
+VIN 100K Error Output 5 8 +VIN VOUT 1
ERROR
VOUT 1.2 30V
RC2951 **Shutdown 3 SD Input GND 4 R1 FB 7 1.23V R2
2950-11
+ .01 F
+ 3.3F
R1 V OUT = V REF ae 1 + ----- o e Ro
2
VREF
Preliminary Information
** Drive with TTL-high to shut down. Ground or leave open if shutdown feature is not to be used. Figure 2. Adjustable Regulator
The complete equation for the output voltage is V OUT R1 = V REF * ae 1 + ----- o + I FB R 1 e Ro
2
Reducing Output Noise
In reference applications it may be advantageous to reduce the AC noise present at the output. One method is to reduce the regulator bandwidth by increasing the size of the output capacitor. Noise can be reduced fourfold by a bypass capacitor across R1, since it reduces the high frequency gain from 4 to unity. Pick 1 C BYPASS @ ----------------------------------2pR 1 * 200Hz or about 0.01 mF. When doing this, the output capacitor must be increased to 3.3 mF to maintain stability. These changes reduce the output noise from 430 mV to 100 mV rms for a 100 kHz bandwidth at 5V output. With the bypass capacitor added, noise no longer scales with output voltage so that improvements are more dramatic at higher output voltages.
V OUT V REF ------------- = -----------------R2 R1 + R2 V OUT R1 + R2 = V REF ae ------------------ o e R2 o R1 = V REF ae 1 + ----- o e Ro
2
V OUT
Adding the error term, R1 V OUT = V REF ae 1 + ----- o + I FB R 2 e R 2o where VREF is the nominal 1.235 reference voltage and IFB is the feedback pin bias current, nominally -20 nA. The minimum recommended load current of 1 mA forces an upper limit of 1.2 MW on the value of R2, if the regulator must work with no load (a condition often found in CMOS in standby). IFB will produce a 2% typical error in VOUT which may be eliminated at room temperature by trimming R1. For better accuracy, choosing R2 = 100k reduces this error to 0.17% while increasing the resistor program current to 12 mA. Since the RC2951 typically draws 60 mA at no load with Pin 2 open-circuited, this is a small price to pay.
6
PRODUCT SPECIFICATION
RC2951
Typical Applications
Unregulated Input 1F 10k1/2 8 6 IN VTAP SENSE RC2951 7 FB GND 4 OUT 1 2k1/2 0.002F IQ 400A 2 +
0.01F Supertex VP12C Output 5V1%@ 0 to 1A 220F
1M1/2
Preliminary Information
Figure 3. 1A Regulator with 1.2V Dropout
Unregulated Input 8 IN RC2951 6 VTAP FB 7 SENSE GND 4 2 + 4.7F 5V Output Load 50mA to 300mA OUT 1 3301/2 27k1/2 2N5432 (2) Error Output 5
+VIN 8 +VIN ERROR VOUT
1 *VOUTAVIN
RC2951 **Shutdown 3 SD Input GND 4
FB 4
Figure 4. 300 mA Regulator with 0.75 Dropout
*Minimum input-output voltage ranges from 40 mV to 400 mV, depending on load current. Current limit is typically 160 mA. +V = 2 30V
Figure 5. Wide Input Voltage Range Current Limiter
1.23 R
IL
Load
IL=
8 VIN VOUT RC2951 Shutdown 3 SD Input GND 4 R 1% FB 7 1 F + 0.1F 1
2950-12
Figure 6. Low Drift Current Source
7
RC2951
PRODUCT SPECIFICATION
Typical Applications (continued)
+VIN 8 +VIN 6 VTAP 2 SENSE VOUT 1 D2 5V Memory Supply 20 + 1F 3.6V Nicad 2N3906 4.7M1/2 8 +VIN ERROR 27k1/2 3 D3 D4 EARLY WARNING 220 20k1/2 Q1 8 +VIN 6 7 3 VTAP 2 SENSE VOUT 1 330k1/2
Main 5V Output
D1
Current Limit Section
+VIN = VOUT +5.0V 0.05
680
RC2951 #1 5 FB ERROR 7 GND 4
470 MJE2955 10k1/2 5 Error Flag R1 + FB VOUT 1 47 4 .033 7 1% R2 4.7 TANT. + 100 F +VOUT @ 2A
RC2951 SD GND
Preliminary Information
2.7M1/2
RESET P VDD R1 R2 For 5VOUT,use internal resistors. Wire pin 6 to 7, & wire pin 2 +VOUT Buss. VOUT = 1.23V 1 +
(
)
FB RC2951 #2 5 SD ERROR GND 4
+ 1F
Figure 9. 2 Ampere Low Dropout Regulator
+VIN C-MOS GATE
*Sleep Input * Early warning flag on low input voltage * Main output latches of f at lower input voltages * Battery backup on auxillary output Operation Reg. #1's VOUT is programmed one diode drop above 5V. Its error flag becomes active when Vin 5.7V. WhenVin drops below 5.3V, the error flag of Reg. #2 becomes active and via Q1 latches the main output off. When Vin again exceeds 5.7V Reg. #1 is back in regulation and the early warning signal rises unlatching Reg. #2 via D3. Error Output 47k1/2 8 +VIN 5 ERROR VOUT
470k1/2 1 100 pF 2N3906 FB 7 +VOUT
RC2951 Shutdown 3 SD Input GND 4
200k1/2 + 3.3F 1% 100k1/2 1% 100k1/2
Figure 7. Regulator with Early Warning and Auxillary Output
+VIN *High input lowers VOUT to 2.5V. 8 470k1/2 5 470k1/2 RC2951 3 Reset SD GND 4 1N 4001 FB 7 R2 R1 + 1F 4 20mA 8 VIN VOUT RC2951 FB 0.1F GND 4 1N457 360 7 2 4 * High for IL < 3.5mA 1 1 +VIN ERROR 1 VOUT +5V 4.7k1/2 Output* 5 VOUT
Figure 10. 5V Regulator with 2.5V Sleep Function
Figure 8. Latch Off When Error Flag Occurs
Min. Voltages A 4V
2950-13
Figure 11. Open Circuit Detector for 4mA to 20mA Current Loop
8
PRODUCT SPECIFICATION
RC2951
Typical Applications (continued)
8 39k1/2 RESET 5 +VIN 2 SENSE VOUT 1 +VOUT = 5V + 1F FB VTAP 6 7
ERROR
RC2951 - *C4 + 3 SD GND 39k1/2 4
+
6V Lead-Acid Battery
1%
100 k1/2
- C1 +
100k1/2 < 5.8V** 100k1/2 < 6.0V**
Preliminary Information
1%
1k1/2
- C2 +
C1-C4 LP339
1%
1k1/2
- C3 +
100k1/2 < 6.2V**
10k1/2 R3 1% 20k1/2
*Optional Latch off when drop out occurs. Adjust R3 for C2 Switching when Vin is 6.0V. **Outputs go low whenVin drops below designated thresholds.
Figure 12. Regulator with State-of-Charge Indicator
For values shown, Regulator shuts down when Vin < 5.5V and turns on again at 6.0V. Current drain in disconnected mode is A 150 A. + 6V Sealed Lead-Acid Battery Source
120k1/2
1.5k1/2** 8 +VIN 1 VOUT RC2951 3 SENSE SD GND 4 FB VTAP 6 1F 2 7 201/2 + + Ni-cad Backup Battery Memory V+ Main V+
+ FB LM385 -
1N457
A 400k1/2* for 5.5V
100k1/2
*Sets disconnect Voltage **Sets disconnect Hysteresis
2950-14
Figure 13. Low Battery Disconnect
9
RC2951
PRODUCT SPECIFICATION
Notes:
Preliminary Information
10
PRODUCT SPECIFICATION
RC2951
Mechanical Dimensions - 8 Lead SOIC
Symbol A A1 B C D E e H h L N a ccc Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
.053 .069 .004 .010 .013 .020 .008 .010 .189 .197 .150 .158 .050 BSC .228 .010 .016 8 0 -- 8 .004 .244 .020 .050
1.35 1.75 0.10 0.25 0.33 0.51 0.20 0.25 4.80 5.00 3.81 4.01 1.27 BSC 5.79 0.25 0.40 8 0 -- 8 0.10 6.20 0.50 1.27
3 6
Preliminary Information
8
5
E
H
1
4
D A1 A SEATING PLANE B -C- LEAD COPLANARITY ccc C a
h x 45 C
e
L
11
RC2951
PRODUCT SPECIFICATION
Ordering Information
Product Number RC2951M RC2951M-3.3 Package 8 pin SOIC 8 pin SOIC
Preliminary Information
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS30002951 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC3403A
Ground Sensing Quad Operational Amplifier
Features
* Class AB output stage - no crossover distortion * Output voltage swings to ground in single supply operation * High slew rate - 1.2 V/mS * Single or split supply operation * Wide supply operation - +2.5V to +36V or 1.25V to 18V * Pin compatible with LM324 and MC3403 * Low power consumption - 0.8 mA/amplifier * Common mode range includes ground
Description
The RC3403A is a high performance ground sensing quad operational amplifier featuring improved dc specifications equal to or better than the standard 741 type general purpose op amp. The ground sensing differential input stage of this op amp provides increased slew rate compared to 741 types.
Block Diagram
Output (A) -Input (A) +Input (A) +Input (B) -Input (B) Output (B)
65-3403A-01
Pin Assignments
Output (D) -Input (D) +Input (D) +Input (C) Output (A) -Input (A) +Input (A) +VS Output (D) -Input (D) +Input (D) -VS +Input (C) -Input (C) Output (C)
65-3403A-02
A +
D +
+ B
C
+ -Input (C) Output (C)
+Input (B) -Input (B) Output (B)
Rev. 1.0.0
PRODUCT SPECIFICATION
RC3403A
Absolute Maximum Ratings
(beyond which the device may be damaged)1 Parameter Supply Voltage Input Voltage Differential Voltage PDTA < 50C Operating Temperature Storage Temperature Junction Temperature Lead Soldering Temperature (60 seconds) For TA > 50C Derate at 6.25mW/C
Notes: 1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded.
Min -0.3
Typ
Max +36 or 18 36 36 468
Units V V V mW C C C C
0 -65
70 150 125 300
Operating Conditions
Parameter qJA Thermal resistance Min Typ 160 Max Units C/W
Low Voltage Electrical Characteristics
+VS = +5V, -VS = GND, and TA = +25C Parameter Input Offset Voltage Input Bias Current Input Offset Current Supply Current Large Signal Voltage Gain Output Voltage Swing1 Channel Separation Power Supply Rejection Ratio
Note: 1. Output will swing to ground.
Conditions
Min
Typ 2.0 -150 30
Max 10 -500 50 5.0
Units mV nA nA mA V/mV Vp-p dB dB
RL = All Amplifiers RL 2kW RL 10kW 1kHz F 200kHz (Input referred) 76 20 3.5
2.5 200 120
Electrical Characteristics
+VS = 15V, 0C TA +70C Parameter Input Offset Voltage Input Bias Current Input Offset Current Large Signal Voltage Gain Output Voltage Swing 2 RL 2kW RL 2kW 15 10 Conditions Min Typ Max 10 -800 200 Units mV nA nA V/mV V
RC3403A
PRODUCT SPECIFICATION
Electrical Characteristics
Parameter Input Offset Voltage Input Bias Current Input Offset Current Input Voltage Range Supply Current Large Signal Voltage Gain Output Voltage Swing1 Common Mode Rejection Ratio Channel Separation Output Source Current Output Sink Current Unity Gain Bandwidth Slew Rate Distortion (Crossover) Power Bandwidth Power Supply Rejection Ratio
Note: 1. Significantly improved performance.
+VS = 15V, TA = +25C Conditions Min Typ 2.0 -150 30 0 RL = On All Op Amps RL 2kW RL 10kW DC 1 kHz to 20kHz +VIN = 1V, -VIN = 0V 20 10 AV = 1, -10 VIN < +10 F = 20kHz, VOUT = 10Vp-p VOUT = 10Vp-p 80 251 13 70 3.0 100 14 90 120 40 20 1.0 1.21 1.0 40 94 Max 6.0
1
Units mV nA nA V mA V/mV V dB dB mA mA MHz V/mS % kHz dB
-500 50 +VS - 2 5.0
1
Electrical Characteristics Comparison - RC3403A, MC3403, LM324
MAX Ratings Supply Voltage Differential Input Voltage Input Voltage Electrical Characteristics Test Conditions Input Offset Voltage Input Offset Current Input Bias Current Input Voltage Range Supply Current Large Signal Voltage Gain Output Voltage Swing Common Mode Rejection Ratio Power Supply Rejection Ratio Unity Gain Bandwidth Slew Rate Output Sink Current Output Source Current Channel Separation Distortion (Crossover) 10 20 25 13 70 80 0 3.0 100 14 90 94 1.0 1.2 20 40 120 1.0 120 1.0 20 Min RC3403A +36 or 18 36 36 Typ 15 2.0 30 150 6.0 50 500 +VS - 2 5.0 20 10 70 76 0 2.8 200 13 90 90 1.0 0.6 0 85 85 1.0 0.4 20 40 120 Max Min MC3403 +36 or 18 36 36 Typ 15 2.0 30 200 8.0 50 500 +VS - 2 7.0 0 0.8 100 +VS - 1.5 Max Min LM324 +32 or 16 32 32 Typ +5.0 2.0 5.0 45 7.0 50 500 +VS - 1.5 2.0 Max Unit V V V Unit V mV nA nA V mA V/mV V dB dB MHz V/mS mA mA dB %
3
PRODUCT SPECIFICATION
RC3403A
Typical Performance Characteristics
120 100 80 AVOL (dB) 60 50 mV/Div. 40
65-3403A-03
VS = 15V TA = +25 C
5.0V/Div.
A V = 100
0 -20 1 10 100 1K F (Hz) Figure 1. Open Loop Gain vs. Frequency 10K 100K
1M 50 S/Div. Figure 2. Sinewave Response
30 25 VOUT P-P (V) 20 15 10
65-3403A-05
40
VS = 15V TA = +25 C R L = 10 k W TA = +25C
30 VOUT P-P (V)
20
0 -5 1 10K 100K F (Hz) Figure 3. Output Voltage vs. Frequency 1M
10M
0
0
2 4
6 8 10 12 14 16 18 20 +VS /-VS (V)
Figure 4. Output Swing vs Supply Voltage
400
180
300 IB (nA)
VS =
15V
170 IB (nA)
200
160
65-3403A-08
65-3403-07
100
0 -75 -55 -35 -15 +5 +25 +45 +65 +85 +105+125 TA (C) Figure 5. Input Bias Current vs. Temperature
150 0 2 4 6
8 10 12 14 16 18 20 +VS/-VS (V)
Figure 6. Input Bias Current vs. Supply Voltage
4
65-3403A-06
5
10
65-3403A-04
20
Note: Class AB output stage produces distortionless sinewave
RC3403A
PRODUCT SPECIFICATION
Typical Applications
R1 30K 2 R2 150K 1/4 3 3403A 0.01F R4 100K VOUT R3 100K R5 100K 0
65-3403A-09
1N914
1 VOUT
Figure 7. Pulse Generator
VREF = VREF
+VS 2 3 1/4 3403A C 1
Trianglewave Output R3 75K 5
R2 300K
Squarewave Output
2
R1 100K RF
1/4 6 3403A
7
F=
R2R1 R1 + R2 if R3 = R2 + R1 4CRFR1
VREF
65-3403A-10
Figure 8. Function Generator
R1 1M (+) VR (-)
+VS 3 1/4 2 3403A R4 1M 1 VOUT R2 10K 3 +VS 1 VOUT
R2 1M
1/4 2 3403A
R1 10K VOUT =
R3 1M +VCM
R1 +V = S (As shown) R2 + R1 2 +VS 2
65-3403A-12
VOUT = VR
65-3403A-11
VOUT =
Figure 9. Ground Referencing a Differential Input Signal
Figure 10. Voltage Reference
5
PRODUCT SPECIFICATION
RC3403A
Typical Applications (continued)
0.05F R 100K +VC 51K R/2 50K
2 1/4 3 3403A +VS 2 1
6 1/4 5 3403A 10K 51K Output 2 7 Output 1
51K 10K Note: Wide control voltage ranges: 0V VC 2 (+VS - 1.5V)
65-3403A-13
Figure 11. Voltage Controlled Oscillator
R1 100K C1 0.1F 2 CIN
R2 1M
AV = 1 +
R1 R2 CIN R1 10K 2
RF 100K
AV = 11 (As shown) 1/4 3 3403A 1 RB 6.2K R3 1M R4 100K -VS (-) C2 10F R5 100K 0
65-3403A-14
CO VOUT RL +VS + RF R1 VIN R2 100K
1/4 3 3403A
1 RB 6.2K
CO
RL 10K
(+) VIN
C1 10F
AV =
2VP-P
AV = 10 (As shown) 2VP-P
65-3403A-15
Figure 12. AC Coupled Non-Inverting Amplifier
Figure 13. AC Coupled Inverting Amplifier
C1 C2 R1 1K R2 1K
R3 2 3 1/4 3403A 1
F O D Center Frequency BW D Bandwidth R in k W C in F Q= Fo BW < 10 Q 3
Design Example: Given: Q = 5, F o = 1 kHz Let R1 = R2 = 10 k W Then R3 = 9 (5) 2 - 10 R3 = 215 k W C= 5 = 1.6 nF 3
C1 = C2 = + 10F R1 = R2 = 1 R3 = 9Q 2- 1
Use scaling factors in these expressions.
65-3403A-16
VREF
If source impedance is high or varies, filter may be preceeded with voltage follower buffer to stabilize filter parameters.
Figure 14. Multiple Feedback Bandpass FIlter
6
RC3403A
PRODUCT SPECIFICATION
Typical Applications (continued)
R2 VOH VREF VIN R1 2 1/4 3 3403A 1 VOUT VOUT Hysteresis VINL = VINH = H= R1 R1 + R2 R1 R1 + R2 (VOL - V REF) + VREF (V OH - VREF ) + VREF (V OH - VOL )
VOL V INL VINH V REF
R1 R1 + R2
65-3403A-17
Figure 15. Comparator with Hysteresis
R6 V1 3 1/4 2 3403A R1 1 R2 6 1/4 5 3403A 7 VOUT
R3 R4 9 1/4 10 3403A 8 R5
VOUT = C (1 + a + b) (V2 - V1) R2 R6 = R5 R7 R1 = R4 R2 = R5 Gain = R6 ( 1 + 2R1 ) = C (1 + a + b) R2 R3 for best CMRR
V2
R7
65-3403A-18
Figure 16. High Impedance Differential Amplifier
50K 5K VOUT
+VS VS 10K 2 1/4 3 3403A VREF = +VS 2 R
65-3403A-19
1
R
C
C
Fo =
1 for FO = 1kHz 2 p RC R = 16 k W C = 0.01 F
Figure 17. Wein Bridge Oscillator
7
PRODUCT SPECIFICATION
RC3403A
Typical Applications (continued)
R R C 100K VIN C1 R2 C 2 1/4 3 3403A 1 VREF 5 R1 R2 Bandpass Output 13 1/4 12 3403A
65-3403A-20
Q=
FO
BW Where: TBP = Center Frequency Gain T N = Bandpass Notch Gain
100K
6 1/4 3403A R3 7 100K 9 1/4 10 3403A VREF 8
FO =
1 2 p RC
VREF
R1 = QR R2 = R1 T BP
14
C1 Notch Output
R3 = T N R2 C1 = 10C
VREF
Example: F O = 1000 Hz BW = 100 Hz T BP = 1 TN = 1 R = 160 k W R1 = 1.6 M W R2 = 1.6 M W R3 = 1.6 M W C = 0.001F
Figure 18. Bi-Quad Filter
Simplified Schematic Diagram (1/4 Shown)
+Vs (4) Q26B Q27 Q26A Q26C Q25 Q24 Q23 Q22 Q3 + Input (3,5,10,12) Q1 Q5 Q2 R4 400 Q14 (2,6,9,13) Q18 Q21 R6 20 Output (1,7,8,14)
Q4
Q6
- Input
CC 7 pF Q7 Q8
Q17 Q13 R3 15K R1 2K Q15 R2 2K Q16
R5 50 Q20
Q9
Q10
Q11
Q12
Q19
-VS or GND (11)
65-3403A-21
8
RC3403A
PRODUCT SPECIFICATION
Mechanical Dimensions - 14-Lead Plastic DIP Package
Symbol A A1 A2 B B1 C D D1 E E1 e eB L N Inches Min. -- .015 .115 Max. .210 -- .195 Millimeters Min. -- .38 2.93 Max. 5.33 -- 4.95 Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E1" do not include mold flashing. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. Terminal numbers are shown for reference only. 4. "C" dimension does not include solder finish thickness. 5. Symbol "N" is the maximum number of terminals. 4 2
.014 .022 .045 .070 .008 .015 .725 .795 .005 -- .300 .325 .240 .280 .100 BSC -- .430 .115 .200 14
.36 .56 1.14 1.78 .20 .38 18.42 20.19 .13 -- 7.62 8.26 6.10 7.11 2.54 BSC -- 10.92 2.92 5.08 14
2
5
D 7 1
E1
D1
8
14
E e A A1 L B1 B eB C
9
PRODUCT SPECIFICATION
RC3403A
Ordering Information
Product Number RC3403AN Temperature Range 0 to 70C Screening Commercial Package 14 Pin Plastic DIP Package Marking RC3403AN
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS30003403A O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC40-XX
Sense Resistors for Fairchild Semiconductor DC-DC Controllers
Features
* Resistor typical tolerance 5% * Resistance wire TCR +20ppm/C * Wire alloy MnCu (mangnin)
Design Equations
The design of the sense resistor must consider carefully the output requirements during normal operation and during a fault condition. If the sense resistor is too high, it may develop enough voltage drop accross it to trip the short circuit detect circuitry so that the DC-DC converter may not be able to deliver the maximum required load current. If the sense resistor is too low, the controller may not be disabled when a certain safe amount of load current is exceeded, thus the power dissipation within the MOSFET(s) may rise to destructive levels. The design equations used to calculate the sense resistor are as follows: I SC ( MIN ) = ( I LOAD + I R + 1 ) V TH ( MIN ) R SENSE ( MAX ) = --------------------------I SC ( MIN ) and, assuming a 10% tolerance, the nominal design value of the sense resistor is given by: R SENSE ( MAX ) R SENSE = --------------------------------------( 1 + 0.10 )
Resistor Dimensions
Type RC40-58 RC40-44 R (mW) 5.8 4.4 D (mm) 1.00 1.00 L (mm) 9.3 7.1 H (mm) 5.0 5.0
Advanced Information
L
H
D
Applications
Controller Type RC5036 RC5036 RC5041/RC5042 RC5041/RC5042 RC5050/RC5051 RC5050/RC5051 ILmax (A) 10 14 13 18 13 18 Rsense Type RC40-58 RC40-36 RC40-58 RC40-36 RC40-58 RC40-36
Wire Sense Resistors
There are several types of sense resitors available to the system designer in a wide range of cost and specifications. The resistors with higher precision (i.e. 1% SMT) demand the highest cost (i.e. $0.47); however a 10% to 15% tolerance is adequate for most DC-DC converters designs and wire resistors offer a very cost effective alternative. Mangnin or Copel wire resistors, made respectively of MnCu and CuNi alloys, have been used extensively in the manufacture of sense resistors used in the Fairchild Semiconductor's family of DC-DC converters. These resistive wires are available in all the most common gages and Table 1 and 2 describe the specifications of Mangnin and Copel for various diameter wire size. Wire with diameter of ~1 mm is best suited to make sense resistors for DC-DC converters used in motherboard applications. Refer to Figure 1 for the typical shape of a wire sense resistor and Graph 1 through 4 for the dimensions of the resistor as function of the load current requirements of the converter. Rev. 0.5.1
System Requirements
The design of the sense resistor is driven by the following system requirements: 1. 2. Load current, (ILOAD). This is the full load DC current the converter is designed to support. The controller short circuit current detect threshold voltage (VTH), which for Fairchild Semiconductor family of Controllers is specified at 120+/-20mV for RC5040/41/ 42/50/51 or 90 10mV for RC5036. The inductor current ripple (IR). A reasonable design guideline is to assume the current ripple is limited to 1.5A.
3.
ADVANCED INFORMATION describes products that are in the planning or early design stage. Specifications may change in any manner without notice. Contact Fairchild Semiconductor for current information.
RC40-XX
PRODUCT SPECIFICATION
Table 1. Mangnin Wire Resistor Specifications Diameter (mm) 1.40 1.30 1.10 1.00 0.90 0.80
Note: 1. J = 104 A/cm2
Table 2. Copel Wire Resistor Specifications AWG 15 16 17 18 19 20 Diameter (mm) 1.45 1.29 1.15 1.02 0.912 0.812 W/ft 0.09049 0.11300 0.14520 0.18370 0.22690 0.28710 mW/m 0.30 0.37 0.48 0.60 0.74 0.94 Imax (Amp) 165 131 104 82 65 52
W/m 0.31831 0.36916 0.51561 0.62389 0.77023 0.97482
mW/mm 0.318 0.369 0.516 0.624 0.770 0.975
Imax (Amp) 154 133 95 79 64 50
Note: 1. J = 104 A/cm2
Advanced Information
L
H = 5.0mm
Figure 1. Manganin or Copel Wire Resistor
2
PRODUCT SPECIFICATION
RC40-XX
Rsense L (mm) vs. ILOAD (A) Copel (AWG 18) 24.0 22.0 20.0 18.0 16.0 14.0 12.0 10.0 8.0 6.0 4.0 2.0 0.0 6 8 10 12 14 16 18 20 22 24 RC5041/42/50/51 ILOAD (A) 26 28 30 24.0 22.0 20.0 18.0 16.0 14.0 12.0 10.0 8.0 6.0 4.0 2.0 0.0
Rsense L (mm) vs. ILOAD (A) Mangnin (dia = 1mm)
Rsense L (mm)
Rsense L (mm)
6
8
10
12 14 16 18 20 22 24 RC5041/42/50/51 ILOAD (A)
26
28
30
Graph 1. Rsense vs. Imax (Copel)
Rsense L (mm) vs. ILOAD (A) Copel (AWG 18) 18.0 16.0 14.0 Rsense L (mm) 12.0 10.0 8.0 6.0 4.0 2.0 0.0 6 8 10 12 14 16 18 20 22 RC5036 ILOAD (A) 24 26 28 30 Rsense L (mm) 16.0 14.0 12.0 10.0 8.0 6.0 4.0 2.0 0.0 6
Graph 2. Rsense vs. Imax (Magnin)
Advanced Information
Rsense L (mm) vs. ILOAD (A) Mangnin (dia = 1mm)
8
10
12
14 16 18 20 22 RC5036 ILOAD (A)
24
26
28
30
Graph 3. Rsense vs. Imax (Copel)
Graph 4. Rsense vs. Imax (Magnin)
3
RC40-XX
PRODUCT SPECIFICATION
Advanced Information
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonable expected to result in a significant injury of the user.
Fairchild Semiconductor Corporation Americas Customer Response Center Tel:1-888-522-5372 Fairchild Semiconductor Europe Fax: Email: Deutsch Tel: English Tel: Italy Tel: +49 (0) 1 80-530 85 86 europe.support@nsc.com +49 (0) 8 141-35-0 +44 (0) 1 793-85-68-56 +39 (0) 2 57 5631
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
Fairchild Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Center, 5 Canto Rd. Tsimshatsui, Kowloon Hong Kong Tel:+852 2737-7200 Fax:+852 2314-0061
National Semiconductor Japan Ltd. Tel:81-3-5620-6175 Fax:81-3-5620-6179
www.fairchildsemi.com 2/98 0.0m Stock#DS300040-XX O 1998 Fairchild Semiconductor Corporation
www.fairchildsemi.com
RC4136
General Performance Quad 741 Operational Amplifier
Features
* * * * Unity gain bandwidth - 3 MHz Short circuit protection No frequency compensation required No latch-up * * * * Large common mode and differential voltage ranges Low power consumption Parameter tracking over temperature range Gain and phase match between amplifiers
Description
The RC4136 is made up of four 741 type independent high gain operational amplifiers internally compensated and constructed on a single silicon chip using the planar epitaxial process. This amplifier meets or exceeds all specifications for 741 type amplifiers. Excellent channel separation allows the use of the RC4136 quad amplifier in all 741 operational amplifier applications providing the highest possible packaging density. The specially designed low noise input transistors allow the RC4136 to be used in low noise signal processing applications such as audio preamplifiers and signal conditioners.
Block Diagram
-Input (A) +Input (A) Output (A) -Input (D) +Input (D) Output (D)
Pin Assignments
-Input (A) +Input (A) Output (A) Output (B) +Input (B) -Input (B) -VS
1 2 3 4 5 6 7 14 13 12 11 10 9 8 65-4136-02
A +
D +
Output (B) -Input (B) B C +
65-4136-01
Output (C) +Input (C) -Input (C) +
-Input (D) +Input (D) Output (D) +VS Output (C) +Input (C) -Input (C)
+Input (B)
Rev. 1.0.0
PRODUCT SPECIFICATION
RC4136
Absolute Maximum Ratings
(beyond which the device may be damaged)1 Parameter Supply Voltage Input Voltage
2
Min RC4136 RM4136
Typ
Max 18 22 30 30
Units V V V V mW mW mW C C C C C C C
Differential Input Voltage Output Short Circuit PDTA < 50C Duration3 SOIC PDIP CerDIP Operating Temperature Storage Temperature Junction Temperature Lead Soldering Temperature (60 seconds) SOIC, PDIP CerDIP DIP SOIC RC4136 RM4136 0 -55 -65 Indefinite
300 468 1042 70 125 150 125 175 300 260
Notes: 1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded. 2. For supply voltages less than 15V, the absolute maximum input voltage is equal to the supply voltage. 3. Short circuit may be to ground, typically 45 mA.
Operating Conditions
Parameter qJC qJA Thermal resistance Thermal resistance SOIC PDIP CerDIP For TA > 50C Derate at SOIC Min Typ 60 200 160 120 5.0 Max Units C/W C/W C/W C/W mW/C
2
RC4136
PRODUCT SPECIFICATION
Electrical Characteristics
(VS = 15V and TA = +25C, unless otherwise noted) RM4136 Parameters Input Offset Voltage Input Offset Current Input Bias Current Input Resistance Large Signal Voltage Gain Output Voltage Swing Input Voltage Range Common Mode Rejection Ratio Power Supply Rejection Ratio Power Consumption Transient Response Rise Time Overshoot Unity Gain Bandwidth Slew Rate Channel Separation RL 2kW F = 1.0kHz, RS =1kW VIN = 20mV, RL = 2kW CL 100pF 0.13 5.0 3.0 1.5 90 0.13 5.0 3.0 1.0 90 mS % MHz V/mS dB RS 10kW RS 10kW RL = , All Outputs RL 2kW, VOUT = 10V RL 10kW RL 2kW 0.3 50 12 10 12 70 76 Test Conditions RS 10kW Min Typ 0.5 5.0 40 5.0 300 14 13 14 100 100 210 340 Max 5.0 200 500 0.3 20 12 10 12 70 76 Min RC4136 Typ 0.5 5.0 40 5.0 300 14 13 14 100 100 210 340 V dB dB mW Max 6.0 200 500 Units mV nA nA MW V/mV V
Electrical Characteristics
(RM = -55C TA = 125, RC = 0C TA = 70, VS = 15V) RM4136 Parameters Input Offset Voltage Input Offset Current Input Bias Current Large Signal Voltage Gain Output Voltage Swing Power Consumption RL 2kW, VOUT = 10V RL 2kW 25 10 240 400 Test Conditions RS 10kW Min Typ Max 6.0 500 1500 15 10 240 400 Min RC4136 Typ Max 7.5 300 800 Units mV nA nA V/mV V mW
3
PRODUCT SPECIFICATION
RC4136
Electrical Characteristics Comparison
(VS = 15V and TA +25C unless otherwise noted) Parameter Input Offset Voltage Input Offset Current Input Bias Current Input Resistance Large Signal Voltage Gain (RL = 2kW) Output Voltage Swing (RL= 2kW) Input Voltage Range Common Mode Rejection Ratio Power Supply Rejection Ratio Transient Response Rise Time Overshoot Unity Gain Bandwidth Slew Rate Input Noise Voltage Density (F= 1kHz) Short Circuit Current 0.13 5.0 3.0 1.0 10 45 0.3 5.0 0.8 0.5 22.5 25 0.8 0.5 mS % MHz V/mS nV/OHz mA RC4136 (Typ.) 0.5 5.0 40 5.0 300 13V 14V 100 100 RC741 (Typ.) 2.0 10 80 2.0 200 13V 13V 90 90 100 |+VS - 1.2V| to -VS |+VS - 1.5V| to -VS 85 100 LM324 (Typ.) 2.0 5.0 55 Units mV nA nA MW V/mV V V dB dB
4
RC4136
PRODUCT SPECIFICATION
Typical Performance Characteristics
100 80 IB (nA) 60 40
65-4136-03
25
VS = 15V
20 IOS (nA) 15 10 5 0 0
VS =
15V
20 0
0
+10
+20
+30
+40
+50
+60
+70
+10
+20
+30
+40
+50
+60
+70
TA (C) Figure 1. Input Bias Current vs. Temperature
TA (C) Figure 2. Input Offset Current vs. Temperature
15 10 5 0 -5
65-4136-05
15
T A = +25 C
10 5 VOUT (V) 0 -5 -10 -15 4
T A = +25 C
VCM (V)
-10 -15 4 6 8 10 12 14 16
RL = 2 k W
18
6
8
10
12
14
16
18
VS (V) Figure 3. Input Common Mode Voltage Range vs. Supply Voltage
+VS/-VS (V) Figure 4. Output Voltage vs. Supply Voltage
800K 240
VS = 15V VS = 15V
600K AVOL (V/mV) PC (mW)
220 200 180 160 0 +10 +20 +30 +40 +50 +60
65-4136-08
400K
RL = 2 k W
65-4136-07
200K
0
0
+10
+20
+30
+40
+50
+60
+70
+70
TA (C) Figure 5. Open Loop Gain vs. Temperature
TA (C) Figure 6. Power Consumption vs. Temperature
65-4136-06
65-4136-04
5
PRODUCT SPECIFICATION
RC4136
Typical Performance Characteristics (continued)
120 100 80 60 40 20
65-4136-09
0 -20 1 10 100 1K 10K 100K F (Hz) Figure 7. Open Loop Gain vs. Frequency 1M
10M
40 36 32 28 24 20 16 12 8 4 0 100
VOUT P-P (V)
AVOL (dB)
VS = 15V T A = +25 C RL = 2 k W
1K
10K F (Hz)
100K
1M
Figure 8. Output Voltage Swing vs. Frequency
28 26 24 22 20 18 16 14 12 10 8 0.1
10
VS = 15V TA = +25 C TA = +25C
8 IQ (mA) 6 4 2 0 3 6 9 12 15
65-4136-12
VOUT P-P (V)
65-4136-11
1.0 RL (kW)
10
0
18
+VS/-VS (V) Figure 10. Quiescent Current vs. Supply Voltage
Figure 9. Output Voltage Swing vs. Load Resistance
10 8 6 4 2 0 -2 -4 -6 -8 -10 0 10
28
VS = 15V TA = +25 C
24 20 VOUT (mV) 16 12 8 4 0 0
10% Rise Time 90% VS = 15V T A = +25 C RL = 2 k W C L = 100 pF
65-4136-14
Output
VOUT (V)
Input
65-4136-13
20 30 Time (S)
40
0.25
0.50 Time (S)
0.75
1.00
1.25
Figure 11. Follower Large Signal Pulse Response
Figure 12. Transient Response Output Voltage vs. Time
6
65-4136-10
RC4136
PRODUCT SPECIFICATION
Typical Performance Characteristics (continued)
140 120 100 THD (%) CS (dB) 80 60 40
65-4136-15
0.6 0.5 0.4 0.3 0.2
VS = 15V TA = +25 C
VOUT = 1 VRMS VS = 30V
20 0 10
0.1 0 10 100 1K F (Hz) 10K
100
1K F (Hz)
10K
100K
100K
Figure 13. Channel Separation vs. Frequency
Figure 14. Total Harmonic Distortion vs. Frequency
0.6 0.5 THD (%) 0.4 0.3 0.2 0.1 0 1 2
VS = 15V R L = 2K A V = 40 dB f = 1 kHz RS = 1k W
3
4
5
6
7
8
9
10
VOUT (V RMS ) Figure 15. Total Harmonic Distortion vs. Output Voltage
65-4136-17
65-4136-16
7
PRODUCT SPECIFICATION
RC4136
RC4136 Versus LM324
Although the LM324 is an excellent device for single-supply applications where ground sensing is important, it is a poor substitute for four 741s in split supply circuits. The simplified input circuit of the RC4136 exhibits much lower noise than that of the LM324 and exhibits no crossover distortion as compared with the LM324 (see Figure 16). The LM324 shows significant crossover distortion and pulse delay in attempting to handle a large signal input pulse.
4136
324
F = 10 kHz VOUT = 8 VP-P
F = 50 kHz V OUT = 8 V P-P
RL = 2 k W AV= 1 VS = 5V
65-4136-18
Figure 16. Comparative Crossover Distortion
40 36 32 28 24 20 16 12 8 4 0 100
120
VS = 15V T A = +25 C R L = 2 kW
100 80 AVOL (dB) 60 40
65-4136-20
4136 741
VOUT P-P (V)
4136 741 324
65-4136-19
20 0 -20 1 10 100 1K 10K 100K F (Hz) Figure 18. Open Loop Gain vs. Frequency 1M
1K
10K F (Hz)
100K
1M
10M
Figure 17. Output Voltage Swing vs. Frequency
8
RC4136
PRODUCT SPECIFICATION
RC4136 Versus LM324 (continued)
+8 +6 +4 VOUT (V) +2 0 -2 -4 -6 -8 0 30 40 Time (S) Figure 19. Follower Large Signal Pulse Response Output Voltage vs. Time 60
Input
65-4136-21
16
Vs = 10V RL = 2 kW Outputs 324
14 12 +VCM (V) 10 8 6 4 2 0 5 10 15 +VS/-VS (V) Figure 20. Input Common Mode Voltage Range vs. Supply Voltage
741 4136 0 C = T A < +70 C
4136
80
20
Typical Applications
+Vs 910K +Vs +Vs 1 1 2 4136A 3 100W 100K 2 5K 91K AV = 10
65-0520
4136A
3 VOUT 100K
+VIN
65-0523
Figure 21. Lamp Driver
Figure 22. Power Amplifier
VIN 1 VIN 2 4136A 3 VOUT
65-0519
2 10K 1 4136A 10M
65-0522
3
VOUT
+VREF
Figure 23. Voltage Follower
Figure 24. Comparator with Hysteresis
65-4136-22
9
PRODUCT SPECIFICATION
RC4136
Typical Applications (continued)
+Vs VIN 16K 16K 1 0.01F 2 4136A 3 100K +Vs 100K 2 0.01F VOUT 0.001F 1 4136A 3 VoUT 1 0 100K 100K
65-0527
100K
100K
65-0521
Figure 25. DC Coupled 1kHz Lowpass Active Filter
Figure 26. Squarewave Oscillator
VIN
390K
0.01 F 120K 0.01 F 390K +Vs 1 4136A 2 4136B 5 10 F 100K 100K 3 39K 6 4 +Vs VoUT
620K 620W
+Vs
65-0526
Figure 27. 1kHz Bandpass Active Filter
1M 100K +Vs 1 VIN 2 4136A 3 VoUT +Vs 100K 10K 100K 0.1 F 10 F
65-0524
+Vs VIN 100K 10K 1 2 4136A 3 VoUT
+Vs 10K
65-0525
100K
10 F
100K
10K
Figure 28. AC Coupled Non-Inverting Amplifier
Figure 29. AC Coupled Inverting Amplifier
10
RC4136
PRODUCT SPECIFICATION
Typical Applications (continued)
0.05 F R 100K +VC* 51K 100K
1 2 4136A 3 51K 6 5 4136B 4 Output 1
R/2 50K
51K
V+/210K
Output 2
10K
65-0528
* Wide control voltage range: 0V < Vc < 2(+Vs -1.5V)
Figure 30. Voltage Control Oscillator (VCO)
20K 1%
20K 1%
2.5K Cal DC Output
4.7 F AC Input 4.7 F
20K 1%
20K 1% 10K 1% 1 2 D1 FD666 4136A 3 D2 FD666 4.7 F
6 5 5.1K
65-0531
4136B
4
10K
Figure 31. Full-Wave Rectifier and Averaging Filter
R2 30K R1 30K Input R3 15K 6 C1 5 R4 7.5K R4 7.5K 4136B 4
1 4136A 2 3 Output Trim R, such that R1 R3 = R2 2R4
10K 741 1K C1 ( mF)
100
65-0530
10 0.0001
C2 1 F
65-0529
0.001
0.001
0.01
1.0
Center Frequency (Hz) Figure 33. Notch Frequency vs. C1
Figure 32. Notch Filter Using the RC4136 as a Gyrator
11
PRODUCT SPECIFICATION
RC4136
Typical Applications (continued)
V IN V4 Q1 5 6 4136B 4 V3 < VIN < V4 2 1 4136A 3 VIN < V4
V3 Q2
9 8 4136C 10 V2 < V IN < V3
V2 Q3
13 V1 14 4136D 12 V IN < V1
65-0532
Figure 34. Multiple Aperture Window Discriminator
(-)
2 1 4136A 3
R2 10K 0.1% R1 45K 1%
R6* 100K 0.1%
5 6 4136B 4 R1 = R4 R2 = R5 R6 = R7 * Matching determines CMRR Av = R6 ( 1 + 2R1 ) R2 R3 VOUT
Inputs
R3 10K 1% R4 45K 1% 4136C 10 R5* 10K 0.1%
8 (+) 9
R7* 100K 0.1%
65-0533
Figure 35. Differential Input Instrumentation Amplifier with High Common Mode Rejection
12
RC4136
PRODUCT SPECIFICATION
Typical Applications (continued)
+15V 10K 10K
VIN1
10K
Q1* 1 2 4136A 3 1K
D4 IN457
10K 6
10K
D1 1N457
5
4136B
4 VoUT = (VIN1) (VIN2) VIN3
10K Q4*
Q2* V IN2 10K 8 10 9 10K 4136C 1K
Q3* 14 1K 12 4136D 13
10K VIN3
D2 1N457
D3 1N457
10K
65-0534
*Matched Transistors
Figure 36. Analog Multiplier/Divider
49.9K
3.3M 0.082 F
DC-1HzN Out
49.9W
100K 100K DUT
1.0 F
2 1 4136A 499K 3 60 dB Wideband Amplifier 10 F 1 Hz 499W 1 F 1000 F 0.1 F 0.01 F 1 kHz 10 F 1 Hz 499K 1 F 6 4 4136B 5 0.01 F 0.1 F
49.9W Compensate as Required
499K
78.7K
3.16K
3.16K 1 Hz 10K
Spot Noise Out
8 10 31.6K 4136C 9 100K
499W
1mV = 1nV/ Hz RMS Stepped 10 dB Attenuator
1 kHz
499K
1 kHz
Selectable Frequency Constant Q Filter
65-0535
Figure 37. Spot Noise Measurement Test Circuit
13
RC4136
PRODUCT SPECIFICATION
Simplified Schematic Diagram
+Vs (11) R1 8.7K Q5 Q10 Q14 (1,6,8,14) -Input +Input (2,5,9,13) D1 R5 50K Q1 Q2 Q13 Q12 R7 50 Q15 15 pF Q9 Q3 Q4 Q11 R9 15K R2 5K -Vs (7)
65-0495
Q6
R6 50
R8 100
Output (3,4,10,12)
Q7
Q8
Z1 5.5V
C1 30 pF
R3 5K
R4 50K
14
RC4136
PRODUCT SPECIFICATION
Mechanical Dimensions
14-Lead Ceramic DIP Package
Inches Min. A b1 b2 c1 D E e eA L Q s1 a Max. Millimeters Min. Max. 8 2 8 4 4 5, 9 7 3 6 Notes: Notes 1. Index area: a notch or a pin one identification mark shall be located adjacent to pin one. The manufacturer's identification shall not be used as pin one identification mark. 2. The minimum limit for dimension "b2" may be .023 (.58mm) for leads number 1, 7, 8 and 14 only. 3. Dimension "Q" shall be measured from the seating plane to the base plane. 4. This dimension allows for off-center lid, meniscus and glass overrun. 5. The basic pin spacing is .100 (2.54mm) between centerlines. Each pin centerline shall be located within .010 (.25mm) of its exact longitudinal position relative to pins 1 and 14. 6. Applies to all four corners (leads number 1, 7, 8, and 14). 7. "eA" shall be measured at the center of the lead bends or at the centerline of the leads when "a" is 90. 8. All leads - Increase maximum limit by .003 (.08mm) measured at the center of the flat, when lead finish applied. 9. Twelve spaces. D
7 1
Symbol
-- .200 .014 .023 .045 .065 .008 .015 -- .785 .220 .310 .100 BSC .300 BSC .125 .200 .015 .060 .005 -- 90 105
-- 5.08 .36 .58 1.14 1.65 .20 .38 -- 19.94 5.59 7.87 2.54 BSC 7.62 BSC 3.18 5.08 .38 1.52 .13 -- 90 105
NOTE 1
E
8
14
s1 eA
e
A Q L b2 b1 a c1
15
PRODUCT SPECIFICATION
RC4136
Mechanical Dimensions (continued)
14-Lead Plastic DIP Package
Inches Min. A A1 A2 B B1 C D D1 E E1 e eB L N -- .015 .115 Max. .210 -- .195 Millimeters Min. -- .38 2.93 Max. 5.33 -- 4.95 Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E1" do not include mold flashing. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. Terminal numbers are shown for reference only. 4. "C" dimension does not include solder finish thickness. 5. Symbol "N" is the maximum number of terminals. 4 2
Symbol
.014 .022 .045 .070 .008 .015 .725 .795 .005 -- .300 .325 .240 .280 .100 BSC -- .430 .115 .200 14
.36 .56 1.14 1.78 .20 .38 18.42 20.19 .13 -- 7.62 8.26 6.10 7.11 2.54 BSC -- 10.92 2.92 5.08 14
2
5
D 7 1
E1
D1
8
14
E e A A1 L B1 B eB C
16
RC4136
PRODUCT SPECIFICATION
Mechanical Dimensions (continued)
14-Lead SOIC Package
Inches Min. A A1 B C D E e H h L N a ccc Max. Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
Symbol
.053 .069 .004 .010 .013 .020 .008 .010 .336 .345 .150 .158 .050 BSC .228 .244 .010 .016 14 0 -- 8 .004 .020 .050
1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 8.54 8.76 3.81 4.01 1.27 BSC 5.79 6.20 0.25 0.40 14 0 -- 8 0.10 0.50 1.27
3 6
14
8
E
H
1
7
D A1 A SEATING PLANE -C- LEAD COPLANARITY ccc C a
h x 45 C
e
B
L
17
PRODUCT SPECIFICATION
RC4136
Ordering Information
Product Number RC4136N RC4136M RM4136D RM4136D/8831 Temperature Range 0 to 70C 0 to 70C -55C to +125C -55C to +125C Military Screening Commercial Commercial Package 14 Pin Plastic DIP 14 Pin Narrow SOIC 14 Pin Ceramic DIP 14 Pin Ceramic DIP Package Marking RC4136N RC4136M
Note: 1. /883 denotes MIL-STD-883, Par. 1.2.1 compliant device.
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS30004136 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC4152
Voltage-to-Frequency Converters
Features
* * * * * * * * * * * Single supply operation Pulse output DTL/TTL/CMOS compatible Programmable scale factor (K) High noise rejection Inherent monotonicity Easily transmittable output Simple full scale trim Single-ended input, referenced to ground V-F or F-V conversion Voltage or current input Wide dynamic range
* Signal isolation: - VFC--opto-isolaton--FVC - ADC with opto-isolation * Signal encoding: - FSK modulation/demodulation - Pulse-width modulation * Frequency scaling * DC motor speed control
Description
The RC4152 is a monolithic circuit containing all of the active components needed to build a complete voltage-tofrequency converter. Circuits that convert a DC voltage to a pulse train can be built by adding a few resistors and capacitors to the internal comparator, one-shot, voltage reference, and switched current source. Frequency-to-voltage converters (FVCs) and many other signal conditioning circuits are also easily created using these converters. The RC4151 was the first monolithic VFC available and offers guaranteed temperature and accuracy specifications. The converter is available in a standard 8-pin plastic DIP.
Applications
* * * * * * * Precision voltage-to-frequency converters Pulse-width modulators Programmable pulse generators Frequency-to-voltage converters Integrating analog-to-digital converters Long-term analog integrators Signal conversion: - Current-to-Frequency - Temperature-to-Frequency - Pressure-to-Frequency - Capacitance-to-Frequency - Frequency-to-Current
Functional Block Diagram
4152
Switched Current Source Output Switched Reference Output Open Collector Output
1
Switched Current Source
Voltage Reference Open Loop Comparator
8 -VS
2
Switched Voltage Reference
7
Comparator Inputs
3
Precision One Shot
6
Ground
4
Open Collector Logic Output Transistor
4152-01
5
One Shot Timing
Rev. 1.0.1
PRODUCT SPECIFICATION
RC4152
Pin Assignments
IOUT 1 RS 2 FOUT 3 GND 4 8 +VS 7 VIN 6 VTH 5 CO
4152-02
Pin Descriptions
Pin 1 2 3 4 5 6 7 8 Function Switched Current Source Output (IOUT) Switched Voltage Reference (RS) Logic Output (Open Collector) (FOUT) Ground (GND) One-Shot R, C Timing (CO) Threshold (VTH) Input Voltage (VlN) +VS
Absolute Maximum Ratings
Parameter Supply Voltage Internal Power Dissipation Input Voltage Output Sink Current (Frequency Output) Output Short Circuit to Ground Storage Temperature Range Operating Temperature Range RC4152 RV4152N 0 -25 +70 +85 C C -65 -0.2 Min. Typ. Max. +22 500 +VS 20 Continuous +150 C Units V mW V mA
Note: 1. "Absolute maximum ratings" are those beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. If the device is subjected to the limits in the absolute maximum ratings for extended periods, its reliability may be impaired. The tables of Electrical Characteristics provides conditions for actual device operation.
Thermal Characteristics
8-Lead Plastic DIP Max. Junction Temp. Max. PD TA<50C Therm. Res qJC Therm. Res qJC For TA>50C Derate at +125C 468 mW -- 160C/W 6.25 mW/C Small Outline SO-8 +125C 300mW -- 240C/W 4.17mW/C
2
RC4152
PRODUCT SPECIFICATION
Electrical Characteristics
(VS = +15V, and TA = +25C unless otherwise noted) Parameters Power Supply Requirements (Pin 8) Supply Current Supply Voltage Input Comparator (Pins 6 and 7) VOS Input Bias Current Input Offset Current Input Voltage Range One Shot (Pin 5) Threshold Voltage Input Bias Current Saturation Voltage Drift of Timing vs. Temperature2 I = 2.2 mA T = 75 ms over the specified temperature range 1)1 RS = 16.7K over specified temperature range Off State Pin 1 = 0V to +10V 1.0 2.0 over specified temperature range ISINK = 3 mA ISINK = 10 mA Off State 1.0 Hz to 10 kHz FOUT = 10 kHz, over specified temperature range +138 50 0.10 1.0 2.5 2.25 50 0.1 0.8 0.1 0.007 75 1.0 0.05 150 2.5 100 0.5 50 100 mA ppm/C %/V nA mA V ppm/C V V mA % ppm/C 0.65 0.67 -50 0.1 30 100 0.69 -500 0.5 50 VS nA V ppm/C ppm/V 0 2.0 -50 30 VS-2 10 -300 100 VS-3 mV nA nA V VS = +15V +7.0 2.5 +15 6.0 +18 mA V Test Conditions Min. Typ. Max. Units
Timing Drift vs. Supply Voltage Switched Current Source (pin Output Current Drift vs. Temperature2 Drift vs. Supply Voltage Leakage Current Compliance Reference Voltage (Pin 2) VREF Drift vs. Temperature2 Logic output (Pin 3) Saturation Voltage Leakage Current Nonlinearity Error (Voltage Sourced Circuit of Figure 3) Temperature Drift (Voltage Sourced Circuit of Figure 3) Voltage2
Notes: 1. Temperature coefficient of output current source (pin 1 output) exclusive of reference voltage drift. 2. Guaranteed but not tested.
3
PRODUCT SPECIFICATION
RC4152
Typical Performance Characteristics
10 KHz Current-Sourced VFC Nonlinearity vs. Input Voltage +0.01 +0.005 NL (% Error) 0 -0.005 -0.01 -0.015 0 1 2 3 4 5 VIN (V) 6 7 8 9 10 NL (% Error) +0.06 +0.03 0 -0.03 -0.06 -0.09 0 1 2 3 4 5 VIN (V) 6 7 8 9 10 100 KHz Current-Sourced VFC Nonlinearity vs. Input Voltage
10 KHz Voltage-Sourced VFC Nonlinearity vs. Input Voltage +0.01 +0.005 NL (% Error) NL (% Error) 0 -0.005 -0.01 -0.015 0 1 2 3 4 5 VIN (V) 10 KHz Precision VFC Nonlinearity vs. Input Frequency +0.01 +0.005 NL (% Error) NL (% Error) 0 -0.005 -0.01 -0.015 0 1 2 3 4 5 6 7 8 9 10 +0.12 +0.08 +0.04 0 -0.04 -0.08 0 1 6 7 8 9 10 +0.10 +0.05 0 -0.05 -0.10 -0.15 0 1
100 KHz Voltage-Sourced VFC Nonlinearity vs. Input Voltage
2
3
4
5 VIN (V)
6
7
8
9
10
100 KHz Precision VFC Nonlinearity vs. Input Frequency
2
3
4
5
6
7
8
9
10
FIN (kHz)
FIN (kHz)
4
4152-03
RC4152
PRODUCT SPECIFICATION
Principles of Operation
The RC4152 contains the following components: an open loop comparator, a precision one-shot timer, a switched voltage reference, a switched current source, and an open collector logic output transistor. These functional blocks are internally interconnected. Thus, by adding some external resistors and capacitors, a designer can create a complete voltage-to-frequency converter. The comparator's output controls the one-shot (monostable timer). The one-shot in turn controls the switched voltage reference, the switched current source and the open collector output transistor. The functional block diagram shows the components and their interconnection. To detail, if the voltage at pin 7 is greater than the voltage at pin 6, the comparator switches and triggers the one-shot. When the one-shot is triggered, two things happen. First, the one-shot begins its timing period. Second, the one-shot's output turns on the switched voltage reference, the switched current source and the open collector output transistor. The one-shot creates its timing period much like the popular 555 timer does, by charging a capacitor from a resistor tied to +VS. The one-shot senses the voltage on the capacitor
(pin 5) and ends the timing period when the voltage reaches 2/3 of the supply voltage. At the end of the timing period, the capacitor is discharged by a transistor similar to the open collector output transistor. Meanwhile, during the timing period of the one-shot, the switched current source, the switched voltage reference, and the open collector output transistor all will be switched on. The switched current source (pin 1) will deliver a current proportional to both the reference and an external resistor, RS. The switched reference (pin 2) will supply an output voltage equal to the internal reference voltage (2.25V). The open collector output transistor we be turned on, forcing the logic output (pin 3) to a low state. At the end of the timing period all of these outputs will turn off. The switched voltage reference has produced an off-on-off voltage pulse, the switched current source has emitted a quanta of charge, and the open collector output has transmitted a logic pulse. To summarize, the purpose of the circuit is to produce a current pulse, well-defined in amplitude and duration, and to simultaneously produce an output pulse which is compatible with most logic families. The circuit's outputs show a pulse waveform in response to a voltage difference between the comparators inputs.
Integrator CB I OUT RB Switched Current Source
4152 1
Voltage Reference Open Loop Comparator +VS
8
100K V IN 0 to +10V
2
RS Current Setting Resistor RS = 16.7K
Switched Voltage Reference
7
0.01 m F
3
Precision One Shot
6
RO
R LOAD
Ground
4
F OUT
Open Collector Output
Open Collector Logic Output Transistor
5
CO
One Shot Timing
4152-04
Figure 1. Single Supply VFC
5
PRODUCT SPECIFICATION
RC4152
Applications
Single Supply VFC
The stand-alone voltage-to-frequency converter is one of the simplest applications for the RC4152. This application uses only passive external components to create the least expensive VFC circuit (see Figure 1). The positive input voltage VIN is applied to the input comparator through a low pass filter. The one-shot will fire repetitively and the switched current source will pump out current pulses of amplitude VREF/RS and duration 1.1 ROCO into the integrator. Because the integrator is tied back to the inverting comparator input, a feedback loop is created. The pulse repetition rate will increase until the average voltage on the integrator is equal to the DC input voltage at pin 7. The average voltage at pin 6 is proportional to the output frequency because the amount of charge in each current pulse is precisely controlled. Because the one-shot firing frequency is the same as the open collector output frequency, the output frequency is directly proportional to VIN. The external passive components set the scale factor. For best linearity, RS should be limited to a range of 12 kW to 20 kW The reference voltage is nominally 2.25V for the RC4152. Recommended values for different operating frequencies are shown in the table below.
Operating Range DC to 1.0 kHz DC to 10 kHz DC to 100 kHz
1 T = ------------F OUT TP V IN ----------- = I OUT ----T RB V REF I OUT = ------------RS where TP = 1.1 R O C O
By rearranging and substituting,
V IN R S 1 F OUT = ------------- ------ ---------------------V REF R B 1.1R O C O
Recommended component values for different operating frequencies are shown in the table below.
Range Input VIN Output FO Scale Factor
RO
CO
CI 0.05 mF
RB 100 kW
0 to -10V 0 to 1.0 kHz 0.1 KHz/V 6.8 kW 0.1 mF 0 to -10V 0 to 10 kHz 1.0 KHz/V 6.8 kW 0.01 mF
0.005 mF 100 kW 100 kW
0 to -10V 0 to 100 kHz 10 KHz/V 6.8 kW 0.001 mF 500 pF
The graphs shown under Typical Performance Characteristics show nonlinearity versus input voltage for the precision current sourced VFC. The best linearity is achieved by using an op amp having greater than 1.0 V/ms slew rate, but any op amp can be used.
Precision Voltage Sourced VFC
This circuit is identical to the current sourced VFC, except that the current pulses into the integrator are derived directly from the switched voltage reference. This improves temperature drift at the expense of high frequency linearity. The switched current source (pin 1) output has been tied to ground, and RS has been put in series between the switched voltage reference (pin 2) and the summing node of the op amp. This eliminates temperature drift associated with the switched current source. The graphs under the Typical Performance Characteristics show that the nonlinearity error is worse at high frequency, when compared with the current sourced circuit.
RO 6.8 kW 6.8 kW 6.8 kW
CO 0.1 mF 0.01 mF 0.001 mF
RB 100 kW 100 kW 100 kW
CB 10 mF 10 mF 10 mF
The single supply VFC is recommended for uses where dynamic range of the input is limited, and the input does not reach 0V. With 10 kHz values, nonlinearity will be less than 1.0% for a 10 mV to 10V input range, and response time will be about 135 ms.
Precision Current Sourced VFC
This circuit operates similarly to the single supply VFC, except that the passive R-C integrator has been replaced by an active op amp integrator. This increases the dynamic range down to 0V, improves the response time, and eliminates the nonlinearity error introduced by the limited compliance of the switched current source output. The integrator algebraically sums the positive current pulses from the switched current source with the current VIN/RB. To operate correctly, the input voltage must be negative, so that when the circuit is balanced, the two currents cancel.
Single Supply FVC
A frequency-to-voltage converter performs the exact opposite of the VFCs function; it converts an input pulse train into an average output voltage. Incoming pulses trigger the input comparator and fire the one-shot. The one-shot then dumps a charge into the output integrator. The voltage on the integrator becomes a varying DC voltage proportional to the frequency of the input signal. Figure 4 shows a complete single supply FVC.
6
RC4152
PRODUCT SPECIFICATION
CI 0.005 mF 1N914 -VS +VS V IN 0 to -10V RB 100K 2 3 1 R S = 16.7K R B+ 100 k W 4 7 OP-27 RL 10k W 6 8 100W
+VL
Offset Adjust
RL 5.1K 2 FOUT Output Frequency 0 FO 10kHz
+VS +VS
1 3 I OUT +V 8 FOUT R S S 4152 4 Gnd 7 VFC VTH VIN CO 5 CO 0.01 mF 6 5k W +VS RO 6.8 k W
10 k W
1 mF
4152-05
Figure 2. Precision Current Sourced VFC
CI 0.005 mF 1N914 -V S +VS V IN 0 to -10V RB 100K 3 1 R S = 16.7K RB+ 100 k W +VS +VS 1 2 IOUT R S 3 +VS 8 FOUT 4152 4 VFC 7 Gnd CO VTH VIN 6 5 RZ 10k W 2 4 7 6 8 100W
OP-27
Offset Adjust
+VL RL 5.1K FOUT Output Frequency 0 FOUT 10kHz
10 k W
CO 0.01 mF
5 kW +VS RO 6.8 k W
1 mF
4152-06
Figure 3. Precision Voltage Sourced VFC
7
PRODUCT SPECIFICATION
RC4152
The input waveform must have fast slewing edges, and the differentiated input signal must be less than the timing period of the one-shot, 1.1 ROCO. A differentiator and divider are used to shape and bias the trigger input; a negative going pulse at pin 6 will cause the comparator to fire the one-shot. The input pulse amplitude must be large enough to trip the comparator, but not so large as to exceed the ICs input voltage ratings. The output voltage is directly proportional to the input frequency:
1.1R O C O R B V REF V OUT = -------------------------------------------- F IN ( Hz ) RS
Precision FVC
Linearity, offset and response time can be improved by adding one or more op amps to form an active lowpass filter at the output. A circuit using a single pole active integrator is shown in Figure 5. The positive output current pulses are averaged by the inverting integrator, causing the output voltage to be negative. Response time can be further improved by adding a double pole filter to replace the single pole filter. Refer to the graphs under Typical Performance Characteristics that show nonlinearity error versus input frequency for the precision FVC circuit.
Output ripple can be minimized by increasing CB, but this will limit the response time. Recommended values for various operating ranges are shown in the following table.
Input Operating Rage 0 to 1.0 kHz 0 to 10 kHz
CIN 0.02 mF
RO
CO
RB
CB
Ripple
6.8 kW 0.1 mF
100 kW 100 mF 1.0 mV 100 kW 10 mF 1.0 mV 1.0 mV
0.002 mF 6.8 kW 0.01 mF
0 to 100 kHz 200 pF
6.8 kW 0.001 mF 100 kW 1.0 mF
+15V 10 k W 10Y k W C IN 0.022 mF FIN Frequency Input 0 FIN 10kHz 10 k W +15V RB 100K V OUT CB 10 mF
4152-07
RO 6.8 kW
CO 0.01 m F 5 CO
7 VIN 6V TH +VS 5 kW 8 4152 VFC I OUT 1
Gnd
4
F OUT 3 RS 2
R S = 16.7K
Figure 4. Single Supply FVC
8
RC4152
PRODUCT SPECIFICATION
RO 6.8 k W +15V 10 k W 10 k W 7 CIN 0.022 mF FIN Frequency Input 0 FO 10kHz 5.0 VP-P Squarewave VIN 5 C O Gnd 4 3 4152 VFC 6 FOUT VTH I OUT R S +VS 1 2 8 5 kW R S = 16.7K 10 k W +15V CI 5 pF -VS +VS 4 2 7 6 OP-27 3 8 RB 100 k W 1 RZ 10 kW RB 100 k W CO 0.01 mF
100W VOUT Voltage Output -10V V O 0
Offset Adjust
+VS
4152-08
9
10
(3) (8) +VS Q41 M N S X U Q40 T Q32 I OUT (1) Q33 2K 3.6K 2K (2) RS Q27 Q26 6.2K 2K Q22 Q21 (6) VTH V IN Q1 (7) Q2 Q3 Q4 Q12 10K Q13 Q14 Q15 10K Q5 Q6 Q7 Q8 2K Q9 2K 2K Q10 Q11 Q17 Q16 Q18 Q19 Q20 10K (4) Gnd Q25 2K -VS 7.8K Q30 Q23 12K D39 D29 6.3V Q34 Q42 Q38 D43 Q35 15K Q36 Q37 Q28 Z Y R W FoUT V CO (5) 4152-09
PRODUCT SPECIFICATION RC4152
Schematic Diagram
RC4152
PRODUCT SPECIFICATION
Notes:
11
PRODUCT SPECIFICATION
RC4152
Ordering Information
Part Number RC4152N RC4152M RV4152N
Notes: N = 8-lead plastic DIP M = 8-lead plastic SOIC
Package N M N
Operating Temperature Range 0C to +70C 0C to 70C -25C to +85C
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 6/25/98 0.0m 003 Stock#DS30004152 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC4153
Voltage-to-Frequency Converter
Features
* 0.1 Hz to 250 kHz dynamic range * 0.01% F.S. maximum nonlinearity error-- 0.1Hz to 10 kHz * 50 ppm/C maximum gain temperature coefficient (external reference) * Few external components required
Applications
* * * * * * * * * * Precision voltage-to-frequency converters Serial transmission of analog information Pulse width modulators Frequency-to-voltage converters A/D converters and long term integrators Signal isolation FSK modulation/demodulation Frequency scaling Motor speed controls Phase lock loop stabilization
Description
The 4153 sets a new standard for ease of application and high frequency performance in monolithic voltage-tofrequency converters. This voltage-to-frequency converter requires only four passive external components for precision operation, making it ideal for many low cost applications such as A/D conversion, frequency-to-voltage conversion,
and serial data transmission. The improved linearity at high frequency makes it comparable to many dual slop A/D converters both in conversion time and accuracy, while retaining the benefits of voltage-to-frequency conversion, i.e., serial output, cost and size. The speed accuracy and temperature performance of the 4153 is achieved by incorporating high speed ECL logic, a high gain, wide bandwidth op amp, and a buried Zener reference on a single monolithic chip.
PRODUCT SPECIFICATION
RC4153
Pin Assignments
4153 -VS 1 Gnd 2 2 VREF 3 VOUT 4 I IN 5 CO 6 Trig 7 IREF VREF 7.3V 14 VOS1 13 VOS2 12 -In 11 +In 10 +VS 9 FOUT
Pin Descriptions
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 -VS REF Gnd VREF Output VOUT (Op Amp) IIN (REF Input) CO (Pulse Width) Trigger Input Circuit Gnd Frequency Output (Open Collector) +VS (+) Op Amp Input (-) Op Amp Input VOS Trim VOS Trim Function
One Shot
8 Gnd 1
4153-01
Absolute Maximum Ratings(1)
Parameter Supply Voltage Internal Power Dissipation Input Voltage Output Sink Current (Frequency Output) Storage Temperature Range Operating Temperature Range RV4153 RC4153 -25 0 +80 +70 C -65 -VS Min. Typ. Max. 18 500 +VS 20 +150 mA C Units V mW
Note: 1. "Absolute maximum ratings" are those beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. If the device is subjected to the limits in the absolute maximum ratings for extended periods, its reliability may be impaired. The tables of Electrical Characteristics provide conditions for actual device operation.
Thermal Characteristics
14-Lead Ceramic DIP Max. Junction Temp Max. PD TA<50C Therm Res qJC Therm Res qJA For TA >50C Derate at +175C 1042 mW 60C/W 120C/W 8.33 mW/C 14-Lead Plastic DIP +125C 468 mW -- 160C/W 6.25 mW/C
2
RC4153
PRODUCT SPECIFICATION
Electrical Characteristics
(VS = 15V and TA = +25C unless otherwise noted) Parameters Power Supply Requirements Supply Voltage Supply Current (+VS, IOUT = 0) (-VS, IOUT = 0) Full Scale Frequency Transfer Characteristics Nonlinearity Error Voltage-to-Frequency1 0.1 Hz FOUT 10 kHz 1.0 Hz FOUT 100 kHz 5.0 Hz FOUT 250 kHz Nonlinearity Error Frequency-to-Voltage 0.1 Hz FIN 10 kHz 1.0 Hz FIN 100 kHz 5.0 Hz FIN 250 kHz Scale Factor Tolerance, F = 10 = kHz
1 K = ---------------------------------2V REF R IN C O
1
Min. 12
Typ. 15 +4.2 -7
Max. 18 +7.5 -10
Units V mA kHz
250
500
0.002 0.025 0.06 0.002 0.05 0.07
0.01 0.05 0.1 0.01 0.1 0.12
%FS %FS %FS %FS %FS %FS
0.5 0.008 7.3 70C)1, 2, 3 75 50 25 50 100 230 25 2.5 0.5 0 to +10 3.0 2.0 -0.5 to +14.3 70 0.5 30 1.0 75 70 25 100 106 350 400 5.0 60 150 100 50 100 150
%
Change of Scale Factor with Supply Reference Voltage (VREF) Temperature Stability (0C to Scale Factor 10 KHz Nominal Reference Voltage Scale Factor (External Ref) 10 KHz FS Scale Factor (External Ref) 100 KHz FS Scale Factor (External Ref) 250 KHz FS Op Amp Open Loop Output Resistance Short Circuit Current Gain Bandwidth Slew Rate Output Voltage Swing (RL 2K) Input Bias Current Input Offset Voltage (Adjustable to 0) Input Offset Current Input Resistance (Differential Mode) Common Mode Rejection Ratio Power Supply Rejection Ratio Large Signal Voltage Gain Product1
%/V V ppm/C ppm/C ppm/C ppm/C ppm/C W mA MHz V/ms V nA mV nA MW dB dB V/mV
3
PRODUCT SPECIFICATION
RC4153
Parameters Switched Current Source Reference Current (External Reference) Digital Input (Frequency-to-Voltage, Pin 7) Logic "0" Logic "1" Trigger Current Logic Output (Open Collector) Saturation Voltage (Pin 9) ISINK = 4 mA ISINK = 10 mA ILEAK (Off State)
Notes: 1. Guaranteed but not tested. 2. VREF Range: 6.6V VREF 8.0V. 3. Over the specified operating temperature range.
Min.
Typ. 1.0
Max.
Units mA
0.5 2.0 -50
V V mA
0.15 0.4 150
0.4 1.0
V V nA
4
RC4153
PRODUCT SPECIFICATION
Typical Performance Characteristics
10 kHz Full Scale Drift Output Frequency vs. Temperature 10.06 10.03 FOUT (kHz) FOUT (kHz) 250.8 250.4 250 kHz Full Scale Drift Output Frequency vs. Temperature
10 9.97 9.94 9.91 -60 -40 -20 0 +20 +40 +60 +80 +100 +120
250.0 249.6 249.2 248.8 -60 -40 -20 0 +20 +40 +60 +80 +100 +120
TA (C)
TA (C)
250 kHz Frequency-to-Voltage Nonlinearity vs. Input Voltage 0.08 0.04 NL (% Error) 0 NL (% Error) 0.09 0.06 0.03
250 kHz Voltage-to-Frequency Nonlinearity vs. Input Voltage
-0.04
0
-0.08 -0.12 0 1 2 3 4 5 VIN (V) 6 7 8 9 10
-0.03 -0.06 0 25 50 75 100 125 150 175 200 225 250 FIN (kHz)
250 kHz Full Scale Peak Nonlinearity vs. Scale Factor 0.10 NL (Absolute % Error) 0.08 F-to-V 0.06 0.04 0.02 0 0 30 60 0 120 150 180 210 240 V-to-F
270
K (kHz)
4153-02
5
PRODUCT SPECIFICATION
RC4153
Typical Performance Characteristics
10 KHz Voltage-to-Frequency Nonlinearity vs. Input Voltage 0.004 0.002 NL (% Error) NL (% Error) 0 0.004 0.002 0 10 KHz Frequency-to-Voltage Nonlinearity vs. Input Frequency
-0.002
-0.002
-0.004 -0.006 0 1 2 3 4 5 VIN (V) 6 7 8 9 10
-0.004 -0.006 0 1 2 3 4 5 6 7 8 9 10
FIN (kHz)
50 KHz Voltage-to-Frequency Nonlinearity vs. Input Voltage 0.01 0.05 NL (% Error) 0 NL (% Error) 0.008 0.004 0
50 KHz Frequency-to-Voltage Nonlinearity vs. Input Frequency
-0.005
-0.004
-0.01 -0.015 0 1 2 3 4 5 VIN (V) 6 7 8 9 10
-0.008 -0.012 0 5 10 15 20 25 30 35 40 45 50
FIN (kHz)
100 KHz Voltage-to-Frequency Nonlinearity vs. Input Voltage 0.04 0.02 NL (% Error) NL (% Error) 0 0.04
100 KHz Frequency-to-Voltage Nonlinearity vs. Input Frequency
0.02 0
-0.02 -0.04 -0.06 0 1 2 3 4 5 VIN (V) 6 7 8 9 10
-0.02 4153-03 0 10 20 30 40 50 60 70 80 90 100 FIN (kHz)
-0.04 -0.06
6
RC4153
PRODUCT SPECIFICATION
Typical Application Circuits
V IN R IN Full Scale 10 kHz R s** -Vs C I = 30 CO Gnd 2 1 4153 14 VOS1 50 kHz 100 kHz 250 kHz CI 0.1mF 0.02 mF 4300 pF 1000 pF CO 3300 pF 680 pF 330 pF 130 pF RIN 20K 20K 20K 20K
2
VREF
VREF 7.3V
13
VOS2 -In
3
12
V OUT 4 11 +In +V S*
VIN CO
5
I REF
10 FOUT RL 5.1K FOUT 8 Gnd 1 t T
6 CO Trig VIN FOUT = 2V REF R IN CO 7
9 One Shot
T= ** For Bipolar Input F OUT VIN RREF + VREF R IN = 2R IN R S V REF C O
1 F OUT
4
(VREF = 7.3V) * VS must be thoroughly decoupled. ** For bipolar input. Resistance in Ohms unless otherwise specified.
t = 1.5 x 10 CO CO 5 x 10 F OUT (Max)
4153-04
-5
Figure 1. Voltage-to-Frequency Converter Minimum Circuit
Full Scale Adjust
Voltage Output
-Vs *
4153 1 14
5K VOS1 R VOS 10K RB 18.7K VOS2 -In R B' 20K C B' +VS 0.01 F (Cer Disk) R L = 5.1K** FOUT** CI
-Vs * Gnd 2
2
VREF 7.3V
13
Full Scale 10 kHz 50 kHz 100 kHz 250 kHz VRIPPLE =
CI 10 m F 2 mF 1 mF 0.2mF
CO 3300 pF 330 pF 150 pF 60 pF
RB 20K 40K 43K 39K
VREF V OUT
3
12
2V REF C O (1 - 1.5 x 104 C O FIN ) CI F IN
+In 4 11
4 T RECOVERY = 1.36 x 10 C I CORB
+Vs *
VIN CO
5
I REF
10
+V S* FOUT Gnd 1
R1 10K FIN (0 -10 kHz) C IN 0.002 pF
CO 3.3 nF Trig R2 5.1K
6
9 One Shot 8
7
VOUT
= 2VREF R B CO F IN
CO
5 x 10 -5 F IN (Max)
V S must be thoroughly decoupled. ** Optional. Resistance in Ohms unless otherwise specified.
4153-05
Figure 2. Frequency-to-Voltage Converter
7
PRODUCT SPECIFICATION
RC4153
Typical Application Circuit (Continued)
Full Scale Adjust VIN (0 to 10V) Full Scale CI 10 kHz 0.1 m F 50 kHz 0.02 m F ROS 10K Zero Adj. VOS2 -In R B' 20K +V S* C B' 0.01 mF (Cer Disk) 100 kHz 250 kHz 4300 pF 1000 pF CO 3300 pF 680 pF 330 pF 130 pF R IN 20K 20K 20K 20K
R IN -Vs 1 CI 0.01 mF (Mylar) -Vs * Gnd 2 2 VREF 7.3V 13
4153
VOS1 14
VREF 3 V OUT 4
12
11
+In
IIN CO CO Trig FOUT = CO VIN 2V REF R IN C O 5 x 10 -5 F OUT (Max)
5
I REF
10 FOUT RL 5.1K
6
9 One Shot 8
Frequency Output Gnd 1
7
* VS must be thoroughly decoupled. Resistance in Ohms unless otherwise specified.
4153-06
Figure 3. Voltage-to-Frequency Converter with Offset and Gain Adjusts
8
RC4153
PRODUCT SPECIFICATION
Principles of Operation
The 4153 consists of several functional blocks which provide either voltage-to-frequency or frequency-to-voltage conversion, depending on how they are connected. The operation is best understood by examining the block diagram as it is powered in a voltage-to-frequency mode (Figure 4). When power is first applied, all capacitors are discharged. The input current, VIN/RIN, causes CI to charge, and point C will try to ramp down. The trigger threshold of the one-shot is approximately +1.3V, and if the integrator output is less than +1.3V, the one-shot will fire and pulse the open collector output E and the switched current source A (see Figures 4 and 5). Because the point C is less than +1.3V, the one-shot fires, and the switched current source delivers a negative current pulse to the integrator. This causes CIN to charge in the opposite direction, and point C will ramp up until the end of the one-shot pulse. At that time, the positive current VIN/RIN will again make point C ramp down until the trigger threshold is reached. When power is applied, the one-shot will continuously fire until the integrator output exceeds the trigger threshold. Once this is reached, the one-shot will fire as needed to keep the integrator output above the trigger threshold. If VIN is increased, the slope of the downward ramp increases, and the one-shot will fire more often in order to keep the integrator output high. Since the one-shot firing frequency is the same as the open collector output frequency, any increase in VIN will cause an increase in FOUT. This relationship is very linear because the amount of charge in each IOUT pulse is carefully defined, both in magnitude and duration. The duration of the pulse is set by the timing capacitor CO (point D). This feedback system is called a charge-balanced loop.
The scale factor K (the number of pulses per second or a specified VIN), is adjusted by changing either RIN and therefore IIN, or by changing the amount of charge in each IOUT pulse. Since the magnitude of IOUT is fixed at 1 milliamp, the way to change the amount of charge is by adjusting the oneshot duration set by CO (IOUT may be adjusted by changing VREF). The accuracy of the relationship between VIN and FOUT is affected by three major sources of error: temperature drift, nonlinearity and offset. The total temperature drift is the sum of the individual drift of the components that make up the system. The greatest source of drift in a typical application is in the timing capacitor, CO. Low temperature coefficient capacitors, such as silver mica and polystyrene, should be measured for drift using a capacitance meter. Experimentation has shown that the lowest tempco's are achieved by wiring a parallel capacitor composed of 70% silver mica and 30% polystyrene. The reference on the chip can be replaced by an external reference with much tighter drift specifications, such as an LM199. The 199's 6.9V output is close to the 4153's 7.3V output, and has less than 10 ppm/C drift. Nonlinearity is primarily caused by changes in the precise amount of charge in each IOUT pulse. As frequency increases, internal stray capacitances and switching problems change the width and amplitude of the IOUT pulses, causing a nonlinear relationship between VIN and FOUT.
+10V V IN +5V
0 A -I OUT
Switched Current Source Output -1.0 mA Switched Current Source Logic (Internal) Integrator Output VTRIGGER ~ +1.3V ~
Integrator
B
CI C
C
R IN VIN 0 to 10V A I oUT Trigger Voltage Reference 7.3V Switched Current Source B Co (Timing) One Shot Ext Load E +VS
-0.65V D One Shot Timing (CO) T = 1.5 x 10 4 C O -4.1V -VS E Logic Output -0.2V V IN F O = 2V REF R IN C O
4153-08
D
Open Collector Output
4153-07
Figure 4. Voltage-to-Frequency Block Diagram
Figure 5. Voltage-to-Frequency Timing Waveforms
9
PRODUCT SPECIFICATION
RC4153
For this reason, the scale factor you choose should be below 1 KHz/V or as low as the acquisition time of your system will allow. Nonlinearity is also affected by the rate of CI to CO. Less error can be achieved by increasing the value of CI, but this affects response time and temperature drift. Optimum value for CI and CO are shown In the tables in Figures 1, 2, and 3. These values represent the best compromise of nonlinearity and temperature drift. Polypropylene, mylar or polystyrene capacitors should be used for CI. The accuracy at low input voltages is limited by the offset and VOS drift of the op amp. To improve this condition, an offset adjust is provided. Once your system is running, it may be calibrated as follows: apply a measured full scale input voltage and adjust RIN until the scale factor is correct. For precise applications, trimming by soldering metal film resistors in parallel is recommended instead of trimpots, which have bad tempco's and are easily taken out of adjustment by mechanical shock. After the scale factor is calibrated, apply a known small input voltage (approximately 10 mV) and adjust the op amp offset until the output frequency equals the input multiplied by the scale factor. The output E consists of a series of negative going pulses with a pulse width equal to the one-shot time. The open collector pull-up resistor may be connected to a different supply (such as 5V for TTL) as long a it does not exceed the value of +VS applied to pin 10. The load current should be
kept below 10 mA in order to minimize strain on the device. Pins 2 and 8 must be grounded in all applications, even if the open collector transistor is not used. Figure 6 shows the complete circuit for a precision frequency-to-voltage converter. The circuit converts an input frequency to a proportional voltage by integrating the switched current source output. As the input frequency increases, the number of IOUT pulses delivered to the integrator increases, thus increasing the average output voltage. Depending on the time constant of the integrator, there will be some ripple on the output. The output may be further filtered, but this will reduce the response time. A second order filter will decrease ripple and improve response time. The input waveform must meet three conditions for proper frequency-to-voltage operation. First, it must have sufficient amplitude and offset to swing above and below the 1.3V trigger threshold (See Figure 6 for an example of AC coupling and offset bias.) Second, it must be a fast slewing waveform having a quick rise time. A comparator may be used to square it up. Finally, the input pulse width must not exceed the one-shot time, in order to avoid retriggering the one-shot (AC couple the Input). Capacitive coupling between the trigger input and the timing capacitor pin may occur if the input waveform is a squarewave or the input has a short period. This can cause gross nonlinearity due to changes in the one-shot timing waveform (See Figure 7). This problem can be avoided by keeping the value of CO small, and thereby keeping the timing period less than the input waveform period.
-15V
+15V
+VS 13 RA F IN 14 7 CA RB 100 W 100K Comparator with Hysteresis 3 5 VOS1 Trig VREF IIN VOS2
1 -VS
10 +VS VOUT 4 RI V OUT+ CI
4153
-In +In
12 11 RI
GND2 GND1 FOUT CO 9 6 2 8 CO Input Coupling
4153-09
Figure 6. Frequency-to-Voltage Precision Converter
10
RC4153
PRODUCT SPECIFICATION
Timing Waveform on C O Proper Operation Input Frequency
Input Frequency Improper Operation Timing Waveform On C O Gitch
4153-10
Figure 7. Frequency-to-Voltage Timing Waveforms
Detailed Circuit Operation
The circuit consists of a buried zener reference (breakdown occurs below the surface of the die, reducing noise and contamination), a high speed one-shot, a high speed switched precision voltage-to-current converter and an open-collector output transistor. Figure 8 shows a block diagram of the high speed one-shot and Figure 9 shows the monolithic implementation. A trigger pulse sets the R-S latch, which lets CO charge from IT. When the voltage on CO exceeds VTH. the comparator resets the latch and discharges CO. Looking at the detailed schematic,
a positive trigger voltage turns on Q5, turns off Q4, and turns on Q3. Q3 provides more drive to Q5 keeping it on and latching the base of Q11 low. This turns on the switched current source and turns off Q1, allowing CO to charge in a negative direction. When the voltage on CO exceeds VTH, Q13's collector pulls Q3's base down, resetting the latch, turning off the switched current source and discharging CO through Q1. Note that all of the transistors in the signal path are NPNs, and that the voltage swings are minimized ECL fashion to reduce delays. Minimum delay means minimum drift of the resultant VFC scale factor at high frequency.
To Switched Current Source
B
C
Trig Reset
Q
IT
D CO V TH R-S Latch Ramp Gen Comparator
4153-11
Figure 8. One-Shot Block Diagram
11
PRODUCT SPECIFICATION
RC4153
Gnd I OUT Q10 Q2 (B) Q7 Q8 Q1 D3 II 1.0 mA Q4 D Q5 Trigger C Q11 Q12 Q6 D2 D1 Q3
VTH
Q13 Q14 CO
IT -V S Ramp Generator Comparator R-S Latch
4153-12
Figure 9. One-Shot (Detail)
The switched current source is shown as a block diagram in Figure 10 and detailed in Figure 11. The summing node (+ input of the op amp) is held at 0V by the amplifier feedback, causing VREF to be applied across R60. This current (VREF/R60), minus the small amplifier bias current, flows through Q35. Q35 develops a VBE dependent on that current. This VBE is developed across Q36. Since Q35 and Q36 are equal in area, the currents are equal. The mirrored current is switched by the one-shot output.
The detail schematic shows the amplifier and load (Q21 through Q34), the mirror transistors (Q35, Q36) and the differential switching transistors (Q7, Q8). The amplifier uses a complementary paraphase input composed of Q21 through Q26 with a current mirror formed by Q27 through Q30, which converts from differential to single-ended output. Level-shift diodes Q32 and Q34 and emitter follower Q31 bootstrap the emitters of the mirror devices Q29 and Q30 to increase gain and lower input offsets, which would otherwise be caused by unbalanced collector voltages on Q23 and Q26.
VREF +7.3V
A
Switched Current Source Output B From One Shot
R60
Q35
Q36
-VS
4153-13
Figure 10. Switched Current Source Block Diagram
12
RC4153
PRODUCT SPECIFICATION
Matching emitter currents in Q35 and Q36 are assured by degeneration resistors R3 and R4. The differential switch allows the current source to remain active continuously, shunting to ground in the off state. This helps stabilize the
output, and again, NPNs reduce switching time, timing errors, and most important, drift of timing errors over temperature.
V REF To +V S R60 R46 Q21 Q22 Q38 Q23 Q24 Q25 +VS Q27 To Bias Network Q28 Q26 C1 To V B Q7 Q8 B I IN A Switched Current Output Source To Collector of Q11
Q35
Q36
Q1 Q29
Q30
Q32
Q31
Q34
R1 34 kW -VS
R43 56.2 kW
R2 56.2 k W
R3 39.2 k W
R4 39.2 k W
4153-14
Figure 11. Switched Current Source (Detail)
13
14
VOS1 VOUT LO +VS VIN -In +In VOS2
VREF
+VS R48 4.8K R59 0.15 -In +In Q81 GND1 GND2 Q83 Q97 IIN R59 VREF VREF -VS +VS Q66 NPN Q92 R55 500 Q93 R57 0.02 Q96 Q90 Q95 R53 0.10 R56 0.02 2 1 One Shot R18 Q80 R54 0.03 Q94 Q91 Q85
N+ AL
RM4153
VOS1 VOS2 VOUT Trig CO FOUT Pulse Output RL +VS Offset Adjust
PRODUCT SPECIFICATION
Q75 Q78 D89 Q82 Q79 RB1
Q76
RB
Schematic Diagram
CI to -In
Q77
Q73 Q97 Q98 Q84 D88
Q74
R
C3 15 pF Q86 R49 1K R50 R51 1K 18K 13 pF R52 22K Q87 C2
Q72
D71 6.3V
R45 5.11
R44 200
GND2
IIN R59 6.8 GND1 Q67 Q33 R18 13.6 R16 20 Q29 Q20 Q31 Q38 Q39 R36 4.82 Q32 Q24 R39 9.6 Q44 Q45 Q46 Q47 Q22 Q23 Q12 Q16 Q17 Q18 D28 6.3 R7 20 Q25 R12 8.25 R24 8.25 R25 8.25 R23 8.25 R8 5.11 R5 40.2 R4 3.92 D18 5.5 R9 20 Q15 C4 15 pF Q27 R10 47.5 Q21 R11 Q26 51.1 Q30 Q28 C1 25 pF R37 3.65 R38 24.3 R6 20 R14 5.92 R13 10 R17 20
+VS
R30 12 R29 12 Q42 R32 .511 Q34 D68 Q36 6.3 Q35 R19 5.11 R20 15 D69 6.3 Q40 Q41 Q48 Q49 Q50 Q43 Q64 Q65 D70 6.3
GND1
R46 6.8K
Q1
Q2
R32 0.511
Q61 Q60 Q59 Q57
Q62 Q63 Q58
Q3
Q5
Q6
Q4
N+
Q56 Q55 R42 30 Q51 Q52 Q53 R22 R21 8.25 8.25 R26 8.25 R27 3.92 R28 8.25 R34 20 R23 8.25 R35 8.25 Q54
Q7
Q8
Q9
Q10
Q11 Q14 R3 3.92
Q13
R1 3.4K
R43 40.2
R2 56.2
-VS CO Trig 4153-15
Notes: All resistor values are in KW Al = Aluminum
RC4153
RC4153
PRODUCT SPECIFICATION
Notes:
15
PRODUCT SPECIFICATION
RC4153
Ordering Information
Part Number RC4153N RV4153N
Notes: N = 14-lead plastic DIP
Package N N
Operating Temperature Range 0C to +70C -25C to 80C
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 6/25/98 0.0m 002 Stock#DS30004153 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC4156/RC4157
High Performance Quad Operational Amplifiers
Features
* * * * Unity gain bandwidth for RC4156 - 3.5 MHz Unity gain bandwidth for RC4157 - 19 MHz High slew rate for RC4156 - 1.6 V/mS High slew rate for RC4157 - 8.0V/mS * Low noise voltage - 1.4 mVRMS * Indefinite short circuit protection * No crossover distortion
Description
The RC4156 and RC4157 are monolithic integrated circuits, consisting of four independent high performance operational amplifiers constructed with an advanced epitaxial process. These amplifiers feature improved AC performance which far exceeds that of the 741 type amplifiers. Also featured are excellent input characteristics and low noise, making this device the optimum choice for audio, active filter and instrumentation applications. The RC4157 is a decompensated version of the RC4156 and is AC stable in gain configurations of -5 or greater.
Block Diagram
Output (A) -Input (A) +Input (A) +Input (B) -Input (B) Output (B)
65-3463-01
Pin Assignments
Output (D) -Input (D) +Input (D) +Input (C) Output (A) -Input (A) +Input (A) +VS +Input (B) -Input (B) Output (B)
1 2 3 4 5 6 7 14 13 12 11 10 9 8 65-3463-02
A +
D +
Output (D) -Input (D) +Input (D) -VS +Input (C) -Input (C) Output (C)
+ B
C
+ -Input (C) Output (C)
Rev. 1.0.0
PRODUCT SPECIFICATION
RC4156/RC4157
Absolute Maximum Ratings
(beyond which the device may be damaged)1 Parameter Supply Voltage Input Voltage2 Differential Input Voltage Output Short Circuit Duration3 PDTA < 50C SOIC PDIP CerDIP Operating Temperature Storage Temperature Junction Temperature Lead Soldering Temperature (60 seconds) For TA > 50C Derate at SOIC, PDIP CerDIP DIP SOIC SOIC PDIP CerDIP 5.0 6.25 8.38 RC4156/RC4157 RM4156/RM4157 0 -55 -65 Indefinite 300 468 1042 70 +125 150 125 175 300 260 mW mW mW C C C C C C C mW/C mW/C mW/C Min Typ Max 20 15 30 Units V V V
Notes: 1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded. 2. For supply voltages less than 15V, the absolute maximum input voltage is equal to the supply voltage. 3. Short circuit to ground on one amplifier only.
Operating Conditions
Parameter qJC qJA Thermal resistance Thermal resistance SOIC PDIP CerDIP Min Typ 60 200 160 120 Max Units C/W C/W C/W C/W
Electrical Characteristics
(VS = 15V, RM = -55C TA +125C, RC = 0C TA +70C) RM4156/4157 Parameters Input Offset Voltage Input Offset Current Input Bias Current Large Signal Voltage Gain Output Voltage Swing Supply Current Average Input Offset Voltage Drift RL 2 kW,VOUT 10V RL 2 kW 25 10 10 5.0 Test Conditions RS 10 kW Min Typ Max 5.0 75 320 15 10 10 5.0 RC4156/4157 Min Typ Max 6.5 100 400 Units mV nA nA V/mV V mA mV/C
2
RC4156/RC4157
PRODUCT SPECIFICATION
Electrical Characteristics
(VS = 15V and TA = +25C unless otherwise noted) RM4156/4157 Parameters Input Offset Voltage Input Offset Current Input Bias Current Input Resistance Large Signal Voltage Gain Output Voltage Swing Input Voltage Range Output Resistance Short Circuit Current Common Mode Rejection Ratio Power Supply Rejection Ratio Supply Current (All Amplifiers) Transient Response (4156) Rise Time Overshoot Slew Rate Unity Gain Bandwidth (4156) Phase Margin (4156) Transient Response (4157) Rise Time Overshoot Slew Rate Unity Gain Bandwidth (4157) Phase Margin (4157) Power Bandwidth Input Noise Voltage 1 Input Noise Current Channel Separation
Note: 1. Sample tested only.
RC4156/4157 Min Typ 1.0 30 60 0.5 25 12 10 12 100 14 13 14 230 25 80 80 Max 5.0 50 300 Units mV nA nA MW V/mV V V V W mA dB dB 5.0 60 25 1.3 2.8 1.6 3.5 50 50 25 6.5 15 8.0 19 50 20 25 1.4 15 108 5.0 7.0 mA nS % V/mS MHz % nS % V/mS MHz % kHz mVRMS pARMS dB
Test Conditions RS 10 kW
Min
Typ 0.5 15 60 0.5
Max 3.0 30 200
RL 2 kW, VOUT 10V RL 10 kW RL 2 kW
50 12 10 12
100 14 13 14 230 25
RS 10 kW RS 10 kW RL =
80 80 4.5 60 25 1.3 2.8 1.6 3.5 50 50 25 6.5 8.0 19 50 20 25 1.4 15 108 5.0 5.0
RL = 2 kW, CL = 50 pF AV = -5
AV = -5 AV = -5, RL = 2 kW, CL = 50 pF VOUT = 20Vp-p F = 20 Hz to 20 kHz F = 20 Hz to 20 kHz
15
3
PRODUCT SPECIFICATION
RC4156/RC4157
Typical Performance Characteristics
140 110 100 90 80 70 60 50 40 30 20 10 0 -10
4156 AVOL F
120 PSRR (dB)
R L = 2K C L = 55 pF
+VS -VS
0 45 90 135 180
65-0738
100 80 60 40 20 0 -100 -75 -50 -25
AVOL (dB)
F (Deg)
1
10
100
1K 10K 100K 1M F (Hz)
10M
0 +25 +50 +75 +100 +125 +150 TA (C)
Figure 1. Open Loop Gain, Phase vs. Frequency
Figure 2. PSRR vs. Temperature
-140 -120 -100 CS (dB) -80 -60 -40 -20 0 10 100 1K F (Hz) Figure 3. Channel Separation vs. Frequency 10K 100K
1K 1K 6 5 1K 1K 2 3
100K
4156/57
1
VOUT1 VOUT2 C.S. = 20 log ( ) 100 VOUT1
100K
4156/57
7
VOUT2
65-0739
1.3 35 Transient Response (Normalized to +25C) 1.2 1.1 en (nV Hz ) 1.0 0.9 0.8 0.7
65-0741
1.4 1.2 IN (pA Hz )
65-0742
30 25 20 15 10 5 0 10 100
en IN
1.0 0.8 0.6 0.4 0.2 10K 0 100K
0.6 -100 -75 -50 -25 0 +25 +50 +75 +100+125+150 TA (C) Figure 4. Transient Response vs. Temperature
1K F (Hz)
Figure 5. Input Noise Voltage, Current Density vs. Frequency
4
65-0740
RC4156/RC4157
PRODUCT SPECIFICATION
Typical Performance Characteristics (continued)
1.3 SR,BW (Normalized to +25C) SR, BW (Normalized to 15V) 1.2 1.1 1.0 0.9 0.8 0.7 0.6 -100 -50 0 +50 TA (C) Figure 6. Slew Rate, Bandwidth vs. Temperature +100
65-0743
1.1 BW 1.0 SR and BW
0.9
0.8
65-0744
0.7
+150
0 2
5
10 VS (V)
15
20
Figure 7. Slew Rate, Bandwidth vs. Supply Voltage
30 30 VOUT P-P (V) 10
VOUT P-P = 28V VS = 15V VOUT P-P = 18V VS = 10V VOUT P-P = 8V VS = 5V
25 VOUT P-P (V)
65-0746
20 15 10
65-0749
1.0
4156 (Voltage Follower) R L = Open C L = 50 pF
05 0 100 1K RL (W ) Figure 9. Output Voltage Swing vs. Load Resistance 10K
0.1 100
1K
10K F (Hz)
100K
1M
100K
Figure 8. Output Voltage Swing vs. Frequency
70 60 50 FM (Deg) 40 30 20 10 0 10 100 1K CL (pF) 10K BW FM 4156
7 6 5 4 3 2 1 0 100K
65-0745
Figure 10. Small Signal Phase Margin, Unity Gain Bandwidth vs. Load Capacitance
BW (MHz)
5
PRODUCT SPECIFICATION
RC4156/RC4157
Typical Performance Characteristics (continued)
140 120 100 CMRR (dB)
65-0747
140 120 100
IB
IB, IOS (nA)
80 60 40 20 0-100 -75 -50 -25
80 60 40 20 0 -100 -75 -50 -25
65-0748
IOS
0 +25 +50 +75+100+125+150 TA (C)
0 +25 +50 +75+100+125+150 TA (C)
Figure 11. Input Bias, Offset Current vs. Temperature
Figure 12. CMRR vs. Temperature
Applications
The RC4156 and RC4157 quad operational amplifiers can be used in almost any 741 application and will provide superior performance. The higher unity gain bandwidth and slew rate make it ideal for applications requiring good frequency response, such as active filter circuits, oscillators and audio amplifiers. The following applications have been selected to illustrate the advantages of using the Fairchild Semiconductor RC4156 and RC4157 quad operational amplifiers. positive then negative, and the comparator switching in a square wave fashion. The amplitude of V2 is adjusted by varying R1. For best operation, it is recommended that R1 and VR be set to obtain a triangle wave at V2 with 12V amplitude. This will then allow A3 and A4 to be used for independent adjustment of output-offset and amplitude over a wide range. The triangle wave frequency is set by C0, R0, and the maximum output voltages of the comparator. A more symmetrical waveform can be generated by adding a back-to-back Zener diode pair as shown in Figure 14. An asymmetric triangle wave is needed in some applications. Adding diodes as shown by the dashed lines is a way to vary the positive and negative slopes independently. The frequency range can be very wide and the circuit will function well up to about 10 kHz. The square wave transition time at V1 is less than 21 mS when using the RC4156.
Triangle and Square Wave Generator
The circuit of Figure 13 uses a positive feedback loop closed around a combined comparator and integrator. When power is applied the output of the comparator will switch to one of two states, to the maximum positive or maximum negative voltage. This applies a peak input signal to the integrator, and the integrator output will ramp either down or up, opposite of the input signal. When the integrator output (which is connected to the comparator input) reaches a threshold set by R1 and R2, the comparator will switch to the opposite polarity. This cycle will repeat endlessly, the integrator charging
6
RC4156/RC4157
PRODUCT SPECIFICATION
+12V (+) +15V VR ~ 0.12V ~ 30K Square Wave Output R0 1K 2 3 4156/57 A R1 20K R2 20K 5K -15V 1K Integrator 5K +15V 12 * Optional - asymmetric ramp slopes -15V 5K Output Offset 13 4156/57 D 14 V3
65-0750
-12V R4 C0 1K 6 100K * 10K 4156/57 5 B 7 V2 R3 20K 9 4 8 V4 Triangle Wave Output 20K +15V Amplitude Adjust
1
V1
4156/57 10 C 11
Comparator
Figure 13. Triangle and Square Wave Generator
10K
R1
65-2051
Figure 14. Triangle Generator--Symmetrical Output Option
Active Filters
The introduction of low-cost quad op amps has had a strong impact on active filter design. The complex multiplefeedback, single op amp filter circuits have been rendered obsolete for most applications. State-variable active-filter circuits using three to four op amps per section offer many advantages over the single op amp circuits. They are relatively insensitive to the passive-component tolerances and variations. The Q, gain, and natural frequency can be independently adjusted. Hybrid construction is very practical because resistor and capacitor values are relatively low and the filter parameters are determined by resistance ratios rather than by single resistors. A generalized circuit diagram of the 2-pole state-variable active filter is shown in Figure 15. The particular input connections and component-values can be calculated for specific applications. An important feature of the state-variable filter is that it can be inverting or non-inverting and can simultaneously provide three outputs: lowpass, bandpass, and highpass. A notch filter can be realized by adding one summing op amp. The RC4156 was designed and characterized for use in active filter circuits. Frequency response is fully specified with minimum values for unity-gain bandwidth, slew-rate, and full-power response. Maximum noise is specified. Output swing is excellent with no distortion or clipping. The RC4156 provides full, undistorted response up to 20 kHz and is ideal for use in high-performance audio and telecommunication equipment. In the state-variable filter circuit, one amplifier performs a summing function and the other two act as integrators. The choice of passive component values is arbitrary, but must be consistent with the amplifier operating range and input signal 7
PRODUCT SPECIFICATION
RC4156/RC4157
R5 100K R4 10K V1 R3* 2 4156/57 3 A 1 R1** 6 4156/57 5 B 7 10 R2** 9 4156/57 C 8 C1 1000 pF C2 1000 pF
VN
R8*
R7*
R6 100K VHP Highpass Ouput V BP Bandpass Output
VLP Lowpass Output
* Input connections are chosen for inverting or non-inverting response. Values of R3,R7,R8 determine gain and Q. ** Values of R1 and R2 determine natural frequency.
65-0751
Figure 15. 2-Pole State-Variable Active Filter
characteristics. The values shown for C1, C2, R4, R5 and R6 are arbitrary. Pre-selecting their values will simplify the filter tuning procedures, but other values can be used if necessary. The generalized transfer function for the state-variable active filter is:
a2 s + a1 s + a0 T ( s ) = ----------------------------------2 s + b1 s + b0
2
The input configuration determines the polarity (inverting or non-inverting), and the output selection determines the type of filter response (lowpass, bandpass, or highpass). Notch and all-pass configurations can be implemented by adding another summing amplifier. Bandpass filters are of particular importance in audio and telecommunication equipment. A design approach to bandpass filters will be shown as an example of the state-variable configuration.
Filter response is conventionally described in terms of a natural frequency w0 in radians/sec, and Q, the quality of the complex pole pair. The filter parameters w0 and Q relate to the coefficients in T(s) as:
w0 = w0 b 0 and Q = ----b0
Design Example Bandpass Filter
For the bandpass active filter (Figure 16) the input signal is applied through R3 to the inverting input of the summing amplifier and the output is taken from the first integrator (VBP). The summing amplifier will maintain equal voltage at the inverting and non-inverting inputs (see Equation 1).
R3R5 R3R4 R4R5 ---------------------------------------------------------R3 + R5 R3 + R4 R4 + R5 R7 ---------------------------------- V HP ( s ) + ---------------------------------- V LP ( s ) + ---------------------------------- V IN ( s ) + -------------------- V BP ( s ) R3R5 R3R4 R4R5 R6 + R7 R4 + -------------------R5 + -------------------R3 + -------------------R3 + R5 R3 + R4 R4 + R5 Equation 1.
8
RC4156/RC4157
PRODUCT SPECIFICATION
R5 100K R4 10K 2 1 3 R7 RC4156/57 A R6 100K R1
Set Center Frequency
VIN Trim Gain and Q
R3
6 5
C1 1000 pF 7 R2
9 10
C2 1000 pF 8 RC4156/57 C
RC4156/57 B
VBP
65-0752
Figure 16. Bandpass Active Filter
These equations can be combined to obtain the transfer function:
1 -V V BP ( s ) = - ----------------- HP ( s ) R1C1S
and
1 -V V LP ( s ) = - ----------------- BP ( s ) R2C2S
R4 1 ------ x -------------- S V BP ( s ) R3 R1C1 ----------------- = ----------------------------------------------------------------------------------------------------------------------------------------------------V IN ( s ) 1 R7 R4 1 2 R4 R4 S + -------------------- ae 1 + ------ + ------ o ae --------------o S + ae ------ o ae ----------------------------- o e R5o e R1C1R2C2o R6 + R7 e R5 R3o e R1C1o
Defining 1/R1C1 as w1, 1/R2C2 as w2, and substituting in the assigned values for R4, R5, and R6, then the transfer function simplifies to:
10 ------- x w 1 s V BP ( s ) R3 ----------------- = ---------------------------------------------------------------------V IN ( s ) 4 10 1.1 + ------R3 2 1 S + --------------------- w 1 s + -----------5 w1 w2 10 1 + ------R7 (dB)
4
0 -10 -20 -30 -40 -50 -60 0.1 1.0
Q = 0.5 Q = 1.0 Q = 2.0 Q = 5.0 Q = 10 Q = 20 Q = 50 Q = 100
65-0753
10
This is now in a convenient form to look at the centerfrequency w0 and filter Q.
w0 = 0.1w 1 w 2
-9
w wo
VBP V IN
w wo
= 1-
1 Q + 1 Q
w 0 = 10
0.1R1R2 and
5
w wo
22
w wo
2
10 1 + ------R7 Q = --------------------- w 0 4 10 1.1 + ------R3
Figure 17. Bandpass Transfer Characteristics Normalized for Unity Gain and Frequency
The frequency responses for various values of Q are shown in Figure 17.
9
PRODUCT SPECIFICATION
RC4156/RC4157
These equations suggest a tuning sequence where w is first trimmed via R1 or R2, then Q is trimmed by varying R7 and/or R3. An important advantage of the state-variable bandpass filter is that Q can be varied without affecting center frequency w0. This analysis has assumed ideal op amps operating within their linear range, which is a valid design approach for a reasonable range of w0 and Q. At extremes of w0 and at high values of Q, the op amp parameters become significant. A rigorous analysis is very complex, but some factors are particularly important in designing active filters. 1. The passive component values should be chosen such that all op amps are operating within their linear region for the anticipated range of input signals. Slew rate, output current rating, and common-mode input range must be considered. For the integrators, the current through the feedback capacitor (I = C dV/dt) should be included in the output current computations.
2.
From the equation for Q, it should seem that infinite Q could be obtained by making R7 zero. But as R7 is made small, the Q becomes limited by the op amp gain at the frequency of interest. The effective closed-loop gain is being increased directly as R7 is made smaller, and the ratio of open-loop gain to closed-loop gain is becoming less. The gain and phase error of the filter at high Q is very dependent on the op amp open-loop gain at w0. The attenuation at extremes of frequency is limited by the op amp gain and unity-gain bandwidth. For integrators, the finite open-loop op amp gain limits the accuracy at the low-end. The open-loop roll-off of gain limits the filter attenuation at high frequency.
3.
The RC4156 quad operational amplifier has much better frequency response than a conventional 741 circuit and is ideal for active filter use. Natural frequencies of up to 10 kHz are readily achieved and up to 20 kHz is practical for some configurations. Q can range up to 50 with very good accuracy and up to 500 with reasonable response. The extra gain of the RC4156 at high frequencies gives the quad op amp an extra margin of performance in active-filter circuits.
Schematic Diagram (1/4 shown)
(4) +Vs R1 4900 Q3 Q2 (2,6,9,13) - Input + Input Q4 (3,5,10,12) D2 C1 R7 20 Q7 Q17 Q10 Q9 R3 18K
65-0735
Q1 R9 30 Q13 Q5 R5 30K Q12 Q16 R6 20 R8 150 To Next Amplifier Q15 (1,7,8,14) Outputs
F1
Q6
Q8
Q11 R4 22K
Q14 R2 10K D1 (11) -Vs
10
RC4156/RC4157
PRODUCT SPECIFICATION
Mechanical Dimensions
14-Lead Ceramic DIP Package
Inches Min. A b1 b2 c1 D E e eA L Q s1 a Max. Millimeters Min. Max. 8 2 8 4 4 5, 9 7 3 6 Notes: Notes 1. Index area: a notch or a pin one identification mark shall be located adjacent to pin one. The manufacturer's identification shall not be used as pin one identification mark. 2. The minimum limit for dimension "b2" may be .023 (.58mm) for leads number 1, 7, 8 and 14 only. 3. Dimension "Q" shall be measured from the seating plane to the base plane. 4. This dimension allows for off-center lid, meniscus and glass overrun. 5. The basic pin spacing is .100 (2.54mm) between centerlines. Each pin centerline shall be located within .010 (.25mm) of its exact longitudinal position relative to pins 1 and 14. 6. Applies to all four corners (leads number 1, 7, 8, and 14). 7. "eA" shall be measured at the center of the lead bends or at the centerline of the leads when "a" is 90. 8. All leads - Increase maximum limit by .003 (.08mm) measured at the center of the flat, when lead finish applied. 9. Twelve spaces. D
7 1
Symbol
-- .200 .014 .023 .045 .065 .008 .015 -- .785 .220 .310 .100 BSC .300 BSC .125 .200 .015 .060 .005 -- 90 105
-- 5.08 .36 .58 1.14 1.65 .20 .38 -- 19.94 5.59 7.87 2.54 BSC 7.62 BSC 3.18 5.08 .38 1.52 .13 -- 90 105
NOTE 1
E
8
14
s1 eA
e
A Q L b2 b1 a c1
11
PRODUCT SPECIFICATION
RC4156/RC4157
Mechanical Dimensions (continued)
14-Lead Plastic DIP Package
Inches Min. A A1 A2 B B1 C D D1 E E1 e eB L N -- .015 .115 Max. .210 -- .195 Millimeters Min. -- .38 2.93 Max. 5.33 -- 4.95 Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E1" do not include mold flashing. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. Terminal numbers are shown for reference only. 4. "C" dimension does not include solder finish thickness. 5. Symbol "N" is the maximum number of terminals. 4 2
Symbol
.014 .022 .045 .070 .008 .015 .725 .795 .005 -- .300 .325 .240 .280 .100 BSC -- .430 .115 .200 14
.36 .56 1.14 1.78 .20 .38 18.42 20.19 .13 -- 7.62 8.26 6.10 7.11 2.54 BSC -- 10.92 2.92 5.08 14
2
5
D 7 1
E1
D1
8
14
E e A A1 L B1 B eB C
12
RC4156/RC4157
PRODUCT SPECIFICATION
Mechanical Dimensions (continued)
14-Lead SOIC Package
Inches Min. A A1 B C D E e H h L N a ccc Max. Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
Symbol
.053 .069 .004 .010 .013 .020 .008 .010 .336 .345 .150 .158 .050 BSC .228 .244 .010 .016 14 0 -- 8 .004 .020 .050
1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 8.54 8.76 3.81 4.01 1.27 BSC 5.79 6.20 0.25 0.40 14 0 -- 8 0.10 0.50 1.27
3 6
14
8
E
H
1
7
D A1 A SEATING PLANE -C- LEAD COPLANARITY ccc C a
h x 45 C
e
B
L
13
PRODUCT SPECIFICATION
RC4156/RC4157
Ordering Information
Product Number RC4156N RC4157N RC4156M RC4157M RM4156D RM4156D/883B Temperature Range 0 to 70C 0 to 70C 0 to 70C 0 to 70C -55C to +125C -55C to +125C Screening Commercial Commercial Commercial Commercial Commercial Military Package 14 Pin Plastic DIP 14 Pin Plastic DIP 14 Pin Wide SOIC 14 Pin Wide SOIC 14 Pin Ceramic DIP 14 Pin Ceramic DIP Package Marking RC4156N RC4157N RC4156M RC4157M RM4156DM RM4156DMB
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 7/28/98 0.0m 002 Stock#DS30004156 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC4190
Micropower Switching Regulator
Features
* * * * * High efficiency - 85% typical Low quiescent current - 215 mA Adjustable output - 1.3V to 30V High switch current - 200 mA Bandgap reference - 1.31V * * * * * Accurate oscillator frequency - 10% Remote shutdown capability Low battery detection circuitry Low component count 8-lead packages including small outline (SO-8)
Description
The RC4190 monolithic IC is a low power switch mode regulator intended for miniature power supply applications. This DC-to-DC converter IC provides all of the active components needed to create supplies for micropower circuits (load power up to 400 mW, or up to 10W with an external power transistor). Contained internally are an oscillator, switch, reference, comparator, and logic, plus a discharged battery detection circuit. Application areas include on-card circuits where a non-standard voltage supply is needed, or in battery operated instruments where an RC4190 can be used to extend battery lifetime. These regulators can achieve up to 85% efficiency in most applications while operating over a wide supply voltage range, 2.2V to 30V, at a very low quiescent current drain of 215 mA. The standard application circuit requires just seven external components for step-up operation: an inductor, a steering diode, three resistors, a low value timing capacitor, and an electrolytic filter capacitor. The combination of simple application circuit, low supply current, and small package make the RC4190 adaptable to a wide range of miniature power supply applications. The RC4190 is most suited for single ended step-up (VOUT > VIN) circuits because the NPN internal switch transistor is referenced to ground. It is complemented by another Fairchild Semiconductor micropower switching regulator, the RC4391, which is dedicated to step-down (VOUT < VIN) and inverting VOUT = -VIN) applications. Between the two devices the ability to create all three basic switching regulator configurations is assured. Refer to the RC4391 data sheet for step-down and inverting applications. With some optional external components the application circuit can be designed to signal a display when the battery has decayed below a predetermined level, or designed to signal a display at one level and then shut itself off after the battery decays to a second level. See the applications section for these and other unique circuits. The RC4190 micropower switching regulator series consists of three devices, each with slightly different specifications. The RM4190 has a 1.5% maximum output voltage tolerance, 0.2% maximum line regulation, and operation to 30V. The RC4190 has a 5.0% maximum output voltage tolerance, 0.5% maximum line regulation, and operation to 24V. Other specifications are identical. Each type is available in plastic and ceramic DIPs, or SO-8 packages.
Block Diagram
4190 LBR LBD C2 Q2
CX
OSC
C1 +1.31V 1.31V REF
VFB
Gnd Q1 +1.2V LX BIAS
IC
+VS
65-3464-01
Rev. 1.0.0
PRODUCT SPECIFICATION
RC4190
Pin Assignments
LBR CX GND LX
1 2 3 4 8 7 6 5
65-3464-02
Pin Definitions
LBD VFB IC +VS
Pin Name LBR CX Gnd LX +VS IC VFB LBD
Pin Number 1 2 3 4 5 6 7 8
Pin Function Description Low Battery (Set) Resistor Timing Capacitor Ground External Inductor Positive Supply Voltage Reference Set Current Feedback Voltage Low Battery Detector Output
Absolute Maximum Ratings
(beyond which the device may be damaged)1 Parameter Supply Voltage (Without External Transistor) PDTA < 50C RM4190 RC4190 SOIC PDIP CerDIP Operating Temperature Storage Temperature Junction Temperature Switch Current For TA > 50C Derate at SOIC, PDIP CerDIP Peak SOIC PDIP CerDIP
Note: 1. Functional operation under any of these conditions is NOT implied.
Min
Typ
Max 30 24 300 468 833
Units V V mW mW mW C C C C C
RM4190 RC4190
-55 0 -65 125 175
125 70 150
375 4.17 6.25 8.33
mA mW/C mW/C mW/C
Operating Conditions
Parameter qJC qJA Thermal resistance Thermal resistance CerDIP SOIC PDIP CerDIP Min Typ 45 200 160 120 Max Units C/W C/W C/W C/W
2
RC4190
PRODUCT SPECIFICATION
Electrical Characteristics
(+VS = +6.0V, IC = 5.0 mA over the full operating temperature range unless otherwise noted.) RM4190 Symbol Parameters +VS VREF ISY Supply Voltage Reference Voltage (Internal) Supply Current Line Regulation LI IC ICO ISO ILBD Load Regulation Reference Set Current Switch Leakage Current Supply Current (Disabled) Low Battery Output Current Oscillator Frequency Temperature Drift V4 = 24V (RC4190) 30V (RM4190) VC 200 mV V8 = 0.4V, V1 = 1.1V 500 1200 200 Measure at Pin 5 I4 = 0 0.5 VOUT < VS < VOUT VS = 0.5 VOUT PL = 150 mW 1.0 Conditions Min 2.6 1.25 1.31 235 0.2 0.5 5.0 Typ Max 30 1.37 350 0.5 1.0 50 30 30 500 1200 200 1.0 Min 2.6 1.20 1.31 235 0.5 0.5 5.0 RC4190 Typ Max 24 1.42 350 1.0 1.0 50 30 30 Units V V mA % VO % VO mA mA mA mA ppm/C
3
PRODUCT SPECIFICATION
RC4190
Electrical Characteristics
(+VS = +6.0V, IC = 5.0 mA, and TA = +25C unless otherwise noted.) RM4190 Symbol +VS VREF ISW ISY ef Parameters Supply Voltage Reference Voltage (Internal) Switch Current Supply Current Efficiency Line Regulation LI FO IC ICO Load Regulation Operating Frequency Range Reference Set Current Switch Leakage Current Supply Current (Disabled) Low Battery Bias Current Capacitor Charging Current Oscillator Frequency Tolerance +VTHX -VTHX IFB ILBD Capacitor Threshold Voltage + Capacitor Threshold Voltage - Feedback Input Current Low Battery Output Current V7 = 1.3V V8 = 0.4V, V1 = 1.1V 500 V4 = 24V (RC4190) 30V (RM4190, RC4190A) VC 200 mV V1 = 1.2V 0.5 VOUT < VS < VOUT VS = +0.5 VOUT PL = 150 mW 0.1 1.0 V4 = 400 mV Measure at Pin 5 I4 = 0 Conditions Min 2.2 1.29 100 1.31 200 215 85 0.04 0.2 25 5.0 0.01 0.2 0.5 75 50 5.0 0.1 1.0 300 Typ Max 30 1.33 Min 2.2 1.24 100 1.31 200 215 85 0.04 0.2 25 5.0 0.01 0.5 0.5 75 50 5.0 300 RC4190 Typ Max 24 1.38 Units V V mA mA % % VO % VO kHz mA mA
ISO I1 ICX
0.1 0.7 8.6 10 1.4 0.5 0.1 1500
5.0
0.1 0.7 8.6 10 1.4 0.5 0.1 500 1500
5.0
mA mA mA % V V mA mA
4
RC4190
PRODUCT SPECIFICATION
Typical Performance Characteristics
4.0 300 250 3.0 200 VS (V) 2.4V 2.0 2.0V 1.8V IQ (A) 150 100 1.0
65-2670
230
215
195
VS = +6V -50 -25 0 +25 +50 TA (C)
0 -75
-50
-25
0
+25 +50 TA (C)
+75 +100 +125
0 -75
+75 +100 +125
Figure 1. Minimum Supply Voltage vs. Temperature
Figure 2. Quiescent Current vs. Temperature
1.33 FO (Normalized) (%) 1.32 VREF (V) 1.31 1.30 1.29 1.28 -75
+2.0 +1.5 +1.0 +0.5 0 -0.5 -1.0 -1.5 -2.0 -75 -50 -25 0 +25 +50 TA (C) Figure 4. Oscillator Frequency vs. Temperature
65-2672
-50
-25
0
+25 +50 TA (C)
+75 +100 +125
65-1488
+75 +100 +125
Figure 3. Reference Voltage vs. Temperature
+2 FO (Normalized) (%) +1
0
-1 -2 0 5 10 15 +VS (V) Figure 5. Minimum Supply Voltage vs. Temperature 20 25
65-2667
30
65-2671
50
5
PRODUCT SPECIFICATION
RC4190
Principles of Operation
Simple Step-Up Converter
The most common application, the step-up regulator, is derived from a simple step-up (VOUT > VBAT) DC-to-EC Converter (Figure 6).
L D (+)
If the switch is opened and closed repeatedly, at a rate much greater than the time constant of the output RC, then a constant dc voltage will be produced at the output. An output voltage higher than the input voltage is possible because of the high voltage produced by a rapid change of current in the inductor. When the switch is opened, the inductor voltage will instantly rise high enough to forward bias the diode, to VOUT + VD. In the complete RC4190 regulator, a feedback control system adjusts the on time of the switch, controlling the level of inductor current, so that the average inductor discharge current equals the load current, thus regulating the output voltage.
VBAT
S
C
RL
VOUT
(-)
65-1646
Figure 6. Simple Set-Up
When switch S is closed, the battery voltage is applied across the inductor L. Charging current flows through the inductor, building up a magnetic field, increasing as the switch is held closed. While the switch is closed, the diode D is reverse biased (open circuit) and current is supplied to the load by the capacitor C. Until the switch is opened, the inductor current will increase linearly to a maximum value determined by the battery voltage, inductor value, and the amount of time the switch is held closed (IMAX = VBAT/ L x TON). When the switch is opened, the magnetic field collapses, and the energy stored in the magnetic field is converted into a discharge current which flows through the inductor in the same direction as the charging current. Because there is no path for current to flow through the switch, the current must flow through the switch, the current must flow through the diode to supply the load and charge the output capacitor.
Complete Step-Up Regulator
A complete schematic of the minimum step-up application is shown in Figure 7. The ideal switch in the DC-to-DC Converter diagram is replaced by an open collector NPN transistor Q1. CF functions as the output filter capacitor, and D1 and LX replace D and L. When power is first applied, the current in R1 supplies bias current to pin 6 (IC). This current is stabilized by a unity gain current source amplifier and then used as bias current for the 1.31V bandgap reference. A very stable bias current generated by the bandgap is mirrored and used to bias the remainder of the chip. At the same time the RC4190 is starting up, current will flow through the inductor and the diode to charge the output capacitor to VBAT - VD.
G E ILX LX R1 6 5 VBAT IC +VS Q1 B OSC GND 3 A CX 2 CX F ID (+) 4 LX D + - RL REF LBR 1 NC LBD 8 NC R3 D1
RC4190
VFB +1.31V 7
R2
+ -
CF C ILOAD VOUT = VREF ( R2 + 1) R3
(-)
65-2673A
Figure 7. Complete Step-Up Regulator
6
RC4190
PRODUCT SPECIFICATION
1.4V A 0.5V (Internal) IL (Max) C 0mA 0.72V (Internal) 0V VBAT LX E VOUT - VBAT LX IMAX 0 mA IMAX F ID 0 mA VOUT + VD VLX VMAX 0.3V (Q1 SAT)
65-2674
CX OSC ILOAD
B
D
VBEQ1
ILX
G
Figure 8. Step-Up Regulator Waveforms
+VS
R1 1M CT * 1 F 7 VFB 6 IC 5 +VS
R4
R5
Motorola MBR140P V OUT Q1 TIP73 R2 CF
4190
CX 2
LX
Q2 2N3904
GND 3
R3 CX
* May not be required
R5 =
50 VS IMAX
R4 = 10 R5
65-2675
Figure 9. High Power Step-Up Regulator (With the addition of a power transistor (TIP73) and a few components, the 4190 can accomodate load power up to 10W.)
At this point, the feedback (pin 7) senses that the output voltage is too low, by comparing a division of the output voltage (set by the ratio of R2 to R3) to the +1.31V reference. If the output voltage is too low then the comparator output changes to a logical zero. The NOR gate then effectively ANDs the oscillator square wave with the comparator signal; if the comparator output is zero AND the oscillator output is low, then the NOR gate output is high and the switch transistor will be forced on. When the oscillator goes high again, the NOR gate output goes low and the switch transistor will turn off. This turning on and off of the switch transistor performs
the same function that opening and closing the switch in the simple DC-to-DC Converter does; i.e., it stores energy in the inductor during the on time and releases it into the capacitor during the off time. The comparator will continue to allow the oscillator to turn the switch on and off until enough charge has been delivered to the capacitor to raise the feedback voltage above 1.31V. Thereafter, this feedback system will vary the duration of the on time in response to changes in load current or battery 7
PRODUCT SPECIFICATION
RC4190
voltage (see Figure 8). If the load current increases (waveform C), then the transistor will remain on (waveform D) for a longer portion of the oscillator cycle (waveform B), thus allowing the inductor current (waveform E) to build up to a higher peak value. The duty cycle of the switch transistor varies in response to changes in load and time. The inductor value and oscillator frequency must be carefully tailored to the battery voltage, output current, and ripple requirements of the application (refer to the Design Equations Section). If the inductor value is too high or the oscillator frequency is too high, then the inductor current will never reach a value high enough to meet the load current drain and the output voltage will collapse. If the inductor value is too low or the oscillator frequency too low, then the inductor current will build up too high, causing excessive output voltage ripple, or over stressing of the switch transistor, or possibly saturating the inductor.
voltage applied across the inductor will discharge into the load. As in the step-up case, the average inductor current equals the load current. The maximum inductor current IMAX will equal (VBAT - VOUT)/L times the maximum on time of the switch transistor (TON). Current flows to the load during both half cycles of the oscillator.
Complete Step-Down Regulator
Most step-down applications are better served by the RC4391 step-down and inverting switching regulator (refer to the RC4391 data sheet). However, there is a range of load power for which the RC4190 has an advantage over the RC4391 in step-down applications. From approximately 500 mW to 2W of load power, the RC4190 step-down circuit of Figure 6 offers a lower component count and simpler circuit than the comparable RC4391 circuit, particularly when stepping down a voltage greater than 30V. Since the switch transistor in the RC4190 is in parallel with the load, a method must be used to convert it to a series connection for step-down applications. The circuit of Figure 11 accomplishes this. The 2N2907 replaces S of Figure 10, and R6 and R7 are added to provide the base drive to the 2N2907 in the correct polarity to operate the circuit properly.
Simple Step-Down Converter
Figure 10 shows a step-down DC-to-DC Converter (VOUT VBAT) with no feedback control.
S L (+)
Greater Than 30V Step-Down Regulator
VBAT D C RL VOUT
(-)
65-1644
Figure 10. Simple Step-Down Converter
Adding a zener diode in series with the base of the 2N2907 allows the battery voltage to increase by the value of the zener, with only a slight decrease in efficiency. As an example, if a 24V zener is used, the maximum battery voltage can go to 48V2 when using a RC4190. Refer to Figure 12.
Notes: 1. The addition of the zener diode will not alter the maximum change of supply. With a 24V zener, the circuit will stop operating when the battery voltage drops below 24V + 2.2V = 26.2V. 2. Maximum battery voltage is 54V when using RM4190 (30V + 24V).
When S is closed, the battery voltage minus the output voltage is applied across the inductor. All of the inductor current will flow into the load until the inductor current exceeds the load current. The excess current will then charge the capacitor and the output voltage will rise. When S is opened, the
2N2907 R6
Lx
V OUT
D1 1N914 R7 5 R1 V BAT R4 6 1 +VS IC LBR GND 3 CX 2 Cx R4 = VS - 1.31V 5 A 260K 50 ~ R6 ~ IL 4190 4 LX VFB 7 R3 R2
CF
R5
65-2676
R5 =
10 VS R7 ~ ~ IL
Figure 11. Complete Step-Down Regulator
8
RC4190
PRODUCT SPECIFICATION
2N2907 R6
Lx
V OUT
D1 1N914 Z1 R2 R7 CF
5 R1 V BAT R4 6 1 IC +VS 4190 LBR GND 3 CX 2
4 LX VFB 7
R3 Cx R4 = VS - 1.31V 5 A 260K 50 ~ R6 ~ IL
65-2677
R5
R5 =
10 VS R7 ~ ~ IL
Figure 12. Step-Down Regulator Greater Than 30V
Design Equations
The inductor value and timing capacitor (CX) value must be carefully tailored to the input voltage, input voltage range, output voltage, and load current requirements of the application. The key to the problem is to select the correct inductor value for a given oscillator frequency, such that the inductor current rises to a high enough peak value (IMAX) to meet the average load current drain. The selection of this inductor value must take into account the variation of oscillator frequency from unit to unit and the drift of frequency over temperature. Use 20% as a maximum change from the nominal oscillator frequency. The worst-case conditions for calculating ability to supply load current are found at the minimum supply voltage; use +VS (min) to calculate the inductor value. Worst-case conditions for ripple are at +VS (max). The value of the timing capacitor is set according to the following equation:
2.4 10 f O ( Hz ) = --------------------C X ( pF )
6
Find a value for the start-up resistor R1:
V S - 1.2V R1 = -----------------------5mA
Find a value for the feedback resistors R2 and R3:
V OUT - 1.31V R2 = ----------------------------------IA 1.31V R3 = -------------IA
Where IA is the feedback divider current (recommended value is between 50 mA and 100 mA).
Step-Up Design Procedure
1. 2. Select an operating frequency and timing capacitor as shown above (10 kHz to 40kHz is typical). Find the maximum on time (add 5 mS for the turn-off base recombination delay of Q1):
1 T ON = --------- + 5ms 2F O
The squarewave output of the oscillator is internal and cannot be directly measured, but is equal in frequency to the triangle waveform measurable at pin 4. The switch transistor is normally on when the triangle waveform is ramping up and off when ramping down. Capacitor selection depends on the application; higher operating frequencies will reduce the output voltage ripple and will allow the use of an inductor with a physically smaller inductor core, but excessively high frequencies will reduce load driving capability and efficiency.
3.
Calculate the peak inductor current IMAX (if this value is greater than 375 mA, then an external power transistor must be used in place of Q1):
V OUT + V D - V S I MAX = ae ---------------------------------------------------- o 2I L e ( F O )T ON [ V S - V SW ]o
where: VS = supply voltage VD = diode forward voltage IL = dc load current VSW = saturation voltage of Q1 (typ 0.5V) 9
PRODUCT SPECIFICATION
RC4190
4.
Find an inductance value for LX:
2.
V S - V SW L X ( Henries ) = ae ------------------------o T ON e I MAX o
Build the circuit and apply the worst case conditions to it, i.e., the lowest battery voltage and the highest load current at the desired output voltage. Adjust the inductor value down until the desired output voltage is achieved, then go a little lower (approximately 20%) to cover manufacturing tolerances. Check the output voltage with an oscilloscope for ripply, at high supply voltages, at voltages as high as are expected. Also check for efficiency by monitoring supply and output voltages and currents [eff = (VOUT) (IOUT)/(+VS)(ISY) x 100%$]. If the efficiency is poor, go back to (1) and start over. If the ripple is excessive, then increase the output filter capacitor value or start over.
5.
The inductor chosen must exhibit approximately this value at a current level equal to IMAX. Calculate a value for the output filter capacitor:
3.
6.
4.
V S I MAX T ON ae -------------------- + I Lo e V OUT o C F ( mF ) = ------------------------------------------------VR
where VR = ripple voltage (peak)
5.
Step-Down Design Procedure
1. 2. 3. Select an operating frequency.
Compensation
Determine the maximum on time (TON) as in the stepup design procedure. Calculate IMAX: When large values (>50 kW) are used for the voltage setting resistors, R2 and R3 of Figure 7, stray capacitance at the VFB input can add a lag to the feedback response, destabilizing the regulator, increasing low frequency ripple, and lowering efficiency. This can often be avoided by minimizing the stray capacitance at the VFB node. It can also be remedied by adding a lead compensation capacitor of 100 pF to 10 nF in parallel with R2 in Figure 7.
2I L I MAX = ----------------------------------------------------------------------V S - V OUT o ( F O ) ( T ON ) ae ---------------------------- + 1 e V OUT - V Do
4.
LX
Calculate LX:
V S - V OUT = ae ---------------------------o ( T ON ) e I MAX o
Inductors
Efficiency and load regulation will improve if a quality high Q inductor is used. A ferrite pot core is recommended; the wind-yourself type with an air gap adjustable by washers or spacers is very useful for breadboarding prototypes. Care must be taken to choose a permeable enough core to handle the magnetic flux produced at IMAX; if the core saturates, then efficiency and output current capability are severely degraded and excessive current will flow though the switch transistor. A pot core inductor design section is provided later in this datasheet. An isolated AC current probe for an oscilloscope (example: Tektronix P6042) is an excellent tool for saturation problems; with it the inductor current can be monitored for nonlinearity at the peaks (a sign of saturation).
5.
Calculate a value for the output filter capacitor:
( V S - V OUT )I MAX T ON ae ---------------------------------------------- + ILo e o V OUT C F ( mF ) = -------------------------------------------------------------------------VR
Alternate Design Procedure
The design equations above will not work for the certain input/output voltage ratios, and for these circuits another method of defining component values must be used. If the slope of the current discharge waveform is much less than the slope of the current charging waveform, then the inductor current will become continuous (never discharging completely), and the equations will become extremely complex. So, if the voltage applied across the inductor during the charge time is greater than during the discharge time, used the design procedure below. For example, a step-down circuit with 20V input and 5V output will have approximately 15V across the inductor when charging, and approximately 5V when discharging. So in this example, the inductor current will be continuous and the alternate procedure will be necessary. 1. Select an operating frequency (a value between 10 kHz and 40 kHz is typical).
Low Battery Detector
An open collector signal transistor Q2 with comparator C2 provides the designer with a method of signaling a display or computer whenever the battery voltage falls below a programmed level (see Figure 8). This level is determined by the +1.3V reference level and by the selection of two external resistors according to the equation:
R4 V TH = V REF ae ------ + 1o e R5 o
Where VTH = Threshold Voltage for Detection
10
RC4190
PRODUCT SPECIFICATION
+Vs
R4 1 LBR C2 R5 V REF 1.31V
65-1651
LBD 8 Q2 I LBD
Another method of automatic shutdown without temperature limitations is the use of a zener diode in series with the IC pin and set resistor. When the battery voltage falls below VZ + 1.2V the circuit will start to shut down. With this connection and the low battery detector, the application can be designed to signal a display when the battery voltage has dropped to the first programmed level, then shut itself off as the battery reaches the zener threshold. The set current can also be turned off by forcing the IC pin to 0.2V or less using an external transistor or mechanical switch. An example of this is shown in Figure 15. In this circuit an external control voltage is used to determine the operating state of the RC4190. If the control voltage VC is a logic 1 at the input of the 4025 (CMOS Triple NOR Gate), the voltage at the IC pin will be less than 0.5V forcing the 4190 off (<0.1 mA ICC). Both the 2N3904 and 2N2907 will be off insuring long shelf for the battery since less than 1.0 mA is drawn by the circuit. When VC goes to a logic 0, 2.0 mA is forced into the IC pin through the 2.2 MW resistor and the NOR gate, and at the same time the 2N3904 and 2N2907 turn on, connecting the battery to the load. As long as VC remains low the circuit will regulate the output to 5.0V. This type of circuit is used to back up the main supply voltage when line interruptions occur, a particularly useful feature when using volatile memory systems.
Figure 13. Low Battery Detector
When the battery voltage drops below this threshold Q2 will turn on and sink over 1500 mA typically. The low battery detector circuitry may also be used for other, less conventional applications (see Figures 19 and 20).
Automatic Shutdown
The bias control current for the reference is externally set by a resistor from the IC pin to the battery. This current can vary from 1.0 mA to 50 mA without affecting the operation of the IC. Interrupting this current will disable the entire circuit, causing the output voltage to go to 0V for step-down applications, and reducing the supply current to less than 1.0 mA. Automatic shutdown of the RC4190 can be achieved using the circuit of Figure 14.
5 +V S VBAT R1 6 IC GND 3
65-2678
9.0V Battery Life Extender
4190
R9
Figure 16 shows a common application: a circuit to extend the lifetime of a 9.0V battery. The regulator remains in its quiescent state (drawing only 215 mA) until the battery voltage decays below 7.5V, at which time it will start to switch and regulate the output at 7.0V until the battery falls below 2.2V. If this circuit operates at its typical efficiency of 80%, with an output current of 10 mA, at 5.0V battery voltage, then the average input current will be IIN = (VOUT x IL) (VBAT x ef) or (7.0V x 10 mA) (5.0V x 0.8 mA) = 17.5 mA.
Figure 14. Automatic Shutdown
A resistor is placed from the IC pin to ground, creating a voltage divider. When the voltage at the IC pin is less than 1.2V, the RC4190 will begin to turn off. This scheme should only be used in limited temperature range applications since the "turn off" voltage at the IC pin has a temperature coefficient of -4.0 mV/C. At 25C, typically 250 nA is the minimum current required by the IC pin to sustain operation. A 5.0 mA voltage divider works well taking into account the sustaining current of 250 nA and a threshold voltage of 0.4V at turn off. As an example, if 3.0V is to be the turn off voltage, then R9 = 1.1/4.75 mA and R1 = (3.0 - 1.1) 5.0 mA or about 240 kW and 390 kW respectively. The tempco at the top of the divider will be -4.0 mV (R1 + R9)/R9 or -10.5 mV/C, an acceptable number for many applications.
Bootstrapped Operation (Step-Up)
In step-up applications, power to the RC4190 can be derived from the output voltage by connecting the +VS pin and the top of R1 to the output voltage (Figure 17). One requirement for this circuit is that the battery voltage must be greater than 3.0V when it is energized or else there will not be enough voltage at pin 5 to start up the IC. The big advantage of this circuit is the ability to operate down to a discharged battery voltage of 1.0V.
11
PRODUCT SPECIFICATION
RC4190
Lx 1.0 mH VBAT 4 5 +V S 2.2M 6 Lx
D1
2N2907
VOUT = 5V CF 37K
2.4K 4190 V FB Cx 2 Cx 7 13K
IC GND 3
1/3 4025 Vc
15K 2N3904
65-2679
Figure 15. Battery Back-Up Circuit
9V to 2.2V VBAT R1 1M
Lx 1.0 mH 6 1 R4* 910K 5 +Vs 4190 Cx 2 Cx 50 pF 4 Lx
1N914
VOUT = 9V To 7V
R2 110K
IC
CF 50F
LBR GND 3 R5* 260K
VFB 7 R3 25K
* Optional
65-2680
Figure 16. 9.0V Battery Life Extender
3V to 9V VBAT R1 1M
Lx 1.0 mH 6 5 +Vs 4190 LBR GND 3 Cx 2 Cx 50 pF 4 Lx VFB
1N914
VOUT = 9V
R2 77K 7 R3 13K
IC 1 R4* 910
CF 50 mF
R5* 260K
* Optional
65-2682
Figure 17. Bootstrapped Operation (Step-Up)
12
RC4190
PRODUCT SPECIFICATION
Buck-Boost Circuit (Step-Up/Down)
A disadvantage of the standard step-up and step-down circuits is the limitation of the input voltage range; for a stepup circuit, the battery voltage must always be less than the programmed output voltage, and for a step-down circuit, the battery voltage must always be greater than the output voltage. The following circuit eliminates this disadvantage, allowing a battery voltage above the programmed output voltage to decay to well below the output voltage (see Figure 18). The circuit operation is similar to the step-up circuit operation, except that both terminal of the inductor are connected to switch transistors. This switching method allows the inductor to be disconnected from the battery during the time the inductor is being discharged. A new discharge path is provided by D1, allowing the inductor to be referenced to ground and independent of the battery voltage. The efficiency of this circuit will be reduced to 55-60% by losses in the extra switch transistor and diode. Efficiency can be
improved by choosing transistors with low saturation voltages and by using power Schottky diodes such as Motorola's MBR030.
Step-Up Voltage Dependent Oscillator
The RC4190's ability to supply load current at low battery voltages depends on the inductor value and the oscillator frequency. Low values of inductance or a low oscillator frequency will cause a higher peak inductor current and therefore increase the load current capability. A large inductor current is not necessarily best, however, because the large amount of energy delivered with each cycle will cause a large voltage ripple at the output, especially at high input voltages. This trade-off between load current capability and output ripple can be improved with the circuit connection shown in Figure 19. This circuit uses the low battery detector to sense for a low battery voltage condition and will decrease the oscillator frequency after a pre-programmed threshold is reached.
+VBAT
D1 1N914
1.0 mH Lx
D2 1N914
+VOUT
2N2906 or Equivalent R1 1M 6 IC 4190 CX 2 Cx R4 2.2K 5 +VS LX 4
CF 100 F R2
VFB 7 GND 3
R3
65-2681
Figure 18. Buck Boost Circuit (Step-Up/Down)
+VBAT R1 1M 6 IC 1 LBR LBD 8 C2 CX 2
Lx
1N914
+VOUT CF
R4
5 +VS 4190
4 LX VFB Gnd 3 7
R2
R5
R3
Cx
65-2683
Figure 19. Step-Up Voltage Dependent Oscillator
13
PRODUCT SPECIFICATION
RC4190
The threshold is programmed exactly as the noram low battery detector connection:
R4 V TH = V REF ae ------ + 1o e R5 o
shows a schematic of a step-down regulator with this connection. R2 and R3 set the output voltage, as in the circuit of Figure 2. Choose resistor values so R5 = R3 and R4 = R2, and make R8 25 to 35 times higher than R3. When the output is shorted, the open collector transistor at pin 8 will force pin 2 low and shut off the oscillator and therefore shut off the external switch transistor. The regulator will then remain in a low current off condition until power is removed and reapplied. C2 provides momentary current to ensure proper startup. This scheme will not work with the simple step-up regulator, but will work with the boost-buck converter, providing short circuit protection in both step-up and step-down modes.
When the battery voltage reaches this threshold, the comparator will turn on the open collector transistor at pin 8, effectively putting C2 in parallel with CX. This added capacitance will reduce the oscillator frequency according to the following equation:
2.4 10 F O = -----------------------C X + C2
-6
Where C is in pF and FO is in Hz. Component values for a typical application might be R2 = 330 kW, R5 = 150 kW, CX = 100 pF, and C2 = 100 pF. These values would set the threshold voltage at 4.1V and change the operating frequency from 48 kHz to 24 kHz. Note that this technique may be used for step-up, step-down, or inverting applications.
RC4190/RC4391 Power Supply
A positive and negative dual tracking power supply using a step-up RC4190 and an inverting RC4391 is shown in Figure 21. The inductor and capacitor values were chosen to achieve the highest practical output currents from a +12V battery, as it decays, while keeping the output voltage ripple under 100 mVp-p at 15V output. The circuit may be adapted to other voltages and currents, but note that the RC4190 is step-up, so VOUT must be greater than VBAT. The output voltages may both be trimmed by adjusting a single resistor value (R3 or R4), because the reference for the negative output is derived from +VOUT. This connection also allows the output voltages to track each other with changes in temperature and line voltage.
Step-Down Regulator With Protection
One disadvantage of the simple application circuits is their lack of short circuit protection, especially for the step-up circuit, which has a very low resistance path for current flow from the input to the output. A current limiting circuit which senses the output voltage and shuts down the 4190 if the output voltage drops too low can be built using the low battery detector circuitry. The low battery detector is connected to sense the output voltage and will shut off the oscillator by forcing pin 2 low if the output voltage drops. Figure 20
VBAT R6 1.0K 6 IC C2 10 F R8 LBD 8 R8 = 35(R3) 4190
2N3635
1N914
+VOUT
R1 1M
Lx R2 5 +VS VFB LBR CX 2 Cx VOUT = 1.31 ( R2 + 1) R3 Gnd 7 1 3 R3 R5 R4
CF
65-2684
Figure 21. Step-Down Regulator with Protection
14
RC4190
PRODUCT SPECIFICATION
The timing capacitors are set up exactly as in the voltage dependent oscillator application of Figure 19. The values of R2, R5, C6, and C4 that are given were chosen to optimize for the +12V battery conditions, setting the threshold for oscillator frequency change at VBAT = +8.5V. As given, this power supply is capable of delivering +45 mA and -15 mA with regulation, until the battery decays below 5.0V. For information on adjusting the RC4391 to meet a specific application refer to the Fairchild Semiconductor RC4391 data sheet.
Negative Step-Up Regulator
In the circuit of Figure 22, a bootstrap arrangement of supply and ground pins helps generate an output voltage more negative than the input voltage. On power-up, the output filter capacitor (CF) will charge through D2 and LX. When the voltage goes below -2.4V, the RC4190 begins switching and charging CF. The output will regulate at a value equal to the reference voltage (1.31V) plus the zener voltage of D1. RZ sets the value of zener current, stabilized at 1.31V/R2.
-I OUT = -15 mA D1 1N914 V REF +1.25V L1 50 H 8 R7 100K 7 6 R1 21M 4
+V BAT (2.4 to 5V) L2 100 H
-V OUT C1 150 F
D2 1N914
+I OUT = 45 mA +VOUT
R7 100K
5 Lx VFB Cx 3
5 6 I +Vs C
4 Lx 4190 VFB LBR 1 7
VREF +Vs 4391 LBD 2 GND LBR 1 R4 100K
C3 200 pF
R2 68K
CF2 330 F
3 GND Cx 2
LBD 8
R3 27K
C6 40 pF To +VOUT C7 20 pF R5 18K C5 20 pF
C4 40 pF +VOUT = VREF ( -VOUT = +VOUT R2 +1) R3 R6 ( ) R7
65-2685
Figure 21. RC4190/RC4391 Power Supply (15V)
D1 R1 1M 7 VFB R2 10K CX 2 CX R3 R4 D2 -V OUT + CF LX -V IN
65-4131
6 IC 4190 Gnd 3
5 +VS LX 4
Q1
Figure 22. Negative Step-Up Regulator
15
16
+VS (5) LX (4) VFB (7) CX (2) Q50 Q13 Q10 Q28 Q27 Q17 Q18 Q30 Q36 Q38 Q48 Q49 C2 29.4pF R8 2K Q31 R7 23K Q8 Q24 Q15 Q14 Q23 R2 70K Q11 Q12 Q16 Q22 R4 131K Q21 Q25 Q26 Q19 Q20 Q34 Q37 R10 80K Q33 Q35 Q39 Q40 Q45 Q46 Q47 Q32 Q9 Q29 Q44 Q41 Q42 Q43 R9 24K
65-2665
PRODUCT SPECIFICATION
Q3
Q4
Simplified Schematic Diagram
Q5
Q6
C1 14.2pF
IC (6)
Q7
Q2
R5 3.5K
Q1
R3 81.5K
R6 34.4K
R1 147K
(8) LBD
(1) LBR
(3) Gnd
RC4190
PRODUCT SPECIFICATION
RC4190
Troubleshooting Chart
Symptom Draws excessive supply current on start-up Possible Problem Battery not "stiff" -- inadequate supply bypass capacitor. Inductance value too low. Operating frequency (FO) too low. Output voltage is low. Inductor "sings" with audible hum. LX in appears noisy -- scope will not synchronize. Inductor current shows nonlinear waveform.
-IMAX ILX Time
65-3464-04
Inductance value too high for FO or core saturating. Not potted well or bolted loosely. Normal operating condition. Inductor is saturating: 1. Core too small. 2. Core too hot. 3. Operating frequency too low.
Inductor current shows nonlinear waveform.
-IMAX ILX Time
65-3464-05
Waveform has resistive component: 1. Wire size too small. 2. Power transistor lacks base drive. 3. Components not rated high enough. 4. Battery has high series resistance.
Inductor current is linear until high current is reached.
-IMAX ILX Time
65-3464-06
External transistor lacks base drive or beta is too low.
Poor efficiency.
Core saturating. Diode or transistor: 1. Not fast enough. 2. Not rated for current level (high VCE SAT). High series resistance. Operating frequency too high.
Motorboating (erratic current pulses).
Loop stability problem -- needs feedback capacitor from VOUT to VFB (pin 7), 100 to 1000 pF.
17
PRODUCT SPECIFICATION
RC4190
Background Information
During the past several years there have been various switching regulator ICs introduced by many manufacturers, all of which attended to the same market, namely controllers for use in power supplies delivering greater than 10W of DC power. Fairchild Semiconductor felt there was another area which could use a switching regulator to even more advance the area of battery powered equipment. Battery powered systems have problems peculiar unto themselves: changes in supply voltage, space considerations, battery life and usually cost. The RC4190 was designed with each of these in mind. The RC4190 was partitioned to work in an eight pin package, making it smaller than other controllers which go into 14 and 16 pin packages. Battery powered applications require the load as seen by the battery to be as small as possible to extend battery life. To this end, the quiescent current of the RC4190 is 15 to 100 times less than controllers designed for nonbattery applications. At the same time, the switch transistor can sink 200 mA at 0.4V, comparable to or better than higher powered controllers. As an example, the 4190 configured in the step-up mode can supply 5.0V at 40 mA output with an input of 3.0V. Cost is usually a primary consideration in battery powered systems. The RC4190, guaranteed to work down to 2.2V, can save the designer and end user money as well because battery costs decrease as the number of cells needed goes down.
Soft Start
+VS
1M
6 CT IC RC4190
65-2076
The delay introduced by the RC time constant at start-up allows the output filter capacitor to charge up, reducing the instantaneous supply current. A typical value for C is in the 0.1mF range.
Bootstrapped Low Voltage Start-Up
Figure 24 shows the bootstrapped application can be "kicked on" using an extra capacitor and triple pole double throw switch (3PDT). This connection allows the circuit to start up using a single Ni-Cad cell of 1.2V to 1.6V. When power is first applied the 1.2V battery does not provide enough voltage to meet the minimum 2.2V supply voltage requirement. The 22mF capacitor, when switched, temporarily doubles the battery voltage to bias up the RC4190.
1N914 D1 LX 100 H 4 22 F TPDT VBAT 1.2V R1 1M 5 +VS LX 4190 IC VBAT CX 100 pF 2 GND 3
65-2078
D2 Motorola MBR140P R2 33K VFB 7 R3 13K
VOUT = +5V, 10 mA CF 22 pF
6
Figure 24. Bootstrapped Low Voltage Start-Up
18
RC4190
PRODUCT SPECIFICATION
When the switch is the down position, the capacitor charges up to the battery voltage. The, when the switch is changed to the up position, the capacitor is put in series connection with the battery, and the doubled voltage is applied directly to the positive power supply lead of the RC4190. This voltage is enough to bias the junctions internal to the RC4190 and gets it started. Then, when the stepped up output voltage reaches a high enough value, diode D1 is forward biased and the output voltage takes over supplying power to the RC4190. The circuit is shown with component values for +5V output, but the circuit can be set up for other voltages.
Question: What happens if too small a core is used? First, one must understand how the inductor's magnetic field works. The magnetic circuit in the inductor is very similar to a simple resistive electrical circuit (see Figure 20). There is a magnetizing force (H, in oersteds), a flow of magnetism, or flux density (B, in Gauss), and resistance to the flux, called permeability (U, in Gauss per oersted). H is equivalent to voltage in the electrical model, flux density is like current flow, and permeability is like resistance (except for two important differences discussed on the following page). First Difference: Permeability, instead of being analogous to resistance, is actually more like conductance (1/R). As permeability increases, flux increases. Second Difference: Resistance is a linear function. As voltage increases, current increases proportionally, and the resistance value stays the same. In a magnetic circuit the value of permeability varies as the applied magnetic force varies. This nonlinear characteristic is usually shown in graph form in ferrite core manufacturer's data sheets. See Figure 26.
Electricity Versus Magnetism
Electrically the inductor must meet just one requirement, but that requirement can be hard to satisfy. The inductor must exhibit the correct value of inductance (L, in Henrys) as the inductor current rises to its highest operating value (IMAX). This requirement can be met most simply by choosing a very large core and winding it until it reaches the correct inductance value, but that brute force technique wastes size, weight and money. A more efficient design technique must be used.
Electrical Circuit I E=I*R E R North
Magentic Circuit
H =B * South
1 U
Flux
65-3464-07
Figure 25. Electricity Versus Magnetism
6000 5000 B Gauss 4000 3000 2000 1000
65-2170
+25C +85C +125C
Stackpole Ceramag 24B Hysteresis Loop vs. Temperature
0 -0.5 0 0.5 1
2 2.5 3 H Oersteds
5
7
9
Figure 26. Typical Manufacturer's Curve Showing Saturation Effect
19
PRODUCT SPECIFICATION
RC4190
As the applied magnetizing force increases, at some point the permeability will start decreasing, and therefore the amount of magnetic flux will not increase any further, even as the magnetizing force increases. The physical reality is that, at the point where the permeability decreases, the magnetic field has realigned all of the magnetic domains in the core material. Once all of the domains have been aligned the core will then carry no more flux than just air; it becomes as if there were no core at all. This phenomenon is called saturation. Because the inductance value, L, is dependent on the amount of flux, core saturation will cause the value of L to decrease dramatically, in turn causing excessive and possibly destructive inductor current.
Core Size
Question: Is core size selected according to load power? Not quite. Core size is dependent on the amount of energy stored, not on load power. Raising the operating frequency allows smaller cores and windings. Reduction of the size of the magnetics is the main reason switching regulator design tends toward higher operating frequency. Designs with the RC4190 should use 75kHz as a maximum running frequency, because the turn off delay of the power transistor and stray capacitive coupling begin to interfere. Most applications are in the 10 to 50kHz range, for efficiency and EMI reasons. The peak inductor current (IMAX) must reach a high enough value to meet the load current drain. If the operating frequency is increased, and simultaneously the inductor value is decreased, then the core can be made smaller. For a given core size and winding, an increase in air gap spacing (an air gap is a break in the material in the magnetic path, like a section broken off a doughnut) will cause the inductance to decrease and IMAX (the usable peak current before saturation) to increase. The curves shown in Figure 26 are typical of the ferrite manufacturer's power HF material, such as Siemens N27 or Stackpole 24B, which are usually offered in standard millimeter sizes including the sizes shown.
Pot Cores for RC4190
Pot core inductors are best suited for the RC4190 micropower switching regulator for several reasons: 1. They are available in a wide range of sizes. RC4190 applications are usually low power with relatively low peak currents (less than 500mA). A small inexpensive pot core can be chosen to meet the circuit requirements. Pot cores are easily mounted. They can be bolted directly to the PC card adjacent to the regulator IC. Pot cores can be easily air-gapped. The length of the gap is simply adjusted using different washer thicknesses. Cores are also available with predetermined air gaps. Electromagnetic interference (EMI) is kept to a minimum. The completely enclosed design of pot core reduces stray electromagnetic radiation--an important consideration of the regulator circuit is built on a PC card with other circuitry.
22X 13 mm 24 Gauge 70 Turns DCW = 0.5W
2. 3.
Use of the Design Aid Graph (Figure 27)
1. 2. From the application requirement, determine the inductor value (L) and the required peak current (IMAX). Observe the curves of the design aid graph and determine the smallest core that meets both the L and I requirements.
4.
Air Gap = 0.02" 3A Air Gap = 0.012"
#1
#2
18X 11 mm 26 Gauge 70 Turns DCW = 0.7W
IMAX (Amperes*)
2A #1 1A #2 #3 0 #4 1 mH 2 mH
Air Gap = 0.006"
#3
#4
11X 7 mm 30 Gauge 50 Turns DCW = 1W
3 mH
Inductor Value (Henries)
*Includes safety margin (25%) to ensure nonsaturation
Figure 27. Inductor Design Aid
20
65-2171
14X 8 mm 28 Gauge 60 Turns DCW = 0.6W
No Air Gap
RC4190
PRODUCT SPECIFICATION
3.
Note the approximate air gap at IMAX for the selected core, and order the core with the gap. (If the gapping is done by the user, remember that a washer spacer results in an air gap of twice the washer thickness, because two gaps will be created, one at the center post and one at the rim, like taking two bites from a doughnut.) If the required inductance is equal to the indicated value on the graph, then wind the core with the number of turns shown in table of sizes. The turns given are the maximum number for that gauge of wire that can be easily wound in the cores winding area. If the required inductance is less than the value indicated on the graph, a simple calculation must be done to find the adjusted number of turns. Find AL (inductance index) for a specific air gap.
L ( indicated ) -------------------------------- = AL 2 Turns
Compare the waveform you see to those pictured in Figure 28. Check for saturation at the highest expected ambient temperature. 7. After the operation in circuit has been checked, reassemble and pot the core using a potting compound recommended by the manufacturer. If the core material differs greatly in magnetic characteristics from the standard power material shown in Figure 22, then the following general equation can be used to help in winding and gapping. This equation can be used for any core geometry, such as an E-E core.
( 1.26 ) ( N ) ( Ae ) ( 10 ) L X = ----------------------------------------------------g = ( le ) ( ue )
2 8
4.
5.
in Henrys/turn2 Then divide the required inductance value by AL to give the actual turns squared, and take the square root to find the actual turns needed.
L ( required ) ActualTurns = -----------------------------AL
Where: N = number of turns Ae = core area from data sheet (in cm2) le = magnetic path length from data sheet (in cm) ue = permeability of core from manufacturer's graph g = center post air gap (in cm)
Manufacturers
Below is a list of several pot core manufacturers: Ferroxcube Company 5083 Kings Highway Saugerties, NY 12477 Indiana General Electronics Keasley, NJ 08832 Siemens Company 186 Wood Avenue South Iselin, NJ 08830 Stackpole Company 201 Stackpole Street St. Mary, PA 15857 TDK Electronics 13-1-Chome Nihonbaski, Chuo-ku, Tokyo
If the actual number of turns is significantly less than the number from the table then the wire size can be increased to use up the left-over winding area and reduce resistive losses. 6. Wind and gap the core as per calculations, and measure the value with an inductance meter. Some adjustment of the number of turns may be necessary. The saturation characteristics may be checked with the inductor wired into the switching regulator application circuit. To do so, build and power up the circuit. Then (recommend Tektronix P6042 or equivalent) around the inductor lead and monitor the current in the inductor. Draw the maximum load current from the application circuit so that the regulator is running at close to full duty cycle.
Proper Operation (Waveform is Fairly Linear)
Improper Operation (Waveform is Nonlinear, Inductor Is Saturating) IMAX
IMAX
0
0
65-3464-08
Figure 28. Inductor Current Waveforms
21
PRODUCT SPECIFICATION
RC4190
Mechanical DImensions
8-Lead Ceramic DIP Package
Inches Min. A b1 b2 c1 D E e eA L Q s1 a Max. Millimeters Min. Max. 8 2, 8 8 4 4 5, 9 7 3 6 Notes: Notes 1. Index area: a notch or a pin one identification mark shall be located adjacent to pin one. The manufacturer's identification shall not be used as pin one identification mark. 2. The minimum limit for dimension "b2" may be .023 (.58mm) for leads number 1, 4, 5 and 8 only. 3. Dimension "Q" shall be measured from the seating plane to the base plane. 4. This dimension allows for off-center lid, meniscus and glass overrun. 5. The basic pin spacing is .100 (2.54mm) between centerlines. Each pin centerline shall be located within .010 (.25mm) of its exact longitudinal position relative to pins 1 and 8. 6. Applies to all four corners (leads number 1, 4, 5, and 8). 7. "eA" shall be measured at the center of the lead bends or at the centerline of the leads when "a" is 90. 8. All leads - Increase maximum limit by .003 (.08mm) measured at the center of the flat, when lead finish applied. 9. Six spaces. D 4 1 Note 1 E
Symbol
-- .200 .014 .023 .045 .065 .008 .015 -- .405 .220 .310 .100 BSC .300 BSC .125 .200 .015 .060 .005 -- 90 105
-- 5.08 .36 .58 1.14 1.65 .20 .38 -- 10.29 5.59 7.87 2.54 BSC 7.62 BSC 3.18 5.08 .38 1.52 .13 -- 90 105
5 s1
8
e
eA
A Q L b2 b1 a c1
22
RC4190
PRODUCT SPECIFICATION
Mechanical DImensions (continued)
8-Lead Plastic DIP Package
Inches Min. A A1 A2 B B1 C D D1 E E1 e eB L N -- .015 .115 .014 .045 .008 .348 .005 .300 .240 Max. .210 -- .195 .022 .070 .015 .430 -- .325 .280 Millimeters Min. -- .38 2.93 .36 1.14 .20 8.84 .13 7.62 6.10 Max. 5.33 -- 4.95 .56 1.78 .38 10.92 -- 8.26 7.11 Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E1" do not include mold flashing. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. Terminal numbers are for reference only. 4. "C" dimension does not include solder finish thickness. 5. Symbol "N" is the maximum number of terminals. 4 2
Symbol
2
.100 BSC -- .430 .115 .160 8
2.54 BSC -- 10.92 2.92 4.06 8 5
D 4 1
E1
D1
5
8
E e A A1 L B1 B eB A2 C
23
PRODUCT SPECIFICATION
RC4190
Mechanical DImensions (continued)
8-Lead SOIC Package
Inches Min. A A1 B C D E e H h L N a ccc Max. Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
Symbol
.053 .069 .004 .010 .013 .020 .008 .010 .189 .197 .150 .158 .050 BSC .228 .010 .016 8 0 -- 8 .004 .244 .020 .050
1.35 1.75 0.10 0.25 0.33 0.51 0.20 0.25 4.80 5.00 3.81 4.01 1.27 BSC 5.79 0.25 0.40 8 0 -- 8 0.10 6.20 0.50 1.27
3 6
8
5
E
H
1
4
D A1 A SEATING PLANE B -C- LEAD COPLANARITY ccc C a
h x 45 C
e
L
24
PRODUCT SPECIFICATION
RC4190
Ordering Information
Product Number RC4190M RC4190N RM4190D RM4190D/883B RV4190N Temperature Range 0 to 70C 0 to 70C -55C to +125C -55C to +125C -25C to +85C Military Industrial Screening Commercial Commercial Package 8 Pin Narrow SOIC 8 Pin Plastic DIP 8 Pin Ceramic DIP 8 Pin Ceramic DIP 8 Pin Plastic DIP
Note: 1. /883B suffix denotes MIL-STD-883, Level B processing.
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS30004190 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC4191/RC4192/RC4193
Micropower Switching Regulator
Features
* * * * * High efficiency - 85% typical Low quiescent current - 215 mA Adjustable output - 1.3V to 30V High switch current - 200 mA Bandgap reference - 1.31V * * * * * Accurate oscillator frequency - 10% Remote shutdown capability Low battery detection circuitry Low component count 8-lead packages
Description
The RC4191/4192/4193 series of monolithic ICs are low power switch mode regulators intended for miniature power supply applications. These DC-to-DC converter ICs provide all of the active components needed to create supplies for micropower circuits. Contained internally are an oscillator, switch, reference, comparator, and logic, plus a discharged battery detection circuit. These regulators can achieve up to 85% efficiency in most applications while operating over a wide supply voltage range, 2.2V to 30V, at a very low quiescent current drain of 215 mA. The standard application circuit requires just seven external components for step-up operation: an inductor, a steering diode, three resistors, a low value timing capacitor, and an electrolytic filter capacitor. The combination of simple application circuit, low supply current, and small package make the RC4193 adaptable to a wide range of miniature power supply applications. The RC4193 is most suited for single ended step-up (VOUT > VIN) circuits because the NPN internal switch transistor is referenced to ground. It is complemented by Fairchild Semiconductor's micropower switching regulator, the RC4391, which is dedicated to step-down (VOUT < VIN) and inverting VOUT = -VIN) applications. Between the two devices the ability to create all three basic switching regulator configurations is assured. Refer to the RC4391 data sheet for step-down and inverting applications. The RC4191/92/93 series of micropower switching regulators consists of three devices, each with slightly different specifications. The RM4191 has a 1.5% maximum output voltage tolerance, 0.2% maximum line regulation, and operation to 30V. The RC4192 has a 3.0% maximum output voltage tolerance, 0.5% maximum line regulation, and operation to 30V. The RC4193 has a 5.0% maximum output voltage tolerance, 0.5% maximum line regulation, and operation to 24V. Other specifications are identical for the RC4191, RC4192 and RC4193. Each type is available in commercial, industrial, and military temperature ranges, and in plastic and ceramic DIPs and S0-8 packages.
Block Diagram
4191/92/93 LBR LBD C2 Q2
CX
OSC
C1 +1.31V 1.31V REF
VFB
LX Q1
IC
+1.2V Gnd BIAS +VS
65-3465-01
Rev. 1.0.0
PRODUCT SPECIFICATION
RC4191/RC4192/RC4193
Pin Assignments
LBR CX LX GND
1 2 3 4 8 7 6 5
65-3465-02
Pin Definitions
LBD VFB IC +VS
Pin Name LBR CX LX Gnd +VS IC VFB LBD
Pin Number 1 2 3 4 5 6 7 8
Pin Function Description Low Battery (Set) Resistor Timing Capacitor External Inductor Ground Positive Supply Voltage Reference Set Current Feedback Voltage Low Battery Detector Output
Absolute Maximum Ratings
(beyond which the device may be damaged)1 Parameter Supply Voltage (Without External Transistor) PDTA < 50C 4191, 4192 4193 SOIC PDIP CerDIP Operating Temperature RM4191/2/3 RV4191/2/3 RC4191/2/3 Storage Temperature Junction Temperature Switch Current For TA > 50C Derate at SOIC, PDIP CerDIP Peak SOIC PDIP CerDIP 4.17 6.25 8.33 -55 -25 0 -65 125 175 375 Min Typ Max 30 24 300 468 833 125 85 70 150 Units V V mW mW mW C C C C C C mA mW/C mW/C mW/C
Note: 1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded.
Operating Conditions
Parameter qJC qJA Thermal resistance Thermal resistance CerDIP SOIC PDIP CerDIP Min Typ 45 240 160 150 Max Units C/W C/W C/W C/W
2
RC4191/RC4192/RC4193
PRODUCT SPECIFICATION
Electrical Characteristics
(+VS = +6.0V, IC = 5.0 mA over the full operating temperature range unless otherwise noted.) 4191 Parameters +VS VREF ISY Supply Voltage Reference Voltage (Internal) Supply Current Line Regulation LI IC ICO ISO ILBD Load Regulation Reference Set Current Switch Leakage Current Supply Current (Disabled) Low Battery Output Current Oscillator Frequency Temperature Drift V3 = 24V (4193) 30V (4191, 4192) VC 200 mV V8 = 0.4V, V1 = 1.1V 400 1200 200 Measure at Pin 5 I3 = 0 0.5 VO < VS < VO VS = 0.5 VO PL = 150 mW 1.0 Conditions Min 2.6 Typ Max Min 30 2.6 4192 Typ Max Min 30 2.6 4193 Typ Max Units 24 V V mA % VO % VO mA mA mA mA ppm/ C
1.25 1.31 1.37 1.23 1.31 1.39 1.20 1.31 1.42 225 0.2 0.5 5.0 350 0.5 1.0 50 30 30 400 1200 200 1.0 235 0.5 0.5 5.0 350 1.0 1.0 50 30 30 400 1200 200 1.0 225 0.5 0.5 5.0 350 1.0 1.0 50 30 30
3
PRODUCT SPECIFICATION
RC4191/RC4192/RC4193
Electrical Characteristics
(+VS = +6.0V, IC = 5.0 mA, and TA = +25C unless otherwise noted.) 4191 Parameters +VS VREF ISW ISY ef LI FO IC ICO ISO I1 ICX Supply Voltage Reference Voltage (Internal) Switch Current Supply Current Efficiency Line Regulation Load Regulation Operating Frequency Range Reference Set Current Switch Leakage Current Supply Current (Disabled) Low Battery Bias Current Capacitor Charging Current Oscillator Frequency Tolerance +VTHX Capacitor Threshold Voltage + Capacitor Threshold Voltage - Feedback Input Current Low Battery Output Current V7 = 1.3V V8 = 0.4V, V1 = 1.1V V3 = 24V (4193), 30V (4191/2) VC 200 mV V1 = 1.2V 0.5 VO < VS < VO VS = +0.5 VOUT PL = 150 mW 0.1 1.0 V3 = 400 mV Measure at Pin 5 I3 = 0 Conditions 2.2 30 2.2 4192 30 2.2 4193 24 V V mA 300 mA % 0.5 0.5 75 50 5.0 5.0 % VO % VO kHz mA mA mA mA mA %
Min Typ Max Min Typ Max Min Typ Max Units 1.29 1.31 1.33 1.27 1.31 1.35 1.24 1.31 1.38 100 200 215 85 0.04 0.2 25 5.0 0.01 0.1 0.7 8.6 10 0.2 0.5 75 50 5.0 5.0 0.1 1.0 300 100 200 215 85 0.04 0.2 25 5.0 0.01 0.1 0.7 8.6 10 0.5 0.5 75 50 5.0 5.0 0.1 1.0 300 100 200 215 85 0.04 0.2 25 5.0 0.01 0.1 0.7 8.6 10
1.4
1.4
1.4
V
-VTHX
0.5
0.5
0.5
V
IFB ILBD
0.1 500 1500
0.1 500 1500
0.1 500 1500
mA mA
4
RC4191/RC4192/RC4193
PRODUCT SPECIFICATION
Typical Performance Characteristics
4.0 300 250 3.0 200 2.0 IQ (A) VS (V) 2.4V 2.0V 1.8V 150 100 1.0
65-2670
230
215
195
VS = +6V -50 -25 0 +25 +50 TA (C)
0 -75
-50
-25
0
+25 +50 TA (C)
+75 +100 +125
0 -75
+75 +100 +125
Figure 1. Minimum Supply Voltage vs. Temperature
Figure 2. Quiescent Current vs. Temperature
1.33 FO (Normalized) (%) 1.32 VREF (V) 1.31 1.30 1.29 1.28 -75
+2.0 +1.5 +1.0 +0.5 0 -0.5 -1.0 -1.5 -2.0 -75 -50 -25 0 +25 +50 TA (C) Figure 4. Oscillator Frequency vs. Temperature
65-2672
-50
-25
0
+25 +50 TA (C)
+75 +100 +125
65-1488
+75 +100 +125
Figure 3. Reference Voltage vs. Temperature
+2 FO (Normalized) (%) +1
0
-1 -2 0 5 10 15 +VS (V) 20 25
65-2667
30
Figure 5. Minimum Supply Voltage vs. Temperature
65-2671
50
5
PRODUCT SPECIFICATION
RC4191/RC4192/RC4193
Applications Discussion
Simple Step-Up Converter
The most common application, the step-up regulator, is derived from a simple step-up (VOUT > VBAT) DC-to-EC Converter (Figure 6).
L D (+)
Complete Step-Up Regulator
A complete schematic of the minimum step-up application is shown in Figure 7. The ideal switch in the DC-to-DC Converter diagram is replaced by an open collector NPN transistor Q1. CF functions as the output filter capacitor, and D1 and LX replace D and L. When power is first applied, the current in R1 supplies bias current to pin 6 (IC). This current is stabilized by a unity gain current source amplifier and then used as bias current for the 1.31V bandgap reference. A very stable bias current generated by the bandgap is mirrored and used to bias the remainder of the chip. At the same time the RC4193 is starting up, current will flow through the inductor and the diode to charge the output capacitor to VBAT - VD. At this point, the feedback (pin 7) senses that the output voltage is too low, by comparing a division of the output voltage (set by the ratio of R2 to R3) to the +1.31V reference. If the output voltage is too low then the comparator output changes to a logical zero. The NOR gate then effectively ANDs the oscillator square wave with the comparator signal; if the comparator output is zero AND the oscillator output is low, then the NOR gate output is high and the switch transistor will be forced on. When the oscillator goes high again, the NOR gate output goes low and the switch transistor will turn off. This turning on and off of the switch transistor performs the same function that opening and closing the switch in the simple DC-to-DC Converter does; i.e., it stores energy in the inductor during the on time and releases it into the capacitor during the off time. The comparator will continue to allow the oscillator to turn the switch on and off until enough charge has been delivered to the capacitor to raise the feedback voltage above 1.31V. Thereafter, this feedback system will vary the duration of the on time in response to changes in load current or battery voltage (see Figure 8). If the load current increases (waveform C), then the transistor will remain on (waveform D) for a longer portion of the oscillator cycle (waveform B), thus allowing the inductor current (waveform E) to build up to a higher peak value. The duty cycle of the switch transistor varies in response to changes in load and time.
VBAT
S
C
RL
VOUT
(-)
65-1646
Figure 6. Simple Set-Up Converter
When switch S is closed, the battery voltage is applied across the inductor L. Charging current flows through the inductor, building up a magnetic field, increasing as the switch is held closed. While the switch is closed, the diode D is reverse biased (open circuit) and current is supplied to the load by the capacitor C. Until the switch is opened, the inductor current will increase linearly to a maximum value determined by the battery voltage, inductor value, and the amount of time the switch is held closed (IMAX = VBAT/L x TON). When the switch is opened, the magnetic field collapses, and the energy stored in the magnetic field is converted into a discharge current which flows through the inductor in the same direction as the charging current. Because there is no path for current to flow through the switch, the current must flow through the switch, the current must flow through the diode to supply the load and charge the output capacitor. If the switch is opened and closed repeatedly, at a rate much greater than the time constant of the output RC, then a constant DC voltage will be produced at the output. An output voltage higher than the input voltage is possible because of the high voltage produced by a rapid change of current in the inductor. When the switch is opened, the inductor voltage will instantly rise high enough to forward bias the diode, to VOUT + VD. In the complete RC4193 regulator, a feedback control system adjusts the on time of the switch, controlling the level of inductor current, so that the average inductor discharge current equals the load current, thus regulating the output voltage.
6
RC4191/RC4192/RC4193
PRODUCT SPECIFICATION
G E ILX LX R1 6 5 VBAT IC +VS Q1 B OSC GND 3 A CX 2 CX F ID (+) 4 LX D + - RL REF LBR 1 NC LBD 8 NC R3 D1
RC4191/92/93
VFB +1.31V 7
R2
+ -
CF C ILOAD VOUT = VREF ( R2 + 1) R3
(-)
65-2673B
Figure 7. Complete Step-Up Regulator
1.4V A 0.5V (Internal) IL (Max) C 0mA 0.72V (Internal) 0V VBAT LX E VOUT - VBAT LX IMAX 0 mA IMAX F ID 0 mA VOUT + VD VLX VMAX 0.3V (Q1 SAT)
65-2674
CX OSC ILOAD
B
D
VBEQ1
ILX
G
Figure 8. Step-Up Regulator Waveforms
7
8
+VS (5) LX (3) VFB (7) CX (2) Q50 Q13 Q10 Q28 Q27 Q17 Q18 Q30 Q36 Q38 Q48 Q49 C2 29.4pF R8 2K Q31 R7 23K Q8 Q24 Q15 Q14 Q23 R2 70K Q11 Q12 Q22 R1 147K Q16 R4 131K Q21 Q25 Q26 Q19 Q20 Q34 Q37 R10 80K Q33 Q35 Q39 Q40 Q45 Q46 Q47 Q32 Q9 Q29 Q44 Q41 Q42 Q43 R9 24K
65-2665
PRODUCT SPECIFICATION
Q3
Q4
Simplified Schematic Diagram
Q5
Q6
C1 14.2pF
IC (6)
Q7
Q2
R5 3.5K
Q1
R3 81.5K
R6 34.4K
RC4191/RC4192/RC4193
(8) LBD
(1) LBR
(4) Gnd
RC4191/RC4192/RC4193
PRODUCT SPECIFICATION
Mechanical DImensions
8-Lead Ceramic DIP Package
Inches Min. A b1 b2 c1 D E e eA L Q s1 a Max. Millimeters Min. Max. 8 2, 8 8 4 4 5, 9 7 3 6 Notes: Notes 1. Index area: a notch or a pin one identification mark shall be located adjacent to pin one. The manufacturer's identification shall not be used as pin one identification mark. 2. The minimum limit for dimension "b2" may be .023 (.58mm) for leads number 1, 4, 5 and 8 only. 3. Dimension "Q" shall be measured from the seating plane to the base plane. 4. This dimension allows for off-center lid, meniscus and glass overrun. 5. The basic pin spacing is .100 (2.54mm) between centerlines. Each pin centerline shall be located within .010 (.25mm) of its exact longitudinal position relative to pins 1 and 8. 6. Applies to all four corners (leads number 1, 4, 5, and 8). 7. "eA" shall be measured at the center of the lead bends or at the centerline of the leads when "a" is 90. 8. All leads - Increase maximum limit by .003 (.08mm) measured at the center of the flat, when lead finish applied. 9. Six spaces. D 4 1 Note 1 E
Symbol
-- .200 .014 .023 .045 .065 .008 .015 -- .405 .220 .310 .100 BSC .300 BSC .125 .200 .015 .060 .005 -- 90 105
-- 5.08 .36 .58 1.14 1.65 .20 .38 -- 10.29 5.59 7.87 2.54 BSC 7.62 BSC 3.18 5.08 .38 1.52 .13 -- 90 105
5 s1
8
e
eA
A Q L b2 b1 a c1
9
PRODUCT SPECIFICATION
RC4191/RC4192/RC4193
Mechanical DImensions (continued)
8-Lead Plastic DIP Package
Inches Min. A A1 A2 B B1 C D D1 E E1 e eB L N -- .015 .115 .014 .045 .008 .348 .005 .300 .240 Max. .210 -- .195 .022 .070 .015 .430 -- .325 .280 Millimeters Min. -- .38 2.93 .36 1.14 .20 8.84 .13 7.62 6.10 Max. 5.33 -- 4.95 .56 1.78 .38 10.92 -- 8.26 7.11 Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E1" do not include mold flashing. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. Terminal numbers are for reference only. 4. "C" dimension does not include solder finish thickness. 5. Symbol "N" is the maximum number of terminals. 4 2
Symbol
2
.100 BSC -- .430 .115 .160 8
2.54 BSC -- 10.92 2.92 4.06 8 5
D 4 1
E1
D1
5
8
E e A A1 L B1 B eB A2 C
10
RC4191/RC4192/RC4193
PRODUCT SPECIFICATION
Mechanical DImensions (continued)
8-Lead SOIC Package
Inches Min. A A1 B C D E e H h L N a ccc Max. Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
Symbol
.053 .069 .004 .010 .013 .020 .008 .010 .189 .197 .150 .158 .050 BSC .228 .010 .016 8 0 -- 8 .004 .244 .020 .050
1.35 1.75 0.10 0.25 0.33 0.51 0.20 0.25 4.80 5.00 3.81 4.01 1.27 BSC 5.79 0.25 0.40 8 0 -- 8 0.10 6.20 0.50 1.27
3 6
8
5
E
H
1
4
D A1 A SEATING PLANE B -C- LEAD COPLANARITY ccc C a
h x 45 C
e
L
11
PRODUCT SPECIFICATION
RC4191/RC4192/RC4193
Ordering Information
Product Number RC4191M/2M/3M RC4191N/2N/3N RV4191N/92N/93N RM4191D/92D/93D RM4191D/883 Temperature Range 0 to +70C 0 to +70C -25 to +85C -55C to +125C -55C to +125C Military Screening Commercial Commercial Package 8 Pin Wide SOIC 8 Pin Plastic DIP 8 Pin Plastic DIP 8 Pin Ceramic DIP 8 Pin Ceramic DIP
Note: 1. /883 suffix denotes MIL-STD-883, Par. 1.2.1 compliant device.
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonable expected to result in a significant injury of the user.
Fairchild Semiconductor Corporation Americas Customer Response Center Tel:1-888-522-5372 Fairchild Semiconductor Europe Fax: Email: Deutsch Tel: English Tel: Italy Tel: +49 (0) 1 80-530 85 86 europe.support@nsc.com +49 (0) 8 141-35-0 +44 (0) 1 793-85-68-56 +39 (0) 2 57 5631
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
Fairchild Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Center, 5 Canto Rd. Tsimshatsui, Kowloon Hong Kong Tel:+852 2737-7200 Fax:+852 2314-0061
National Semiconductor Japan Ltd. Tel:81-3-5620-6175 Fax:81-3-5620-6179
www.fairchildsemi.com 2/98 0.0m Stock#DS30004191 O 1998 Fairchild Semiconductor Corporation
www.fairchildsemi.com
RC4194
Dual Tracking Voltage Regulators
Features
* Simultaneously adjustable outputs with one resistor to 42V * Load current - 200 mA with 0.04% load regulation * Internal thermal shutdown at TJ = +175C * External balance for VOUT unbalancing * 3W power dissipations
Description
The RC/RM4194 are dual polarity tracking regulators designed to provide balanced or unbalanced positive and negative output voltages at currents to 200 mA. A single external resistor adjustment can be used to change both outputs between the limits of 50 mV and 42V. These devices are designed for local "on-card" regulation, eliminating distribution problems associated with singlepoint regulation. To simplify application the regulators require a minimum number of external parts. The device is available in three package types to accommodate various power requirements. The K (TO-66) power package can dissipate up to 3W at TA = +25C. The D 14-pin dual in-line will dissipate up to 1W and the N 14-pin dual in-line will dissipate up to 625 mW.
Block Diagram
4194 +VOUT +VS
20K
GND
Comp+
100A Current Source
RSET
Bal
20K Comp-
Thermal Shutdown
RO -VOUT
-VS
3R
R
65-4194-01
Rev. 1.0.0
PRODUCT SPECIFICATION
RC4194
Pin Assignments
-VS (Case) +VS +VOUT NC +VOUT 6 Comp+ 7 8 Bal 9 1 5 4 3 2 RO R SET GND Comp+ Bal CompNC -V S 3 4 5 6 7 12 11 10 9 8 GND R SET RO NC -VOUT 1 2 14 +V S 13 NC
Comp-
-VOUT
65-4194-02
65-4194-03
Absolute Maximum Ratings
(beyond which the device may be damaged)1 Parameter Supply Voltage Supply Input to Output Voltage Differential Load Current RC4194 RM4194 RC4194 RM4194 PDIP CerDIP TO-66 Metal Can PDTA < 50C PDIP CerDIP TO-66 Metal Can Operating Temperature (Tj) Storage Temperature Junction Temperature PDIP CerDIP TO-66 Metal Can Lead Soldering Temperature (60 seconds) For TA > 50C Derate at TO-66 Metal Can PDIP CerDIP
Note: 1. Functional operation under any of these conditions is NOT implied.
Min
Typ
Max 35 45 35 45 100 150 250 468 1042 2381
Units V V V V mA mA mA mW mW mW C C C C C C C mW/C mW/C mW/C
RC4194 RM4194
0 -55 -65
70 125 150 125 175 150 300 23.81 6.25 8.38
2
RC4194
PRODUCT SPECIFICATION
Operating Conditions
Parameter qJC qJA Thermal Resistance Thermal Resistance CerDIP TO-66 Metal Can PDIP CerDIP TO-66 Metal Can Min Typ 60 7 160 120 42 Max Units C/W C/W C/W C/W C/W
Electrical Characteristics
(5 VOUT VMAX; -VIN -8V; IL = 1mA; RM4194: -55C Tj +125C; RC4194: 0C Tj +70C unless otherwise specified) Parameters Line Regulation Load Regulation1 Test Conditions DVS = 0.1 VIN 4194K: IL < 200 mA 4194D: IL < 100 mA VS = (VOUT + 5)V Min Typ 0.04 0.002 Max 0.1 0.004 Units %VOUT %VOUT/IL (mA)
Output Voltage Drift With Temperature2 Positive Output Negative Output Supply Current3 (Positive) VOUT = 5V VOUT = 5V VS = VMAX, VOUT = 0V, IL = 0 mA VS = VMAX, VOUT = 0V, IL = 0 mA RM4194 RC4194 Output Voltage Scale Factor Output Voltage Range RSET = 71.5 kW, Tj = +25C, VS = VMAX RM4194: RSET = 71.5 kW, IL = 25 mA RC4194: RSET = 71.5 kW, IL = 25 mA Output Voltage Tracking Ripple Rejection Input-Output Voltage Differential Short Circuit Current Output Noise Voltage Internal Thermal Shutdown
Notes: DV OUT 1. Measured as ae ------------------ 100%o I L (mA) e V OUT o 2. Output voltage temperature drift guaranteed by design. 3. The current drain will increase by 50mA/VOUT on positive side and 100mA/VOUT on negative side. 4. The specifications above apply for the given junction temperatures since pulse test conditions are used.
0.002 0.003 +0.8 -1.8 9.5 9.5 2.38 0.05 0.05 0.4 2.5
0.015 0.015 +2.5 -4.0 45 35 2.62 42 42 2.0
%/C %/C mA mA V V kW/V V V % dB V mA mVRMS C
Supply Current4 (Negative) Supply Voltage
F = 120 Hz, Tj = +25C IL = 50 mA, Tj = +25C VS = 30V, Tj = +25C CL = 4.7 mF, VOUT = 15V, F = 10 Hz to 100 kHz 3.0
70 300 250 175
3
PRODUCT SPECIFICATION
RC4194
Typical Performance Characteristics
150 Load Regulation (% VOUT/IL) Ripple Rejection (dB) 130 110 90 70 50
65-0201
0.06 0.05 0.04 0.03 0.02 0.01 0 -0.01 0 20 40 60 IL (mA) Tj = +25C
65-0202
Tj = +125C
VOUT = 15V
30 10 0 100 1K F (Hz) 10K
100K
80 100 120 140 160 180 200
Figure 1. Ripple Rejection vs. Frequency
Figure 2. Load Regulation vs. Load Current
Output Voltage Tracking (% VOUT)
0.8 0.6 0.4 0.2 0 -0.2 -0.4 C -0.6 -60 -40 -20 0 A B
65-0203
+20 +40 +60 +80 +100+120+140 Tj (C)
A = % Tracking of VOUT B = T.C. for Positive Regulator C = T.C. for Negative Regulator Figure 3. Output Voltage Tracking vs. Temperature
4
RC4194
PRODUCT SPECIFICATION
Typical Applications
0.01F +VOUT To Additional Comparators 4.7F** +VS Comp+ +VOUT RA (Typically 15 RC4805s)
+VS
RM4194 -VS -VS R SET Comp- Gnd 71.5K R0
Bal RB
4805
R0
-VOUT
-V OUT = -5V To Additional Comparators 4.7F
0.01F
R O (k1/2 ) = 2.5 (-VOUT ) Adjust R O for -VOUT = -5V (12.5 kW ) R F1 = R F2 = 20 k1/2 (See Schematic) R F1 + VOUT = -VOUT R F2 R A = when +VOUT RA RB -VOUT
65-0205
R B = when +VOUT -V OUT For +VOUT = 5 when -VOUT = -5V RA = RB =
Figure 4. Unbalanced Output Voltage -- Comparator Application
2N4905 or equiv. 0.1 mF
R SC*
2N2297 or equiv. +VS 47W +VS +VOUT GND Comp+ +V OUT 60F** 4194 -VS 47 W -VS 0.1 m F R0 2N2297 or equiv. 71.5K Load regulation 10 mV @ 2.5A R SC* 2N914 or equiv. *R SC = 0.7 I SC R O (k W) = 2.5 V O R SET CompR0 -V OUT 60F -V OUT
**Optional usage - Not as critical as -VO bypass capacitors. Note: Compensation and bypass capacitor connections should be close as posibe to the 4194
65-0206
Figure 5. High Output Application
5
PRODUCT SPECIFICATION
RC4194
Typical Applications (continued)
+VOUT = +15V 0.001F 4.7F** +VS +VS Comp+ 4194 -VS -VS R SET Comp71.5K R0 4.7F 0.001F
65-0204
To Additional Op Amps +VOUT
741 R0 -V OUT
(Typically 180 741s) -V OUT = -15V To Additional Op Amps
Gnd
R O (k1/2) = 2.5 V OUT
Figure 6. Balanced Output Voltage -- Op Amp Application
+VS = +25V 2 In Out 6 0.01F
REF-02 Gnd 4 R2 250 -VS 4.87K 14 3 Ref+ -V S RefV LC B1 CC 16 Comp DAC-08 1 IO B8 2 13 +VS IO 2R 0 R1 2.49K RC4194K VOUT = 4 I O R1 0.001 7 5 Comp + +VS +V O
6 10F
+V OUT (0 to +19.92V)
15
4 IO
3R SET NC
-VO 1 10F
-V OUT (0 to -19.92V)
5 6 7 8 9 10 11 12 MSB Binary Inputs LSB
Comp- -VS Gnd Case 4 9 0.001 -VS = -25V
Adjust R2 for -19.92V at -VOUT with all "1s" at binary inputs, then optionally adjust R3 for +19.92V at +VOUT +Vo
65-1725
6
Optional Tracking Adjustment
R3
RC4194K
Bal -Vo
8 100K 1
100K
Figure 7. Digitally Controlled Dual 200 mA Voltage Regulator
6
RC4194
PRODUCT SPECIFICATION
RC4194 Switchable Power Supply
The outputs of the RC4194 can be simultaneously switched on or off under logic control as shown in Figure 8. In the "off" state, the outputs will be forced to a minimum voltage, or about 20 mV, rather than becoming open-circuit. The turn-on time, with the outputs programmed to 12V, is approximately 200 mS. This circuit works by forcing the R0 pin to ground with an analog switch. Refer to the RC4194 internal schematic diagram. A reference voltage that regulates with respect to -VS is generated at the RSET pin by the zener diode Q12 and the buffer circuit of Q11 and Q13. When the external 71.5k RSET resistor is connected between the RSET pin and -VS, a precision current of 100 mA is generated which then flows into Q13's collector. Since Q13's collector is tied to the R0 pin, the 100 mA current will develop a ground-referenced voltage drop proportional to the value of R0, which is then amplified by the internal error amplifier. When the analog switch in Figure 8 turns on, it effectively shorts out R0 and causes 0V to be applied to the error amplifier. The output voltage in the off state will be approxi-mately 20 mV. If a higher value (50 to 100 mV) is acceptable, then the DG201 analog switch can be replaced with a low-cost small signal transistor, as shown in the alternate switch configuration.
Compensation
For most applications, the following compensation technique is sufficient. The positive regulator section of the RC4194 is compensated by a 0.001 mF ceramic disc capacitor from the Comp+ terminal to ground. The negative regulator requires compensation at two points. The first is the Comp- pin, which should have 0.001 mF to the -VS pin, or case. A ceramic disc is ideal here. The second compen-sation point for the negative side is the -VOUT terminal, which ideally should be a 4.7 mF solid tantalum capacitor with enough reserve voltage capacity to avoid the momentary shorting and reforming which can occur with tantalum caps. For systems where the cost of a solid tantalum capacitor cannot be justified, it is usually sufficient to use an aluminum capacitor with a 0.03 mF ceramic disc in parallel to bypass high frequencies. In addition, if the rectifier filter capacitors have poor high frequency characteristics (like aluminum electrolytics) or if any impedance is in series with the +VS and -VS terminals, it is necessary to bypass these two points with 0.01 mF ceramic disc capacitors. Just as with monolithic op amps, some applications may not require these bypass caps, but if in doubt, be sure to include them.
C 0.001 F +VS +VS Comp- 0.001 m F 4194 -VS RSET RSET 71.5K R0 Gnd -VOUT 4.7 F -12V Comp+ +VOUT 4.7 F +12V
-VS
+VS
-VS DG201 * Gnd
R0 30K
* Alternate Switch Configuration 4194 R0
Logic
47K 2N3904 30K
*Quad SPST CMOS Analog Switch
65-4083
Figure 8. 12V Switchable Power Supply
7
PRODUCT SPECIFICATION
RC4194
All compensation and bypass caps should have short leads, solid grounds, and be located as close to the 4194 as possible. Refer to Figure 9 for recommended compensation circuitry.
0.001F Comp+ 4194 -VS R0 -VOUT RSET Comp4.7F R0 RSET * -VOUT
+VS 0.01F -VS
+VS
+VOUT
+VOUT
Protection
In systems using monolithic voltage regulators, a number of conditions can exist which, left uncorrected, will destroy the regulator. Fortunately, regulators can easily be protected against these potentially destructive conditions. Monolithic regulators can be destroyed by any reversal of input or output voltage polarity, or if the input voltage drops below the output voltage in magnitude. These conditions can be caused by inductive loads at the inputs or outputs of the regulator. Other problems are caused by heavy loads at the unregulated inputs to the regulator, which might cause the input voltage to drop below the output voltage at turn-off. If any of the preceding problem conditions are present in your system, it is recommended that you protect the regulator using diodes. These diodes should be high speed types capable of handling large current surges. Figure 10 shows all six of the possible protection diodes. The diodes at the inputs and outputs prevent voltages at those points from becoming reversed. Diodes from outputs to inputs prevent the output voltage from exceeding the input voltage. Chances are that the system under consideration will not require all six diodes, but if in doubt, be sure to include them.
0.001F 0.01F Note: All Capacitors are Ceramic Disc Except * = Solid Tantalum
65-4201
Figure 9. RC4194 Recommended Compensation
Sometimes occasions arise in which the RC4194 ratings must be exceeded. One example is the "brownout." During a brownout, line voltages may be reduced to as low as 75 VRMS, causing the input voltage to the RC4194 to drop below the minimum dropout voltage. When this happens, the negative output voltage can go to positive. The maximum amount of current available is approximately 5 mA. In general this is not enough current to damage most ICs which the RC4194 might be supplying, but it is a potentially destructive condition. Fortunately, it is easy to protect against. As shown in the typical application circuit in Figure 11, a diode, D, can be connected to the negative output.
Brownout Protection
The RC4194 is one of the most easily applied and troublefree monolithic ICs available. When used within the data sheet ratings (package power dissipation, maximum output current, minimum and maximum input voltages) it provides the most cost-effective source of regulated 15V for powering linear ICs.
0.001F +VS 0.01F +VS Comp+ +VOUT +VOUT
4194 -VS R 0 -V OUT RSET Comp4.7F * R0 R SET 0.001 F -V OUT
-VS
To -V OUT 0.01F
Note: All Capacitors are Ceramic Disc Except * = Solid Tantalum
65-4202
Figure 10. RC4194 Regulator Showing All Protective Diodes
8
RC4194
PRODUCT SPECIFICATION
If a small signal silicon diode is used, it will clamp the negative output voltage at about +0.55V. A Schottky barrier or germanium device would clamp the voltage at about +0.3V. Another cure which will keep the negative output negative at all times is the 1 mW resistor connected between the +15V output and the Comp- terminal. This resistor will then supply drive to the negative output transistor, causing it to saturate to -1V during the brownout.
Let's look at an application where a user is trying to determine whether the RC4194 in a high temperature environment will need a heatsink. Given: TJ at thermal shutdown = 150C TA = 125C qJ-A = 41.6C/W, K (TO-66) pkg. VIN = 40V VOUT = 30V IQ = 1 mA + 75 mA/VOUT x 30V = 3.25 mA*
TJ - TA q J - A = -----------------PD TJ - TA P D = -----------------qJ - A = ( V IN - V OUT ) I O + V IN I Q
Heatsinking
Voltage Regulators are power devices which are used in a wide range of applications. When operating these devices near their extremes of load current, ambient temperature and input-output differential, consideration of package dissipation becomes important to avoid thermal shutdown at 175C. The RC4194 has this feature to prevent damage to the device. It typically starts affecting load regulation approximately 2C below 175C. To avoid shutdown, some form of heatsinking should be used or one of the above operating conditions would need to be derated.* The following is the basic equation for junction temperature:
TJ = TA + PD qJ - A Equation 1
Solve for IO,
V IN I Q TJ - TA I O = ------------------------------------------------ - ---------------------------------q J - A ( V IN - V OUT ) ( V IN - V OUT ) 150C - 125C 40 3.25 10 I O = ---------------------------------------- - --------------------------------------41.6C/W 10V 10
-3
where TJ = junction temperature (C) TA = ambient air temperature (C) PD = power dissipated by device (W) qJ-A = thermal resistance from junction to ambient air (C/W) The power dissipated by the voltage regulator can be detailed as follows:
P D = ( V IN - V OUT ) I O + V IN I Q Equation 2
= 60 mA - 13 mA ~ 47 mA If this supply current does not provide at least a 10% margin under worst case load conditions, heatsinking should be employed. If reliability is of prime importance, the multiple regulator approach should be considered. In Equation 1, qJ-A can be broken into the following components: qJ-A = qJ-C + qC-S + qS-A where qJ-C = junction-to-case thermal resistance qC-S = case-to-heatsink thermal resistance qS-A = heatsink-to-ambient thermal resistance
where VIN = input voltage VOUT = regulated output voltage IO = load current IQ = quiescent current drain
------------------------------ *The current drain will increase by 50mA/VOUT on positive side and 100mA/VOUT on negative side
9
PRODUCT SPECIFICATION
RC4194
In the above example, let's say that the user's load current is 200 mA and he wants to calculate the combined qC-S and qS-A he needs: Given: IO = 200 mA,
TJ - TA q J - A = -------------------------------------------------------------------------( V IN - V OUT ) I O + V IN I Q 50C - 125C = ---------------------------------------------------------------------------------3 10V 200mA + 40 3.25 10
Given qJ-C = 7.15C/W for the 4194 in the K package, qC-S + qS-A = 11.75C/W - 7.15C/W = 4.6C/W When using heatsink compound with a metal-to-metal interface, a typical qC-S = 0.5C/W for the K package. The remaining qS-A of approximately 4C/W is a large enough thermal resistance to be easily provided by a number of heatsinks currently available. Table 1 is a brief selection guide to heatsink manufacturers.
= 11.75C/W
Table 1. Commercial Heatsink Selection Guide
No attempt has been made to provide a complete list of all heatsink manufacturers. This list is only representative. qS-A1(C/W) 0.31 - 1.0 1.0 - 3.0 3.0 - 5.0 Manufacturer/Series or Part Number TO-66 Package Thermalloy -- 6441, 6443, 6450, 6470, 6560, 6590, 6660, 6690 Wakefield -- 641 Thermalloy -- 6123, 6135, 6169, 6306, 6401, 6403, 6421, 6423, 6427, 6442, 6463, 6500 Wakefield -- 621, 623 Thermalloy -- 6606, 6129, 6141, 6303 IERC -- HP Staver -- V3-3-2 5.0 - 7.0 Wakefield -- 690 Thermalloy -- 6002, 6003, 6004, 6005, 6052, 6053, 6054, 6176, 6301 IERC -- LB Staver-- V3-5-2 7.0 - 10.0 Wakefield -- 672 Thermalloy -- 6001, 6016, 6051, 6105, 6601 IERC -- LA, uP Staver -- V1-3, V1-5, V3-3, V3-5, V3-7 10.0 - 25.0 20 30 32 34 45 60 Thermalloy -- 6-13, 6014, 6015, 6103, 6104, 6105, 6117 Dual In-line Package Thermalloy -- 6007 Thermalloy -- 6010 Thermalloy -- 6011 Thermalloy -- 6012 IERC -- LI Wakefield -- 650, 651
Staver Co., Inc.: 41-51 N Saxon Ave., Bay Shore, NY 11706 IERC: 135 W Magnolia Blvd., Burbank, CA 91502 Thermalloy: P.O. Box 34829, 2021 W Valley View Ln., Dallas, TX Wakefield Engin Ind: Wakefield, MA 01880 * All values are typical as given by manufacturer or as determined from characteristic curves supplied by manufacturer.
10
RC4194
Comp+ (7) +Vs (5) Q28 Q38 Q40 Q32 Q35 R19 3000 Q36 Q33 Q36 R20 200 Q42 R21 1.1 -VOUT (6) R23 20K Q34 Q37 R24 20K Q44 R8 5000 Q16 Q20 R9 15K Q45 (1) Q25 C1 10 pF Q12 R6 30K Q8 Q23 Q22 R3 5000 R7 5000 R11 3900 R10 1650 Q19 Q24 Q46 Q18 Q43 R14 3000 W R15 1.1 W 200W 8 kW Q26 Q27 -VOUT Q7 Q10 Q9 Q13 Q11 Q17 Q21 Q31 Bal RF2 R18 10K Q47 (4) Gnd RF1 Q41 Q30
Q29
Simplified Schematic Diagram
(8)
Q1
R4 500
R5 25K
Q3
Q4
Q2
R1 12K
Q6
Q5
R2 680
PRODUCT SPECIFICATION
Note: Pin numbers are for K package.
(3) RSET
(2) R0
-VS To Case
(9) Comp-
65-0198
11
PRODUCT SPECIFICATION
RC4194
Mechanical Dimensions
9-Lead Metal Can IC Header Package
oD oD1 A ob oD oD1 e e1 F op q r1 r2 S Notes: 1. All leads--increase maximum limit by .003 (.08mm) when lead finish is applied. e1 op Inches Min. .250 .028 -- .470 .190 .093 .050 .360 .142 .958 -- -- .570 Max. .340 .034 .620 .500 .210 .107 .075 -- .152 .962 .350 .145 .590 Millimeters Min. 6.35 .71 -- 11.94 4.83 2.36 1.27 9.14 3.61 24.33 -- -- 14.48 Max. 8.64 .86 15.75 12.70 5.33 2.72 1.91 -- 3.86 24.43 8.89 3.68 14.99 1
Symbol
Notes
A
F
ob
S
e
r2
r1 q
12
RC4194
PRODUCT SPECIFICATION
Mechanical Dimensions (continued)
14-Lead Ceramic DIP Package
Inches Min. A b1 b2 c1 D E e eA L Q s1 a Max. Millimeters Min. Max. 8 2 8 4 4 5, 9 7 3 6 Notes: Notes 1. Index area: a notch or a pin one identification mark shall be located adjacent to pin one. The manufacturer's identification shall not be used as pin one identification mark. 2. The minimum limit for dimension "b2" may be .023 (.58mm) for leads number 1, 7, 8 and 14 only. 3. Dimension "Q" shall be measured from the seating plane to the base plane. 4. This dimension allows for off-center lid, meniscus and glass overrun. 5. The basic pin spacing is .100 (2.54mm) between centerlines. Each pin centerline shall be located within .010 (.25mm) of its exact longitudinal position relative to pins 1 and 14. 6. Applies to all four corners (leads number 1, 7, 8, and 14). 7. "eA" shall be measured at the center of the lead bends or at the centerline of the leads when "a" is 90. 8. All leads - Increase maximum limit by .003 (.08mm) measured at the center of the flat, when lead finish applied. 9. Twelve spaces. D
7 1
Symbol
-- .200 .014 .023 .045 .065 .008 .015 -- .785 .220 .310 .100 BSC .300 BSC .125 .200 .015 .060 .005 -- 90 105
-- 5.08 .36 .58 1.14 1.65 .20 .38 -- 19.94 5.59 7.87 2.54 BSC 7.62 BSC 3.18 5.08 .38 1.52 .13 -- 90 105
NOTE 1
E
8
14
s1 eA
e
A Q L b2 b1 a c1
13
PRODUCT SPECIFICATION
RC4194
Mechanical Dimensions (continued)
14-Lead Plastic DIP Package
Inches Min. A A1 A2 B B1 C D D1 E E1 e eB L N -- .015 .115 Max. .210 -- .195 Millimeters Min. -- .38 2.93 Max. 5.33 -- 4.95 Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E1" do not include mold flashing. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. Terminal numbers are shown for reference only. 4. "C" dimension does not include solder finish thickness. 5. Symbol "N" is the maximum number of terminals. 4 2
Symbol
.014 .022 .045 .070 .008 .015 .725 .795 .005 -- .300 .325 .240 .280 .100 BSC -- .430 .115 .200 14
.36 .56 1.14 1.78 .20 .38 18.42 20.19 .13 -- 7.62 8.26 6.10 7.11 2.54 BSC -- 10.92 2.92 5.08 14
2
5
D 7 1
E1
D1
8
14
E e A A1 L B1 B eB C
14
PRODUCT SPECIFICATION
RC4194
Ordering Information
Product Number RC4194N RC4194D RC4194K RM4194D RM4194D/883B RM4194K Temperature Range 0 to +70C 0 to +70C 0 to +70C -55C to +125C -55C to +125C -55C to +125C Screening Commercial Commercial Commercial Commercial Military Commercial Package 14 pin Plastic DIP 14 pin Ceramic DIP 9 pin TO-66 14 pin Ceramic DIP 14 pin Ceramic DIP 9 pin TO-66 7705401CA SMD Number
Note: 1. /883B suffix denotes MIL-STD-883, Par. 1.2.1 compliant device.
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS30004194 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC4195
Fixed 15V Dual Tracking Voltage Regulator
Features
* 15V operational amplifier power at reduced cost and component density * Thermal shutdown at TJ = +175C in addition to short circuit protection * Output currents to 100 mA * May be used as single output regulator with up to +50V output * Available in TO-66, TO-99 and 8-lead mini-DIP
Description
The RM/RC4195 is a dual polarity tracking regulator designed to provide balanced positive and negative 15V output voltages at currents up to 100mA. This device is designed for local "on-card" regulation, eliminating distribution problems associated with single point regulation. The regulator is intended for ease of application. Only two external components are required for operation (two 10 mF bypass capacitors). The device is available in four package types to accommodate various applications requiring economy, high power, dissipation, and reduced component density.
Block Diagram
4195
Comp+
+VS
GND 700
+15VOUT
Comp-
14.3K Bal 15K
-VS
65-3467-01
-15VOUT
Pin Assignments
-VS (Case) NC 6 Comp+ 7 8 GND Comp- 9 1 54 3 2 Bal 3 Comp- -15VOUT
65-0091
+VS NC Comp+ +15VOUT GND 2 1
+VS
8 7
+15VOUT
Comp+ 1 GND 2
8 7 6 5
+VS +15VOUT Bal -15VOUT
65-0093
6 5 4 -VS
Bal Comp- 3 -15VOUT
65-0092
-VS 4
Rev. 1.0.0
PRODUCT SPECIFICATION
RC4195
Absolute Maximum Ratings
(beyond which the device may be damaged)1 Parameter Supply Voltage (VS) to Ground Load Current PDTA < 50C PDIP/TO-99 TO-66 PDIP TO-99 TO-66 Junction Temperature PDIP TO-99 TO-66 Storage Temperature Operating Temperature (Tj) Lead Soldering Temperature (60 sec) For TA > 50C Derate at PDIP TO-99 TO-66 6.25 5.26 23.81 RC4195 RM4195 -65 0 -55 Min Typ Max 30 150 100 468 658 2381 125 175 150 150 70 125 300 Units V mA mA mW mW mW C C C C C C C mW/C mW/C mW/C
Note: 1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded.
Operating Conditions
Parameter qJC qJA Thermal resistance Thermal resistance TO-99 TO-66 PDIP TO-99 TO-66 Min Typ 50 7 160 190 42 Max Units C/W C/W C/W C/W C/W
2
RC4195
PRODUCT SPECIFICATION
Electrical Characteristics
(IL = 1mA; VS = 20V, CL = 10mF; RM4195: -55C Tj +125C; RC4195: 0C Tj +70C unless otherwise specified)1 Parameters Line Regulation Load Regulation Output Voltage Drift With Temperature Supply Current Supply Voltage Output Voltage Output Voltage Tracking Ripple Rejection Input-Output Voltage Differential Short Circuit Current Output Noise Voltage Internal Thermal Shutdown F = 120 Hz, TA = +25C IL = 50 mA Tj = +25C Tj = +25C, F = 100Hz to 120 kHz 3.0 220 60 175 Tj = +25C VS = 30V, IL = 0 mA 18 14.5 15.0 50 75 Test Conditions VS = 18V to 30V IL = 1mA to 100mA Min Typ 2 5 0.005 1.5 Max 20 30 0.015 4.0 30 15.5 300 Units mV mV %/C mA V V mV dB V mA mVRMS C
Note: 1. The specifications above apply for the given junction temperatures since pulse test conditions are used.
3
PRODUCT SPECIFICATION
RC4195
Typical Performance Characteristics
-2 0 2 Output Voltage Deviation (mV) 4 6 8 10
65-0094
2.5
RM4195: -55 C to +150 C
Standby Current (mA)
2.0 1.5 1.0 0.5 0 16
RC4195: 0 C RM4195: -55 C +25 C +125 C
RC4195: 0 C to +125 C
12 14 0
20
40
60 IL (mA)
80
100
18
20
22
24 VIN (V)
26
28
30
32
Figure 1. Output Load Regulation
Figure 2. Standby Current Drain
Minium Output/Output Voltage Differential (V)
4.0
VOUT = 20 mV
2.5
T j = RC4195: 0 C T j = RM4195: -55 C
2.0
2.0
Tj = +25 C T j = +25 C
K Package (W)
T
800 600
1.5 1.0 0.5 0 -75 N
400 200 0 +75 +100 +125
1.0
RC4195: 0 C to +125 C Negative Regulator RM4195: -55 C to +150 C
65-0095
N & T Packages (mW)
3.0
Positive Regulator
K
1000
0 0
20
40
60 IL (mA)
80
100
-50
-25
0
+25 +50 Tj (C)
Figure 3. Regulator Dropout Voltage
Figure 4. Power Dissipation
200 Total Load Current (mA) 160 120 80 40 0 0 2.0 4.0 No Heat Sink Infinite Heat Sink 6.0 8.0 10 12 14 Input/Output Voltage Differential (V) Figure 5. Maximum Current Capability N Package
65-0096
Ripple Attenuation (dB)
T Package
K Package
16
0 -10 -20 -30 I L = 0 mA -40 -50 -60 -70 -80 -90 -100 100 1.0K
Negative Regulator Positive Regulator
10K F (Hz)
100K
1M
Figure 6. Ripple Rejection
4
65-0099
65-0098
65-0097
Vs = 18V T J = TA
RC4195
PRODUCT SPECIFICATION
Typical Applications
+18V to +30V +VS -18V to -30V -VS GND 4195 -VOUT +15V at 100 mA +VOUT 10 F -15V at 100 mA 10 F
65-0100
Figure 7. Balanced Output (VOUT = 15V)
+53V to +60V +VS 4195 -VS GND VOUT = +15V (1 + R2 ) R1 VOUT < + VS < 60V
VOUT = +50V at 100 mA +VOUT Bal -VOUT R1 15K R2 35K 10 F
65-0101
Figure 8. Positive Single Supply (+15V < VOUT < +50V)
2N4905 or Equiv. 0.1 F
*RSC
47 +VS 47 -VS +VS
GND
Comp+ +VOUT 4195 60 F -VOUT
+VOUT = +15V
-VS
-VOUT = -15V 60 F
Comp- 2N2297 or Equiv. 0.1 F
Load Regulation 10 mA @ 2.5A *RSC 2N4914 or Equiv. *RSC = 0.7 ISC
65-0102
Figure 9. High Output Current
5
PRODUCT SPECIFICATION
RC4195
Brownout Protection
The RC4195 is one of the most easily applied and troublefree monolithic ICs available. When used within the data sheet ratings (package power dissipation, maximum output current, minimum and maximum input voltages) it provides the most cost-effective source of regulated 15V for powering linear ICs. Sometimes occasions arise in which the RC4195 ratings must be exceeded. One example is the "brownout". During a brownout, line voltages may be reduced to as low as 75 VRMS, causing the input voltage to the RC4195 to drop below the minimum dropout voltage. When this happens, the negative output voltage can go to positive. The maximum amount of current available is approximately 5 mA. In general this is not enough current to damage most ICs which the RC4195 might be supplying, but it is a potentially destructive condition. Fortunately, it is easy to protect against. As shown in the typical application circuit, a diode, D, can be connected to the negative output. If a small signal silicon diode is used, it will clamp the negative output voltage at about +0.55V. A Schottky barrier or germanium device would clamp the voltage at about +0.3V. Another cure which will keep the negative output negative all times is the 1 mW resistor connected between the +15V output and the Comp- terminal. this resistor will then supply drive to the negative output transistor, causing it to saturate to -1V during the brownout.
avoid thermal shutdown at 175C. The RC4195 has this feature to prevent damage to the device. It typically starts affecting load regulation approximately 2C below 175C. To avoid shutdown, some form of heatsinking should be used or one of the above operating conditions would need to be derated.* The following is the basic equation for junction temperature:
TJ = TA + PD qJ - A Equation 1
where TJ = junction temperature (C) TA = ambient air temperature (C) PD = power dissipated by device (W) qJ-A = thermal resistance from junction to ambient air (C/W) The power dissipated by the voltage regulator can be detailed as follows:
P D = ( V IN - V OUT ) I O + V IN I Q Equation 2
where VIN = input voltage VOUT = regulated output voltage IO = load current IQ = quiescent current drain
Heatsinking
When operating these devices near their extremes of load current, ambient temperature and input-output differential, consideration of package dissipation becomes important to
Balanced Output (VOUT = 15V)
1M1/2
+18V To +30V +VS
Comp- +V OUT 4195
+15V at 100 mA 10 F -15V at 100 mA
-18V To -30V -VS Gnd
-VOUT 10 F D
65-3467-03
Figure 10. Typical Application Circuit ------------------------------ *In allowing for process deviations, the user should work with a maximum allowable function temperature of 150C. **The current drain will increase by 50mA/VOUT on positive side and 100mA/VOUT on negative side
6
RC4195
PRODUCT SPECIFICATION
Let's look at an application where a user is trying to determine whether the RC4195 in a high temperature environment will need a heatsink. Given:
In Equation 1, qJ-A can be broken into the following components: qJ-A = qJ-C + qC-S + qS-A where
TJ at thermal shutdown = 150C TA = 125C qJ-A = 41.6C/W, K (TO-66) pkg. VIN = 40V VOUT = 30V IQ = 1 mA + 75 mA/VOUT x 30V = 3.25 mA**
TJ - TA q J - A = -----------------PD TJ - TA P D = -----------------qJ - A = ( V IN - V OUT ) I O + V IN I Q
qJ-C = junction-to-case thermal resistance qC-S = case-to-heatsink thermal resistance qS-A = heatsink-to-ambient thermal resistance In the above example, let's say that the user's load current is 200 mA and he wants to calculate the combined qC-S and qS-A he needs: Given: IO = 200 mA,
TJ - TA q J - A = -------------------------------------------------------------------------( V IN - V OUT ) I O + V IN I Q 50C - 125C = ---------------------------------------------------------------------------------3 10V 200mA + 40 3.25 10
Solve for IO,
V IN I Q TJ - TA I O = ------------------------------------------------ - ---------------------------------q J - A ( V IN - V OUT ) ( V IN - V OUT ) 150C - 125C 40 3.25 10 I O = ---------------------------------------- - --------------------------------------41.6C/W 10V 10
-3
= 11.75C/W Given qJ-C = 7.15C/W for the 4194 in the K package, qC-S + qS-A = 11.75C/W - 7.15C/W = 4.6C/W When using heatsink compound with a metal-to-metal interface, a typical qC-S = 0.5C/W for the K package. The remaining qS-A of approximately 4C/W is a large enough thermal resistance to be easily provided by a number of heatsinks currently available. Table 1 is a brief selection guide to heatsink manufacturers.
= 60 mA - 13 mA ~ 47 mA If this supply current does not provide at least a 10% margin under worst case load conditions, heatsinking should be employed. If reliability is of prime importance, the multiple regulator approach should be considered.
7
PRODUCT SPECIFICATION
RC4195
Table 1. Commercial Heatsink Selection Guide
No attempt has been made to provide a complete list of all heatsink manufacturers. This list is only representative. qS-A* (C/W) 0.31 - 1.0 1.0 - 3.0 3.0 - 5.0 Manufacturer/Series or Part Number TO-66 Package Thermalloy -- 6441, 6443, 6450, 6470, 6560, 6590, 6660, 6690 Wakefield -- 641 Thermalloy -- 6123, 6135, 6169, 6306, 6401, 6403, 6421, 6423, 6427, 6442, 6463, 6500 Wakefield -- 621, 623 Thermalloy -- 6606, 6129, 6141, 6303 IERC -- HP Staver -- V3-3-2 5.0 - 7.0 Wakefield -- 690 Thermalloy -- 6002, 6003, 6004, 6005, 6052, 6053, 6054, 6176, 6301 IERC -- LB Staver-- V3-5-2 7.0 - 10.0 Wakefield -- 672 Thermalloy -- 6001, 6016, 6051, 6105, 6601 IERC -- LA, uP Staver -- V1-3, V1-5, V3-3, V3-5, V3-7 10.0 - 25.0 12.0 - 20.0 Thermalloy -- 6-13, 6014, 6015, 6103, 6104, 6105, 6117 TO-99 Package Wakefield -- 260 Thermalloy -- 1101, 1103 Staver -- V3A-5 20.0 - 30.0 Wakefield -- 209 Thermalloy -- 1116, 1121, 1123, 1130, 1131, 1132, 2227, 3005 IERC -- LP Staver -- F5-5 3.0 - 50.0 Wakefield -- 207 Thermalloy -- 2212, 2215, 225, 2228, 2259, 2263, 2264 Dual In-line Package 20 30 32 34 45 60 Thermalloy -- 6007 Thermalloy -- 6010 Thermalloy -- 6011 Thermalloy -- 6012 IERC -- LI Wakefield -- 650, 651
Staver Co., Inc.: 41-51 N Saxon Ave., Bay Shore, NY 11706 IERC: 135 W Magnolia Blvd., Burbank, CA 91502 Thermalloy: P.O. Box 34829, 2021 W Valley View Ln., Dallas, TX Wakefield Engin Ind: Wakefield, MA 01880 * All values are typical as given by manufacturer or as determined from characteristic curves supplied by manufacturer.
8
RC4195
PRODUCT SPECIFICATION
Simplified Schematic Diagram
+Vs (8) R1 10K Q4 Q5 R5 1K Q6 Q17 Q18 Q7 C1 24 pF Q16 Ground (2) Q8 R7 3 +15V Output (7) R6 15K Comp+ (1)*
Comp(3)
R4 7.5K
Z2 Z3
R8 800 R9 15K
Q1 Q2 Q19 Z1 R2 8.9K Q14 Q9 Q10 C2 30 pF
Balance (6)
R10 15.8K -15V Output (5) Q15
Q3 R3 528 Q11 Q12 Q13
R11 15K
R12 (3) -Vs (4)
*Pin numbers are for 8-pin packages.
65-0090
9
PRODUCT SPECIFICATION
RC4195
Mechanical Dimensions
8-Lead Plastic DIP Package
Inches Min. A A1 A2 B B1 C D D1 E E1 e eB L N -- .015 .115 .014 .045 .008 .348 .005 .300 .240 Max. .210 -- .195 .022 .070 .015 .430 -- .325 .280 Millimeters Min. -- .38 2.93 .36 1.14 .20 8.84 .13 7.62 6.10 Max. 5.33 -- 4.95 .56 1.78 .38 10.92 -- 8.26 7.11 Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E1" do not include mold flashing. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. Terminal numbers are for reference only. 4. "C" dimension does not include solder finish thickness. 5. Symbol "N" is the maximum number of terminals. 4 2
Symbol
2
.100 BSC -- .430 .115 .160 8
2.54 BSC -- 10.92 2.92 4.06 8 5
D 4 1
E1
D1
5
8
E e A A1 L B1 B eB A2 C
10
RC4195
PRODUCT SPECIFICATION
Mechanical Dimensions (continued)
8-Lead Metal Can IC Header Package
oD Symbol oD1 A ob ob1 oD oD1 oD2 e e1 F k k1 L L1 L2 Q a Notes: e1 1. (All leads) ob applies between L1 & L2. ob1 applies between L2 & .500 (12.70mm) from the reference plane. Diameter is uncontrolled in L1 & beyond .500 (12.70mm) from the reference plane. 2. Measured from the maximum diameter of the product. 3. Leads having a maximum diameter .019 (.48mm) measured in gauging plane, .054 (1.37mm) +.001 (.03mm) -.000 (.00mm) below the reference plane of the product shall be within .007 (.18mm) of their true position relative to a maximum width tab. a 4. The product may be measured by direct methods or by gauge. 5. All leads - increase maximum limit by .003 (.08mm) when lead finish is applied. k k1 Inches Min. Max. Millimeters Min. Max. 1, 5 1, 5
Notes
L1
F
Q
A
L2 L
ob BASE and SEATING PLANE ob1
REFERENCE PLANE
.165 .185 .016 .019 .016 .021 .335 .375 .305 .335 .110 .160 .200 BSC .100 BSC -- .040 .027 .034 .027 .045 .500 .750 -- .050 .250 -- .010 .045 45 BSC
4.19 4.70 .41 .48 .41 .53 8.51 9.52 7.75 8.51 2.79 4.06 5.08 BSC 2.54 BSC -- 1.02 .69 .86 .69 1.14 12.70 19.05 -- 1.27 6.35 -- .25 1.14 45 BSC
2 1 1 1
e
oD2
11
PRODUCT SPECIFICATION
RC4195
Mechanical Dimensions (continued)
9-Lead Metal Can IC Header Package
oD oD1 A ob oD oD1 e e1 F op q r1 r2 S Notes: 1. All leads--increase maximum limit by .003 (.08mm) when lead finish is applied. e1 op Inches Min. .250 .028 -- .470 .190 .093 .050 .360 .142 .958 -- -- .570 Max. .340 .034 .620 .500 .210 .107 .075 -- .152 .962 .350 .145 .590 Millimeters Min. 6.35 .71 -- 11.94 4.83 2.36 1.27 9.14 3.61 24.33 -- -- 14.48 Max. 8.64 .86 15.75 12.70 5.33 2.72 1.91 -- 3.86 24.43 8.89 3.68 14.99 1
Symbol
Notes
A
F
ob
S
e
r2
r1 q
12
PRODUCT SPECIFICATION
RC4195
Ordering Information
Product Number RC4195N RC4195T RC4195K RM4195T RM4195T/883B RM4195K Temperature Range 0 to +70C 0 to +70C 0 to +70C -55C to +125C -55C to +125C -55C to +125C Screening Commercial Commercial Commercial Commercial Military Commercial Package 8 Pin Plastic DIP 8 Pin TO-99 Metal Can 9 Pin TO-66 Metal Can 8 Pin TO-99 Metal Can 8 Pin TO-99 Metal Can 9 Pin TO-66 Metal Can
Note: 1. /883B suffix denotes MIL-STD-883, Par. 1.2.1 compliant device.
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS30004195 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC4200
Analog Multiplier
Features
* High accuracy * Nonlinearity - 0.1% Temperature coefficient - 0.005%/C * Multiple functions * Multiply, divide, square, square root, RMS-to-DC conversion, AGC and modulate/demodulate * Wide bandwidth - 4 MHz * Signal-to-noise ratio - 94 dB
Description
The RC4200 analog multiplier has complete compensation for nonlinearity, the primary source of error and distortion. This multiplier also has three onboard operational amplifiers designed specifically for use in multiplier logging circuits. These amplifiers are frequency compensated for optimum AC response in a logging circuit, the heart of a multiplier, and can therefore provide superior AC response. The RC4200 can be used in a wide variety of applications without sacrificing accuracy. Four-quadrant multiplication, two-quadrant division, square rooting, squaring and RMS conversion can all be easily implemented with predictable accuracy. The nonlinearity compensation is not just trimmed at a single temperature, it is designed to provide compensation over the full temperature range. This nonlinearity compensation combined with the low gain and offset drift inherent in a well-designed monolithic chip provides a very high accuracy and a low temperature coefficient.
Applications
* Low distortion audio modulation circuits * Voltage-controlled active filters * Precision oscillators
Block Diagram
I2 I1 - + - VOS2 + + - Q3 I3 Q4 I4 VOS1
Q2
Q1
RC4200
65-4200-01
Rev. 1.2.0
RC4200
PRODUCT SPECIFICATION
Functional Description
The RC4200 multiplier is designed to multiply two input currents (I1 and I2) and to divide by a third input current (I4). The output is also in the form of a current (I3). A simplified circuit diagram is shown in the Block Diagram. The nominal relationship between the three inputs and the output is: I1 I2 I 3 = -------I4 (1)
Previous multiplier designs have suffered from an additional undesired linear term in the above equation; the collector current times the emitter resistance. The ICrE term introduces a parabolic nonlinearity even with matched transistors. Fairchild Semiconductor has developed a unique and proprietary means of inherently compensating for this undesired ICrE term. Furthermore, this Fairchild Semiconductor developed circuit technique compensates linearity error over temperature changes. The nonlinearity versus temperature is significantly improved over earlier designs. From equation (2) and by assuming equal transistor junction temperatures, summing base-to-emitter voltage drops around the transistor array yields: I2 I3 I4 I1 KT ------- In ------ = In ------ - In ------ - In -----I S1 I S2 I S3 I S4 q This equation reduces to: I S1 I S2 I1 I2 -------- = -------------I S3 I S4 I3 I4 (4) =0 (3)
The three input currents must be positive and restricted to a range of 1 mA to 1 mA. These currents go into the multiplier chip at op amp summing junctions which are nominally at zero volts. Therefore, an input voltage can be easily converted to an input current by a series resistor. Any number of currents may be summed at the inputs. Depending on the application, the output current can be converted to a voltage by an external op amp or used directly. This capabilty of combining input currents and voltages in various combinations provides great versatility in application. Inside the multiplier chip, the three op amps make the collector currents of transistors Q1, Q2 and Q4 equal to their respective input currents (I1, I2, and I4). These op amps are designed with current source outputs and are phase-compensated for optimum frequency response as a multiplier. Power drain of the op amps was minimized to prevent the introduction of undesired thermal gradients on the chip. The three op amps operate on a single supply voltage (nominally -15V) and total quiescent current drain is less than 4 mA. These special op amps provide significantly improved performance in comparison to 741-type op amps. The actual multiplication is done within the log-antilog configuration of the Q1-Q4 transistor array. These four transistors, with associated proprietary circuitry, were specially designed to precisely implement the relationship. kT I CN V BEN = ------ In -------Q I SN (2)
The rate of reverse saturation current IS1IS2/IS3IS4, depends on the transistor matching. In a monolithic multiplier this matching is easily achieved and the rate is very close to unity, typically 1.01%. The final result is the desired relationship: I1 I2 I 3 = -------I4 (5)
The inherent linearity and gain stability combined with low cost and versatility makes this new circuit ideal for a wide range of nonlinear functions.
Pin Assignments
I2 VOS2 -VS I3 (Output) 1 2 3 4
65-4200-07
8 7 6 5
I1 VOS1 GND I4
2
PRODUCT SPECIFICATION
RC4200
Absolute Maximum Ratings
Parameter Supply Voltage1 RM4200/4200A RC4200/4200A Operating Temperature Range RM4200/4200A RC4200/4200A -65 -55 -55 0 Input Current Storage Temperature Range Min. Max. -22 -5 +150 +125 +125 +70 Unit V mA C C C C
Notes: 1. For a supply voltage greater than -22V, the absolute maximum input voltage is equal to the supply voltage. 2. Observe package thermal characteristics.
Thermal Characteristics
(Still air, soldered into PC board) 8-Lead Plastic DIP Maximum Junction Temperature Maximum PD TA < 50C Thermal Resistance qJC Thermal Resistance qJA For TA > 50C Derate at +125C 468mW -- 160C/W 6.25mW/C 8-Lead SOIC +125C 300mW -- 240C/W 4.17mW/C 8-Lead Ceramic DIP +175C 833mW 45C/W 150C/W 8.33mW/C
Electrical Characteristics
(Over operating temperature range, VS = -15V unless otherwise noted) 4200A Parameters Total Error as Multiplier Test Conditlons TA = +25C Untrimmed1 With External Trim Versus Temperature Versus Supply (-9 to -18V) Nonlinearity
2
4200 Max. Min. 2.0 Typ. Max. Units 3.0 0.2 0.005 0.1 0.1 0.3 1.0 1000 10 500 % % %/C %/V % mA mV nA
Min.
Typ.
0.2 0.005 0.1
50mA I1,2,4 250 mA, TA = +25C 1.0 I1 = I2 = I4 = 150 mA TA = +25C I1 = I2 = I4 = 150 mA TA = +25C I1 = I2 = I4 = 150 mA 1.0
Input Current Range (I1, I2 and I4) Input Offset Voltage Input Bias Current Average Input Offset Voltage Drift Output Current Range (I3)3
1000 5.0 300 50 1000
100 mV/C 1.0 1000 mA
3
RC4200
PRODUCT SPECIFICATION
Electrical Characteristics (continued)
(Over operating temperature range, VS = -15V unless otherwise noted) 4200A Parameters Frequency Response, -3dB point Supply Voltage Supply Current I1 = I2 = I4 = 150 mA TA = +25C Test Conditlons Min. Typ. 4.0 -15 Max. Min. 4200 Typ. 4.0 -15 Max. Units MHz V mA
-18
-9.0 4.0
-18
-9.0 4.0
Notes: 1. Refer to Figure 6 for example. 2. The input circuits tend to become unstable at I1, I2, I4 < 50 mA and linearity decreases when I1, I2, I4 > 250 mA (eq. @ I1 = I2 = 500 mA, nonlinearity error 0.5%). 3. These specifications apply with output (I3) connected to an op amp summing junction. If desired, the output (I3) at pin (4) can be used to drive a resistive load directly. The resistive load should be less than 700W and must be pulled up to a positive supply such that the voltage on pin (4) stays within a range of 0 to +5V.
Applications Discussion
Current Multiplier/ Divider
The basic design criteria for all circuit configurations using the RC4200 multiplier is contained in equation (1), that is, I1 I2 I 3 = -------I4 The current-product-balance equation restates this as: I1 I2 = I3 I4
R1 + V I1 = X R1 R2 + I2 = VY R2
Dynamic Range and Stability
The precision dynamic range for the RC4200 is from +50 mA to +250 mA inputs for I1, I2 and I4. Stability and accuracy degrade if this range is exceeded. To improve the stability for input currents less than 50 mA, filter circuits (RSCS) are added to each input (see Figure 2).
(6)
R4 I4 V I4 = Z R4 + +VZ
R1 VX RS
8 I1 7
5 I4
R4 +VZ RS CS
VX
8 I1 7
5
CS R2 VY I2 RS CS 2 1
RC4200
4 3 -VS 6 I3
RO VO +VS - A1 + -VS
65-4200-03
RC4200
VY 1 I2 2 3 -VS 6
Ammeter 4 I3
65-4200-02
A
RS = 10k Ohms CS = 0.005 F
Figure 2. Current Multiplier/Divider with Filters
Figure 1. Current Multiplier/Divider
Amplifier A1 is used to convert the I3 current to an output voltage. Multiplier: Vz = constant 0 Divider: Vy = constant 0
4
PRODUCT SPECIFICATION
RC4200
Voltage Multiplier/Divider
R1 VX 8 I1 7 5 I4 R4 VZ
Resistors Ra and Rb extend the range of the VX and VY inputs by picking values such that: V X ( min. ) V REF I 1 ( min. ) = ----------------------- + ------------- = 50 mA, R1 Ra V X (max.) V REF and I 1 (max.) = ----------------------- + ------------- = 250 mA, R1 Ra V Y (min.) V REF also I 2 (min.) = ---------------------- + ------------- = 50 mA, R2 Rb
RO VO
RC4200
R2 VY I2 2 3 VXVY VV = OZ R1R2 ROR4 -VS
65-4200-04
1 4 6 I3
V Y (max.) V REF and I 2 (max.) = ----------------------- + ------------- = 250 mA. R2 Rb Resistor RC supplies bias current for I3 which allows the output to go negative. Resistors RCX and RCY permit equation (6) to balance, ie.:
V o ae V REF o ae V 0 V REF V X ae V X V REF o ae V Y V REF o Y c -------- + --------------- / c -------- + --------------- / = c ------ + --------------- + ------------ + ------------ / c --------------- / R R R R Ro R oe R e R0 e R1 CY o e D o CX C b a 2 V VV VV VV REF Y REF X REF YX ----------------- + ------------------------- + ------------------------- + --------------- = RR RR RR RR ab 2a 1b 12 2 V VV VV VV REF 0 REF X REF Y REF ----------------------- + ------------------------- + ------------------------- + ---------------RR RR R R RR cd 0d cx d CY d
Figure 3. Voltage Multiplier/Divider
VX VY R0 R4 Solving for V 0 = ------------------------------------VZ R1 R2 For a multiplier circuit V Z = V R = cons tan t R0 R4 Therefore: V 0 = V X V Y K where K = -------------------VR R1 R2 For a divider circuit V Y = V R = cons tan t VX VR R0 R4 Therefore: V 0 = ------- K where K = -------------------VZ R1 R2
Cross-Product Cancellation
Cross-products are a result of ths VXVR and VYVR terms. To the extend that R1Rb = RCXRD, and R2Ra = RCYRd cross-product cancellation will occur.
Extended Range
The input and output voltage ranges can be extended to include 0 and negative voltage signals by adding bias currents. The RSCS filter circuits are eliminated when the input and biasing resistors are selected to limit the respective currents to 50 mA min. and 250 mA max.
Arithmetic Offset Cancellation
The offset caused by the VREF2 term will cancel to the extent that RaRb = R0Rd, and the result is: V 0 V REF VY VX --------------- = -------------------- or V 0 = V X V Y K R0 Rd R1 R2 R0 Rd where K = --------------------------V REF R 1 R 2
Extended Range Multiplier
+VREF RA VX (Input) RB 8 R1 I1 7 RC 5 I4 RD
Resistor Values
Inputs: V X ( min. ) V X V X (max.)
RO VO (Output)
RC4200
R2 VY (Input) I2 2 3 RC4 6 -VS 1 4 I3 +VS
DV X = V X (max.) - V X (min.) V Y ( min. ) V Y V Y (max.) DV Y = V Y (max.) = V Y (min.) V REF = Constant (+7V to +18V)
RCX
-VS
65-4200-05
V0 K = --------------- ( Design Requirements ) VX VY
Figure 4. Extended Range Multiplier
5
RC4200
PRODUCT SPECIFICATION
DV X DV Y V REF R 1 = ---------------- , R 2 = ---------------- , R d = ---------------200mA 200mA 250mA DV X V REF R a = ------------------------------------------------------------------------------250mADV X - 200mA V X ( max. ) DV X V REF R b = ------------------------------------------------------------------------------250mADV Y - 200mA V Y ( max. ) Ra Rb R1 Rb R2 Ra -, R c = ------------ , R CX = ------------ R cy = -----------Rd Rd Rd DV X DV Y K R 0 = ---------------------------160mA
Multiplying Circuit Offset Adjust
10K R5 = R9 = R16 50K R7 = R11 = R14, = 100W R6 = R10 = 100W (VS/0.05) R15 = 100W (VS/0.10) R8 = R1 | | Ra R12 = R2 | | Rb R13 = R0 | | RC | | RCX | | RCY
+VREF Ra R1 VX (Input) XOS +VS R6 R5 -VS VY (Input) R7 0.1 F 1 +VS R9 YOS -VS RCY RCX R10 R12 R11 0.1 F 3 -VS - 6 R2 I2 2 4 I3 R8 I1 Rb Rc 8 7 5 I4 Rd 100 Rd R17 R18 -VS R19 R20 ZOS +VS
RC4200
R17-R20 can be used to help cancel crossproduct errors caused by resistor product mismatch. RO VO (Output)
RC5534
+ 0.1 F +VS R13 R16 VOS R15 R14 -VS
65-4200-06
Figure 5. Multiplying Circuit Offset Adjust
Procedure
1. 2. 1.Set all trimmer pots to 0V on the wiper. 2.Connect VX input to ground. Put in a full scale square wave on VY input. Adjust XOS(R5) for no square wave on V0 output (adjust for 0 feedthrough). 3. 3.Connect VY input to ground. Put in a full scale square wave on VX input. Adjust YOS(R9) for no square wave on V0 output (adjust for 0 feedthrough). 4.Connect VX and VY to ground. Adjust VOS(R16) for 0V on V0 output.
4.
6
PRODUCT SPECIFICATION
RC4200
Extended Range Divider
+VREF +VREF Ra Rb R az Rc Rd
Notice that it is necessary to match the above resistor crossproducts to within the amount of error tolerable in the output offset, i.e., with a 10V F.S. output, 0.1% resistor crossproduct match will give 0.1% x 10V. untrimmable output offset voltage.
Resistor Values
Inputs: VX(min.) VX VX(max.)
VZ (Output)
R1 VX (Input)
8 I1 7 RC4200 Multiplier 1 I2 2 3 -VS 6
5 I4
R4
DVX = VX(max.) = VX(min.) VZ(min.) VZ VZ(max.) DVZ = VZ(max.) = VZ(min.) VREF = Constant (+7V to +18V)
4 I3
RO
VO (Output)
Outputs: V0 (min.) V0 V0 (max.) DV0 = V0 (max.) = V0 (min.) V0 VZ K = -------------- ( Design Requirement ) VX DV 0 DV REF DV Z R 0 = ---------------- , R b = ----------------- , R 4 = ---------------750mA 250mA 200mA DV 0 V REF R c = ----------------------------------------------------------------------------750mADV 0 - 700mA V 0 ( max. ) DV X V REF R d = -----------------------------------------------------------------------------250mADV Z - 200mA V Z ( max. ) Rc Rd Rc R4 R0 Rd R a = ------------ , R az = ------------ , R ao = -----------Rb Rb Rb DV 0 DV Z R 1 = ---------------------600mAK
+VS
RC5534 -VS ao
65-4200-08
R
Figure 6. Extended Range Divider
As with the extended range multiplier, resistors Raz and Rao are added to cancel the cross-product error caused by the biasing resistors, i.e.
ae V 0 V REF o ae V Z V REF o ae V X V 0 V Z V REF o ae V REF o c -------- + --------- + --------- + --------------- / c --------------- / = c ------ + --------------- / c ------- + --------------- / Ro R oe R R o e Rb o e R0 e R 1 R ao R az D C 4 a 2 V VV VV VV REF Z REF 0 REF X REF ------------------------- + ----------------------- + ------------------------ + ---------------- = RR RR RR RR ab az b ao b 1b 2 V VV VV VV REF 0Z 0 REF Z REF --------------- + ----------------------- + ------------------------ + ---------------RR RR RR RR cd 04 0d 4c
To cancel cross-product and arithmetic offset: RaoRb = R0Rd, RazRb = R4Rc and RaRb = RcRd and the result is: V0 VZ VX V X V REF --------------------- = -------------- or V 0 = ----------R0 R4 VZ K R1 Rb V REF R 0 R 4 where K = --------------------------R1 Rb
7
RC4200
PRODUCT SPECIFICATION
Divider Circuit with Offset Adjustment
+VREF
Ra
Rb
R AX 8
Rc
Rd VZ (Input) +VS R12 R13 Z OS VZ (Offset) -VS
R1 VX (Input) +VS R5 R7 +VS YOS R18 R21 = Rb R19 R20 -VS R9 0.1 m F -VS 0.1 mF I2 V X (Offset) R6 X OS R8
5 I4 RC4200 Multiplier R10
R4
I1 7
R11
1 4 2 3 -VS 6 I3 RO
VO (Output)
R
ao
0.1 m F R14 +VS R16 R17 V OS V O (Offset) R15 -VS
R18-R21 can be used in place of R9 to help cancel gain error due to resistor product mis-match (See Appendix 1).
65-1878
General 10K R5 = R13 = R17 50K R7 + R8 R1 | | Ra | | Raz | | Rao R6 R7 (VS/0.05) R9 = Rb R10 100 x R4 R11 = 20K R12 = 100K R14 + R15 R0 | | Rc R16 R15 (VS/0.10)
Example: Two-Quad Divider V0 = K(VX/VZ), K = k, VREF = +VS = +15V -10 VX +10, therefore DVX = 20 0 VZ +10, therefore DVZ = 20 -10 V0 +10, therefore DV0 = 20 R0 = 26.7K R1 = 333K Rb = 60K R5, R13, R17 = 10K R4 = 50K R7, R15 = 1K Rc = 37.5K R8, R11 = 20K Rd = 300K R6, R9, R16 = 300K Ra = 187.5K R10 = 4.7M Raz = 31.25 R12 = 100K Rao = 133K
Figure 7. Divider Circuit with Offset Adjustment
8
PRODUCT SPECIFICATION
RC4200
Divider Circuit Offset Adjustment Procedure
1. 2. Set each trimmer pot to 0V on the wiper. Connect VX (input) to ground. Put a DC voltage of approximatey 1/2 VZ (max.) DC on the VZ (input) with an AC (squarewave is easiest) voltage of 1/2 VZ (max.) peak-to-peak superimposed on it. Adjust XOS (R5) for zero feedthrough. (No AC at V0)
V z (Max.)
Square Root Circuit V0 = NOVX
+V REF
Ra
Rb
Rc
Rd
R1 VX (Input)
8 I1 7 RC4200 Multiplier
5 I4
R4
1/2 V z (Max.)
1/2 Vz (Max.)
I2
1 4 2 3 6 I3 +VS RO VO (Output)
0V
3.
Connect VX (input) to VZ (input) and put in the 1/2 VZ(max.) DC with an AC of approximately 20 mV less than VZ(max.). Adjust ZOS (R13) for zero feedthrough.
V z (Max.) 1/2 Vz (Max.) 0V ~ 10 mV ~
65-1868
-VS
R ao
-VS 65-1877
Figure 8.
2V V 2 VV V2 VV V V VV 0 REF 0 REF 0 0 REF REF REF X REF ------------------------- + ---------------- + ----------------------- = -------------- + ----------------------- + ----------------------- + ---------------RR RR RR RR RR RR RR c4 04 ao b ab cd 1b 0d If R R = R R and R R R R + R R R R = R R R R ab cd ao b 0 d ao b c 4 cd04 V RR VV V2 REF 0 4 X REF 0 Then -------------- = ------------------------- or V 2= V K where K = ------------------------------0 X RR RR RR 1b 1b 04 and V 0 X =N V X where N = K
4.
Return VX (Input) to ground and connect VZ(max.) DC on VZ(input). Adjust output VOS(R17) for VO = 0VO Connect VX (input) to VZ (input) and and in VZ (max.) DC. (The output will equal K.) Decrease the input slowly until the output (V0 - K) deviates beyond the desired accuracy. Adjust ZOS to bring it back into tolerance and return to Step 4. Continue steps 4 and 5 until VZ reduces to the lowest value desired.
0V
V ( max. )and V ( max. ) = N V ( max. ) X 0 X
5.
V 0 N = ------------ ( Design Requirements ) V X V ( max. ) 2 0 = --------------------------2 74mA N
R
1
Notice that as the input to VX and VZ gets closer to zero (an illegal state) the system noise will predominate so much that an integrating voltmeter will be very helpful.
V REF R = R = --------------a d 50mA R V REF = R = ---------------c 150mA V ( max. ) 0 = ----------------------50mA V ( max. ) 0 = ----------------------125mA V ( max. ) 0 = ----------------------225mA
b
R
4
R
ao
R
0
9
RC4200
PRODUCT SPECIFICATION
Square Root Circuit Offset Adjust
+V REF
Ra R1 VX (Input) +VS R6 XOS R5 R7 +VS YOS R14 R17 = Rb R15 R16 -VS R9 -VS R8
Rb 8 I1 7 RC4200 Multiplier
Rc 5 I4
Rd R4
1 0.1 m F I2 2 0.1 m F 3 -VS 6 4 I3 RO +VS VO (Output)
R
ao
0.1 mF R10
-VS +VS R12 R13 V OS R11
R14-R17 can be used in place of R9 to help reduce linearity error due to resistor product mis-match (See Appendix 1).
-VS
65-1876
Figure 9. Square Root Circuit Offset Adjust
10K R 5 = R 13 50K R 7 = 100W VS R 6 = R 7 --------0.05 R 8 = R 1 || R a || R ao R9 = Rb R 10 = R 0 || R C R 11 = 100W VS R 12 = R 11 -----0.1
Procedure
1. 2. Set both trimmer pots to 0V on the wiper. Put in a full scale (0 to VX(max.) squarewave on VX input. Adjust XOS(R5) for proper peak-to-peak amplitude on V0 output. (Scaling adjust) Connect VX input to ground. Adjust VOS(R13) for 0V on V0 output.
3.
10
PRODUCT SPECIFICATION
RC4200
Squaring Circuits V0 = K VX2
+V REF
Ra R1 VX (Input)
Rb 8 I1 7 RC4200 Multiplier 5
Rc
Rd
I4
R1 I2
1 4 2 3 -VS 6 I3 +VS RO VO (Output)
RCX
RC5534
-VS
65-1875
Figure 10. Squaring Circuit
V X2 2V X V REF V REF 2 V 0 V REF V REF 2 V X V REF ------- + ------------------------- + ------------- = -------------------- + ------------- + --------------------R1 Ra R0 Rd Rc Rd Rc Rd R1 2 R a2 if R a2 = R c R d and R 1 R a = 2R CX R D R0 Rd V 0 V REF V X2 then -------------------- = -------2 or V 0 = KV X2 where K = -------------------- 2 R0 Rd R1 V REF R 1 VX(min.) VX VX(max.) DVX = VX(max.) - VX(min.)
V0 K = -------2 (Design Requirement) VX DV X R 1 = ---------------200mA DV X V REF R a = ------------------------------------------------------------------------------250mADV X - 200mA V X ( max. ) V REF R d = ---------------250mA R a2 R c = -----Rd R1 Ra R cx = -----------2R d DVX 2 K R 0 = -----------------160mA 11
RC4200
PRODUCT SPECIFICATION
Squaring Circuits Offset Adjust
+VREF
Ra R1 R5
Rb
Rc 8 5 I4
Rd R7 = 100 Rd R9
+VS
VX (Input)
R10 Z OS R8
I1
7
-VS
R1
0.1 mF 1 R6 I2 2
RC4200 Multiplier
R7-R10 can be used to cancel all linearity errors caused by input offsets and resistor product mis-match (See Appendix 1).
4 0.1 m F R CX +VS R14 VOS R13 R15 R16 3 -VS 6 I3
RO VO (Output)
+VS
-VS 0.1 m F
65-1874
-VS
Figure 11. Squaring Circuit Offset Adjust
10K R 10 = R 11 50K R 8 , R 15 = 100W R 9 , R 14 VS = 100W -----0.1
Procedure
1. 2. 3. 1.Set both trimmer pots to 0V on the wiper. 2.Put in a full scale (VX) squarewave on VX input. Adjust ZOS(R10) for uniform output. 3.Connect VX input to ground. Adjust VOS(R11) for 0V on V0 outputs.
R 5 , R 6 = R 1 || R a R 16 = R 0 || R c || R a
12
PRODUCT SPECIFICATION
RC4200
Appendix 1--System Errors
There are four types of accuracy errors which affect overall system performance. They are: * Nonimearity--Incremental deviation from absolute accuracy. See Note 1. * Scaling Error--Linear deviation from absolute accuracy. * Output Offset--Constant deviation from absolute accuracy. * Feedthrough.--Cross-product errors caused by input offsets and external circuit limitations. See Note 2. This nonlinearity error in the transfer function of the RC4200 is 0.1% maximum (0.03 maximum for the RC4200A). That is, I1 I2 I 3 = -------- 0.1% F.S. ( 4 ) I4 The other system errors are caused by voltage offsets on the inputs of the RC4200 and can be as high as 3.0% (2.0% for RC4200A). VX VY R0 R4 V 0 = --------------- ------------ 3.0% F.S. ( 3 ) ( 4 ) VZ R1 R2
R1 VX R4 I4 RC4200 Multiplier R2 VY I2 2 3 -VS 6 1 4 I3 RO VO +VS
Errors Caused by Input Offsets
V0 = 1 R0R4 VXVY VV VXVOSY V0VOSZ VOSXVOSY VZ VZ Y OSX R0R4
VY Feedthrough VX Feedthrough Scaling Error Output Offset Error
System errors can be greatly reduced by externally trimming the input offset voltages of the RC4200. (3.0% F.S. for RC4200 and 0.1% for RC4200A.)
VX R1 8 5 R4 VZ +VS R1 X OS -VS +VS R2 1 RO VO 7 RC4200 Multiplier VY 100 R4 ZOS -VS 4 2 3 -VS -VS Ideal Op-Amp V OS = 0 6
+VS
R2
8 I1 7
5
VZ
65-1870
If XOS = XOSX, YOS = YOSY, ZOS = -VOSZ, VX VY R0 R4 ( then V O --------------- ------------ 0.3% F.S.3 ) VZ R1 R2
Figure 13. RC4200 with Input Offset Adjustment
Extended Range Circuit Errors
The extended range configurations have a disadvantage in that additional accuracy errors may be introduced by resistor product mismatching.
Ideal Op-Amp V OS = 0
65-1871
Multiplier
An error in resistor product matching will cause an equivalent feedthrough or output offset error. See Figure 6. R1Rb = RCXRd a, VX feedthrough (VY = 0) = IaVX R2Ra = RCYRd b, VY feedthrough (VX = 0) = bVY RaRb = RCRd g, V0 offset (VX = VY = 0) = gVREF*
Note: * Output offset errors can always be trimmed out with the output op amp offset adjust, VOS (R16).
Figure 12. Notes: 1. The input circuits tend to become unstable at I1, I2, I4 < 50 mA and linearity decreases when I1, I2, I4 > 250 mA (e.g., @ I1 = I2 = 500mA nonlinearity error 0.5%). 2. This section will not deal with feedthrough which is proportional to frequency of operation and caused by stray capacitance and/or bandwidth limitations. (refer to Figure 12.) 3. Not including resistor tolerance or output offset on the operational amplifier. 4. For 50 mA I1, I2, I4 250 mA.
13
RC4200
PRODUCT SPECIFICATION
Reducing Mismatch Errors
You need not use 0.01% resistors to reduce resistor product mismatch errors. Here are a couple of ways to obtain maximum accuracy out of the extended range multiplier (see Figure 4) using 1% resistors.
Method 1 VX feedthrough, for example, occurs when VY = 0 and VOSY 0. This VX feedthrough will equal VXVOSY. Also, if VOSZ 0, there is a VX feedthrough equal to VXVOSZ. A resistor-product error of a will cause a VX feedthrough of aVX. Likewise, VY feedthrough errors are: VYVOSX, VYVOSZ and bVY
Select Rd to be 1% or 2% below (or above) the calculated value. This will cause a and b to both be positive (or negative) by nearly the same amount. Now the effective value of Rd can be trimmed with an offset adjustment ZOS(R20) on pin 5. This technique causes: a slight gain error which can be compensated with the R0 value, and an output of offset error that can be trimmed with VOS(R16) on the output op amp.
Extended Range Divider
The only cross-product error of interest is the VZ feedthrough (VX = 0 and VOSX 0) which is easily adjusted with XOS(R5). See Figure 6. Resistor product mismatch will cause scaling errors (gain) that could be a problem for very low values of VZ. Adjustments to YOS(R18) can be made to improve the high gain accuracy.
Total feedthrough: VXVOSY VYVOSX aVX bVY (VX + VY) VOSZ By carefully abusing XOS(R5), YOS(R9) and ZOS(R20) this equation can be made to very nearly equal zero and the feedthrough error will practically disappear. A residual of set will probably remain which can be trimmed outwith VOS(R16) at the output of amp.
Method 2
Square Root and Squaring
These circuits are functions of single variables so feedthrough, as such, is not a consideration. Cross product errors will effect incremental accuracy that can be corrected YOS(R14) or ZOS(R10). See Figure 9 and Figure 11.
Notice that the ratios of R1Rb:RCXRd and R2Ra:RCYRd are both dependent of Rd also that R1, R2, Ra and Rb are all functions of the maximum input requirements. By designing a multiplier for the same input ranges on both VX and VY then R1 = R2, RCX = RCY and Ra = Rb. (Note: it is acceptable to design a four quadrant multiplier and use only two quadrants of it.)
14
PRODUCT SPECIFICATION
RC4200
Appendix 2--Applications
Design Considerations for RMS-to-DC Circuits
Average Value Consider Vin = Asinwt. By definition,
Therefore, the rms value of Asinwt becomes: A V rms = -----2
RMS Value for Rectified Sine Waves Consider Vin = |A sin wt|, a rectified wave. To solve,
V AG =
o0 VIN dt
T -2
integrate of each half cycle. 1 2 i.e. -- TV in dt = T0
Where T = Period w = 2pf 2p = ----T
o
1 -T
o0
T -- 2 2A sin 2 wt
dt+
oT- ( -Asinwt ) dt -2 2
T
VIN
A
1 2 2 This is the same as -- TA sin wt dt 1
o0
so, |Asinwt| rms = Asinwt rms
t 0 T 2 T
65-1873
Practical Consideration: |Asinwt| has high-order harmonics; Asinwt does not. Therefore, non-ideal integrators may cause different errors for two approaches.
(a) VIN a2 Low Pass Filter
2
2 V AG = -T
o0 A sin wt dt
T -2 0
T -2
V O = VIN rms
2A 1 -= ------ - --- cos wt Tw
(b) VIN Absolute Value VIN a2 b
VIN VO Low Pass Filter VO = A VG V IN2
2A = ------ [ - cos ( p ) + cos ( 0 ) ] 2p 2 Average Value of Asinwt is -- A p
RMS Value
65-4200-09
Figure 14.
Again, consider VIN = Asinwt V rms = V AVG = 1 -T
V IN Avg --------V0
2
= V0 Avg ( VIN
2 2
o0 [ VIN ]2 dt
T
implies V 0 = V0 =
)
V rms for Asinwtdt: V rms = 1 -T
o0 A sin wt dt
2 2 2T
T
Avg VIN
V rms =
A -----T
2
o0
11 -- - -- cos 2 cos 2 wt dt -22
T 0
V rms =
AT 1 ------ -- - ------ sin2 wt 2 2 4w AT ------ -22 A -----2
2 2
V rms =
V rms =
15
RC4200
PRODUCT SPECIFICATION
+V REF
100K VIN 100K
100K 8
167K 5
60K
300K
100K 8
100K 5
300K 200K
13.3K 7 RC4200A Multiplier 50K 100K 50K 2 3 -VS 83.3K 0.1 mF
1/2 RC5532
22 m F
7 10K 1 RC4200A Multiplier X
X2
1 4 6 250K* 60K
4 2 3 -VS 6
44.4K** VOUT
1/2 RC5532
0.1 mF 80K +VS 15K 30K 10K 10K 100 -VS +VS
45.5 K 30K
*Determines sacle factor (K) for X 2 function. **Determines sacle factor (K) for X function. +Vs = +VREF = +15V -Vs = -15V
100
-VS
65-1869
Figure 15. RMS to DC Converter VOUT=OVIN2
Amplitude Modulator with A.G.C.
In many AC modulator applications, unwanted output modulation is caused by variations in carrier input amplitude. The versatility of the RC4200 multiplier can be utilizes to eliminate this undesired fluctuation. The extended range multiplier circuit (Figure 4) shows an output amplitude inversely proportional to the reference voltage VREF. VX VY R0 Rd i.e., V 0 = --------------- -----------V REF R 1 R 2 By making VREF proportional to VY (where VY is the carrier input) such that: V REF = V H =
If VH is made proportional to the average value of Asinwt (i.e., 2A/p) and scaled by a value of p/2 then: VH=A and if: VX = Modulating input (VM) and: VY Carrier input (Asinwt) R0 Rd Then: V0 = K VM sinwt where K = -----------R1 R2 The resistor scaling is determined by the dynamic range of the carrier variation and modulating input. The resistor values are solved, as with the other extended range circuits, in terms of the input voltages. Input voltages: Modulation voltage (VM): 0 VM VX(max.) Carrier (VY): VY = Asinwt Carrier amplitude fluctuation (DA): A(min.) sint VY A(max.) sinWwt Dynamic Range (N): A(max.)/A(min.), A(max.) = VH(max.) and A(min.) = VH(min.)
o ( VY )
Then the denominator becomes a variable value that automatically provides constant gain, such that the modulating input (VX) modulates the carrier (VY) with a fixed scale factor even though the carrier varies in amplitude.
16
PRODUCT SPECIFICATION
RC4200
Ra R1 +VS 10K 100 -VS VY = A SIN w t R2 +V S 10K 100 -VS 30K R1 Ra
Ra 5 Ra
VM
8 7
Ra RC4200 Multiplier RO
0.1 mF 1 R2 Ra
30K
2 4 0.1 mF 3 -VS 6 1/4 RC4156 0.1 m F R* VO = VM sin w t +VS
R1 R2
10K R3 30K R3 30K 1N914 1/4 RC4156 1/2 R3 15K C1 470 -VS R3 30K p R3 47K 2 1/4 RC4156 30K
VH = p AVG A sin w t = A 2
*R1 1N914
R2
Ra
RO
65-1866
Figure 16. Amplitude Modulator with A.G.C.
The maximum and minimum values for I1 and I2 lead to: V X ( max. ) V H ( max. ) I 1 (max.) = ------------------------ + ------------------------ = 250mA R1 Ra V H ( min. ) I 1 (min.) = ----------------------- = 50mA V M( min. ) = 0 Ra A ( max. ) V H ( max. ) I 2 (max.) = -------------------- + ------------------------ = 250mA Ra R2 V H ( min. ) I 2 (min.) = ----------------------- = 50mA Ra For a dynamic range of N, where A ( max. ) N = -------------------- < 5, A ( min. ) These equations combine to yield: V X (max.) A(max.) R 1 = -------------------------------- , R2 -------------------------------- , ( 5 - N )50mA ( 5 - N )50mA R1 R2 A(min.) -, R a = ------------------ and R O = K -----------50mA Ra
Example 1 VY = Asinwt 2.5V A 10V, therefore N = 4 0V VM 10V, therefore VX(max.) = 10V K = 1, therefore V0 = VM sinwt
V X (max.) 10V R 1 = ----------------------- = ------------- = 200K 50mA 50mA A(max.) 10V R 1 = ------------------- = ------------- = 200K 50mA 50mA A(min.) 2.5V R a = ------------------ = ------------- = 50K 50mA 50mA R1 R2 200K 200K R O = K ------------ = 1 -------------------------------- = 800K Ra 50K
Example 2 VY = Asinwt 3 A 6, therefore N = 2 0V VM 8V, therefore VX(max.) = 8V K = 0.2, therefore V0 = 0.2 VM sinwt
so: R1 = 53.3K, R2 = 40K Ra = 60K and R0 = 7.11K
17
RC4200
PRODUCT SPECIFICATION
Inputs VZ R1 VX Rs +VS Cs VOS1 R1 -VS VY Rs +VS Cs VOS2 2 3 -VS 6 RO I2 4 I3 VOS3 1/4 4156 0.1 mF +VS 50 mV R2 100 0.1 mF 1 Gain Adj. Output VO 7 RC4200 Multiplier RO I1 8 5 I4 50 mV VOS4 ADJ R4 100 R4
+VS
-VS
100 -VS 50 mV
0.1 m F
RS = 10K, C S = 0.005 mF VX VY K Vz R O R4 R1 R2
100 mV -VS
Vs = Where K =
65-1867
Limited Range, First Quadrant Applications
The following circuit has the advantage that cross-product errors are due only to input offsets and nonlinearity error is sightly error is slightly less for lower input currents. The circuit also has no standby current to add to the noise content, although the signal-to-noise ratio worsens at very low input currents (1-5 mA) due to the noise current of the input stages. The RSCS filter circuits are added to each input to improve the stability for input currents below 50 mA.
Thermal Symmetry
I2 Thermal Symmetry Line VOS2 -VS Output I3 1 2 3 4 8 7 6 5 I1 VOS1 GND I4
65-0070
Caution!
The bandpass drops off significantly for lower currents (<50 mA) and non-symmetrical rise and fall times can cause second harmonic distortion.
The scale factor is sensitive to temperature gradients across the chip in the lateral direction. Where possible, the package should be oriented such that forces generating temperature gradients are located physically on the line of thermal symmetry. This will minimize scale-factor error due to thermal gradients.
18
PRODUCT SPECIFICATION
RC4200
Vx
Relative Output (dB)
200 mA ac* 8 150 mA dc 7 250 mA dc 4200 1 2 3 -15V 6
+3
5 250 mA dc Vz
+1 -1 -3 -5 -7 -9 -11 10 10
2
VY
4
Vo
* Peak to Peak
10
3
10
4
10
5
10
6
10
7
Frequency (Hz)
Vx
250 mA dc
8 7
5
250 mA dc
+3
Vz
Relative Output (dB)
+1 -1 -3 -5 -7 -9 -11 10
2 3 4 5 6 7
VY
200 mA ac* 1 150 mA dc 2
4200
4 3 6
Vo
* Peak to Peak
-15V
10
10
10
10
10
10
Frequency (Hz)
Vx
250 mA dc
8 7
Relative Output (dB)
5 83.4 mA ac* 167 mA dc 4200
+3
Vz
+1 -1 -3 -5 -7 -9 -11 10 10
2
VY
250 mA dc
1 2 3 -15V 6 4 Vo
* Peak to Peak
10
3
10
4
10
5
10
6
10
7
Frequency (Hz) Figure 18. Outputs
65-1865
65-1864
65-1863
19
RC4200
PRODUCT SPECIFICATION
300 250 5 nA I1 ( mA) 200 I4 ( mA) 4 nA 150 100 1.0 nA 50 50 1.2 nA 100 150 200 I2 ( mA) Figure 19a. Output Noise Current (I3) vs. Input Currents (I1, I2) for I4 = 250mA 3 nA 2.5 nA 2 nA
250
nA
2n
200
4
nA
A
3
5n
A
A 6n A 7n
150
9n
A
65-1861
100
1.5 nA 250 300
50 50
25 nA
100
150 I1 ( mA)
200
250
Figure 19b. Output Noise Current (I3) vs. Input Currents (I4, I1) for I2 = 250mA
250 AC Feedthrough (mVP-P) 200 150 100 50 0 1.0 10 100 1K 10K 100K Frequency (Hz) Figure 20. AC Feedthrough vs. Frequency Multiplier Configuration VV Vo = X Y 10 VY = 0 VX = 10 sin w t
65-1860
VX = 0 VY = 10 sin w t
1M
20
65-1862
A 11 n A 15 n
PRODUCT SPECIFICATION
RC4200
Mechanical Dimensions
8-Lead SOIC Package
Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
Symbol A A1 B C D E e H h L N a ccc
Inches Min. .053 .004 .013 .008 .189 Max. .069 .010 .020 .010 .197
Millimeters Min. 1.35 0.10 0.33 0.20 4.80 Max. 1.75 0.25 0.51 0.25 5.00
.150 .158 .050 BSC .228 .010 .016 8 0 -- 8 .004 .244 .020 .050
3.81 4.01 1.27 BSC 5.79 0.25 0.40 8 0 -- 8 0.10 6.20 0.50 1.27
3 6
8
5
E
H
1
4
D A1 A SEATING PLANE B -C- LEAD COPLANARITY ccc C a
h x 45 C
e
L
21
RC4200
PRODUCT SPECIFICATION
Mechanical Dimensions (continued)
8-Lead Plastic DIP Package
Inches Min. A A1 A2 B B1 C D D1 E E1 e eB L N -- .015 .115 .014 .045 .008 .348 .005 .300 .240 Max. .210 -- .195 .022 .070 .015 .430 -- .325 .280 Millimeters Min. -- .38 2.93 .36 1.14 .20 8.84 .13 7.62 6.10 Max. 5.33 -- 4.95 .56 1.78 .38 10.92 -- 8.26 7.11 Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E1" do not include mold flashing. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. Terminal numbers are for reference only. 4. "C" dimension does not include solder finish thickness. 5. Symbol "N" is the maximum number of terminals. 4 2
Symbol
2
.100 BSC -- .430 .115 .160 8
2.54 BSC -- 10.92 2.92 4.06 8 5
D 4 1
E1
D1
5
8
E e A A1 L B1 B eB A2 C
22
PRODUCT SPECIFICATION
RC4200
Mechanical Dimensions (continued)
8-Lead Ceramic DIP Package
Inches Min. A b1 b2 c1 D E e eA L Q s1 a Max. Millimeters Min. Max. 8 2, 8 8 4 4 5, 9 7 3 6 Notes: Notes 1. Index area: a notch or a pin one identification mark shall be located adjacent to pin one. The manufacturer's identification shall not be used as pin one identification mark. 2. The minimum limit for dimension "b2" may be .023 (.58mm) for leads number 1, 4, 5 and 8 only. 3. Dimension "Q" shall be measured from the seating plane to the base plane. 4. This dimension allows for off-center lid, meniscus and glass overrun. 5. The basic pin spacing is .100 (2.54mm) between centerlines. Each pin centerline shall be located within .010 (.25mm) of its exact longitudinal position relative to pins 1 and 8. 6. Applies to all four corners (leads number 1, 4, 5, and 8). 7. "eA" shall be measured at the center of the lead bends or at the centerline of the leads when "a" is 90. 8. All leads - Increase maximum limit by .003 (.08mm) measured at the center of the flat, when lead finish applied. 9. Six spaces. D 4 1 Note 1 E
Symbol
-- .200 .014 .023 .045 .065 .008 .015 -- .405 .220 .310 .100 BSC .300 BSC .125 .200 .015 .060 .005 -- 90 105
-- 5.08 .36 .58 1.14 1.65 .20 .38 -- 10.29 5.59 7.87 2.54 BSC 7.62 BSC 3.18 5.08 .38 1.52 .13 -- 90 105
5 s1
8
e
eA
A Q L b2 b1 a c1
23
RC4200
PRODUCT SPECIFICATION
Ordering Information
Part Number RC4200N RC4200AN RC4200M RC4200AM RM4200D RM4200AD RM4200AD/883B Package 8-Lead Plastic DIP 8-Lead Plastic DIP 8-Lead SOIC 8-Lead SOIC 8-Lead Ceramic DIP 8-Lead Ceramic DIP 8-Lead Ceramic DIP Operating Temperature Range 0C to +70C 0C to +70C 0C to +70C 0C to +70C -55C to +125C -55C to +125C -55C to +125C
Note: /883B suffix denotes MIL-STD-883, Level B processing
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS30004200 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC4207
Precision Monolithic Dual Operational Amplifier
Features
* * * * * Low Noise - 0.35 mVp-p (0.1 Hz to 10 Hz) Ultra-low VOS - 75 mV Ultra-low VOS drift - 1.3 mV/C Long term VOS stability - 0.2 mV/Mo Low input bias and offset currents - 5 nA * * * * High gain - 400 V/mV Fits 4558 socket Industry standard pinout 8-lead mini-DIP
Description
Designed for low level signal conditioning and instrumentation applications, the 4207 is a precision dual amplifier combining excellent DC input specifications with low input noise characteristics. Ultra low input offset voltage, low drift, high CMRR, and low input bias currents serve to reduce input related errors to less than 0.01% in a typical high gain instrumentation amplifier system (AV = 1000). The 4207 contains two separate amplifiers with a high degree of isolation between them; each is complete requiring no external compensation capacitors or offset nulling potentiometers. The inherent VOS is typically less than 150 mV, resulting in superior temperature drift, and this low initial offset is further reduced by "Zener-zap" nulling when the wafers are tested. Advanced thin film and nitride dielectric processing allows the 4207 to achieve its high performance and small size (the 4207 is offered in 8-lead DIPs). The 4207 fits the industry standard 8-lead op amp pin-out.
Block Diagram
Output A -Input A +VS Output B
Pin Assignments
Output A -Input A +Input A -VS -Input B +Input B
1 2 3 4 8 7 6 5
65-4207-02
+VS Output B -Input B +Input B
A
+Input A -VS
B
65-3468-01
Rev. 1.0.1
PRODUCT SPECIFICATION
RC4207
Absolute Maximum Ratings
(beyond which the device may be damaged)1 Parameter Supply Voltage Input Voltage2 Differential Input Voltage Internal Power Dissipation3 PDTA < 50C Output Short Circuit Duration Junction Temperature Storage Temperature Operating Temperature Lead Soldering Temperature (60 sec) For TA > 50C Derate at 6.25 -65 0 Min Typ Max 18 18 30 500 468 Indefinite 125 150 70 300 C C C C mW/C Units V V V mW mW
Notes: 1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded. 2. For supply voltages less than 18V, the absolute maximum input voltage is equal to the supply voltage. 3. Observe package thermal characteristics.
Operating Conditions
Parameter qJA Thermal resistance Min Typ 160 Max Units C/W
Electrical Characteristics
(VS = 15V, 0C TA +70C unless otherwise noted) 4207F Parameters Input Offset Voltage Average Input Offset Voltage Input Offset Current Average Input Offset Current Drift Input Bias Current Average Input Bias Current Drift Input Voltage Range Common Mode Rejection Ratio Power Supply Rejection Ratio Large Signal Voltage Gain Maximum Output Voltage Swing Power Consumption VCM = 10V VS = 4.0V to 16.5V RL > 2.0kW, VOUT = 10V RL > 2.0kW RL = 10 94 94 200 11 Drift2 Test Conditions Min Typ 45 0.3 2.0 8.0 2.0 13 13.5 120 115 450 12.6 150 240 10 92 92 75 11 10 Max 150 1.3 10 Min 4207G Typ 85 0.7 1.6 12 3.0 18 13.5 106 100 400 12.6 150 240 15 15 Max 250 Units mV mV/C nA pA/C nA pA/C V dB dB V/mV V mW
2
RC4207
PRODUCT SPECIFICATION
Electrical Characteristics
(VS = 15V, and TA = +25C unless otherwise noted) 4207F Parameters Input Offset Voltage Long Term VOS Input Offset Current Input Bias Current Input Noise Voltage Input Noise Voltage Density 0.1 Hz to 10 Hz FO = 10 Hz FO = 100 Hz FO = 1000 Hz Input Noise Current Input Noise Current Density 0.1 Hz to 10 Hz FO = 10 Hz FO = 100 Hz FO = 1000 Hz Input Resistance (Diff. Mode) Input Resistance (Com. Mode) Input Voltage Range4 VCM = 11V VS = 4.0V to 16.5V RL 2kW, VOUT = 10V VOUT = 1.0V RL = 1KW, VS = 4.0V Output Voltage Swing RL 10kW RL 2kW RL 1kW Slew Rate Closed Loop Bandwidth Open Loop Output Resistance Power Consumption Crosstalk RL 2kW AVOL = +1.0 VOUT = 0, IOUT = 0 VS = 15V, RL = VS = 4.0V, RL = DC 126 11 100 100 400 200 12.5 12 11 0.1 Common Mode Rejection Ratio Power Supply Rejection Ratio Large Signal Voltage Gain
3
4207G Max 75 5 5 Min Typ 60 0.5 2 2 0.35 10.3 10 9.6 14 0.32 0.14 0.12 31 120 11 94 94 250 100 12.5 12 11 0.1 14 110 104 400 200 13 12.8 12 0.3 1.5 60 200 50 126 160 48 155 240 64 dB V/ms MHz W mW V
pA ----------Hz nV ----------Hz
Test Conditions Stability1
Min
Typ 30 0.2 0.5 0.5 0.35 10.3 10 9.6 14 0.32 0.14 0.12 60 200 14 126 110 600 400 13 12.8 12 0.3 1.5 60 150 35 155
Max 150 10 10
Units mV mV/Mo nA nA mVp-p
pAp-p
MW GW V dB dB V/mV
Notes: 1. Long Term Input Offset Voltage Stability refers to the averaged trend line of VOS vs. Time over extended periods after the first 30 days of operation. Excluding the initial hour of operation, changes in VOS during the first 30 operating days are typically 2.5 mV. 2. Guaranteed by design. 3. Input Offset Voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power. 4. The input protection diodes do not allow the device to be removed or inserted into the circuit without first removing power.
3
PRODUCT SPECIFICATION
RC4207
Typical Performance Characteristics
85 75 VS = 15V R = 1001/2 +120 +80 At V DIFF 0.5V I B 3nA -120 -80 -40 0 +40 VS = 15V T A = +25 C -20 -10 0 +10 +20 +80 +120 +30
65-0368
VOS ( V)
0 -40
25
65-0366
-80 -120 -30
0 -50 0 +50 +100
TA (C) Figure 1. Input Offset Voltage vs. Temperature
VDIFF (V) Figure 2. Input Bias Current vs. Differential Input Voltage
8 VS = 15V
2.5 2.0 V S = 15V
6
4
IOS (nA)
IB (nA)
1.5 1.0 0.5 0 -50 0 +50 +100
2
65-0369
0 -50 0 +50 +100
TA (C) Figure 3. Input Bias Current vs. Temperature
TA (C) Figure 4. Input Offset Current vs. Temperature
130 120
120 110 T A = +25 C
CMRR (dB)
100 90 80 70 60 1.0 10 100 1K 10K
65-0371
PSRR (dB)
110
100 90 80 70 60 50 0.1 1.0 10 100 1K
65-0372
100K
10K
F (Hz) Figure 5. CMRR vs. Frequency
F (Hz) Figure 6. PSRR vs. Frequency
4
65-0370
-IB (mA)
50
+IB (mA)
+40
RC4207
PRODUCT SPECIFICATION
Typical Performance Characteristics (continued)
1000 T A = +25 C 800 80 120 VS = 15V T A = +25 C
AVOL (V/mV)
600 400 200 0 0 5 10 15
AVOL (dB)
40
0
65-0374
65-0373
20
-40 0.1
1
10
100
1K
10K 100K 1M
10M
VS (V) Figure 7. Open Loop Gain vs. Supply Voltage
F (Hz) Figure 8. Open Loop Gain vs. Frequency
100 80 V S = 15V T A = +25 C
28 24
VOUTp-p (V)
AVCL (dB)
60 40 20 0 -20 0 100 1K 10K
20 16 12 8
V S = 15V T A = +25 C
65-0375A
4 0 1 10 100
100K
1M
10M
1000
F (Hz) Figure 9. Closed Loop Response for Various Gain Configurations
F (kHz) Figure 10. Maximum Undistorted Output vs. Frequency
20 VS = 15V T A = +25C V IN = 10mV +VOUT -VOUT 10
15
VOUT (V)
5
65-0377
0 0.1 1.0 10
RL (k1/2) Figure 11. Output Voltage vs. Load Resistance to Ground
65-0376
5
PRODUCT SPECIFICATION
RC4207
Typical Performance Characteristics (continued)
1000 T A = +25 C 100 60 1. VIN (Pin 3) = -10mV, VOUT = +15V 2. VIN (Pin 3) = +10mV, VOUT = -15V
50
PC (mW)
ISC (mA)
1 40 2
65-0379
10
65-0378A
30 VS = 15V T A = +25 C 20 0 1
1 0 20 40 50
2
3
4
+VS to -VS (V) Figure 12. Power Consumption vs. Total Supply Voltage
Time (Min) Figure 13. Output Short Circuit Current vs. Time
Typical Applications
R1 10K V1 R2 10K V2 R3 10K V3 3 4 R5 2.5K -15V R1 = R2 = R3 = R4
65-0381 65-0382
R4 10K
R1 Sensing Junction 2
R3
+15V 8 1/2 4207 1 VOUT
+15V 2 8 1/2 4207 1 VOUT
3 Reference Junction 4 R2 -15V R4 R1 R3 R2 R4
Figure 14. Adjustment-Free Precision Summing Amplifier
Figure 15. High Stability Thermocouple Amplifier
R3 10K R1 10K 2 +15V 8 1
R4 10K
R5 10K
VIN 10V
+15V D1 6 8 7 0 to +10V VOUT
1/2 4207 A 3 4 -15V
1/2 4207 B 5 4 D2 -15V
VA R2 10K
65-0383
Figure 16. Precision Absolute Value Circuit
6
RC4207
Output A (1) +VS (8) Output B (7)
Amplifier B
Amplifier A
R2B 5K Q31 Q29 Q33 Q34 Q35 Q32 R33 1.5K Q16 Q36 Q18 Q15 R17 20 Q56 R18 20 D3 Q19 Q17 Q23 Q11 Q4 Q3 R14 5K R13 5K Q10 Q9 Q13 Q12 Q55 Q38 Q39 R30 800 Q22 Q49 R31 375 R8 2K R9 50 R10 180 R26 1K Q45 Q44 Q43 Q40 Q42 Q41 Q50 Q37 .33 .67 Q51 Q54 +Input B (5) Q53 .75 .25 Q30 R32 100K R19 250 R20 188 R21 450
Schematic Diagram
Z1
Z2 Z4
R2C 2.4K
R1E 36.6K Q24 R1B 5K R2A 125K C1 30 pF Q25 Q26 Q6 Q14 R28 2K R4 750 Q7 R5 30K R29 360 Q5 Q8 C3 75 pF Q1 2X Q2 2X R3 750 C2B 20 R15 84 R27 1.2K R16 1.5K C2A 50 pF
Z3
R1D 15.7K
R1C 5.3K
R34 1.5K Q52 Q57 -Input B (6)
-Input A (2)
R24 200
D1
D2
+Input A (3)
R25 200
Q47 Q20 2X R11 16K R12 10K R22 32K R23 10K R6 200 R7 200
Q21
Q48
(4) -VS
65-2660
PRODUCT SPECIFICATION
7
PRODUCT SPECIFICATION
RC4207
Mechanical Dimensions - 8-Lead Plastic DIP Package
Symbol A A1 A2 B B1 C D D1 E E1 e eB L N Inches Min. -- .015 .115 .014 .045 .008 .348 .005 .300 .240 Max. .210 -- .195 .022 .070 .015 .430 -- .325 .280 Millimeters Min. -- .38 2.93 .36 1.14 .20 8.84 .13 7.62 6.10 Max. 5.33 -- 4.95 .56 1.78 .38 10.92 -- 8.26 7.11 Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E1" do not include mold flashing. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. Terminal numbers are for reference only. 4. "C" dimension does not include solder finish thickness. 5. Symbol "N" is the maximum number of terminals. 4 2
2
.100 BSC -- .430 .115 .160 8
2.54 BSC -- 10.92 2.92 4.06 8 5
D 4 1
E1
D1
5
8
E e A A1 L B1 B eB A2 C
8
PRODUCT SPECIFICATION
RC4207
Ordering Information
Product Number RC4207FN RC4207GN Temperature Range 0 to +70C 0 to +70C Screening Commercial Commercial Package 8 Pin Plastic DIP 8 Pin Plastic DIP
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS30004207 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC4227
Dual Precision Operational Amplifier
Features
* Very low noise Spectral noise density - 3.8 nV/OHz 1/F noise corner frequency - 2.7 Hz * Very low VOS drift - 0.3 mV/Mo; 0.3 mV/C * High gain - 500 V/mV * High output drive capability - 10V into 1K load * High slew rate - 2.7 V/mS * * * * * * * Wide gain bandwidth product - 8 MHz High common mode rejection ratio - 104 dB Low input offset voltage - 75 mV Low frequency noise - 0.08 mVp-p (0.1 Hz to 10 Hz) Low input offset current - 2.5 nA Industry standard pinout 8-Lead DIP
Description
The RC4227, a dual version of the OP-27, is designed for instrumentation grade signal conditioning where low noise (both spectral density and burst), wide bandwidth, and high slew rate are required along with low input offset voltage, low input offset temperature coefficient, and low input bias currents. These features are all available in a device which is internally compensated for excellent phase margin (70) in a unity gain configuration. Digital nulling techniques performed at wafer sort make it feasible to guarantee temperature stable input offset voltages as low as 75 mV max. Input bias current cancellation techniques are used to obtain 45 nA max. input bias currents. In addition to providing superior performance for audio frequency range applications, the RC4227 design uniquely addresses the needs of the instrumentation designer. Power supply rejection and common mode rejection are both in excess of 100 dB. A phase margin of 70 at unity gain guards against peaking (and ringing) in low gain feedback circuits. Stable operation can be obtained with capacitive loads up to 2000 pF1. The drift performance is, in fact, so good that the system designer must be cautioned that stray thermoelectric voltages generated by dissimilar metals at the contacts to the input terminals are enough to degrade its performance. For this reason it is also important to keep both input terminals at the same relative temperature. The performance of the RC4227 is achieved using precision amplifier design techniques coupled with a process that combines nitride transistors and capacitors with precision thin-film resistors. The die size savings of nitride capacitors and thin film resistors allow the RC4227 to be offered in an 8-pin mini-dip package and fit the industry standard dual op amp pinout.
Note: 1. By decoupling the load capacitance with a series resistor of 50W or more, load capacitances larger than 2000 pF can be accommodated.
Block Diagram
Output A -Input A +VS Output B
A
+Input A -VS
B
-Input B +Input B
65-3468-01
Rev. 1.0.0
PRODUCT SPECIFICATION
RC4227
Absolute Maximum Ratings
(beyond which the device may be damaged)1 Parameter Supply Voltage Input Voltage
2
Min
Typ
Max 18 18 0.7 658
Units V V V mW mW
Differential Input Voltage Internal Power Dissipation3 PDTA < 50C Output Short Circuit Duration Junction Temperature Storage Temperature Operating Temperature Lead Soldering Temperature (60 sec) For TA > 50C Derate at PDIP CerDIP 6.25 8.33 RM4227B RC4227F/G PDIP CerDIP -65 -55 0 PDIP CerDIP
468 833 Indefinite 125 175 150 125 70 300
C C C C mW/C
Notes: 1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded. 2. For supply voltages less than 18V, the absolute maximum input voltage is equal to the supply voltage. 3. Observe package thermal characteristics.
Operating Conditions
Parameter qJC qJA Thermal resistance Thermal resistance CerDIP PDIP CerDIP Min Typ 45 160 150 Max Units C/W C/W C/W
2
RC4227
PRODUCT SPECIFICATION
Electrical Characteristics
(VS = 15V, and TA +25C unless otherwise noted) 4227B/F Parameters Input Offset Voltage Long Term VOS Input Offset Current Input Bias Current Input Noise Voltage Input Noise Voltage Density 0.1 Hz to 10 Hz FO = 10 Hz FO = 30 Hz FO = 1000 Hz Input Noise Current Density FO = 10 Hz FO = 30 Hz FO = 1000 Hz Input Resistance (Diff. Mode) Input Resistance (Com. Mode) Input Voltage Range
2, 4 3
4227G Max 150 10 15 Min Typ 30 0.4 5 7.5 0.08 3.8 3.3 3.2 1.7 1.0 0.4 4.0 2.0 11 100 100 400 300 200 12 11 0.1 5.0 200 126 12.3 120 118 800 600 400 13.8 12 0.3 8.0 70 180 155 240 V/ms MHz W mW dB V MW GW V dB dB V/mV
pA ----------Hz
Test Conditions Stability1
Min
Typ 20 0.3 2.5 5 0.08 3.8 3.3 3.2 1.7 1.0 0.4 5.0 2.5
Max 180 15 25
Units mV mV/Mo nA nA mVp-p
nV ----------Hz
11 VCM = 11V VS = 4.0V to 16.5V RL 2kW, VOUT = 10V VOUT = 10V, RL = 1KW VOUT = 1.0V VS = 4.0V, RL 1.0kW 104 104 500 400 250 12 11 1.5 5.0 RL = 126
12.3 123 120 1000 800 500 13.8 12 2.7 8.0 70 160 155
Common Mode Rejection Ratio Power Supply Rejection Ratio Large Signal Voltage Gain
Output Voltage Swing Slew Rate2
RL 2.0kW RL 1kW RL 2.0kW
Gain Bandwidth Product Open Loop Output Resistance VOUT = 0, IOUT = 0 Power Consumption Crosstalk
Notes: 1. Long Term Input Offset Voltage Stability refers to the averaged trend line of VOS vs. Time over extended periods after the first 30 days of operation. Excluding the initial hour of operation, changes in VOS during the first 30 operating days are typically 2.5 mV. 2. Guaranteed by design. 3. Input Offset Voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power. 4. The input protection diodes do not allow the device to be removed or inserted into the circuit without first removing power.
3
PRODUCT SPECIFICATION
RC4227
Electrical Characteristics
(VS = 15V, -55C TA +125C unless otherwise noted) 4227B Parameters Input Offset Voltage1
2
Test Conditions
Min
Typ 120 0.3 10 15
Max 400 3.5 35 45
Units mV mV/C nA nA V dB dB V/mV V
Average Input Offset Voltage Drift Input Offset Current Input Bias Current Input Voltage Range Common Mode Rejection Ratio Power Supply Rejection Ratio Large Signal Voltage Gain Output Voltage Swing Power Consumption
10 VCM = 10V VS = 4.0V to 16.5V RL 2 kW, VOUT = 10V RL 2.0 kW RL = 100 100 350 11
11.5 119 114 650 13.2 200 280
mW
Notes: 1. Input offset voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power. 2. This parameter is tested on a sample basis only.
Electrical Characteristics
(VS = 15V, 0C TA +70C unless otherwise noted) 4227F Parameters Input Offset Voltage Average Input Offset Voltage Drift2 Input Offset Current Input Bias Current Input Voltage Range Common Mode Rejection Ratio Power Supply Rejection Ratio Large Signal Voltage Gain Output Voltage Swing Power Consumption VCM = 10V VS = 4.0V to 16.5V RL > 2.0kW, VOUT = 10V RL > 2.0kW RL = 10 100 100 350 11 Test Conditions Min Typ 45 0.3 8 10 11.8 121 116 700 13.5 180 240 Max 150 1.3 15 30 10 92 92 250 11 200 Min 4227G Typ 85 0.4 10 15 11.8 118 114 500 13.5 280 35 45 Max 250 Units mV mV/C nA nA V dB dB V/mV V mW
4
RC4227
PRODUCT SPECIFICATION
Typical Performance Characteristics
0.1 F 100K 101/2 2 1/2 4227 D.U.T 1 2K 3 OP-07 4.7 F 2 100K 2.2 F 110K 6 4.3K 22 F Scope x1 RIN = 1M
3
24.3K 0.1 F Notes: 1. Peak-to-peak noise measured in a 10-second interval. 2. The device under test should be warmed up for 3 minutes and shielded from air currents. 3. Voltage gain = 50,000.
65-3469-01
Figure 1. 0.1 Hz to 10 Hz Noise Test Circuit (1/2 Shown)
100 90 80
130 110 90
AV (dB)
Test Time of 10 Sec Further Limits Low Frequency (<0.1 Hz) Gain
65-0004
AV (dB)
70 60 50 40 30 0.01 0.1 1.0 10
70 50 30 10 -10 1 10 100 1K 10K 100K 1M
65-0005
10M 100M
100
F (Hz) Figure 2. 0.1Hz to 10Hz Noise Gain vs. Frequency
F (Hz) Figure 3. Open Loop Gain vs. Frequency
25 20 16 AV
FM (Deg)
f
80 VS = 15V T A = +25 C FM = 70 100 120
70 60
10 fM GBW VS = +15V 9
10 5 0 -5
140 160 180 200 220
50 4
8
SR (V/mS)
3 2 -75
7 SL 6 -50 -25 0 25 50 75 100 125
-10 1 10 100
F (MHz)
65-0006
TA (C)
65-0007
Figure 4. Gain, Phase Shift vs. Frequency
Figure 5. Slew Rate, Gain Bandwidth Product, Phase Margin vs. Temperature
GBW (MHz)
AV (dB)
FM (Deg)
5
PRODUCT SPECIFICATION
RC4227
Typical Performance Characteristics (continued)
10
T A = +125 C
18 16 14 12 VOUT (V) 10 8 6 4
65-0008A
8 ISY (mA)
+VOUT
6
T A = +25 C T A = -55 C
-VOUT VS = 15V T A = +25 C
65-0009A
4
2 0 -2 0 1.0 RL (k W )
2 5 15 25 +VS to -VS (V) 35
45
10
Figure 6. Supply Voltage vs. Total Supply Voltage
Figure 7. Maximum Output Swing vs. Load Resistance
60
2.5 T A = +25 C 2.0 I SC (+)
50
ISC (mA)
40
AVOL (V/ V)
V S = 15V T A = +25 C
RL = 2 k W 1.5 RL = 1 k W
30
I SC (-)
1.0 0.5
10 0
0 0 5 10 15 20
1
2
3
4
5
25
Time (Min)
VS (V)
Figure 8. Short Circuit vs. Time
Figure 9. Open-Loop Gain vs. Total Supply Voltage
28 24 20 VOUT P-P (V) 16 12 8
65-0012
16
T A = -55 C V S = 15V T A = +25 C
12 8 VCM (V) 4 0 -4 -8
TA = +25 C T A = +125 C
TA = -55 C T A = +25 C
0 1K 10K 100K F (Hz) 1M
10M
-16 0 5 10 VS (V) 15
20
Figure 10. Maximum Undistorted Output vs. Frequency
Figure 11. Common-Mode Input Range vs. Supply Voltage
6
65-0013
4
-12
T A = +125 C
65-0011A
65-0010
20
RC4227
PRODUCT SPECIFICATION
Typical Performance Characteristics (continued)
10 V S = 15V T A = +25 C 5 100 741
eN (nV/ Hz)
eN (nV/ Hz)
1/F Corner 10
4277
1/F Corner
Low Noise Audio Op Amp
1/F Corner = 2.7Hz
65-0014
Instrumentation Range to DC Audio Range to 20 kHz
1 1 10 100
1 1 10 100
1000
1000
F (Hz) Figure 12. Input Noise Voltage Density vs. Frequency
F (Hz) Figure 13. Op Amp Compensation Input Noise Voltage Density vs. Frequency
10.0
100W 500K
10K
IN (pA/ Hz)
500K
e no
1.0
in =
] e no 2 - (130 nV) 2 ] 1/2 1M x 100
0.1 10
100 F (Hz)
1K
10K
Figure 14. Input Noise Current Density vs Frequency
65-0016
1/F Corner 140 Hz
7
65-0015
1/F Corner 2.7 Hz
8
Output A (1) +VS (8) Output B (7)
Amplifier B
PRODUCT SPECIFICATION
Amplifier A
R2B 1K Q31 Q29 Q33 Q34 Q35 Q32 R33 1.5K Q16 Q36 Q18 Q15 R17 20 Q56 R18 20 D3 Q19 Q17 Q23 Q11 Q4 Q3 R14 5K R13 5K Q10 Q9 Q13 D12 Q55 Q38 Q39 R30 800 Q22 Q49 R31 375 R8 2K R9 50 R10 180 R26 1K Q45 Q44 Q43 Q40 Q42 Q41 Q50 Q37 .33 .67 Q51 Q54 +Input B (5) R34 1.5K Q52 Q57 -Input B (6) Q53 .75 .25 Q30 R32 100K R19 250 R20 188 R21 450
Z1
Z2
R2C 1.25K
Z4
R1E 12.1K Q24 R2A 15.5K C1 30 pF Q25 Q26 Q6 R27 1.2K R3 750 R4 750 Q7 R5 30K R29 360 Q8 C3 75 pF C2B 20 R15 84 Q14 C2A 50 pF R16 1.5K
Z3
R1D 5.5K
R1C 5.3K
R1B 1K
Simplified Schematic Diagram
R1A 15.5K
R28 2K Q5 Q2 2X
-Input A (2)
Q1 2X
D1
D2
+Input A (3)
Q47 Q20 2X R12 10K R22 32K R23 10K R6 200 R7 200
Q21
Q48
R11 16K
(4) -VS
65-2662
RC4227
RC4227
PRODUCT SPECIFICATION
Mechanical Dimensions
8-Lead Ceramic DIP Package
Inches Min. A b1 b2 c1 D E e eA L Q s1 a Max. Millimeters Min. Max. 8 2, 8 8 4 4 5, 9 7 3 6 Notes: Notes 1. Index area: a notch or a pin one identification mark shall be located adjacent to pin one. The manufacturer's identification shall not be used as pin one identification mark. 2. The minimum limit for dimension "b2" may be .023 (.58mm) for leads number 1, 4, 5 and 8 only. 3. Dimension "Q" shall be measured from the seating plane to the base plane. 4. This dimension allows for off-center lid, meniscus and glass overrun. 5. The basic pin spacing is .100 (2.54mm) between centerlines. Each pin centerline shall be located within .010 (.25mm) of its exact longitudinal position relative to pins 1 and 8. 6. Applies to all four corners (leads number 1, 4, 5, and 8). 7. "eA" shall be measured at the center of the lead bends or at the centerline of the leads when "a" is 90. 8. All leads - Increase maximum limit by .003 (.08mm) measured at the center of the flat, when lead finish applied. 9. Six spaces. D 4 1 Note 1 E
Symbol
-- .200 .014 .023 .045 .065 .008 .015 -- .405 .220 .310 .100 BSC .300 BSC .125 .200 .015 .060 .005 -- 90 105
-- 5.08 .36 .58 1.14 1.65 .20 .38 -- 10.29 5.59 7.87 2.54 BSC 7.62 BSC 3.18 5.08 .38 1.52 .13 -- 90 105
5 s1
8
e
eA
A Q L b2 b1 a c1
9
RC4227
PRODUCT SPECIFICATION
Mechanical Dimensions (continued)
8-Lead Plastic DIP Package
Inches Min. A A1 A2 B B1 C D D1 E E1 e eB L N -- .015 .115 .014 .045 .008 .348 .005 .300 .240 Max. .210 -- .195 .022 .070 .015 .430 -- .325 .280 Millimeters Min. -- .38 2.93 .36 1.14 .20 8.84 .13 7.62 6.10 Max. 5.33 -- 4.95 .56 1.78 .38 10.92 -- 8.26 7.11 Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E1" do not include mold flashing. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. Terminal numbers are for reference only. 4. "C" dimension does not include solder finish thickness. 5. Symbol "N" is the maximum number of terminals. 4 2
Symbol
2
.100 BSC -- .430 .115 .160 8
2.54 BSC -- 10.92 2.92 4.06 8 5
D 4 1
E1
D1
5
8
E e A A1 L B1 B eB A2 C
10
PRODUCT SPECIFICATION
RC4227
Ordering Information
Product Number RC4227FN RC4227GN RM4227BD RM4227BD/8831 Temperature Range 0 to +70C 0 to +70C -55C to +125C -55C to +125C Military Screening Commercial Commercial Package 8 Pin Plastic DIP 8 Pin Plastic DIP 8 Pin Ceramic DIP 8 Pin Ceramic DIP
Note: 1. /883 suffix denotes MIl-STD-883, Par. 1.2.1 compliant device.
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS30004227 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC4277
Dual Precision Operational Amplifier
Features
* * * * * High DC precision Very low VOS - 30 mV Very low VOS drift - 0.3 mV/C High open-loop gain - 5000 V/mV High CMRR - 120 dB * * * * High PSRR - 120 db Low noise - 0.35 mVp-p (0.1 Hz to 10 Hz) Low input bias current - 3.0 nA Low power consumption - 140 mW
Description
The RC4277 provides the highest precision available in a dual bipolar operational amplifier. A monolithic dual version of the RC4077, the RC4277 is designed to replace OP-07 and OP-77 type amplifiers in applications requiring high PC board layout density. The RC4277 has a well-balanced, mutually supporting set of input specifications. Low VOS, low IB, high open-loop gain, and excellent matching characteristics combine to raise the performance level of many instrumentation, low-level signal conditioning, and data conversion applications. PSRR, CMRR, VOS drift, and noise levels also support high precision operation. The high performance of the RC4277 results from two innovative and unconventional manufacturing steps, plus careful circuit layout and design. The key steps are SiCr thin-film resistor deposition and post-package trimming of the input offset voltage characteristic. The low 75 mV max VOS specification is maintained in high-volume production by way of the post-package trim procedure, where internal resistors are trimmed through the device input leads at the final test operation. Devices retain this low offset through the stability and accuracy of the trimmed thin-film resistors. The RC4277 is available in 8-lead plastic and ceramic DIPs.
Block Diagram
Output A -Input A +VS Output B
A
+Input A -VS
B
-Input B +Input B
65-3468-01
Rev. 1.0.0
PRODUCT SPECIFICATION
RC4277
Absolute Maximum Ratings
(beyond which the device may be damaged)1 Parameter Supply Voltage Input Voltage2 Dissipation3 PDIP CerDIP Output Short Circuit Duration Junction Temperature Storage Temperature Operating Temperature Lead Soldering Temperature (60 sec) For TA > 50C Derate at PDIP CerDIP 6.25 8.33 RV4277 RC4277 PDIP CerDIP -65 -25 0 Differential Input Voltage Internal Power PDTA < 50C Min Typ Max 22 22 30 500 468 833 Indefinite 125 175 150 85 70 300 C mW/C C C C Units V V V mW mW
Notes: 1. Functional operation under any of these conditions is NOT implied. 2. For supply voltages less than 22V, the absolute maximum input voltage is equal to the supply voltage. 3. Observe package thermal characteristics.
Operating Conditions
Parameter qJC qJA Thermal resistance Thermal resistance CerDIP PDIP CerDIP Min Typ 45 160 150 Max Units C/W C/W C/W
2
RC4277
PRODUCT SPECIFICATION
Electrical Characteristics
(VS = 15V, and TA = +25C unless otherwise noted) Parameters Input Offset Voltage Long Term VOS
3
Test Conditions
Min
Typ 30 25 0.3 0.5 0.5
Max 75 150 5.0 5.0
Units mV mV mV/Mo nA nA mVp-p
nV ----------Hz
Input Voltage Offset Match Stability1 Input Offset Current Input Bias Current Input Noise Voltage Input Noise Voltage Density 0.1 Hz to 10 Hz FO = 10 Hz FO = 100 Hz FO = 1000 Hz Input Noise Current Density FO = 10 Hz FO = 100 Hz FO = 1000 Hz Input Voltage Range2, 4 VCM = 11V VS = 4V to 16.5V RL 2kW, VOUT = 10V RL 10kW RL 2kW RL 1kW Slew Rate Closed Loop Bandwidth Open Loop Output Resistance Power Consumption Crosstalk RL 2kW AVCL = +1.0 VOUT = 0, IOUT = 0 VS = 15V, RL = 126 11 110 110 1300 12.5 12 11 0.1 Common Mode Rejection Ratio Power Supply Rejection Ratio Large Signal Voltage Gain Output Voltage Swing
0.35 10.3 10 9.6 0.32 0.14 0.12 14 132 132 350 13 12.8 12 0.3 0.8 60 60 155 100
pA ----------Hz
V dB dB V/mV V
V/ms MHz W mW dB
Notes: 1. Long Term Input Offset Voltage Stability refers to the averaged trend line of VOS vs. Time over extended periods after the first 30 days of operation. Excluding the initial hour of operation, changes in VOS during the first 30 operating days are typically 2.5 mV. 2. Guaranteed by design. 3. Input Offset Voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power. 4. The input protection diodes do not allow the device to be removed or inserted into the circuit without first removing power.
3
PRODUCT SPECIFICATION
RC4277
Electrical Characteristics
(VS = 15V, 0C TA +70C unless otherwise noted) Parameters Input Offset Voltage Average Input Offset Voltage Drift Input Offset Current Input Bias Current Input Voltage Range Common Mode Rejection Ratio Power Supply Rejection Ratio Large Signal Voltage Gain Output Voltage Swing Power Consumption VCM = 10V VS = 4V to 16.5V RL > 2kW, VOUT = 10V RL > 2kW RL = 10 110 110 1300 11
2
Test Conditions 0C TA +70C -25C TA +85C
Min
Typ 50 50 0.3 1.5 1.5 13.5 124 124 3000 12.6 70
Max 120 135 1.0 5.0 5.0
Units mV mV/C nA nA V dB dB V/mV V
120
mW
Notes: 1. Input offset voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power. 2. This parameter is tested on a sample basis only.
Typical Applications
R1 10K V1 R2 10K V2 R3 10K V3 R6 2.5K 2 3 4 +15V 8 1/2 4277 1 VOUT Reference Junction R2 -15V R4
65-4232 65-4233
R4 10K Sensing Junction
R1
R3
+15V 2 3 4 8 1/2 4277 1 VOUT
-15V
R1 R3
=
R2 R4
Figure 1. Adjustment-Free Precision Summing Amplifier
Figure 2. High Stability Thermocouple Amplifier
4
RC4277
PRODUCT SPECIFICATION
Typical Applications (continued)
R3 10K R4 10K R5 10K
VIN 10V
R1 10K 2 3
+15V D1 8 1/2 4277 A 4 1 5 6
+15V 8 1/2 4277 B 4 7 VOUT 0V to +10V
-15V VA R2 10K
D2
-15V
65-4234
Figure 3. Precision Absolute Value Circuit
R2 5K
R5 50K
1/2 4277 R1 50K 5K
R3 5K
1/2 4277
V OUT
R4 5K
5K R1 = R5 = 10 R2 R2 = R3 R4 = R5 (-) AV = R4 R5
65-4427
(+)
VIN
Note: This circuit can tolerate input voltages that exceed the 4277's supply voltage rating as long as the slew rate do not exceed the op amp's slew rate.
Figure 4. High Voltage Differential Amplifier
R1 R/n
R
R2 VIN R/(n-1) 1/2 4277 VOUT VOUT VIN xR3 VOUT = 2(2X-1)
n
0.5
1
R3 POT X Position
-n
65-4428
65-3062
Figure 5. Polarity Changing Gain Controlled Amplifier
Figure 6. Gain Controlled Amplifier Transfer Function
5
PRODUCT SPECIFICATION
RC4277
Typical Applications (continued)
R1 10K (+) R3 10K
1/2 4277 VIN +VS R2 10K (-) R4 10K R5 10K
1/2 4277 IOUT
R3 = R4 R1 = R2 R3 IOUT = -VIN ( R1R5 ) Input Voltage Range = R1 (+VS - 1.5V) R3
-VS
RLOAD
65-4429
Figure 7. Differential Input Current Source
RG
R2
R1 +15V 1/2 4277 (-) VIN (+)
R1
R2
1/2 4277
VOUT
RG = Optional Gain Adjust AV = - ( R2 + 1) R1 -15V
65-4430
Figure 8. High Input Impedance Subtractor
6
RC4277
PRODUCT SPECIFICATION
Typical Applications (continued)
R1A V1 R2A
1/2 4277
VOUT RG R3
R1B V2
R2B
VO =
R2 R1
RG (V2 - V1) R3
1/2 4277
Note: This circuit provides a linear relationship between the RG potentiometer setting and circuit gain.
65-4431
Figure 9. Difference Amplifier with Linear Gain Control
1/2 4277 R1 V1 RG V2 R2 1/2 4277 20K 20K
R3A
R4A
1/2 4277
VOUT
R3B
R4B
1/2 4277
Note: The driven shield will reduce the effects of cable capacitance on ac CMRR.
65-4432
Figure 10. Three Op Amp Instrumentation Amplifier with Driven Shield
7
8
Z2 Z6 Z5 Q10 2X Q42 1X R2F 30K Z4 AL 100 pF N+ C1 Q19 R2C 3.5K R16 30 Q5 1X Q13 4X Q18 Q23 R2H 2.2K R2E 1.7K Z3 Q21 2X R1C 5K R2G 5K R1A 75K R2A 75K Q9 C2A 50 pF Q6 Q33 Q34 R28 3.3K C3 33 pF Q7 Q8 R18 1.5K Q39 Q40 Q11 Q20 Q22 Q12 Q25 Q26 VPNP Q102 4X Q103 Q35 Q29 Q36 Q30 Q32 Q38 C2B 25 pF R17 30 Q101 Q43 2X R101 500K R2J 21.2K Output A (1) B (7) Q31 Q27 Q28 Q2 2X Q1 2X R19 700 Q41 Q3 R4 10K R3 10K Q4 Q15 4X R9A 3K R9B 3K R12A 5.75K Q14 R14 67 R13 230 Q16 Q17 R6 2.5K R8A 10K R8B 10K R12B 875 Q104 R12C 1K R102 140K
65-4235
+VS (8)
PRODUCT SPECIFICATION
Schematic Diagram
Z1
R1E 900
R1H 2.2K
Z2
R1C 7.2K
R1F 30K
Z1
R1J 20K
Q37
D2
R21 500
+Input A (3) B (5)
D1
-Input A (2) B (6)
R22 500
-VS (4)
One Section of Two
RC4277
RC4277
PRODUCT SPECIFICATION
RM4277 SPICE Macro Model
This circuit models AC and DC characteristics including slew rate, bandwidth, VOS, IB, IOS, CMRR, output voltage range, and gain. The circuit produces typical values for these parameters.
(5)
F BIAS2 VBIAS 0.5 (1) R B1 500 D1 DP (27) R B2 500 D2 DP (22) (28)
R C1 8.8K (11)
R C2 8.8K C1 8 pF
FBIAS1 V BIAS 0.5 (12)
DP DP
VC 1.6 (25) DP DP (8) R O1 80 R2 100K (4)
D3 DP
(6)
C2 20 PF
(7)
V LIM 0V
(2)
D4 DP Q2 QP (3) R E2 4.5K (10) I EE 7 mA R EE 16 MEG Q1 QP (14) R E1 4.5K C EE 2 pF (21)
G CM 1E - 12
GA 1.1E - 4
(9) VB 0V E GROUND 0V
FB
R O2 30
(0)
(40)
DE DP
H LIM V LIM 1.0
V LN 25V D LN DP
V LP 25V D LP DP
(26) VE 1.8
V BIAS 0V Q3 QP
RP 180K
IP 990 mA
(30) (3)
65-4447
9
PRODUCT SPECIFICATION
RC4277
Mechanical Dimensions
8-Lead Ceramic DIP Package
Inches Min. A b1 b2 c1 D E e eA L Q s1 a Max. Millimeters Min. Max. 8 2, 8 8 4 4 5, 9 7 3 6 Notes: Notes 1. Index area: a notch or a pin one identification mark shall be located adjacent to pin one. The manufacturer's identification shall not be used as pin one identification mark. 2. The minimum limit for dimension "b2" may be .023 (.58mm) for leads number 1, 4, 5 and 8 only. 3. Dimension "Q" shall be measured from the seating plane to the base plane. 4. This dimension allows for off-center lid, meniscus and glass overrun. 5. The basic pin spacing is .100 (2.54mm) between centerlines. Each pin centerline shall be located within .010 (.25mm) of its exact longitudinal position relative to pins 1 and 8. 6. Applies to all four corners (leads number 1, 4, 5, and 8). 7. "eA" shall be measured at the center of the lead bends or at the centerline of the leads when "a" is 90. 8. All leads - Increase maximum limit by .003 (.08mm) measured at the center of the flat, when lead finish applied. 9. Six spaces. D 4 1 Note 1 E
Symbol
-- .200 .014 .023 .045 .065 .008 .015 -- .405 .220 .310 .100 BSC .300 BSC .125 .200 .015 .060 .005 -- 90 105
-- 5.08 .36 .58 1.14 1.65 .20 .38 -- 10.29 5.59 7.87 2.54 BSC 7.62 BSC 3.18 5.08 .38 1.52 .13 -- 90 105
5 s1
8
e
eA
A Q L b2 b1 a c1
10
RC4277
PRODUCT SPECIFICATION
Mechanical Dimensions (continued)
8-Lead Plastic DIP Package
Inches Min. A A1 A2 B B1 C D D1 E E1 e eB L N -- .015 .115 .014 .045 .008 .348 .005 .300 .240 Max. .210 -- .195 .022 .070 .015 .430 -- .325 .280 Millimeters Min. -- .38 2.93 .36 1.14 .20 8.84 .13 7.62 6.10 Max. 5.33 -- 4.95 .56 1.78 .38 10.92 -- 8.26 7.11 Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E1" do not include mold flashing. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. Terminal numbers are for reference only. 4. "C" dimension does not include solder finish thickness. 5. Symbol "N" is the maximum number of terminals. 4 2
Symbol
2
.100 BSC -- .430 .115 .160 8
2.54 BSC -- 10.92 2.92 4.06 8 5
D 4 1
E1
D1
5
8
E e A A1 L B1 B eB A2 C
11
PRODUCT SPECIFICATION
RC4277
Ordering Information
Product Number RC4277FN RV4277FD Temperature Range 0C to +70C 0C to 70C Screening Commercial Commercial Package 8 Pin Plastic DIP 8 Pin Ceramic DIP
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS30004277 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC431A
Low-Voltage Adjustable Precision Shunt Regulator
Features
* * * * * * Low voltage operation to 1.24V 1% reference voltage tolerance Output voltage adjustable from Vref to 12V Low 80mA operational cathode current 0.25W typical output impedance TO-92 and SOT23-5 packages
Description
The RC431A is a low-voltage 3-terminal adjustable precision voltage reference regulator. It has an excellent thermal stability over the standard commercial temperature range. The output voltage can be set to any value between Vref (1.24V) and 12V using two external resistors. The RC431A operates from a lower voltage (1.24V) than the traditional shunt regulator references which operate from 2.5V. When used with an optocoupler, the RC431A will be an ideal voltage reference in an isolated feedback circuit for use in switched-mode power supplies and modular DC-DC converters. The RC431A has a low output impedance of active output circuitry offering a very sharp turn-on characteristic. The RC431A will be an excellent replacement for lowvoltage zener diodes in many applications such as on-board regulation and adjustable power supplies.
Applications
* Voltage reference for discrete power circuits
Symbol
REF Anode Cathode
65-431A-01
Block Diagram
CATHODE
REF
+ _
Vref = 1.24V
65-431A-02
ANODE
Rev. 1.0.3
RC431A
PRODUCT SPECIFICATION
Pin Assignments
SOT-23 PACKAGE (TOP VIEW)
NC NC CATHODE 1 2 3 4 REF 5 ANODE
TO-92 PACKAGE (TOP VIEW)
CATHODE ANODE REF
65-431A-03
NC = No internal connection
Equivalent Schematic
CATHODE
REF A
ANODE
65-431A-04
Absolute Maximum Ratings
Ratings are over full operating free-air temperature range unless otherwise noted. Cathode voltage, VKA Continuous cathode current IK Reference current, Iref Power dissipation Storage temperature range 13.2V -20mA to 20mA -0.05mA to 3mA See Dissipation Rating Table -65 to 150C
Notes: 1. Functional operation under these conditions is not implied. Permanent damage may occur if the device is subjected to conditions outside these ratings.
Recommended Operating Conditions
Parameter Cathode voltage, VKA Cathode current, IK Operating temperature range in free-air, TA Min. VREF 0.1 0 Max. 12 15 70 Units V mA C
2
PRODUCT SPECIFICATION
RC431A
Dissipation Rating Table
Package TO-92 SOT23-5 Power Rating TA 25C 775mW 150mW Derating Factor TA 25C 6.2mW/OC 1.2mW/oC Power Rating TA = 70C 496mW 96mW
Electrical Specifications
TA = 25C (unless otherwise noted), at free-air Symbol Vref Parameters Reference Voltage Conditions VKA = Vref, TA = 25C IK = 10mA, TA = 0 to 70C Vref (dev) DVref DVKA Iref Vref deviation over full temperature range (see note 2) Ratio of Vref change in cathode voltage change Reference terminal current VKA = Vref, IK = 10mA, See note 2 and Figure 1. IK = 10mA, DVKA = Vref to 6V. See figure 2. IK = 10mA, R1 = 10KW, R2 = See figure 2. IK = 10mA, R1 = 10KW, R2 = See note 1 & figure 2. VKA = Vref See figure 1. VKA = 6V, Vref = 0 See figure 3. VKA = Vref, f 1KHz IK = 0.1mA to 15mA, See figure 1. Min. 1.228 1.221 4 -1.5 Typ. 1.24 Max. 1.252 1.259 12 -2.7 mV mV V mA Units V
0.15
0.5
Iref(dev)
Iref deviation over full temperature range (see note 2) Minimum cathode current for regulation Off-state cathode current Dynamic impedance (see note 3)
0.05
0.3
mA
IK(min) Ioff |ZKA|
55 0.001 0.25
80 0.1 0.4
mA mA W
Notes: 1. Functional operation under these conditions is not implied. Permanent damage may occur if the device is subjected to conditions outside these ratings. 2. Full temperature range is 0C to 70C. 3. The deviation parameters Vref(dev) and Iref(dev) are defined as the differences between the maximum and minimum values obtained over the rated temperature range. The average full-range temperature coefficient of the reference input voltage, Vref, is defined as:
V ref
{ V ref ( dev ) V ref a T A = 25Cn } 10 a ppm/Cn = --------------------------------------------------------------------------------------------DT A
6
where DTA is the rated operating free-air temperature range of the device. Vref can be positive or negative depending on whether minimum Vref or maximum Vref, respectively, occurs at the lower temperature. 4. The dynamic impedance is defined as: iZKAi= DVKA/ DIK When the device is operating with two external resistors (see Figure 2), the total dynamic impedance of the circuit is given by:
R1 DV Z KA = ------- Z KA ae 1 + ------o e R 2o DI
3
RC431A
PRODUCT SPECIFICATION
Parameter Measurement Information
V IN VIN IK VOUT R1 Iref IK V OUT
R2 V ref
65-431A-05
V ref
65-431A-06
Figure 1. Test Circuit for VKA = VREF, VOUT = VKA = VREF
Figure 2. Test Circuit for VKA > VREF, VOUT = VKA = VREF x (1+R1/R2) + IREF x R1
V IN
VOUT I OFF
65-431A-07
Figure 3. Test Circuit for IOFF
Iref-Reference Input Current (nA)
Vref-Reference Voltage (V)
1.250 1.246 1.242 1.238
lk = 10 mA
lk = 10 mA, R1 = 10 k1/2, R2 = infinite 250 200 150 100 50 -40
1.230 -40 -20
0
20
40
60
80
100
-20
0
20
40
60
80
100
Tj--Junction Temp. (C)
Tj--Junction Temp. (C)
Figure 4. Reference Voltage vs. Junction Temp.
Figure 5. Reference Input Current vs. Junction Temp. VKA = Vref, T = 25C 150 120 90 60 30 0 -30 -60 -90 -120 -150 -1 -0.5 0
15 lk-Cathode Current (mA) 10 5 0 -5 -10 -15
VKA = Vref, T = 25C
lk-Cathode Current (A)
-1
-0.5
0
0.5
1
1.5
0.5
1
1.5
VKA-Cathode Voltage (V)
VKA-Cathode Voltage (V) Figure 7. Cathode Current vs. Cathode Voltage
Figure 6. Cathode Current vs. Cathode Voltage
4
PRODUCT SPECIFICATION
RC431A
Ioff-Off State Cathode Current (nA)
Del Vref / Del Vka (mV/V)
40.0 30.0 20.0 10.0
VKA = 6V, Vref = 0V
1.4 1.2 1.0 0.8 0.6 0.4 0.2
lk = 10 mA, Del VKA = Vref to 6V
0.0 -40
-20
0
20
40
60
80
100
0.0 -40
-20
0
20
40
60
80
100
Tj--Junction Temperature (C)
Tj--Junction Temperature (C)
Figure 8. Off-State Cathode Current vs. Junction Temperature
100 |Zka|-Reference Impedance (1/2)
Figure 9. Ratio of Delta Reference Voltage to Delta Cathode Voltage vs. Junction Temperature
10
1
1001/2 OUTPUT IK 1001/2 +
0.1
0.01 1000
10000
100000 f-Frequency (Hz)
1000000
10000000
GND
Figure 10. Reference Impedance vs. Frequency
Figure 11. Test Circuit for Reference Impedance
5
RC431A
PRODUCT SPECIFICATION
Mechanical Dimensions
TO-92 Package
Inches Min. A b c oD E e e1 L S a .170 .015 .014 .175 .125 .095 .045 .500 .080 4 Max. .210 .021 .020 .205 .165 .105 .055 -- .115 6 Millimeters Min. 4.32 .38 .36 4.45 3.18 2.41 1.14 12.70 2.03 4 Max. 5.33 .53 .51 5.21 4.19 2.67 1.40 -- 2.92 6 Notes: Notes 1. Package outline exclusive of any mold flashes dimension. 2. Package outline exclusive of burr dimension.
Symbol
S c
E-PIN C 1/16 A b e
a
E
e1
oD
L
6
PRODUCT SPECIFICATION
RC431A
Mechanical Dimensions (continued)
SOT23-5 Package
Symbol A A1 B c D E e e1 H L a Inches Min. .170 .014 .008 .003 .106 .059 Max. .195 .020 .020 .010 .122 .071 Millimeters Min. .90 .00 .20 .08 2.70 1.50 Max. 1.45 .15 .50 .25 3.10 1.80 Notes: Notes 1. Package outline exclusive of mold flash & metal burr. 2. Package outline exclusive of solder plating. 3. EIAJ Ref Number SC-74A.
.037 BSC .075 BSC .087 .126 .004 .024 0 10
.95 BSC 1.90 BSC 2.20 3.20 .10 .60 0 10
B
e L
E
H
e1 D
c
A
A1
7
RC431A
PRODUCT SPECIFICATION
Ordering Information
Product Number RC431AM RC431AT Package SOT23-5 TO-92
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS3000431A O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC4391
Inverting and Step-Down Switching Regulator
Features
* Versatile -- Inverting function (+ to -) Step-down function Adjustable output voltage Regulates supply changes * Micropower -- Low quiescent current -- 170 mA Wide supply range -- 4V to 30V * High performance -- High switch current -- 375 mA High efficiency -- 70% typically * Low battery detection capability * 8-lead mini-DIP or S.O. package
Description
Fairchild Semiconductor's RC4391 is a monolithic switch mode power supply controller for micropower circuits. The RC4391 integrates all the active functions needed for low power switching supplies, including oscillator, switch, reference and logic, into a small package. Also, the quiescent supply current drawn by the RC4391 is extremely low; this combination of low supply current, function, and small package make it adaptable to a variety of miniature power supply applications. The RC4391 complements another Fairchild Semiconductor switching regulator IC, the RC4190. The RC4190 is dedicated to step-up (VOUT > VIN) applications, while the RC4391 was designed for inverting (VOUT = -VIN) and step-down (VOUT < VIN) applications. Between the two devices the ability to create all three basic switching regulator configurations is assured. Refer to the RC4190 data sheet for information on step-up applications. The functions provided are:
Block Diagram
RC4391 LBR C2 Q2 C1 VFB
* * * * * *
Squarewave oscillator (adjustable externally) Bandgap voltage reference High current PNP switch transistor Feedback comparator Logic for gating the comparator Circuitry for detecting a discharged battery condition (in battery powered systems)
VREF LBD +1.25V REF/Bias OSC Q1 Gnd CX VREF +VS
Few external components are required to build a complete DC-to-DC converter: * * * * * Inductor Low value capacitor to set the oscillator frequency Electrolytic filter capacitor Steering diode Two resistors
CX
65-3471-01
Rev. 1.1.1
PRODUCT SPECIFICATION
RC4391
Pin Assignments
LBR LBD CX GND
1 2 3 4 8 7 6 5
65-3471-02
Pin Descriptions
VFB VREF +VS LX
Pin Number 1 2 3 4 5 6 7 8
Pin Function Description Low Battery Resistor (LBR) Low Battery Detector (LBD) Timing Capacitor (CX) Ground External Inductor (LX) +Supply Voltage (+VS) +1.25V Reference Voltage (VREF) Feedback Voltage (VFB)
Absolute Maximum Ratings
Parameter Internal Power Dissipation Supply Voltage1 Operating Temperature (Pin 6 to Pin 4 or Pin 6 to Pin 5) RC4391 RV4391 RM4391 Storage Temperature Junction Temperature Switch Current (IMAX) PD TA <50C PDIP, SOIC CerDIP Peak PDIP CerDIP SOIC Lead Soldering Temperature (10 seconds) 0 -25 -55 -65 Conditions Min Typ Max 500 +30 70 85 125 150 125 175 375 468 833 300 300 Unit mW V C C C C C C mA mW mW mW C
Note: 1. The maximum allowable supply voltage (+VS) in inverting applications will be reduced by the value of the negative output voltage, unless an external power transistor is used in place of Q1.
Thermal Characteristics
8-Lead Plastic DIP Therm. Res qJC Therm. Res. qJA For TA >50C Derate at -- 160C/W 6.25 mW/C 8-Lead Ceramic DIP 45C/W 150C/W 8.33 mW/C Small Outline SO-8 -- 240C/W 4.17 mW/C
2
RC4391
PRODUCT SPECIFICATION
Electrical Characteristics
(VS = +6.0V, over the full operating temperature range unless otherwise noted) Symbol +VS ISY VREF VOUT LI1 Parameters Supply Voltage Supply Current Reference Voltage Output Voltage Line Regulation VOUT nom = -5.0V VOUT nom = -15V VOUT nom = -5.0V, CX = 150pF VS = +5.8V to +15V VOUT nom = -15V, CX = 150pF VS = +5.8V to +15 L01 Load Regulation VOUT nom = -5.0V, CX = 350pF, VS = +4.5V, PLOAD = 0mW to 75mW VOUT nom = -15V, CX = 350pF, VS = +4.5V, PLOAD = 0mW to 75mW ICO Switch Leakage Current Pin 5 = -20V 0.2 0.1 0.3 30 mA 0.2 0.5 1.5 3.0 %VOUT 2.0 4.0 Condition (Note 1) VS = +25V 1.13 -5.5 -16.5 Min 4.0 300 1.25 -5.0 -15.0 Typ Max 30 500 1.36 -4.5 -13.5 %VOUT Units V mA V V
Note: 1. The maximum allowable supply voltage (+VS) in inverting applications will be reduced by the value of the negative output voltage, unless an external power transistor is used.
3
PRODUCT SPECIFICATION
RC4391
Electrical Characteristics
(VS = +6.0V, TA = +25C unless otherwise noted) Symbol ISY Parameters Supply Voltage Condition VS = +4.0V, No External Loads VS = +25V No External Loads VOUT LI1 Output Voltage Line Regulation VOUT nom = -5.0V VOUT nom = -15V VOUT nom = -5.0V CX = 150pF, VS = +5.8V to +15V VOUT nom = -15V, CX = 150pF VS = +5.8V to +15V L01 Load Regulation VOUT nom = -5.0V, CX = 350pF, VS = +4.5V, PLOAD = 0mW to 75mW VOUT nom = -15V, CX = 350pF, VS = +4.5V, PLOAD = 0mW to 75mW VREF ISW ICO ICX ILBDL ILBD0 ILBRB Reference Voltage Switch Current Switch Leakage Current Cap. Charging Current LBD Leakage Current LBD On Current LBR Bias Current Pin 5 = 5.5V Pin 5 = -24V Pin 3 = 0V Pin 1 = 1.5V, Pin 2 = 6.0V Pin 1 = 1.1V, Pin 2 = 0.4V Pin 1 = 1.5V 210 6.0 1.18 75 1.25 100 0.01 10 0.01 600 0.7 5.0 14 5.0 1.32 V mA mA mA mA mA mA 0.07 0.14 0.2 0.4 %VOUT 1.0 2.0 1.5 3.0 -5.35 -15.85 -5.0 -15.0 -4.65 -14.15 %VOUT V 300 500 Min Typ 170 Max 250 Units mA
4
RC4391
PRODUCT SPECIFICATION
Typical Performance Characteristics
6.5 6.0 5.5 FO (kHz) FO (kHz) 5.0 4.5 4.0
65-3268
8 7 6 5 4 3 2 1 0 -55 0 25 TA (C) Figure 2. Oscillator Frequency vs. Temperature 70 125
65-3272
3.5 3.0 0 5 10 15 +VS (V) Figure 1. Oscillator Frequency vs. Supply Voltage 20
25
1.260
1.260
1.255 VREF (V) VREF (V)
1.255
1.250
1.250
1.245
65-3269
1.245
65-3273
1.240
-55
0
25 TA (C)
70
125
1.240
4
6
10 +VS (V)
20
30
Figure 3. Reference Voltage vs. Temperature
Figure 4. Reference Voltage vs. Supply Voltage
600 500
4
3 IC (mA) +VS (V)
65-3270
400 300 200
2
1 100 20 10 0 1 2 3
4
65-3271
5
6
7
8
0
-55
0
25 TA (C)
70
125
VCE (SAT) (V) Figure 5. Collector Current vs. Q1 Saturation Voltage
Figure 6. Minimum Supply Voltage vs. Temperature
5
PRODUCT SPECIFICATION
RC4391
Principles of Operation
The basic switching inverter circuit is the building block on which the complete inverting application is based. A simplified diagram of the voltage inverter circuit with ideal components and no feedback circuitry is shown in Figure 7. When the switch S is closed, charging current from the battery flows through the inductor L, which builds up a magnetic field, increasing as the switch is held closed. When the switch is opened, the magnetic field collapses, and the energy stored in the magnetic field is converted into a current which flows through the inductor in the same direction as the changing current. Because there is no path for this current to flow through the switch, the current must flow through the diode to charge the capacitor C. The key to the inversion is the ability of the inductor to become a source when the charging current is removed. The equation V = L (di/dt) gives the maximum possible voltage across the inductor; in the actual application, feedback circuitry and the output capacitor will decrease the output voltage to a regulated fixed value. A complete schematic for the standard inverting application is shown in Figure 8. The ideal switch in the simplified diagram is replaced by the PNP transistor switch between pins 5 and 6. CF functions as the output filter capacitor, and D1 and LX replace D and L. When power is first applied, the ground sensing comparator (pin 8) compares the output voltage to the +1.25V voltage
reference. Because CF is initially discharged a positive voltage is applied to the comparator, and the output of the comparator gates the squarewave oscillator. This gated squarewave signal turns on, then off, the PNP output transistor. This turning on and off of the output transistor performs the same function as opening and closing the ideal switch in the simplified diagram; i.e., it stores energy in the inductor during the on time and releases it into the capacitor during the off time. The comparator will continue to allow the oscillator to turn the switch transistor on and off until enough energy has been stored in the output capacitor to make the comparator input voltage decrease to less than 0V. The voltage applied to the comparator is set by the output voltage, the reference voltage, and the ratio of R1 to R2.
S D +VS L C VOUT (-)
(+)
65-1601
Figure 7. Simple Inverting Regulator
To +Vs
R3 260K LBR R4 590K R6 100K LBD C2 Q2 C1 VFB
C F* 33F
-V OUT
R1
Parts List R1 = R2 = Cx = Lx = D1 F
-5.0V Output 300 k W 75 k W
-15V Output 900 k W 75 k W
VREF +1.25V REF/Bias VREF
R2
C1 0.1F 1N914
150 pF 150 pF 1.0 mH Dale TE3 Q4 TA
LBD Output CX A Cx GND D Q1 LX RC4391 B OSC +VS +Vs
= Optional R1 ) R2
-VOUT = (1.25V) (
Lx
E
65-1602
*Caution: Use current limiting protection circuit for high values of CF (Figure 13) Figure 8. Inverting Regulator - Standard Circuit
6
RC4391
PRODUCT SPECIFICATION
1.78V A 0.62V CX
B
(Internal)
O SC
IL I LOAD C 0 mA +V S D VBAT LX E V OUT LX (Internal) +V S - 0.7V Max I LX 0 mA I MAX ID F 0 mA +V S - V SW G Ground -V OUT - V D
65-2472
V BEQ1
V LX
Figure 9. Inverting Regulator Waveforms
This feedback system will vary the duration of the on time in response to changes in load current or battery voltage (see Figure 9). If the load current increases (waveform C), then the transistor will remain on (waveform D) for a longer portion of the oscillator cycle, (waveform B) to build up to a higher peak value. The duty cycle of the switch transistor varies in response to changes in load and line.
S
L
(+)
+VS
D
C
RL
VOUT
(-)
65-2473
Step-Down Regulator
The step-down circuit function is similar to inversion; it uses the same components (switch, inductor, diode, filter capacitor), and charges and discharges the inductor by closing and opening the switch. The great difference is that the inductor is in series with the load; therefore, both the charging current and the discharge current flow into the load. In the inverting circuit only the discharge current flows into the load. Refer to Figure 10. When the switch S is closed, current flows from the battery, through the inductor, and through the load resistor to ground. After the switch is opened, stored energy in the inductor causes current to keep flowing through the load, the circuit being completed by the catch diode D. Since current flows to the load during charge and discharge, the average load cur-
Figure 10. Simple Step-Down Regulator
rent will be greater than in an inverting circuit. The significance of that is that for equal load currents the step-down circuit will require less peak inductor current than an inverting circuit. Therefore, the inductor will not require as large of a core, and the switch transistor will not be stressed as heavily for equal load currents. Figure 11 depicts a complete schematic for a step-down circuit using the RC4391. Observe that the ground lead of the 4391 is not connected to circuit ground; instead, it is tied to the output voltage. It is by this rearrangement that the feedback system, which senses voltages more negative than the ground lead, can be used to regulate a non-negative output voltage.
7
PRODUCT SPECIFICATION
RC4391
When power is first applied, the output filter capacitor is discharged so the ground lead potential starts at 0V. The reference voltage is forced to +1.25V above the ground lead and pulls the feedback input (pin 8) more positive than the ground lead. This positive voltage forces the control network to begin pulsing the switch transistor. As the switching action pumps up the output voltage, the ground lead rises with the output until the voltage on the ground lead is equal to the feedback voltage. At that point, the control network reduces the time on time of the switch to maintain a constant output. This control network will vary the on time of the switch in response to changes in load current or battery voltage (see Figure 12). If the load current increases (waveform C), then the transistor will remain on (waveformD) for a longer portion of the oscillator cycle, (waveform B), thus allowing the
inductor current (waveform E) to build up to a higher peak value. The duty cycle of the switch transistor varies in response to changes in load and line.
Design Equations
The inductor value and timing capacitor (CX) value must be carefully tailored to the input voltage, input voltage range, output voltage, and load current requirements of the application. The key to the problem is to select the correct inductor value for a given oscillator frequency, such that the inductor current rises to a high enough peak value (IMAX) to meet the average load current drain. The selection of this inductor value must take into account the variation of oscillator frequency from unit to unit and the drift of frequency over temperature. Use 30% as a maximum variation of oscillator frequency.
R1 LBR C2 Q2 C1 R2 LBD VREF +1.25V REF/Bias VREF VFB
CX A Cx GND +V OUT
B OSC D
+VS
+Vs
Q1 LX RC4391 E Lx F D1 1N914
65-2475
CF +VOUT
R1 = (1.25V) ( ) R2
Important Note: This circuit must have a minimum load 1 mA always connected. Figure 11. Step-Down Regulator - Standard Circuit
8
RC4391
PRODUCT SPECIFICATION
1.78V A 0.62V
CX
B
(Internal)
OSC
IL I LOAD C 0 mA +VS D VBAT LX E V OUT - V BAT LX (Internal) +V - 0.7V I MAX I LX 0 mA VBEQ1
+V S - VSW F VOUT VS ( -0.7V)
65-2474
VLX
Figure 12. Step-Down Regulator Waveforms
The oscillator creates a squarewave using a method similar to the 555 timer IC, with a current steering flip-flop controlled by two voltage sensing comparators. The oscillator frequency is set by the timing capacitor (CX) according to the following equation.
-6 4.1x10 F O ( Hz ) = ---------------------C ( pF ) x
2. Find the maximum on time TON (add 3mS for the turn off base recombination delay of Q1):
1 T ON = --------- + 3mS 2F O
3. Calculate the peak inductor current IMAX (if this value is greater than 375mA then an external power transistor must be used in place of Q1):
( V OUT + V D )2I L I MAX = --------------------------------------------------------( F O ) ( T ON ) ( V S - V SW )
The squarewave output of the oscillator is internal and cannot be directly measured, but is equal in frequency to the triangle waveform measurable at pin 3. The switch transistor is normally on when the triangle waveform is ramping up and off when ramping down. Capacitor selection depends on the application; higher operating frequencies will reduce the output voltage ripple and will allow the use of an inductor with a physically smaller inductor core, but excessively high frequencies will reduce load driving capability and efficiency.
Where: VS = Supply Voltage VSW = Saturation Voltage of Q1 (typically 0.5V) VD = Diode Forward Voltage (typically 0.7V) IL = DC Load Current 4. Find an inductance value for LX:
V S - V SW L X ( Henries ) = ae ------------------------o ( T ON ) e I MAX o
Inverting Design Procedure
1. Select an operating frequency and timing capacitor value as shown above (frequencies from 10kHz to 50kHz are typical).
The inductor chosen must exhibit this value of inductance and have a current rating equal to IMAX.
9
PRODUCT SPECIFICATION
RC4391
Step-Down Design Procedure
1. Select an operating frequency. 2. Determine the maximum on time TON as in the inverting design procedure. 3. Calculate IMAX:
2I L I MAX = ---------------------------------------------------------------------------( V S - V OUT ) ( F O ) ( T ON ) -------------------------------- + 1 ( V OUT - V D )
Compensation
When large values (> 50 kW) are used for the voltage setting resistors (R1 and R2 of Figure 8) stray capacitance at the VFB input can add lag to the feedback response, destabilizing the regulator, increasing low frequency ripple, and lowering efficiency. This can often be avoided by minimizing the stray capacitance at the VFB node. It can also be remedied by adding a lead compensation capacitor of 100 pF to 10 nF. In inverting applications, the capacitor connects between -VOUT and VFB; for step-down circuits it connects between ground and VFB. Most applications do not require this capacitor.
4. Calculate LX:
V S - V SW L X (Henries) = ae ------------------------o ( T ON ) e I MAX o
Inductors
Efficiency and load regulation will improve if a quality high Q inductor is used. A ferrite pot core is recommended; the wind-yourself type with an air gap adjustable by washers or spacers is very useful for bread-boarding prototypes. Care must be taken to choose a core with enough permeability to handle the magnetic flux produced at IMAX. If the core saturates, then efficiency and output current capability are severely degraded and excessive current will flow through the switch transistor. A pot core inductor design section is provided later in this datasheet. An isolated AC current probe for an oscilloscope (example: Tektronix P6042) is an excellent tool for saturation problems; with it the inductor current can be monitored for nonlinearity at the peaks (a sign of saturation).
Alternate Design Procedure
The design equations above will not work for certain input/ output voltage ratios, and for these circuits another method of defining component values must be used. If the slope of the current discharge waveform is much less than the slope of the current charging waveform, then the inductor current will become continuous (never discharging completely), and the equations will become extremely complex. So, if the voltage applied across the inductor during the charge time is greater than during the discharge time, use the design procedure below. For example, a step-down circuit with 20V input and 5V output will have approximately 15V across the inductor when charging, and approximately 5V when discharging. So in this example the inductor current will be continuous and the alternate procedure will be necessary. The alternate procedure may also be used for discontinuous circuits. 1. Select an operating frequency based on efficiency and component size requirements (a value between 10kHz and 50kHz is typical). 2. Build the circuit and apply the worst case conditions to it, i.e., the lowest battery voltage and the highest load current at the desired output voltage. 3. Adjust the inductor value down until the desired output voltage is achieved, then decrease its value by 30% to cover manufacturing tolerances. 4. Check the output voltage with an oscilloscope for ripple, at high supply voltages, at voltages as high as are expected. Also check for efficiency by monitoring supply and output voltages and currents:
( V OUT ) ( I OUT ) ae eff = -----------------------------------------o e ( +V S ) ( I SY )x100o
Low Battery Detector
An open collector signal transistor Q2 with comparator C2 provides the designer with a method of signaling a display or computer whenever the battery voltage falls below a programmed level (see Figure 13). This level is determined by the +1.25V reference level and by the selection of two external resistors according to the equation:
R4 V TH = V REF ae ------ + 1o e R5 o
When the battery drops below this threshold Q2 will turn on and sink typically 600mA. The low battery detection circuit can also be used for other less conventional applications such as the voltage dependent oscillator circuit of Figure 18.
+Vs R4 1 LBR C2 R5 V REF 1.25V
65-1651A
LBD Q2
2 I LBD
5. If the efficiency is poor, go back to Step 1 and start over. If the ripple is excessive, then increase the output filter capacitor value or start over.
Figure 13. Low Battery Detector
10
RC4391
PRODUCT SPECIFICATION
Device Shutdown
The entire device may be shut down to an extremely low current non-operating condition by disconnecting the ground (pin 4). This can be easily done by putting an NPN transistor in series with ground pin and switching it with an external signal. This switch will not affect the efficiency of operation, but will add to and increase the reference voltage by an amount equal to the saturation voltage of the transistor used. A mechanical switch can also be used in series between circuit ground and pin 4, without introducing any reference offset.
The following external power transistor circuits may demand some adjustment to resistor values to satisfy various power levels and input/output voltages. CX and LX values must be selected according to the design equations (pages 2-213 and 2-214).
Inverting Medium Power Application
Figure 8 is a schematic of an inverting medium power supply (250mW to 1W) using an external PNP switch transistor. Supply voltage is applied to the IC via R3: when the internal switch transistor is turned on current through R4 is also drawn through R3; creating a voltage drop from base to emitter of the external switch transistor. This drop turns on the external transistor. Voltage pulses on the supply lead (pin 6) do not affect circuit operation because the internal reference and bias circuitry have good supply rejection capabilities. A power Schottky diode is used for higher efficiency.
Power Transistor Interfaces
The most important consideration in selecting an external power transistor is the saturation voltage at IC = IMAX. The lower the saturation voltage is, the better the efficiency will be. Also, a higher beta transistor requires less base drive and therefore less power will be. Also, a higher beta transistor requires less base drive and therefore less power will be consumed in driving it, improving efficiency losses in the interface. The part numbers given in the following applications are recommended, but other types may be more appropriate depending on voltage and power levels. When troubleshooting external power transistor circuits, ensure that clean, sharp-edged waveforms are driving the interface and power transistors. Monitor these waveforms with an oscilloscop--disconnect the inductor, and tie the VFB input (pin 8) high through a 10K resistor. This will cause the regulator to pulse at maximum duty cycle without drawing excessive inductor currents. Check for expected on time and off time, and look for slow rise times that might cause the power transistor to enter its linear operating region.
Inverting High Power Application
For higher power applications (500mW to 5W), refer to Figure 9. This circuit uses an extra external transistor to provide well controlled drive current in the correct phase to the power switch transistor. The value of R3 sets the drive current to the switch by making the interface transistor act as a current source. R4 and R5 must be selected such that the RC time constant of R4 and the base capacitance of Q2 do not slow the response time (and affect duty cycle), but not so low in value that excess power is consumed and efficiency suffers. The resistor values chosen should be proportional to the supply voltage (values shown are for +5V).
Step-Down Power Applications
Figures 16 and 17 show medium and high power interfaces modified to perform step-down functioning. The design
+5V
C1 0.1F
R2 62 k1/2
R3 1k1/2
Q1 2N3635 -24V
5
7
6
5 Lx R4 501/2
VFB VREF +Vs 4391 Cx 3 150 pF Cx
Motorola MBR030
CF 100F
220H R1 1.2 M1/2
GND 4
65-2476
Figure 14. Inverting Medium Power Application
11
PRODUCT SPECIFICATION
RC4391
+Vs
R6 1K C1 0.1F R5 2K
Q1 TIP116
R2
Q2 2N33904 MBR140P -V OUT
5 VFB
7 6 5 VREF +Vs L x 4391
R4 4.7K
R3 7501/2
Lx R1
CF
Cx 3 Cx
GND 4
65-2478
Figure 9. Inverting High Power Application
equations and suggestions for the circuits of Figures 14 and 15 also apply to these circuits. For a certain range of load power, the RC4193 can be used for step-sown applications. A load range from 400mW to 2W can be sustained with fewer components (especially when stepping down greater than 30V) than the comparable RC4391 circuit. Refer to Fairchild Semiconductor's RC4191/4192/4193 data sheet for a schematic of this medium power step-down application.
The threshold is programmed exactly as the normal low battery detector connection:
R4 V TH = V REF ae ------ + 1o e R5 o
Voltage Dependent Oscillator
The RC4391's ability to supply load current at low battery voltages depends on the inductor value and the oscillator frequency. Low values of inductance or a low oscillator frequency will cause a higher peak inductor current and therefore increase the load current capability. A large inductor current is not necessarily best , however, because the large amount of energy delivered with each cycle will cause a large voltage ripple at the output, especially at high input voltages. This trade-off between load current capability and output ripple can be improved with the circuit connection shown in Figure 18. This circuit uses the low battery detector to sense for a low battery voltage condition and will decrease the oscillator frequency after a pre- programmed threshold is reached.
When the battery voltage reaches this threshold the comparator will turn on the open collector transistor at pin 2, effectively pulling CY in parallel with CX. This added capacitance will reduce the oscillator frequency, according to the following equation:
-6 4.1x10 F O ( Hz ) = -----------------------------------------------C X ( pF ) + C Y ( pF )
Current Limiting
The oscillator (CX) pin can be used to add short circuit protection and to protect against over current at start-up (when using large values for the output filter capacitor --greater than 100 mF). A transistor VBE is used as a current sensing comparator which resets the oscillator upon sensing an over current condition, thus providing cycle-by-cycle current limiting. Figure 19 shows how this is applied.
12
RC4391
PRODUCT SPECIFICATION
+Vs
C1 0.1 F
R2
R3 1K 2N3635 8 VFB 7 6 VREF +Vs 4391 Cx 3 Cx +V OUT GND 4 5 Lx R4 30 - 1001/2 Lx
R1
MBR030
Note: A minimum load 1mA must be connected.
CF
65-2479
Figure 16. Step-Down Medium Power Application
TIP116 * 6 +1.3V R2 5K 8V FB R1 5K CX 3 CX 470 pF 7 VREF +VS 4391 LX 5 2N3904
MBR140P
5001/2
250H
VBAT
GND 4
R4 20K
R3 1K (+) V OUT (+5V at 1A as shown) (-)
65-2077
470 pF
CF Note: A minimum load 1mA must be connected. *Optional -- Extends supply voltage range.
470F
Figure 17. Step-Down High Power Application
To +VS
OSC +1.25V
CX
3 CX
+VS
1W
LBD
2
CV
+VS 2N3906 or Equivalent 3 CX
65-2053
R4 1 LBR R5 C2 Q2 CX 4391
65-2159
Figure 18. Voltage Dependent Oscillator
Figure 18. Current Limiting
13
14
LBR (1) LBD (2) CX (3) Q2 Q3A 0.5 R5 10K Q35 Q36 Q10 Q21 Q20 Q28 D16 R6 20K R7 10K Q40 D18 Q22 Q23 Q29 50X D15 Q11 Q12 Q27 10X Q37 Q38 Q39 Q3B 0.5 Q17 Q18 Q19 0.1 0.1 0.1 Q3 Q31 0.9 Q32 0.9 Q33 0.9 Q34 1.1 Q4B R11 160K Q9 D17 Q44 Q14 Q15 Q16 2X R8 150K D7 D8 D9 Q25 Q26 40X Q41 D13 Q24 D10 Q13 Q42 2X D12 Q43 2X D14 (7) VREF (8) VFB (5) LX (4) GND
65-6364
+VS (6)
PRODUCT SPECIFICATION
R1 540K
Q1
Q4 0.6
0.3
Q5
Q6
Simplified Schematic Diagram
C1 25 pF
Q7 4X
R2 3K
Q8
R3 8.2K
Q45
Q46
R9 60K
R4 76K
R10 50K
RC4391
RC4391
PRODUCT SPECIFICATION
Troubleshooting Chart
Symptom Draws excessive supply current on star-up. Possible Problems Inductance value too low. Output frequency (FO) too low. Combination of low resistance inductor and high value filter capacitor -- needs current limiting circuit (Figure 13). Output voltage is low. Inductor "sings" with audible hum. LX pin appears noisy -- scope will not synchronize.
-IMAX ILX Time
Inductance value too high for FO or core saturating. Not potted well or bolted loosely. Normal operating condition. Inductor is saturating: 1. Core too small. 2. Core too hot. 3. Operating frequency too low.
Inductor current shows nonlinear waveform. Waveform has resistive component:
-IMAX ILX Time
1. Wire size too small. 2. Power transistor lacks base drive. 3. Components not rated high enough. 4. Battery has high series resistance. External transistor lacks base drive or beta is too low.
Inductor current shows nonlinear waveform.
-IMAX ILX Time
Inductor current is linear until high current is reached. Poor efficiency. Core saturating. Diode or transistor: 1. Not fast enough. 2. Not rated for current level (high VCESAT). High series resistance. Operating frequency too high. Motorboating (erratic current pulses). Loop stability problem -- needs feedback from VOUT to VFB (pin 8), 100pF to 1000pF
15
PRODUCT SPECIFICATION
RC4391
Pot Core Inductor Design
Electrical Circuit I E=I*R E R North H =B * South 1 U Magentic Circuit
Flux
65-3464-07
Figure 20. Electricity vs. Magnetism
Electricity Versus Magnetism
Electrically the inductor must meet just one requirement, but that requirement can be hard to satisfy. The inductor must exhibit the correct value of inductance (L, in Henrys) as the inductor current rises to its highest operating value (IMAX). This requirement can be met most simply by choosing a very large core and winding it until it reaches the correct inductance value, but that brute force technique wastes size, weight and money. A more efficient design technique must be used. Question: What happens if too small a core is used? First, one must understand how the inductor's magnetic field works. The magnetic circuit in the inductor is very similar to a simple resistive electrical circuit. There is a magnetizing force (H, in oersteds), a flow of magnetism, or flux density (B, in Gauss), and a resistance to the flux, called permeability (U, in Gauss per oersted). H is equivalent to voltage in the electrical model, flux density is like current flow, and permeability is like resistance (except for two important differences discussed to the right). First Difference: Permeability instead of being analogous to resistance, is actually more like conductance (1/R). As permeability increases, flux increases. Second Difference: Resistance is a linear function. As voltage increases, current increases proportionally, and the resistance value stays the same. In a magnetic circuit the value of permeability varies as the applied magnetic force varies. This nonlinear characteristic is usually shown in graph form in ferrite core manufacturer's data sheet. As the applied magnetizing force increases, at some point the permeability will start decreasing, and therefore the amount of magnetic flux will not increase any further, even as the magnetizing force increases. The physical reality is that, at
the point where the permeability decreases, the magnetic field has realigned all of the magnetic domains in the core material. Once all of the domains have been aligned the core will then carry no more flux than just air, it becomes as if there were no core at all. This phenomenon is called saturation. Because the inductance value, L, is dependent on the amount of flux, core saturation will cause the value of L to decrease dramatically, in turn causing excessive and possibly destructive inductor current.
6000 5000 B Gauss 4000 3000 2000 1000
65-2170
+25C +85C +125C
Stackpole Ceramag 24B Hysteresis Loop vs. Temperature
0 -0.5 0 0.5 1
2 2.5 3 H Oersteds
5
7
9
Figure 21. Typical Manufacturer's Curve Showing Saturation Effects
Pot Cores for RC4391
Pot core inductors are best suited for the RC4391 switching regulator for several reasons: 1. They are available in a wide range of sizes. RC4391 applications are usually low power with relatively low peak currents (less than 500mA). A small inexpensive pot core can be chosen to meet the circuit requirements. 2. Pot cores are easily mounted. They can be bolted directly to the PC card adjacent to the regulator IC.
16
RC4391
PRODUCT SPECIFICATION
3. Pot cores can be easily air-gapped. The length of the gap is simply adjusted using different washer thicknesses. cores are also available with predetermined air gaps. 4. Electromagnetic interference (EMI) is kept to a minimum. the completely enclosed design of a pot core reduces stray electromagnetic radiation--an important consideration if the regulator circuit is built on a PC card with other circuitry. Not quite. Core size is dependent on the amount of energy stored, not on load power. Raising the operating frequency allows smaller cores and windings. Reduction of the size of the magnetics is the main reason switching regulator design tends toward higher operating frequency. Designs with the RC4391 should use 75 kHz as a maximum running frequency, because the turn off delay of the power transistor and stray capacitive coupling begin to interfere. Most applications are in the 10 to 50 kHz range, for efficiency and EMI reasons. The peak inductor current (IMAX) must reach a high enough value to meet the load current and simultaneously the inductor value is decreased, then the core can be made smaller. For a given core size and winding, an increase in air gap spacing (an air gap is a break in the material in the magnetic path, like a section broken off a doughnut) will cause the inductance to decrease and IMAX (the usable peak current before saturation )to increase. The curves shown are typical of the ferrite manufacturer's power HF material, such as Siemens N27 or Stackpole 24B, which are usually offered in standard millimeter sizes including the sizes shown.
Use of the Design Aid Graph
1. From the application requirement, determine the inductor value (L) and the required peak current (IMAX). 2. Observe the curves of the design aid graph and determine the smallest core that meets both the L and I requirements. 3. Note the approximate air gap at IMAX for the selected core, and order the core with the gap. (If the gapping is done by the user, remember that a washer lspacer results in an air gap of twice the washer thickness, because two gaps will be created, one at the center post and one at the rim, like taking two bites from a doughnut.) 4. If the required inductance is equal to the indicated value on the graph, then wind the core with the number of turns shown in the table of sizes. The turns given are the maximum number for that gauge of wire that can be easily wound in cores winding area. 5. If the required inductance is less than the value indicated on the graph, a simple calculation must be done to find the adjusted number of turns. Find AL (inductance index) for a specific air gap.
inHenries L ( indicated ) -------------------------------- = AL ae -------------------------o 2o 2 e Turn Turns
Then divide the required inductance value by AL to give the actual turns squared, and take the square root to find the actual turns needed.
L ( required ) ActualTurns = -----------------------------AL
#1
22X 13 mm 24 Gauge 70 Turns DCW = 0.5W
Air Gap = 0.02" 3A Air Gap = 0.012"
#2
18X 11 mm 26 Gauge 70 Turns DCW = 0.7W
IMAX (Amperes*)
2A #1 1A #2 #3 0 #4 1 mH 2 mH
Air Gap = 0.006"
#3
#4
11X 7 mm 30 Gauge 50 Turns DCW = 1W
3 mH
Inductor Value (Henries)
*Includes safety margin (25%) to ensure nonsaturation
Figure 22. Inductor Design Aid
65-2171
14X 8 mm 28 Gauge 60 Turns DCW = 0.6W
No Air Gap
17
PRODUCT SPECIFICATION
RC4391
If the actual number of turns is significantly less than the number from the table then the wire size can be increased to use up the leftover winding area and reduce resistive losses. 6. Wind and gap the core as per calculations, and measure the value with an inductance meter. Some adjustment of the number of turns may be necessary. The saturation characteristics may be checked with the inductor wired into the switching regulator application circuit. To do so, build and power up the circuit. Then clamp an oscilloscope current probe (recommend Tektronix P6042 or equivalent) around the inductor lead and monitor the current in the inductor. Draw the maximum load current from the application circuit so that the regulator is running at close to full duty cycle. Compare the waveform you see to those pictured. Check for saturation at the highest expected ambient temperature. 7. After the operation in circuit has been checked, reassemble and pot the core using a potting compound recommended by the manufacturer. If the core material differs greatly in magnetic characteristics from the standard power material shown in Figure 16, then the following general equation can be used to help in winding and gapping. This equation can be used for any core geometry, such as an E-E core.
( 1.26 ) ( N ) ( Ae ) ( 10 ) L X = ----------------------------------------------------g = ( le/ue )
2 8
Where: N = number of turns Ae = core area from data sheet (in cm2) le = magnetic path length from data sheet (in cm) ue =permeability of core from manufacturer's graph g = center post air gap (in cm)
Manufacturers
Below is a list of several pot core manufacturers: Ferroxcube Company 5083 Kings Highway Saugerties, NY 12477 Indiana General Electronics Keasley, NJ 08832 Siemens Company 186 Wood Avenue South Iselin, NJ 08830 Stackpole Company 201 Stackpole Street St. Mary, PA 15857 TDK Electronics 13-1, 1-Chrome Nihonbaski, Chuo-ku, Tokyo
Proper Operation (Waveform is Fairly Linear)
Improper Operation (Waveform is Nonlinear, Inductor Is Saturating) IMAX
IMAX
0
0
65-3464-08
Figure 23. Inductor Current Waveforms
18
RC4391
PRODUCT SPECIFICATION
Mechanical Dimensions
8-Lead Ceramic DIP Package
Inches Min. A b1 b2 c1 D E e eA L Q s1 a Max. Millimeters Min. Max. 8 2, 8 8 4 4 5, 9 7 3 6 Notes: Notes 1. Index area: a notch or a pin one identification mark shall be located adjacent to pin one. The manufacturer's identification shall not be used as pin one identification mark. 2. The minimum limit for dimension "b2" may be .023 (.58mm) for leads number 1, 4, 5 and 8 only. 3. Dimension "Q" shall be measured from the seating plane to the base plane. 4. This dimension allows for off-center lid, meniscus and glass overrun. 5. The basic pin spacing is .100 (2.54mm) between centerlines. Each pin centerline shall be located within .010 (.25mm) of its exact longitudinal position relative to pins 1 and 8. 6. Applies to all four corners (leads number 1, 4, 5, and 8). 7. "eA" shall be measured at the center of the lead bends or at the centerline of the leads when "a" is 90. 8. All leads - Increase maximum limit by .003 (.08mm) measured at the center of the flat, when lead finish applied. 9. Six spaces. D 4 1 Note 1 E
Symbol
-- .200 .014 .023 .045 .065 .008 .015 -- .405 .220 .310 .100 BSC .300 BSC .125 .200 .015 .060 .005 -- 90 105
-- 5.08 .36 .58 1.14 1.65 .20 .38 -- 10.29 5.59 7.87 2.54 BSC 7.62 BSC 3.18 5.08 .38 1.52 .13 -- 90 105
5 s1
8
e
eA
A Q L b2 b1 a c1
19
PRODUCT SPECIFICATION
RC4391
Mechanical Dimensions (continued)
8-Lead Plastic DIP Package
Inches Min. A A1 A2 B B1 C D D1 E E1 e eB L N -- .015 .115 .014 .045 .008 .348 .005 .300 .240 Max. .210 -- .195 .022 .070 .015 .430 -- .325 .280 Millimeters Min. -- .38 2.93 .36 1.14 .20 8.84 .13 7.62 6.10 Max. 5.33 -- 4.95 .56 1.78 .38 10.92 -- 8.26 7.11 Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E1" do not include mold flashing. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. Terminal numbers are for reference only. 4. "C" dimension does not include solder finish thickness. 5. Symbol "N" is the maximum number of terminals. 4 2
Symbol
2
.100 BSC -- .430 .115 .160 8
2.54 BSC -- 10.92 2.92 4.06 8 5
D 4 1
E1
D1
5
8
E e A A1 L B1 B eB A2 C
20
RC4391
PRODUCT SPECIFICATION
Mechanical Dimensions (continued)
8-Lead SOIC Package
Inches Min. A A1 B C D E e H h L N a ccc Max. Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
Symbol
.053 .069 .004 .010 .013 .020 .008 .010 .189 .197 .150 .158 .050 BSC .228 .010 .016 8 0 -- 8 .004 .244 .020 .050
1.35 1.75 0.10 0.25 0.33 0.51 0.20 0.25 4.80 5.00 3.81 4.01 1.27 BSC 5.79 0.25 0.40 8 0 -- 8 0.10 6.20 0.50 1.27
3 6
8
5
E
H
1
4
D A1 A SEATING PLANE B -C- LEAD COPLANARITY ccc C a
h x 45 C
e
L
21
PRODUCT SPECIFICATION
RC4391
Ordering Information
Part Number RC4391N RC4391M RV4391N RM4391D Package 8 Lead Plastic DIP 8 Lead Plastic SOIC 8 Lead Plastic DIP 8 Lead Ceramic DIP Operating Temperature Range 0C to +70C 0C to +70C -25C to +85C -55C to +125C
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS30004391 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC4558
Dual High-Gain Operational Amplifier
Features
* 2.5 MHz unity gain bandwidth * Supply voltage 22V for RM4558 and 18V for RC/RV4558 * Short-circuit protection * No frequency compensation required * * * * * No latch-up Large common-mode and differential voltage ranges Low power consumption Parameter tracking over temperature range Gain and phase match between amplifiers
Description
The RC4558 integrated circuit is a dual high-gain operational amplifier internally compensated and constructed on a single silicon IC using an advanced epitaxial process. Combining the features of the 741 with the close parameter matching and tracking of a dual device on a monolithic chip results in unique performance characteristics. Excellent channel separation allows the use of this dual device in dense single 741 operational amplifier applications. It is especially well suited for applications in differential-in, differential-out as well as in potentiometric amplifiers and where gain and phase matched channels are mandatory.
Block Diagram
Output (A) -Input (A) -Input (A) _ A + _ B + Output (B) -Input (B) +Input (B)
65-4558-01
Rev. 1.0.0
PRODUCT SPECIFICATION
RC4558
Pin Assignments
+VS Output (A) Output (A)
8 1 2 3 4 5 7 6
1 2 3 4
8 7 6 5
65-3473-03
+VS Output (B) -Input (B) +Input (B)
Output (B) -Input (A) -Input (B) +Input (A) -VS
-Input (A)
+Input (A)
+Input (B)
65-3473-02
-VS
Absolute Maximum Ratings
(beyond which the device may be damaged)1 Parameter Supply Voltage Input Voltage2 SOIC PDIP CerDIP TO-99 Junction Temperature Operating Temperature Lead Soldering Temperature Output Short Circuit Duration3 SOIC, PDIP CerDIP, TO-99 RM4558 RC4558 PDIP, CerDIP, TO-99 (60 sec) SOIC (10 sec) -55 0 RM4558 RC4558 Differential Input Voltage PDTA < 50C Min Typ Max 22 18 15 30 300 468 833 658 125 175 125 70 300 260 Indefinite C C C V V mW Units V
Notes: 1. Functional operation under any of these conditions is NOT implied. 2. For supply voltages less than 15V, the absolute maximum input voltage is equal to the supply voltage. 3. Short circuit may be to ground on one op amp only. Rating applies to +75C ambient temperature.
Matching Characteristics
(VS = 15V, TA = +25C unless otherwise specified) Parameter Voltage Gain Input Bias Current Input Offset Current Test Conditions RL 2 kW RL 2 kW RL 2 kW Typ 1.0 15 7.5 Units dB nA nA
2
RC4558
PRODUCT SPECIFICATION
Electrical Characteristics
(VS = 15V and TA = +25C unless otherwise specified) RM4558 Parameters Input Offset Voltage Input Offset Current Input Bias Current Input Resistance Large Signal Voltage Gain Output Voltage Swing Input Voltage Range Common Mode Rejection Ratio Power Supply Rejection Ratio Power Consumption Transient Response Rise Time Overshoot Slew Rate Channel Separation Unity Gain Bandwidth (Gain = 1) RS 10kW RS 10kW RL = VIN = 20 mV RL = 2kW CL 100pF RL 2kW F = 10kHz, RS = 1kW 2.5 0.3 35 0.8 90 3.0 2.0 0.3 35 0.8 90 3.0 mS % V/mS dB MHz RL 2kW, VOUT = 10V RL 10kW RL 2kW 0.3 50 12 10 12 70 76 Test Conditions RS 10kW Min Typ 1.0 5.0 40 1.0 300 14 13 13 100 100 100 170 Max 5.0 200 500 0.3 20 12 10 12 70 76 Min RC4558 Typ 2.0 5.0 40 1.0 300 14 13 13 100 100 100 170 Max Units 6.0 200 500 mV nA nA MW V/mV V V V dB dB mW
The following specifications apply for RM = -55C TA +125C, RC = 0 TA +70C RM4558 Parameters Input Offset Voltage Input Offset Current RC4558 Input bias Current RC4558 Large Signal Voltage Gain Output Voltage Swing Power Consumption RL 2kW, VOUT = 10 RL 2kW RL = 25 10 120 200 1500 15 10 120 200 800 nA V/mV V mW 500 300 nA Test Conditions RS 10kW Min Typ Max 6.0 Min RC4558 Typ Max 7.5 Units mV
3
PRODUCT SPECIFICATION
RC4558
Typical Performance Characteristics
100 80 IB (nA) 60 40 20 0
VS = 15V
25 20 IOS (nA) 15 10 5
65-0211
VS =
15V
0 0 +10 +20 +30 +40 +50 +60 TA (C) Figure 2. Input Offset Current vs. Temperature
0
+10
+20
+30
+40
+50
+60
+70
+70
TA (C) Figure 1. Input Bias Current vs. Temperature
15 10 5 AVOL (dB) VCM (V) 0 -5
65-0213
120
T A = +25 C
100 80 60 40 20 0 -20 1 10 100 1K 10K 100K F (Hz) Figure 4. Open Loop Voltage Gain vs. Frequency 1M
65-0214
-10 -15 4 6 8 10 12 14 16
18
10M
VS (V) Figure 3. Input Common Mode Voltage Range vs. Supply Voltage
800K 140
VS = 15V VS = 15V
600K AVOL (V/mV) PC (mV)
120 100 80 60 0 +10 +20 +30 +40 +50 +60
65 0216
400K
RL = 2 k W
200K
65-0215
0
0
+10
+20
+30
+40
+50
+60
+70
+70
TA (C) Figure 5. Open Loop Voltage Gain vs. Temperature
TA (C) Figure 6. Power Consumption vs. Temperature
4
65-0212
RC4558
PRODUCT SPECIFICATION
Typical Performance Characteristics (continued)
15 10 5 VOUT (V) 0 -5
65-0217
T A = +25 C
-15 4
6
8
10
12
14
16
18
1.0 RL (kW)
10
+VS/-VS (V) Figure 7. Output Voltage Swing vs. Supply Voltage
Figure 8. Output Voltage Swing vs. Load Resistance
40 36 32 28 24 20 16 12 8 4 0 100
5
VS = 15V T A = +25 C RL = 2 k W
4 IQ (mA) 3
T A = +25 C
VOUT P-P (V)
2 1 0 0
65-0219
1K
10K F (Hz)
100K
1M
3
6
9 12 +VS/-VS (V)
15
18
Figure 9. Output Voltage Swing vs. Freqeuncy
Figure 10. Quiescent Current vs. Supply Voltage
28 24 20 VOUT (mV)
90% VS = 15V T A = +25 C RL = 2 k W C L = 100 pF
65-0221
12 8 4 0
VOUT (V)
16
0
0.25
0.50 Time (S)
0.75
1.00
1.25
0
10
20 30 Time (S)
40
Figure 11. Transient Response Output Voltage vs. Time
Figure 12. Follower Large Signal Pulse Response Output Voltage vs. Time
65-0222
10% Rise Time
10 8 6 4 2 0 -2 -4 -6 -8 -10
VS = 15V TA = +25 C
Output
Input
65-0220
65-0218
-10
RL = 2 k W
28 26 24 22 20 18 16 14 12 10 8 0.1
VS = 15V TA = +25 C
VOUT P-P (V)
5
PRODUCT SPECIFICATION
RC4558
Typical Performance Characteristics (continued)
100
VS = 15V T A = +25 C R S = 50 W A V = 60 dB
1000
VS = 15V T A = +25 C R S = 50 W A V = 60 dB
0
65-0223
en (nV/ Hz)
IN (pA/ Hz)
10
100
10
65-0224
0.1 1 10 100 F (Hz) 1K 10K
1 0 10 100 F (Hz) Figure 14. Input Noise Voltage Density vs. Frequency 1K 10K
100K
100K
Figure 13. Input Noise Current Density vs. Frequency
140 120 100 THD (%) CS (dB) 80 60 40
65-0225
0.6 0.5 0.4 0.3 0.2
VS = 15V TA = +25 C
VS = 15V R L = 2K A V = 40 dB f = 1 kHz RS = 1k W
20 0 10
0 1 2 3 4 5 6 7 8 9 VOUT (V RMS ) Figure 16. Total Harmonic Distortion vs Output Voltage
100
1K F (Hz)
10K
100K
10
Figure 15. Channel Separation vs. Frequency
0.6 0.5 THD (%) 0.4 0.3 0.2 0.1 0 10 100 1K
VOUT = 1 VRMS VS = 30V
10K
100K
F (Hz) Figure 17. Distortion vs. Frequency
6
65-0227
65 0226
0.1
RC4558
PRODUCT SPECIFICATION
Typical Applications
+VS +VS
2 3 4558A VIN 3 1 VOUT
8
4558A 2 4
1
100 W
5K
65-0228
65-0229
Figure 18. Voltage Follower
Figure 19. Lamp Driver
910K
+VS
2 100K 3 4558A 1 VOUT 91K A V = 10
65-0230
-VIN 10K +VREF
2 3 4558A 1 VOUT
100K
VIN
10M
65-0231
Figure 20. Power Amplifier
Figure 21. Comparator With Hysteresis
16K 100K VOUT 2 0.001F V IN 16K 2 1 1 0 0.01F
0.01F VOUT
+VS
4558A
4558A 3
1 100K
+VS
100K
3
4
100K 100K
65-0232
100K
65-0233
Figure 22. Squarewave Oscillator
Figure 23. DC Coupled 1kHz Low-Pass Active Filter
7
PRODUCT SPECIFICATION
RC4558
Typical Applications (continued)
1M VOUT 2 3 1M +VS 8 4558A 4 +VS 100K +VS 0.1F 10F 4 100K 10K 100K 10K 10 mF 100K 3 1 VIN 10K 100K +VS 2 4558A 4 1 VOUT
VIN 100K
65-0234
65-0236
Figure 24. AC Coupled Non-Inverting Amplifier
Figure 25. AC Coupled Inverting Amplifier
VIN
390K
0.01F +VS
120K 390K 2
VOUT
-VS 4558A 1 39K 6 8 4558B 5 4 7
6201/2
0.01 F 3
4
10F 620K 100K +VS 100K
65-0235
Figure 26. 1kHz Bandpass Active Filter
0.05 F 100K 100K +VC* 2 51K R/2 50K 4558A 3 5 51K +VS /2 VOUT 2 10K 4558B 1 51K 6 7 VOUT 1
* Wide control voltage range: 0V < VS < 2(+VS - 1.5VS)
65-0237
Figure 27. Voltage Controlled Oscillator (VCO)
8
RC4558
PRODUCT SPECIFICATION
Simplified Schematic Diagram
+VS (8) R1 8.7K Q5 Q10 Q14 (2,6) -Input +Input (3,5) D1 R5 50K C2 15 pF Q3 Q4 R3 5K R4 50K Q2 Q1 Q13 Q12 R7 27 Q15 Q9 Q11 5.8K R2 5K -VS (4)
65-0208
Q6
R6 27 120
Output (1,7)
Q7 Q8
D2
C1 15 pF
9
PRODUCT SPECIFICATION
RC4558
Ordering Information
Product Number RC4558M RC4558N RM4558D RM4558D/883B Temperature Range 0 to 70C 0 to 70C 0 to 70C -55C to +125C Screening Commercial Commercial Commercial Military Package 8 Pin Wide SOIC 8 Pin Plastic DIP 8 Pin Ceramic DIP 8 Pin Ceramic DIP
Note: 1. /883B suffix denotes MIL-STD-883, Par. 1.2.1 compliant device.
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS30004558 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC4559
Dual High-Gain Operational Amplifier
Features
* * * * Unity gain bandwidth - 4.0 MHz Slew rate - 2.0 V/mS Low noise voltage - 1.4 mVRMS Supply voltage - 22V for RM4559 and 18V for RC4559 * No frequency compensation required * * * * * No latch up Large common mode and differential voltage ranges Low power consumption Parameter tracking over temperature range Gain and phase match between amplifiers
Description
The RC4559 integrated circuit is a high performance dual operational amplifier internally compensated and constructed on a single silicon chip using an advanced epitaxial process. These amplifiers feature improved AC performance which far exceeds that of the 741-type amplifiers. The specially designed low-noise input transistors allow the RC4559 to be used in low-noise signal processing applications such as audio preamplifiers and signal conditioners. The RC4559 also has more output drive capability than 741-type amplifiers and can be used to drive a 600W load.
Block Diagram
Output (A) -Input (A) -Input (A) _ A + _ B + Output (B) -Input (B) -Input (B)
65-3473-01
Pin Assignments
+VS Output (A) Output (A)
8 1 2 3 4 5 7 6
1 2 3 4
8 7 6 5
65-3473-03
+VS Output (B) -Input (B) +Input (B)
Output (B) -Input (A) -Input (B) +Input (A) -VS
-Input (A)
+Input (A)
+Input (B)
65-3473-02
-VS
Rev. 1.0.0
PRODUCT SPECIFICATION
RC4559
Absolute Maximum Ratings
(beyond which the device may be damaged)1 Parameter Supply Voltage Input Voltage2 SOIC PDIP CerDIP TO-99 Junction Temperature Operating Temperature Lead Soldering Temperature Output Short Circuit Duration3 SOIC, PDIP CerDIP, TO-99 RM4559 RC4559 PDIP, CerDIP, T0-99 (60 sec) SOIC (10 sec) -55 0 RM4559 RC4559 Differential Input Voltage PDTA < 50C Min Typ Max 22 18 15 30 300 468 833 658 125 175 125 70 300 260 Indefinite C C C V V mW Units V
Notes: 1. Functional operation under any of these conditions is NOT implied. 2. For supply voltages less than 15V, the absolute maximum input voltage is equal to the supply voltage. 3. Short circuit may be to ground on one op amp only. Rating applies to +75C ambient temperature.
Matching Characteristics
(VS = 15V, TA = +25C unless otherwise specified) Parameter Voltage Gain Input Bias Current Input Offset Current Test Conditions RL 2 kW Typ 1.0 15 7.5 Units dB nA nA
2
RC4559
PRODUCT SPECIFICATION
Electrical Characteristics
(VS = 15V and TA = +25C unless otherwise specified) RM4559 Parameters Input Offset Voltage Input Offset Current Input Bias Current Input Resistance (Differential Mode) Large Signal Voltage Gain Output Voltage Swing RL 2kW, VOUT = 10V RL 10kW RL 2kW RL 600W Input Voltage Range Common Mode Rejection Ratio Power Supply Rejection Ratio Supply Current Transient Response Rise Time Overshoot Slew Rate Unity Gain Bandwidth Power Bandwidth Input Noise Voltage1 Input Noise Current Channel Separation VOUT = 20Vp-p F=20Hz to 20kHz F=20Hz to 20kHz Gain = 100, F = 10kHz, RS = 1kW RS 10kW VIN = 20 mV RL = 2kW CL 100pF 1.5 3.0 24 80 35 2.0 4.0 32 1.4 25 90 5.0 1.5 3.0 24 80 35 2.0 4.0 32 1.4 25 90 5.0 mS % V/mS MHz kHz mVRMS pARMS dB RS 10kW RS 10kW RL = 0.3 50 12 10 9.5 12 80 82 Test Conditions RS 10kW Min Typ 1.0 5.0 40 1.0 300 14 13 10 13 100 100 3.3 5.6 Max 5.0 100 250 0.3 20 12 10 9.5 12 80 82 Min RC4559 Typ 2.0 5.0 40 1.0 300 14 13 10 13 100 100 3.3 5.6 V dB dB mA Max 6.0 100 250 Units mV nA nA MW V/mV V
The following specifications apply for RM = -55C TA +125C, RC = 0 TA +70C Input Offset Voltage Input Offset Current Input Bias Current Large Signal Voltage Gain Output Voltage Swing Supply Current
Note: 1. Sample tested only.
6.0 300 500
7.5 200 300 15 10
mV nA nA V/mV V
RL 2kW, VOUT = 10V RL 2kW RL =
25 10 4.0 6.6
4.0
6.6
mA
3
PRODUCT SPECIFICATION
RC4559
Typical Performance Characteristics
100 80 IB (nA) 60 40 20 0
VS = 15V
25 20 IOS (nA) 15 10 5 0 0 +10 +20 +30 +40 +50 +60 TA (C) Figure 2. Input Offset Current vs. Temperature
VS = 15V
65-0211
0
+10
+20
+30
+40
+50
+60
+70
+70
TA (C) Figure 1. Input Bias Current vs. Temperature
15 10 5 AVOL (dB) VCM (V) 0 -5
65-0213
120
T A = +25 C
100 80 60 40 20 0 -20 1 10 100 1K 10K 100K F (Hz) Figure 4. Open Loop Gain Voltage vs. Frequency 1M
65-0214
-10 -15 4 6 8 10 12 14 16
18
10M
VS (V) Figure 3. Input Common Mode Voltage Range vs. Supply Voltage
800K 140
VS = 15V VS = 15V
600K AVOL (V/mV) PC (mV)
120 100 80 60 0 +10 +20 +30 +40 +50 +60
65-0216
400K
RL = 2 k W
200K
65-0215
0
0
+10
+20
+30
+40
+50
+60
+70
+70
TA (C) Figure 5. Open Loop Voltage Gain vs. Temperature
TA (C) Figure 6. Power Consumption vs. Temperature
4
65-0212
RC4559
PRODUCT SPECIFICATION
Typical Performance Characteristics (continued)
15 10 5 VOUT (V) 0 -5
65-0217
T A = +25 C
-15 4
6
8
10
12
14
16
18
1.0 RL (kW)
10
+VS/-VS (V) Figure 7. Output Voltage SWing vs. Supply Voltage
Figure 8. Output Voltage Swing vs. Load Resistance
40 36 32 28 24 20 16 12 8 4 0 100
5
VS = 15V T A = +25 C RL = 2 k W
4 IQ (mA) 3
T A = +25 C
VOUT P-P (V)
2 1 0 0
65-0219
1K
10K F (Hz)
100K
1M
3
6
9 12 +VS/-VS (V)
15
18
Figure 9. Output Voltage Swing vs. Frequency
Figure 10. Quiescent Current vs. Supply Voltage
28 24 20 VOUT (mV)
90% VS = 15V T A = +25 C RL = 2 k W C L = 100 pF
65-0221
12 8 4 0
VOUT (V)
16
10% Rise Time
10 8 6 4 2 0 -2 -4 -6 -8 -10 0 10
VS = 15V TA = +25 C
Output
Input
65-0222
0
0.25
0.50 Time (S)
0.75
1.00
1.25
20 30 Time (S)
40
Figure 11. Transient Response Output Voltage vs. Time
Figure 12. Follower Large Signal Pulse Response Output Voltage vs. Time
65-0220
65-0218
-10
RL = 2 k W
28 26 24 22 20 18 16 14 12 10 8 0.1
VS = 15V TA = +25 C
VOUT P-P (V)
5
PRODUCT SPECIFICATION
RC4559
Typical Performance Characteristics (continued)
100
VS = 15V T A = +25 C R S = 50 W A V = 60 dB
1000
VS = 15V T A = +25 C R S = 50 W A V = 60 dB
0
65-0223
en (nV/ Hz)
IN (pA/ Hz)
10
100
10
65-0224
0.1 1 10 100 F (Hz) 1K 10K
1 0 10 100 F (Hz) Figure 14. Input Noise Voltage Density vs. Frequency 1K 10K
100K
100K
Figure 13. Input Noise Current Density vs. Frequency
140 120 100 THD (%) CS (dB) 80 60 40
65-0225
0.6 0.5 0.4 0.3 0.2
VS = 15V TA = +25 C
VS = 15V R L = 2K A V = 40 dB f = 1 kHz RS = 1k W
20 0 10
0 1 2 3 4 5 6 7 8 9 VOUT (V RMS )
100
1K F (Hz)
10K
100K
10
Figure 15. Channel Separation vs. Frequency
Figure 16. Total Harmonic Distortion vs. Output Voltage
30 VOUT P-P (V) 10
VOUT P-P = 28V VOUT P-P = 18V VOUT P-P = 8V
VS = 15V VS = 10V
0.6 0.5 THD (%) 0.4 0.3 0.2
65-0239
VOUT = 1 VRMS VS = 30V
VS = 5V
01
0.1 0 10 100 1K F (Hz) Figure 18. Distortion vs. Frequency 10K
0.1 100
1K
10K F (Hz)
100K
1M
100K
Figure 17. Output Voltage Swing vs. Frequency
6
65-0227
(Voltage Follower) R L = Open C L = 50 pF
65-0226
0.1
RC4559
PRODUCT SPECIFICATION
Typical Applications
10K 620 Input 0.33F 0.33F 0.33 mF 20K 620W Output
1K
1K
2 1 4559A 3
6 5
7 4559B 1 4559A
2 3
6 4559B 5
7
0.33 mF
0.33F
1.62K
1.62K
1K
1K
0.33 mF
13.2K
65-0240
Figure 19. 400Hz Lowpass Butterworth Active Filter
V INA
V INB
2.2F 5K 0.068F 50K 5K 0.068F
2.2F 5K 0.068F 50K 5K 0.068F VS = 15V
0.068F 5K VOUTA 2 1 4559A 3 1.67K 10K 50K 50K 1.67K 0.068F 0.068F 5K
0.068F
6 4559B 5 10K
7
V OUTB
65-0241
Figure 20. Stereo Tone Control
7
PRODUCT SPECIFICATION
RC4559
Typical Applications (continued)
V INA 3 1 4559A 1M1/2 5F 2 6 4559B 47K 47K 1M 5F V INB 5 7 VS = 15V V OUTB
V OUTA
750 pF
750 pF
100K
0.0027F 1.2K 1.2K
0.0027F
100K
65-0242
Figure 21. RIAA Preamplifier
Threshold Detector 2 3 4559A 1 Amp. Freq. 140K 1.4K
Integrator C1 0.1F
6 5 4559B 7 VOUT
10K
1M 8.2K
65-0243
Figure 22. Triangular-Wave Generator
0.02F
Sine Output 0.01F 2 Cosine Output 7
22M
3 4559A 0.01F
1
10M
6 5 4559B
50K 22M FO = 1 Hz 6.3V 6.3V
65-0244
Figure 23. Low Frequency Sine Wave Generator with Quadrature Output
8
RC4559
PRODUCT SPECIFICATION
Simplified Schematic Diagram
+VS (8) R1 8.7K Q5 Q10 Q14 (2,6) -Input +Input (3,5) D1 R5 50K C2 15 pF Q3 Q4 R3 5K R4 50K Q2 Q1 Q13 Q12 R7 27 Q15 Q9 Q11 5.8K R2 5K -VS (4)
65-0208
Q6
R6 27 120
Output (1,7)
Q7 Q8
D2
C1 15 pF
9
PRODUCT SPECIFICATION
RC4559
Mechanical Dimensions
8-Lead Ceramic DIP Package
Inches Min. A b1 b2 c1 D E e eA L Q s1 a Max. Millimeters Min. Max. 8 2, 8 8 4 4 5, 9 7 3 6 Notes: Notes 1. Index area: a notch or a pin one identification mark shall be located adjacent to pin one. The manufacturer's identification shall not be used as pin one identification mark. 2. The minimum limit for dimension "b2" may be .023 (.58mm) for leads number 1, 4, 5 and 8 only. 3. Dimension "Q" shall be measured from the seating plane to the base plane. 4. This dimension allows for off-center lid, meniscus and glass overrun. 5. The basic pin spacing is .100 (2.54mm) between centerlines. Each pin centerline shall be located within .010 (.25mm) of its exact longitudinal position relative to pins 1 and 8. 6. Applies to all four corners (leads number 1, 4, 5, and 8). 7. "eA" shall be measured at the center of the lead bends or at the centerline of the leads when "a" is 90. 8. All leads - Increase maximum limit by .003 (.08mm) measured at the center of the flat, when lead finish applied. 9. Six spaces. D 4 1 Note 1 E
Symbol
-- .200 .014 .023 .045 .065 .008 .015 -- .405 .220 .310 .100 BSC .300 BSC .125 .200 .015 .060 .005 -- 90 105
-- 5.08 .36 .58 1.14 1.65 .20 .38 -- 10.29 5.59 7.87 2.54 BSC 7.62 BSC 3.18 5.08 .38 1.52 .13 -- 90 105
5 s1
8
e
eA
A Q L b2 b1 a c1
10
RC4559
PRODUCT SPECIFICATION
Mechanical Dimensions (continued)
8-Lead Plastic DIP Package
Inches Min. A A1 A2 B B1 C D D1 E E1 e eB L N -- .015 .115 .014 .045 .008 .348 .005 .300 .240 Max. .210 -- .195 .022 .070 .015 .430 -- .325 .280 Millimeters Min. -- .38 2.93 .36 1.14 .20 8.84 .13 7.62 6.10 Max. 5.33 -- 4.95 .56 1.78 .38 10.92 -- 8.26 7.11 Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E1" do not include mold flashing. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. Terminal numbers are for reference only. 4. "C" dimension does not include solder finish thickness. 5. Symbol "N" is the maximum number of terminals. 4 2
Symbol
2
.100 BSC -- .430 .115 .160 8
2.54 BSC -- 10.92 2.92 4.06 8 5
D 4 1
E1
D1
5
8
E e A A1 L B1 B eB A2 C
11
PRODUCT SPECIFICATION
RC4559
Mechanical Dimensions (continued)
8-Lead SOIC Package
Inches Min. A A1 B C D E e H h L N a ccc Max. Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
Symbol
.053 .069 .004 .010 .013 .020 .008 .010 .189 .197 .150 .158 .050 BSC .228 .010 .016 8 0 -- 8 .004 .244 .020 .050
1.35 1.75 0.10 0.25 0.33 0.51 0.20 0.25 4.80 5.00 3.81 4.01 1.27 BSC 5.79 0.25 0.40 8 0 -- 8 0.10 6.20 0.50 1.27
3 6
8
5
E
H
1
4
D A1 A SEATING PLANE B -C- LEAD COPLANARITY ccc C a
h x 45 C
e
L
12
RC4559
PRODUCT SPECIFICATION
Mechanical Dimensions (continued)
8-Lead Metal Can IC Header Package
oD Symbol oD1 A ob ob1 oD oD1 oD2 e e1 F k k1 L L1 L2 Q a Notes: e1 1. (All leads) ob applies between L1 & L2. ob1 applies between L2 & .500 (12.70mm) from the reference plane. Diameter is uncontrolled in L1 & beyond .500 (12.70mm) from the reference plane. 2. Measured from the maximum diameter of the product. 3. Leads having a maximum diameter .019 (.48mm) measured in gauging plane, .054 (1.37mm) +.001 (.03mm) -.000 (.00mm) below the reference plane of the product shall be within .007 (.18mm) of their true position relative to a maximum width tab. a 4. The product may be measured by direct methods or by gauge. 5. All leads - increase maximum limit by .003 (.08mm) when lead finish is applied. k k1 Inches Min. Max. Millimeters Min. Max. 1, 5 1, 5
Notes
L1
F
Q
A
L2 L
ob BASE and SEATING PLANE ob1
REFERENCE PLANE
.165 .185 .016 .019 .016 .021 .335 .375 .305 .335 .110 .160 .200 BSC .100 BSC -- .040 .027 .034 .027 .045 .500 .750 -- .050 .250 -- .010 .045 45 BSC
4.19 4.70 .41 .48 .41 .53 8.51 9.52 7.75 8.51 2.79 4.06 5.08 BSC 2.54 BSC -- 1.02 .69 .86 .69 1.14 12.70 19.05 -- 1.27 6.35 -- .25 1.14 45 BSC
2 1 1 1
e
oD2
13
PRODUCT SPECIFICATION
RC4559
Ordering Information
Product Number RC4559M RC4559N RC4559D RM4559D RM4559D/883B RM4559T RM4559T/883B Temperature Range 0 to 70C 0 to 70C 0 to 70C -55C to +125C -55C to +125C -55C to +125C -55C to +125C Screening Commercial Commercial Commercial Commercial Military Commercial Military Package 8 Pin Wide SOIC 8 Pin Plastic DIP 8 Pin Ceramic DIP 8 Pin Ceramic DIP 8 Pin Ceramic DIP 8 Pin TO-99 Metal Can 8 Pin TO-99 Metal Can
Note: 1. /883B suffix denotes MIL-STD-883, Par. 1.2.1 compliant device.
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS30004559 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC4560
Wide-Bandwidth Dual Operational Amplifier
Features
* * * * * * * * * * Unity gain bandwidth (AV = 1) -- 10 MHz Slew rate -- 4.0V/mS Noise voltage at 1 kHz -- 7.0nV/ Hz Noise voltage current at 1 kHz -- 0.4pA/ Hz 10V Output into 400W loads (25mA) Supply current per amplifier -- 1.8mA Input offset voltage -- 2.0mV Input offset current -- 5.0nA Unity gain frequency compensated Output short circuit protected
Description
The RC4560 integrated circuit is a high-gain, wide-bandwidth, dual operational amplifier capable of driving 20V peak-to-peak into 400W loads. The RC4560 combines many of the features of the RC4558 as well as providing the capability of wider bandwidth, and higher slew rate make the RC4560 ideal for active filters, data and telecommunications, and many instrumentation applications. The availability of the RC4560 in the surface mounted SOIC package allows it to be used in critical applications requiring very high packing densities.
Schematic Diagram (1/2 Shown)
+VS (8) R1 8.7K Q5 Q10 Q14 (2,6) Q2 Inputs Q12 (3,5) D1 R5 50K C2 15 pF Q3 Q4 R3 5K R4 50K R7 27 Q15 Q9 Q11 5.8K R2 5K -VS (4)
65-0208
Q6
Q1
Q13
R6 27 120
Output (1,7)
Q7 Q8
D2
C1 15 pF
Rev. 1.0.0
RC4560
PRODUCT SPECIFICATION
Pin Assignments
(Top View) 1 2 3 4 8 7 6 5
Pin Descriptions
Pin 1 2 3 4 5 6 7 8 Function A Output A -Input A +Input +VS B +Input B -Input B Output -VS
A B
Thermal Characteristics
SOIC Max. Junction Temp. Max. PDTA < 50C Therm. Res. QJC Therm. Res. QJA For TA > 50C Derate at 125C 300mW -- 240C/W Plastic DIP 125C 468mW -- 160C/W
4.17mW/C 6.25mW/C
Absolute Maximum Ratings
(beyond which the device may be damaged) Parameter Supply Voltage Input Voltage1 Differential Input Voltage Output Short Circuit Duration2 Operating Temperature Range Lead Soldering Temperature RC4560N RC4560M Max. 18V 15V 30V Indefinite -20C to +75C +300C +260C
Matching Characteristics
(VS = 15V, TA = +25C) Parameter Voltage Gain Input Bias Current Input Offset Current Input Offset Voltage RS 10 kW Conditions RL 2 kW Typ. 1.0 15 7.5 0.2 Units dB nA nA mV
Notes: 1. For supply voltages less than 15V, the absolute maximum input voltage is equal to the supply voltage. 2. Short circuit may be to ground on one amp only. Rating applies to +75C ambient temperature.
2
PRODUCT SPECIFICATION
RC4560
Electrical Characteristics
(VS = 15V and TA = +25C unless otherwise specified) Parameters Input Offset Voltage Input Offset Current Input Bias Current Input Resistance (Differential Mode) Large Signal Voltage Gain Output Voltage Swing Input Voltage Range Common Mode Rejection Ratio Power Supply Rejection Ratio Power Consumption Transient Response Rise Time Overshoot Slew Rate Channel Separation Unity Gain Bandwidth Input Offset Voltage Input Offset Current Input Bias Current Large Signal Voltage Gain Output Voltage Swing Power Consumption RL 2kW, VOUT = 10V RL 2kW TA = +75C TA = -20C 15 10 135 165 200 230 RS 10kW RS 10kW RL = VIN = 20 mV, RL = 2kW CL 100pF RL 2kW, Gain = 1 f = 10kHz RS = 1kW, Gain = 100 AV = +1, VO = -3dB RS 10kW RL 2kW, VOUT = 10V RL 10kW IO 25mA 0.3 20 12 10 12 70 76 Test Conditions RS 10kW Min. Typ. 2.0 5.0 50 0.1 300 14 11.5 13 90 90 135 0.05 35 4.0 100 10 7.0 300 800 200 V dB dB mW mS % V/mS dB MHz mV nA nA V/mV V mW Max. 6.0 200 500 Units mV nA nA MW V/mV V
The following specifications apply for -20C TA +75C
3
RC4560
PRODUCT SPECIFICATION
Typical Performance Characteristics
Input Bias Current vs. Ambient Temperature
100 Input Offset Current (nA) Input Bias Current (nA) 80 60 40 20 0
VS = 15V
Input Offset Current vs. Ambient Temperature
25 20 15 10 5 0 0 +10 +20 +30 +40 +50 +60 Temperature (C)
VS = 15V
65-0211
0
+10
+20
+30
+40
+50
+60
+70
+70
Temperature (C)
Common Mode Range vs. Supply Voltage
15 Common Mode Voltage (V) 10 5 0 -5
65-0213
Open Loop Voltage Gain vs. Frequency
120 100 Voltage Gain 80 60 40 20 0 -20 1 10 100 1K 10K 100K 1M
65-0214
TA = +25 C
-10 -15 4 6 8 10 12 14 16 18
10M
Supply Voltage (V)
Frequency (Hz)
Open Loop Gain vs. Temperature 800K
VS = 15V
Power Consumption vs. Ambient Temperature
200 Power Consumption (mW) 180 160 140 120 100 80 60 0 +10 +20 +30 +40 +50 +60
65-0216
600K Voltage Gain
VS = 15V
400K
RL = 2 k W
200K
65-0215
0
0
+10
+20
+30
+40
+50
+60
+70
+70
Temperature (C)
Temperature (C)
4
65-0212
PRODUCT SPECIFICATION
RC4560
Typical Performance Characteristics (continued)
Typical Output Voltage vs. Supply Voltage
15 10 Output Swing (V) 5 0 -5
65-0217
Output Voltage Swing vs. Load Resistance
28 26 24 22 20 18 16 14 12 10 8 0.1 Peak-to-Peak Output Swing (V)
T A = +25 C
VS = 15V TA = +25C
-15 4 6 8 10 12 14 16 Supply Voltage (V)
18
1.0 Load Resistance (kW)
10
Output Voltage vs. Frequency
40 36 32 28 24 20 16 12 8 4 0 100 Peak-to-Peak Output Swing (V) 10
RL = 2 k W R L = 40 k W VS = 15V T A = +25 C
Quiescent Current vs. Supply Voltage
Quiescent Current (mA)
8 6
TA = +25 C
4 2 0 0 3 6 9 12 Supply Voltage (V) 15 18
1K
10K Frequency (Hz)
100K
1M
65-0219
Transient Response
28 24 20 Output (mV) 16 12 8 4 0 0
10% Rise Time 90% VS = 15V T A = +25 C RL = 2 k W C L = 100 pF
65-0221
Voltage Follower Large Signal Pulse Response
10 8 6 4 2 0 -2 -4 -6 -8 -10 0 4
VS = 15V TA = +25C
Output Voltage (V)
Output
Input
65-0222
100
200 Time (nS)
300
400
500
8 Time (nS)
12
16
65-0220
65-0218
-10
RL = 2 k W
5
RC4560
PRODUCT SPECIFICATION
Typical Performance Characteristics (continued)
Input Noise Voltage vs. Frequency
1000 Noise Current (pA/ Hz) Noise Voltage (nV/ Hz)
VS = 15V TA = +25C
Input Noise Current vs. of Frequency
100
VS = 15V TA = +25C
100
10
10
65-0223
1
65-0224
1 1
10
100
1K
10K
100K
0.1 1 10 100 1K 10K Frequency (Hz)
100K
Frequency (Hz)
Channel Separation
140 120 100 80 60 40
65-0225
Total Harmonic Distortion vs. Output Voltage
Total Harmonic Distortion (%) 0.6 0.5 0.4 0.3 0.2
65-0226
Channel Separation (dB)
VS = 15V R L = 2K A V = 40dB f = 1kHz RS = 1k W
20 0 10
VS = 15V TA = +25C
0.1 0 1 2 3 4 5 6 7 8 9 VO Output Voltage (VRMS )
100
1K Frequency (Hz)
10K
100K
10
Distortion vs. Frequency
Total Harmonic Distortion (%) 0.6 0.5 0.4 0.3 0.2 0.1 0 10 100 1K Frequency (Hz) 10K
65-0227
VO = 1.0VRMS VS = 30V RIAA Compensation
100K
6
PRODUCT SPECIFICATION
RC4560
Notes
7
RC4560
PRODUCT SPECIFICATION
Notes
8
PRODUCT SPECIFICATION
RC4560
Notes
9
RC4560
PRODUCT SPECIFICATION
Mechanical Dimensions
Symbol A A1 B C D E e H h L N a ccc Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
.053 .069 .004 .010 .013 .020 .008 .010 .189 .197 .150 .158 .050 BSC .228 .010 .016 8 0 -- 8 .004 .244 .020 .050
1.35 1.75 0.10 0.25 0.33 0.51 0.20 0.25 4.80 5.00 3.81 4.01 1.27 BSC 5.79 0.25 0.40 8 0 -- 8 0.10 6.20 0.50 1.27
3 6
8
5
E
H
1
4
D A1 A SEATING PLANE B -C- LEAD COPLANARITY ccc C a
h x 45 C
e
L
10
PRODUCT SPECIFICATION
RC4560
Mechanical Dimensions
8-Lead Plastic DIP Package
Symbol A A1 A2 B B1 C D D1 E E1 e eB L N Inches Min. -- .015 .115 .014 .045 .008 .348 .005 .300 .240 Max. .210 -- .195 .022 .070 .015 .430 -- .325 .280 Millimeters Min. -- .38 2.93 .36 1.14 .20 8.84 .13 7.62 6.10 Max. 5.33 -- 4.95 .56 1.78 .38 10.92 -- 8.26 7.11 Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E1" do not include mold flashing. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. Terminal numbers are for reference only. 4. "C" dimension does not include solder finish thickness. 5. Symbol "N" is the maximum number of terminals. 4 2
2
.100 BSC -- .430 .115 .160 8
2.54 BSC -- 10.92 2.92 4.06 8 5
D 4 1
E1
D1
5
8
E e A A1 L B1 B eB A2 C
11
RC4560
PRODUCT SPECIFICATION
Ordering Information
Product Number RC4560M RC4560N Temperature Range -20 to +75C -20 to +75C Package 8-Lead SOIC 8-Lead Plastic DIP
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS30004560 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC4741
General Purpose Operation Amplifier
Features
* * * * * * * * * Unity gain bandwidth -- 3.5 MHz High slew rate -- 1.6 V/mS Low noise voltage -- 9 nV/OHz Input offset voltage -- 0.5 mV Input bias current -- 60 nA Indefinite short circuit protection No crossover distortion Internal compensation Wide power supply range -- 2V to 20V
Applications
* Universal active filters * Audio amplifiers * Battery powered equipment
Package
14 pin DIP
Description
The RC4741 is a monolithic integrated circuit, consisting of four independent operational amplifiers constructed with the planar epitaxial process. These amplifiers feature AC and DC performance which exceed that of the 741 type amplifiers. Its superior bandwidth, slew rate and noise characteristics make it an excellent choice for active filter or audio amplifier applications. A wide range of supply voltages (2V to 20V) can be used to power the RC4741, making it compatible with almost any system including battery powered equipment.
Block Diagram
Output (A) -Input (A) +Input (A) +Input (B) -Input (B) Output (B)
65-3474-01
Output (D) -Input (D) +Input (D) +Input (C) B C -Input (C) Output (C)
A
D
Rev. 0.9.1
PRODUCT SPECIFICATION
RC4741
Absolute Maximum Ratings
(beyond which the device may be damaged)1 Parameter Supply Voltage Input Voltage2 Differential Input Voltage PDTA < 50C PDIP CerDIP SOIC Output Short Circuit Duration3 PDIP, SOIC CerDIP Storage Temperature Operating Temperature Lead Soldering Temperature RM4741 RC4741 60 sec, DIP 10 sec, SOIC -65 -55 0 Junction Temperature Min Typ Max 20 15 30 468 1042 300 Indefinite 125 175 150 125 70 300 260 C C C C Units V V V mW
Notes: 1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded. 2. For supply voltages less than 15V, the absolute maximum input voltage is equal to the supply voltage. 3. Short circuit to ground on one amplifier only.
Operating Conditions
Parameter qJC Thermal resistance qJA Thermal resistance Min CerDIP PDIP CerDIP SOIC PDIP CerDIP SOIC Typ 60 160 120 200 6.25 8.38 5.0 Max Units C/W C/W
For TA > 50C Derate at
mW/C
2
RC4741
PRODUCT SPECIFICATION
Electrical Characteristics
(VS = 15V and TA = 25C unless otherwise specified) RM4741 Parameters Input Offset Voltage Input Offset Current Input Bias Current Input Resistance Large Signal Voltage Gain Input Voltage Range Output Resistance Output Current Common Mode Rejection Ratio Supply Current (All Amplifiers) Transient Response Rise Time Overshoot Slew Rate Unity Gain Bandwidth Power Bandwidth Input Noise Voltage Density Channel Separation VOUT = 20Vp-p, RL = 2k F = 1kHz VOUT 10V RS 10kW DV = 5 4.5 75 25 1.6 3.5 25 9.0 108 5.0 5.0 75 25 1.6 3.5 25 9.0 108 7.0 mA nS % V/mS MHz kHz nV/ OHz dB 5 80 RL 2kW, VOUT 10V 50 12 300 15 5 80 Test Conditions RS 10kW Min Typ 0.5 15 60 0.5 100 25 12 300 15 Max 3.0 30 200 Min RC4741 Typ 1.0 30 60 0.5 50 Max 5.0 50 300 Units mV nA nA MW V/mV V W mA dB
Electrical Characteristics
(VS = 15V, RM = -55 C TA +125 C, RC = 0C TA + 70C) RM4741 Parameters Input Offset Voltage Input Offset Current Input Bias Current Large Signal Voltage Gain Output Voltage Swing Supply Current (All Amplifiers) Average Input Offset Voltage Drift Common Mode Rejection Ratio Power Supply Rejection Ratio RS 10kW, DV 5.0V RS 10kW, DV 5.0V 74 80 5.0 74 80 5.0 mV/C dB dB RL 2kW VOUT 10V RL 10kW RL 2kW 12 10 13.7 12.5 10 12 10 13.7 12.5 10 mA 25 Test Conditions RS 10kW Min Typ 4.0 Max 5.0 75 325 15 Min RC4741 Typ 5.0 Max 6.5 100 400 Units mV nA nA V/mV
3
PRODUCT SPECIFICATION
RC4741
Typical Performance Characteristics
Open Loop Gain, Phase vs. Frequency PSRR vs. Temperature
180 1 10 100 1K 10K 100K 1M F (Hz) 10M
0 -100 -75 -50 -25
0 +25 +50 +75 +100+125 +150 TA (C)
Channel Separation vs. Frequency
-140 -120 -100 CS (dB) -80
1K 1K 2 3
100K
4741A
1
V OUT1 CS = 20 log V OUT2 100 VOUT1
-60 -40 -20 0 10 100 1K F (Hz) 10K 100K
65-0779
100K 1K 1K 6 5 4741B 7 V OUT2
Transient Response vs. Temperature
Input Noise Voltage vs. Frequency
1.3 Transient Response (Normalized to +25C) 1.2 en (nV/ Hz) 1.1 1.0 0.9 0.8
65-0781
35 30 25 20 15 10 5 0 10 100
en IN
1.4 1.2 1.0 0.8 0.6 0.4 0.2 10K 0 100K IN (PA/ Hz)
65-0782
0.7 0.6 -100 -75 -50 -25
0 +25 +50 +75 +100 +125 +150 TA (C)
1K F (Hz)
65-3474-02
4
65-0780
110 100 90 80 70 60 50 40 30 20 10 0
140 AVOL
R L = 2K C L = 55 pF
120 0 F (Deg) 45 90 135
65-0778
+VS -VS
100 PSRR (dB) 80 60 40 20
AVOL (dB)
F
RC4741
PRODUCT SPECIFICATION
Typical Performance Characteristics (continued)
Slew Rate, Bandwidth vs. Temperature Slew Rate, Bandwidth vs. Supply Voltage
SR, BW (Normalized to 15V)
12 SR, BW (Normalized to +25C)
1.1
BW
11
1.0
10
SR BW
65-0783
0.9
SR & BW
9
0.8
65-0784
8 -50
0.7
-25
0
+25
+50
+75 +100 +125
0 2
5
10 +VS/-VS (V)
15
20
TA (C)
Small Signal Phase Margin, Unity Gain Bandwidth vs. Load Capacitance
Output Voltage Swing vs. Frequency
70 60 50 FM (Deg) 40 30 20 10 0 10 100 1K CL (pF) 10K
BW FM R L = 2K
7 6 5 BW (MHz) VOUT P-P (V) 4 3 2 1 0 100K
65-0786
30 10
VOUT P-P = 28V VS = 15V VOUT P-P = 18V VS = 10V VOUT P-P = 8V VS = 5V VOUT P-P = 2V VS = 2V
1.0
0.1 100
1K
10K F (Hz)
100K
1M
Input Bias, Offset Current vs. Temperature
CMRR vs. Temperature
140 120 IB, IOS (nA) CMRR (dB) 100 80 60 40 20 0 -100 -75 -50 -25
65-0788
140 120 100
IB
80 60 40
65-0789
IOS
20 0 -100 -75 -50 -25
0 +25 +50 +75 +100 +125 +150 TA (C)
0 +25 +50 +75 +100 +125 +150 TA (C)
65-3474-03
65-0787
(Voltage Follower) R L = Open CL = 50 pF
5
PRODUCT SPECIFICATION
RC4741
Typical Performance Characteristics (continued)
Output Voltage Swing vs. Frequency
30 25 VOUT P-P (V) 20 15 10
65-0790
5 0 100 1K RL ( W) 10K
100K
Schematic Diagram (1/4 shown)
+VS (4) R1 4900 Q2 (2,6,9,13) - Input R9 30 Q4 + Input (3,5,10,12) R5 30K D2 Q5 Q13 Q12 Q16 R6 20 R8 50 R7 20 Q17 F1 To Next Amplifier (1,7,8,14) Q15 Output Q3 Q1
C1 15 pF Q7 Q8 R3 18K Q9 R4 22K Q10 Q11
Q6
Q14 R2 10K
D1 -VS (11)
65-0776
6
PRODUCT SPECIFICATION
RC4741
Ordering Information
Product Number RC4741M RC4741N RM4741D RM 4741D/883B Temperature Range 0C to +70C 0C to +70C -55C to +125C -55C to +125C Military Screening Commercial Package 14 pin Small Outline IC 14 pin Plastic DIP 14 pin Ceramic DIP 14 pin Ceramic DIP Package Marking
Note: /883B suffix denotes Mil-Std-883, Level B processing.
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 7/24/98 0.0m 002 Stock#DS30004741 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC4861
1/2W Audio Power Amplifier with Shutdown
Features
* * * * * * Low VOS, typically 2mV THD 0.3% typically at 0.5W output power Drives 8W and 4W non-powered speakers User programmable gain Internal thermal limiting circuitry 8 pin SOIC package
Description
The RC4861 sound driver is an audio device that can be used on PC motherboards and add-in sound cards. It consists of H-bridge connected output drivers for headphones or speakers.
Preliminary Information
Applications
* * * * * Multimedia PC motherboards and add-in sound cards Companion chip to sigma-delta sound codecs Low power portable systems Toys and games Cellular phones
The output drivers can deliver up to 0.5 Watt of continuous average output power into 8W speaker from a 5V source. The drivers use class AB amplifiers and maintain a low bias current. A shut down function disables the device for power savings when not in use. The thermal limiting circuitry becomes active if the chip temperature exceeds 150C.
Block Diagram
6 VDD 4 3 -IN
- 40 k1/2 40 k1/2 50 k1/2 - Av=-1 +
Vo1 5
+IN +
2 Bypass
VDD/2 50 k1/2
Vo2 8
1 Shutdown
Bias GND 7
65-4861-01
Rev. 0.9.3
PRELIMINARY INFORMATION describes products that are not in full production at the time of printing. Specifications are based on design goals and limited characterization. They may change without notice. Contact Fairchild Semiconductor for current information.
RC4861
PRODUCT SPECIFICATION
Pin Assignments
SHUTDOWN BYPASS +IN -IN
1 2 3 4 8 7 6 5
65-4861-02
VO2 GND VDD VO1
Absolute Maximum Ratings
Supply Voltage, VDD 6.0V 150C -65 to +150C 300C 2000V
Preliminary Information
Junction Temperature, TJ Storage Temperature, TS Lead Soldering Temperature, 10 seconds ESD Threshold, ESD (Human Body Model)
Note: 1. Functional operation under any of these conditions is not implied. Performance is guaranteed only if Operating Conditions are not exceeded
Operating Conditions
Parameter Power Supply, VDD Input Voltage Logic High, VIH Input Voltage Logic Low, VIL Ambient Operating Temperature, TA 0 Conditions Min. 2.7 VDD-0.8 Typ. 5.0 Max. 5.5 VDD 0.8 70 Units V V V C
2
PRODUCT SPECIFICATION
RC4861
Electrical Characteristics
VDD = 5V, f = 1kHz, RL = 8W, unless otherwise specified. Parameter AV ISS Itotal VOS PO THD PSRR Voltage Gain, Open Loop Shutdown current Power Supply Current, Output Offset Voltage RMS Output Power Total Harmonic Distortion Shutdown pin HIGH, VDD = 5V No load VIN = 0V RL = 8W, VDD = 5V fO = 1kHz, PO = 0.5W 65 0.5 0.3 75 1 Conditions Min. Typ. 90 0.6 6.5 2 10 10 20 Max. Units dB mA mA mV W % dB
Power Supply Rejection Ratio fO = 1kHz, DVDD = 0.2Vp-p Input Referenced 0.1 mF bypass cap
Preliminary Information
Typical Application Circuit
(Demo board is available for circuit in Figure 1).
Cf 5 pF Rf 20 k1/2 VDD +*CS Ci Ri 6 4- 3+ 2 7 1 5 8 RL 81/2
Audio Input
1.0 F 20 k1/2 *CB
**Shutdown GND
65-4861-03
Figure 1. Audio Amplifier with AVD = 2 * CS and CB size depend on specific application requirements and constraints. Typical values of CS and CB are 0.1 mF **Pin 1 should be connected to VDD to disable the amplifier or to GND to enable the amplifier. This pin should not be left floating.
3
RC4861
PRODUCT SPECIFICATION
Single Ended Application Circuit
Rf 20 k1/2 VDD +*CS Ci Ri 6 4- 3+ 2 7 1 5 8
CO + 220 F ***0.1F ***2 k1/2
65-4861-04
Audio Input
1 F 20 k1/2 *CB
RL 81/2
**Shutdown GND
Preliminary Information
Figure 2. Single Ended Amplifier with AV= -1 * CS and CB size depend on specific application requirements and constraints. Typical values of C S and CB are 0.1 mF **Pin 1 should be connected to VDD to disable the amplifier or to GND to enable the amplifier. This pin should not be left floating. ***These components create a "dummy" load for pin 8 for stability purposes.
External Components Description (for Figure 1)
Components Ri Ci Rf CS CB Cf Functional Description Inverting input resistance which sets the closed-loop gain in conjunction with Rf . This resistor also forms a high pass filter with Ci at fC = 1/(2p Ri Ci ). Input coupling capacitor which blocks DC voltage at the amplifier's input terminals. Also creates a highpass filter with Ri at fC = 1/(2p Ri Ci ). Feedback resistance which sets closed-loop gain in conjuncticn with Ri. Av = -Rf/Ri Supply bypass capacitor which provides power supply filtering. Bypass pin capacitor which provides half supply filtering. Used when a differential gain of over 10 is desired. Cf in conjunction with Rf creates a low-pass filter which bandwidth limits the amplifier and prevents high frequency oscillation bursts. fC = 1/(2p Rf Cf )
4
PRODUCT SPECIFICATION
RC4861
Typical Performance Characteristics
1.8 1.6 1.4 THD + N (%) THD + N (%) 1.2 1.0 0.8 0.6 0.4 0.2 0 10 20 50 75 100 200 100 200 500 500 10 20 50 75 1000 2500 1000 2500 5000 5000 10000 15000 10000 15000 20000 20000 Cb=1uF, Av=2 0.5 Cb=1uF, Av=10
THD+N vs. FREQUENCY
Cb=0.1uF, Av=2
2.5
THD+N vs. FREQUENCY
2.0
Cb=0.1uF, Av=10
1.5
1.0
FREQUENCY (Hz)
FREQUENCY (Hz)
Preliminary Information
THD+N vs. FREQUENCY
1.8 1.6 1.4 THD + N (%) THD+N (%) 1.2 1.0 0.8 0.6 0.4 0.2 0 10 20 50 75 100 200 500 1000 2500 5000 10000 15000 20000 Cb=1uF, Av=20 Cb=0.1uF, Av=20 0.1 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 20 60
THD+N vs. OUTPUT POWER
FREQ.= 1 KHz, Av=2, Cb=1uF
100
200
300
400
500
600
OUTPUT POWER (mW)
FREQUENCY (Hz)
THD+N vs. OUTPUT POWER
0.1 0.09 0.08 THD+N (%) 0.07 0.06 0.05 0.04 0.03 20 60 100 200 300 400 500 600 OUTPUT POWER (mW) SUPPLY CURRENT (mA) FREQ.=20KHz, Av=2, Cb=1uF 7.00 6.50 6.00 5.50 5.00 4.50 4.00 3.50 3.00 2.50 2.00 2.0
SUPPLY CURRENT vs. SUPPLY VOLTAGE (NO LOAD, Vpin 1 = 0 V)
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)
PSRR vs. FREQ.
(Power Supply Rejection Ratio) 85 80 75 70 PSSR (dB) 65 60 55 50 45 40 100 500 1000 5000 FREQUENCY (Hz) 10000 20000
5
RC4861
PRODUCT SPECIFICATION
Notes:
Preliminary Information
6
PRODUCT SPECIFICATION
RC4861
Mechanical Dimensions - 8-Lead SOIC Package
Symbol A A1 B C D E e H h L N a ccc Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
.053 .069 .004 .010 .013 .020 .008 .010 .189 .197 .150 .158 .050 BSC .228 .010 .016 8 0 -- 8 .004 .244 .020 .050
1.35 1.75 0.10 0.25 0.33 0.51 0.20 0.25 4.80 5.00 3.81 4.01 1.27 BSC 5.79 0.25 0.40 8 0 -- 8 0.10 6.20 0.50 1.27
3 6
Preliminary Information
8
5
E
H
1
4
D A1 A SEATING PLANE B -C- LEAD COPLANARITY ccc C a
h x 45 C
e
L
7
RC4861
PRODUCT SPECIFICATION
Ordering Information
Product Number RC4861M Package 8 pin SOIC
Preliminary Information
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS30004861 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
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RC5011
Step-up Regulator for Notebook Computers
Features
* Combines 5V precision linear regulator and boost-mode DC-DC converter * High efficiency - 85% typical * 6V to 22V input range (30V peak) * Independent output enable control * 10mA shutdown current * Operates with companion RC5023 to form complete notebook computer power supply * 8 pin SOIC package
Description
The RC5011 is a combination 5V precision linear regulator and switch-mode boost converter suitable for use in notebook PC power supplies. The 5V regulator can drive loads in excess of 40mA, while the boost converter can be used to provide 12V for Flash BIOS or PCMCIA requirements.
Advanced Information
Applications
* Complete notebook PC power supply when combined with RC5023 triple output DC-DC converter * Sub-notebooks and PDAs * PCMCIA and LCD panels
Operating over a 6V to 22V (30V peak) input range, the RC5011 can be used as a standalone IC acheiving switch mode efficiencies of up to 85%. The RC5011 can also be used with the Fairchild Semiconductor RC5023 triple output DC-DC converter to generate the 5V, 3.3V, 12V and 2.xV required for typical Pentium(R) notebook computers. When used with the RC5023, the RC5011 acts as an input stage that provides 5V for the RC5023 Vcc as well as 12V for BIOS or PCMCIA. Using this scheme, system efficiencies of 88% can be realized for the entire 4-output solution.
Block Diagram
+VBAT
RC5011
EN5V
+5V REGULATOR
VOUT
EN12V
INTERNAL REGULATOR & REFERENCE
OSC CX
DRV
1.25V
in+ in-
out
VFB
GND
Rev. 0.5.1
ADVANCED INFORMATION describes products that are in the planning or early design stage. Specifications may change in any manner without notice. Contact Fairchild Semiconductor for current information.
RC5011
PRODUCT SPECIFICATION
Pin Assignments
EN5V CX GND EN12V
1 2 3 4 8 7 6 5
65-5011-02
VBAT VOUT DRV VFB
Pin Descriptions
Pin Number Pin Name Pin Function Description 1 EN5V 5V output enable. TTL-compatible input disables 5V linear regulator when set to logic LOW. Serves as system global enable/disable when used with RC5023 companion IC. Oscillator timing capacitor. Connecting an external capacitor to this pin sets the internal oscillator frequency. Ground. Connect this pin to system ground so that ground loops are avoided. 12V output enable. TTL-compatible input disables the switch-mode converter when set to logic LOW. Voltage feedback. Input for the voltage feedback control loop. FET Driver output for switch-mode converter. Connect this pin to the gate of an N-channel MOSFET. The trace from this pin to the MOSFET gate should be as short as possible (<0.5"). 5V linear regulator output. Connect this pin to loads up to 40mA or to VCCL pin of RC5023 when used in the notebook computer power supply system. Battery Supply Voltage. Connect to system battery or other 6V to 30V source.
Advanced Information
2 3 4 5 6
CX GND EN12V VFB DRV
7 8
VOUT VBAT
Absolute Maximum Ratings1
Supply Voltage, VBAT Power Dissipation, TA < 50C Storage Temperature Junction Temperature Lead Soldering Temperature, 10 seconds
2
32V 300mW -65 to 150C 125C 300C
Notes: 1. Functional operation under any of these conditions is not implied. Performance is guarenteed only if Operating Conditions are not exceeded.
2. For TA > 50C, derate at 4.2mW/C.
Operating Conditions
Parameter Supply Voltage, VBAT Input Logic HIGH Input Logic LOW Ambient Temp Min 6 2 0 Typ Max 30 0.8 70 Units V V V C
2
PRODUCT SPECIFICATION
RC5011
Electrical Characteristics - Switch-mode Converter
VBAT = 6V, Fosc = 50KHz, TA = 0 to 70C using circuit in Figure 1, unless otherwise noted. Parameter Output Voltage Output Driver Voltage Swing Line Regulation Load Regulation Output Ripple/Noise Reference Voltage Efficiency Operating Frequency Range Oscillator Frequency Precision Capacitor Charging Current Capacitor Threshold Voltage + Capacitor Threshold Voltage - Feedback Input Current VFB = 1.25V 4.0 VBAT = 6V to 22V IL = 0 to 200mA IL = 200mA, BW = 20MHz Internal Reference 1.19 80 1.0 10 8.0 1.4 0.5 0.1 Conditions Set by external resistors Min. 12 4.5 0.2 0.1 100 1.25 85 75 0.4 0.2 250 1.37 Typ. Max. 30 Units V V % % mV V % KHz % mA V V mA
Advanced Information
Electrical Characteristics - Linear Regulator
VBAT = 6V, TA = 0 to 70C using circuit in Figure 1, unless otherwise noted. Parameter Output Setpoint Accuracy Line Regulation Load Regulation Output Temperature Drift 1 Cumulative DC Accuracy Output Drive Current Conditions No Load VBAT = 6V to 22V IL = 0 to 40mA IL = 40mA Min. Typ. 3 +0.4 -1.0 +100 Max. +0.8 -2.5 +150 5 40 Units % % % ppm/C % mA
Note: 1. Cumulative DC Accuracy includes Setpoint Accuracy, Line/Load Regulation and Temperature Drift.
Electrical Characteristics - Common
VBAT = 6V, Fosc = 50KHz, TA= 25C using circuit in Figure 1, unless otherwise noted. Parameter Supply Current Conditions VBAT = 6 to 22V, No load VBAT = 6V, EN5V LOW VBAT = 6V, EN12V = LOW Vbat = 6V, EN5V = EN12V = LOW Min. Typ. 1.5 0.8 0.5 0.5 Max. 2.5 1.5 1.5 1.5 Units mA mA mA mA
3
RC5011
PRODUCT SPECIFICATION
Test Circuit
5VIN VBAT L1 10H 1 2 3 4 RC5011 EN5V CX GND EN12V VBAT VOUT DRV VFB 8 7 6 5 R7 13.3K IN5817 M1 Si9410 R6 110K C1 300F +5V D1 +12V
EN5V EN12V
CX 100pF
Advanced Information
Figure 1. Standard Test Circuit Schematic
Application Information
Step-Up (Boost mode) Converter
A complete schematic of the minimum step-up converter application is shown in Figure 1. Upon application of power (VBAT) and a logic high signal on the EN5V pin, the fixed 5V precision bandgap reference will become active and source up to 40mA of load current. If the 5V regulator is not needed, a logic low on the EN5V pin will disable the 5V regulator and reduce the supply current, thus minimizing power consumption. A 1mF capacitor connected from the 5V output to ground is recommended to reduce noise on the 5V output. A logic high signal placed on the EN12V pin enables the switch mode regulator. Included in the switch-mode controller is a precision bandgap regulator that generates both a 1.25V reference and a 4V reference internally. The 4V reference is effectively "filtered " from the VBAT supply to increase the power supply rejection of the IC, thus making it less susceptable to changes in the battery voltage and noise. The 1.25V reference is used for comparison against the divided down output voltage occuring at the voltage feedback (VFB) input. A voltage supply connected to one side of the inductor as shown will cause the filter capacitor to instantaneously charge to VBAT -VF, where VF is the forward voltage of the blocking diode. The voltage on the output capacitor C1 is also applied to resistor voltage divider R6 and R7, where the ratio of these resistors determines the final output voltage. The VFB node is connected to one side (-input) of a voltage comparator and the other side (+input) is connected to the 1.25V reference. If the voltage across C1 is less than the programmed value set by the ratio of R6 and R7, the output of the comparator will be at logic high.
One input of a NAND logic gate is connected to the comparator output, while the other NAND input is connected to the oscillator output. A logic high will allow the NAND output to respond to the oscillator input, thus allowing the totem-pole inverter to pulse the gate of the external N-channel MOSFET. The totem-pole inverter is referenced to VBAT since this higher voltage will allow a higher gate drive and reduce the RDS,ON value of the MOSFET. When the FET is turned on, the inductor conducts current to ground through the FET. When the FET is turned off, diode D1 charges the output capacitor C1. The VFB node will continuously monitor the output voltage and allow the oscillator to drive the MOSFET until the voltage at VFB surpasses the internal 1.25V reference voltage. At this time the output of the comparator switches to a logic low state, which forces the NAND output high. The totem-pole inverter will then transition low and turn off the MOSFET. Because the output voltage is now higher than VBAT, the blocking diode prevents any further current flow into the output capcitor or the load. This condition will remain until the output voltage drops enough to lower the VFB node below 1.25V, at which time the process starts again. Using this system, the feedback network will vary the MOSFET duty cycle in response to changes in load current or battery voltage. The inductor value and oscillator frequency must be carefully tailored to the battery voltage, output current, and ripple requirements of the application. If either the inductor value or the oscillator frequency is too high, the inductor current will never reach a value high enough to meet the load current drain and the output voltage will collapse. If the inductor value or the oscillator frequency is too low, the inductor current will become excessive, causing higher output voltage ripple, inductor core saturation, or MOSFET destruction due to over-stress.
4
PRODUCT SPECIFICATION
RC5011
Design Equations
The inductor (L1) and timing capacitor (CX) values must be tailored to the input voltage range, output voltage, and load current requirements of the application. The key to the problem is to select the correct inductor value for a given oscillator frequency such that the inductor current rises to a peak value (Imax) sufficient to meet the average load current drain. The worst-case conditions for calculating its ability to supply load current are found at the minimum supply voltage. Therefore, VBAT,MIN is used to calculate the inductor value. Conversely, the worst-case condition for output voltage ripple will occur at VBAT,MAX. The value of the timing capacitor is set according to the following equation: FO(Hz) = (5 x 10-6)/Cx The output of the oscillator is measured at pin 2 (CX) and the voltage at the CX pin will be a triangle waveform. By pulling the VFB pin above 1.25V, the oscillator square wave output can be measured directly at pin 6 (DRV). Capacitor selection will depend on the specific application; higher operating frequencies will reduce the output voltage ripple and will allow the use of an inductor with a physically smaller inductor core, but excessively high frequencies will reduce load driving capability and efficiency. Maximum on time of the MOSFET is calculated as follows: Ton = 1/2FO + 0.5mS
The 0.5mS term is added to represent the MOSFET gate-discharge time, although it is an approximation only and should be checked for the specific MOSFET used. The peak inductor current is:
V OUT + V F - V BAT I MAX = ae ------------------------------------------------------------------o 2IDC e ( F O )T on [ V BAT - V DS, ON ]o
where: VBAT VF IDC VDS,ON = supply voltage = diode forward voltage = dc load current = drain-source on voltage of MOSFET
Inductor value:
Advanced Information
V BAT - V DS, ON LX ( Henries ) = ae ----------------------------------------o TON e o I MAX
Output filter capacitor:
V BAT I MAX T ON ae ---------------------------- + IDCo e V OUT o C1 ( mF ) = -----------------------------------------------------------V RIPPLE
where VRIPPLE = Peak output voltage ripple To reduce system power consumption when the switch-mode section is not in use, the circuit shown in Figure 2 is recommended. This circuit prevents any load connected to VOUT from drawing current out of VBAT.
5VIN VBAT R1 40K
100K R2 RC5011 EN5V EN12V 1 2 CX 100pF 3 4 EN5V CX GND EN12V VBAT VOUT DRV VFB 8 7 6 5 R7 13.3K R3 40K
Q1 2N2222
L1 10H D1 +12V IN5817 +5V M1 Si9410 R6 110K C1 300F
Figure 2. Standard Test Schematic with 12V Shutdown Circuit added
5
RC5011
PRODUCT SPECIFICATION
Notebook Power Supply Application
RC5011/RC5023 System
The RC5011/RC5023 Portable Power Supply System is designed to cost-effectively address the notebook computer power supply requirements. The RC5011 generates the +12V power supply while also providing the startup 5V supply current for the RC5023. The RC5011 is designed on a high voltage technology which can support battery voltages as high as 32V. The 5V linear regulator from the RC5011 rejects the large potential battery voltage changes and provides a well-regulated +5V to power the RC5023. To optimize efficiency, the RC5023 utilizes an internal 5V switch to remove the +5V supply coming from the RC5011 and to then utilize the efficient +5V switcher output to supply the power for the digital logic, analog control circuitry, and output drivers of the RC5023.
The RC5023 has an internal comparator which senses the difference between the regulator 5V from the RC5011 and the output of the 5V switch-mode regulator. When the switch-mode regulator output exceeds 4.5V, the comparator commands the analog switch within the RC5023 to convert the +5V supply source from the RC5011 to the +5V switchmode output. Thus, power is now drawn from the 88% efficient switch-mode regulator rather than the less efficient 5V linear regulator in the RC5011. The 5V linear regulator in the RC5011 remains connected to the RC5023 and continues to power both the bandgap reference as well as the 5Vswitch comparator; however the current consumption of these blocks is small and will not have a significant effect on the overall efficiency of the power supply system.
Advanced Information
RC5011 OSC +12V RC5023 VBAT Docking AC EN12V System Battery 6-22V Adaptor AC Bat AC ON Power Management Unit EN5V EN5 EN3.3 +2.9V EN2.9 VREF 5V LIN 5V Switch +5V OSC +3.3V +3.3V (Logic) +2.9V (CPU) +5V (Disk) VREF +12V (PCMCIA)
AC DET
Low Bat
Figure 3. Notebook Computer Power Supply System using the RC5011 and RC5023
6
PRODUCT SPECIFICATION
RC5011
6V-30V VBAT
+ C22 33F GND C12 33F GND + D3
5V + C9 4.7F GND CV 100nF + C5V 10F C10 4.7F GND + D4 D2 + C8 4.7F GND + C11 33F GND GND 2.9V OUTPUT ENABLE EN2
EN3
+3.3 OUTPUT ENABLE
C5 1 2 3 C6 100pF X4 4 5 6 7 8 X5 9 10 11 12 13 GND 14 RC5023
EN3 IFB3 VFB3 FETOP3 HIDRV3 VCCQP3 PGND3 VCCSW LDRV3 VCCL VFB5 REF VSS IFB5 EN2 IFB2 VFB2 VFBR2 FETOP2 HIDRV2 VCCOP2 LDRV2 GNDP LDRV5 FETOP5 HIDRV5 VCCQP5 EN5
28 27 26 25 24 23 22 21 20 19 18 17 16 15 X7 GND C7 100F X6
0.1F
X2
L2 9.4H
R2 +2.9V 12m R8 3.3K 2.5V + C2 660F
R3 +3.3V L1 10H
LINEAR 5V OUTPUT ENABLE
L3 9.4H
12m + C3 660F GND
D6
X3 C13 33F GND L4 9.4H D7
D5
5V LINEAR REGULATOR OUTPUT
R9 19.4K
CL1 + 4.7F 2.5V REF GND
Advanced Information
GND R4 12m + C4 660F +5V
+12V OUTPUT ENABLE
U2
EN12V
EN5V 1 2 3 GND CX 100pF 4
EN5V VBAT CX VOUT RC5011 VSS DRV EN12V VFB U1
8 7 6 5 R7 13.3K D1 X1 R6 110K + C1 300F EN5 +5V OUTPUT ENABLE +12V
GND
Figure 4.
RC5023/RC5011 Power Supply System Bill of Materials
Reference L2-L4 X2-X7, X1 D5-D7 D2-D4, D1 R2-R4 C2-C4 C5-C7, CV C8-C10, CLI C11-C13, C22 C5V R8 R9 RC5023 L1 C1 CX R6 R7 RC5011 Qty 3 7 3 4 3 6 4 4 4 1 1 1 1 1 2 1 1 1 1 Specification 9.4mH, 2.8A Inductors N-channel MOSFETs 3.3A, 20V SMT diodes 1.1A, 20V SMT diodes 1 watt 12m ohm, 1% resistors 330mF, 10V tantalum capacitors 0.1mF, 16V ceramic capacitors 4.7mF, 10V tantalum capacitors 33mF, 35V tantalum capacitors 10mF, 10V tantalum capacitors 3.3K ohm, 0.1% resistor 19.4K ohm, 0.1% resistor Triple-Output DC-DC Converter 10mH, 2.65A inductor 100mF, 20V tantalum capacitor 100pF, 16V ceramic capacitor 110K ohm, 1% resistor 133K ohm, 1% resistor 12V Complement of RC5023 CDRH125 595D107X0020R2T GRM40C0G101J050BD Part No. PE-53631 Si4410DY NSQ03A02L EC10QS02L LRC-2512 595D337X0010R2T GRM40X7R104K025BL NR Series 595D336X0035R2T NR Series Manufacturer Pulse Engineering Siliconix Nihon Nihon IRC Sprague Murata NEC Sprague NEC Panasonic Panasonic Fairchild Semiconductor Sumida Sprague Murata Panasonic Panasonic Fairchild Semiconductor
7
RC5011
PRODUCT SPECIFICATION
Ordering Information
RC5011M 8 pin SOIC
Advanced Information
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonable expected to result in a significant injury of the user.
Fairchild Semiconductor Corporation Americas Customer Response Center Tel:1-888-522-5372 Fairchild Semiconductor Europe Fax: Email: Deutsch Tel: English Tel: Italy Tel: +49 (0) 1 80-530 85 86 europe.support@nsc.com +49 (0) 8 141-35-0 +44 (0) 1 793-85-68-56 +39 (0) 2 57 5631
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
Fairchild Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Center, 5 Canto Rd. Tsimshatsui, Kowloon Hong Kong Tel:+852 2737-7200 Fax:+852 2314-0061
National Semiconductor Japan Ltd. Tel:81-3-5620-6175 Fax:81-3-5620-6179
www.fairchildsemi.com 2/98 0.0m Stock#DS30005011 O 1998 Fairchild Semiconductor Corporation
www.fairchildsemi.com
RC5011/RC5023 Demonstration Board
Power Supply Solution for Notebook Computers
Features
* * * * * Output voltages 5V, 12V, 3.3V and 2.9V >93% System efficency 6V to 30V operation Independent output enable/disable Global power-down for low power sleep mode
Description
The RC5011/RC5023 demonstration board is intended to assist designers in developing an efficient, low cost power system for notebook computers using the RC5011 and RC5023 voltage regulator ICs. The demo board accepts an input voltage from 6V to 30V for battery operation. Using both regulators, the demo board outputs four unique voltages required by most portable PC systems; 12V for flash bios, 5V for digital logic, 3.3V for RAM and other logic and 2.9V for the CPU. Using synchronous operation on all but the 12V output, the system can realize efficiencies in excess of 93% for extended battery life. Independent output enable functions as well as a global power-down allow for a multitude of low power sleep modes.
Advanced Information
Block Diagram
RC5011 OSC +12V RC5023 VBAT Docking AC EN12V System Battery 6-22V Adaptor AC Bat AC ON Power Management Unit EN5V EN5 EN3.3 +2.9V EN2.9 VREF 5V LIN 5V Switch +5V OSC +3.3V +3.3V (Logic) +2.9V (CPU) +5V (Disk) VREF +12V (PCMCIA)
AC DET
Low Bat
Rev. 0.5.1
ADVANCED INFORMATION describes products that are in the planning or early design stage. Specifications may change in any manner without notice. Contact Fairchild Semiconductor for current information.
RC5011/5023
DEMONSTRATION BOARD
Jumper Settings
The board is fitted with several jumpers to enable each output as well as the entire power supply system. The jumper settings are presented in Table 1 and their locations are illustrated in Figure 2. Each jumper has three posts mounted perpendicular to the board. The middle post is connected to appropriate the IC control pin, with the outer two pins connected to VCC and GND, respectively. The output is disabled by connecting the jumper between the center post and VCC and is disabled by connecting it between the center post and GND. The absence of a jumper will disable the output.
Power-up Check List
1. 2. 3. Set up the jumpers as illustrated in Table 1, above. Connect the positive power lead to the Vbat terminal. Connect the positive lead of external 5V source to the single post between the EN12V jumper and the +3.3V OUT posts. Connect the negative power lead to one pair of GND terminals (two pairs exist). Connect the negative lead of the external 5V to a pair of GND terminals. Connect loads to desired outputs. Returns from the loads may be connected to either pair of GND terminals. Apply power and check for correct output voltages. If no output is observed, turn off power and check all connections again.
4. 5.
Table 1. Jumper Settings for RC5011 + RC5023 Demonstration Board
6. 7.
Advanced Information
Active Output 2.9V 3.3V 5V 12V
Jumper Designation EN2 EN3 EN5 EN12V EN5
Jumper Position VCC VCC VCC VCC VCC
NOTE: Both the EN12V and the EN5 jumpers must be connected to Vcc in order to enable the 12V output.
Precautions
* Beware of ESD! It is recommended that this demonstration board be used only in an ESD-controlled location to reduce the risk of damage resulting from ESDrelated stress. * Use Kelvin connected test points. Voltage drops in the main current path can greatly reduce the observed efficiency characteristics of this demonstration board. * Do not attempt to draw more than 200mA from the 12V output. Overloading this output will result in permanent damage to the RC5011.
2
6V-30V VBAT VCCP
+ C22
33F VCCSW
GND
DEMONSTRATION BOARD
C12 D3 C10 CV GND GND GND GND C5 1
EN3 IFB3 VFB3 FETOP3 VFBR2 VFB2 IFB2 EN2
+ + C9 + 4.7F 33F + C11 D4 + C8 D2 4.7F + 4.7F GND C5V 100nF 10F
5V
33F GND
CONTROL INPUT FOR +2.X [V] EN2
EN3 2 3 4 X2 5
HIDRV3 VCCQP3 PGND3 VCCSW LDRV3 VCCL VFB5 REF VSS IFB5 EN5 VCCQP5 HIDRV5 FETOP5 LDRV5 GNDP LDRV2 VCCOP2 HIDRV2 FETOP2
CONTROL OUTPUT FOR +3.3V RC5023 28 27 26 25 24 23 22 21 20 19 18 17 16 15 X7 GND C7 100F X6 X3 C13 33F GND L1 9.4H D7 0.1F
+3.3V X4 D6 X5 9 11 12 13 GND U2 HIDRV5 8 7 D1 +12V +12V_OUT R6 R70 13.25K 116K + C1 200F 6 5 14
5V LINEAR REGULATOR OUTPUT 10
R3 6 GND 5V 8 7
1.3 9.4H
C6 100pF
L2 9.4H
R2 12m R8
+2.X [V]
OUT 29 + C2 2.5V R9 660F
OUT33 12m + C3 660F GND CL1 + 2.5V 4.7F REF GND
L1 10H
GND R4 12m + C4 660F +5V OUT
CONTROL INPUT FOR LINEAR +5V OUT
CONTROL INPUT FOR +12V OUT
Figure 1. RC5011/5023 Demo Board Application Schematic
EN5 CONTROL INPUT FOR +5V GND
EN12V
EN5V 1
EN5V VBAT
2
3
VOUT CX RC5011 DRV VSS
GND
4
EN12V VFB
RC5011/5023
CX 220pF
U1
Advanced Information
3
RC5011/5023
DEMONSTRATION BOARD
5023
Advanced Information
Figure 2. RC5011/RC5023 Demo Board Layout Table 2. RC5011/5023 Demo Board Application Bill of Materials
Reference L2 - L4 X2 - X7, X1 D5 - D7 D1 - D4 R2 - R4 C2 - C4 C5 - C7,CV C8 - C10,CLI C11- C13,C22 C5V R8 R9 RC5023 L1 C1 CX R6 R7 RC5011
Description 9.4uH, 2.8A Inductors N-channel MOSFETs 3.3A, 20V SMT diodes 1.1A, 20V SMT diodes 1 watt, 12mW, 1% resistors 330mF, 10V tantalum capacitors 0.1mF, 16V ceramic capacitors 4.7mF, 10V tantalum capacitors 33mF, 35V tantalum capacitors 10uF, 10V tantalum capacitor 20KW, 0.1% resistor 100KW, 0.1% resistor Triple DC-DC controller IC 10mH, 2.65A inductor 100mF, 20V tantalum capacitor 100pF, 16V ceramic capacitor 116KW, 1% resistor 13.25KW, 1% resistor 12V step-up controller IC
Part No. PE-53631 Si4410DY NSQ03A02L EC10QS02L LRC-2512 595D337X0010R2T GRM40X7R104K025 NR Series 595D336X0035R2T NR Series
Manufacturer Pulse Engineering Siliconix Nihon Nihon IRC Sprague muRata NEC Sprague NEC Panasonic Panasonic Fairchild Semiconductor
Qty 3 7 3 4 3 6 4 4 4 1 1 1 1 1 2 1 1 1 1
CDRH125 595D107X0020R2T GRM40C0G101J050
Sumida Sprague muRata Panasonic Panasonic Fairchild Semiconductor
4
DEMONSTRATION BOARD
RC5011/5023
Additional Information
For technical assistance regarding this demonstration board, please contact Fairchild Semiconductor Applications department at (415) 966-7779. For additional product information, please contact Fairchild Semiconductor Marketing at (415) 962-7982. Individual product data sheets can also be obtained by calling Fairchild Semiconductor' automated RayFAX system at (415) 988-2123.
Advanced Information
5
RC5011/5023
DEMONSTRATION BOARD
Notes:
Advanced Information
6
RC5011/5023
DEMONSTRATION BOARD
Notes:
Advanced Information
7
DEMONSTRATION BOARD
RC5011/5023
Advanced Information
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonable expected to result in a significant injury of the user.
Fairchild Semiconductor Corporation Americas Customer Response Center Tel:1-888-522-5372 Fairchild Semiconductor Europe Fax: Email: Deutsch Tel: English Tel: Italy Tel: +49 (0) 1 80-530 85 86 europe.support@nsc.com +49 (0) 8 141-35-0 +44 (0) 1 793-85-68-56 +39 (0) 2 57 5631
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
Fairchild Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Center, 5 Canto Rd. Tsimshatsui, Kowloon Hong Kong Tel:+852 2737-7200 Fax:+852 2314-0061
National Semiconductor Japan Ltd. Tel:81-3-5620-6175 Fax:81-3-5620-6179
www.fairchildsemi.com 2/98 0.0m Stock#DS30005011 O 1998 Fairchild Semiconductor Corporation
www.fairchildsemi.com
RC5031
Adjustable Switching Regulator
Features
* High power switched-mode DC-DC controller can source in excess of 13A * Output voltage adjustable from 1.5V to 3.6V * 85% efficiency * Cumulative accuracy < 3% over line, load, temperature and transient variations * Overvoltage and short circuit protection * Built-in soft start
Description
The RC5031 is a high power, switch-mode DC-DC controller that provides an accurate, adjustable output for high-end microprocessors requiring unique supply voltages. The RC5031 has built-in Soft Start feature which offers system protection during power-up by reducing both inrush current and output overshoot. When combined with the appropriate external circuitry, the RC5031 can deliver load currents as high as 13A at efficiencies as high as 88%. Through the use of external resistors, the RC5031 can generate output voltages from 1.5V up to 3.6V. The RC5031 is designed to operate in a "constant on-time" (patent pending) control mode under all load conditions. Its accurate low TC reference eliminates the need for precision external components in order to achieve the tight tolerance voltage regulation required by most CPU-based applications. Short circuit current protection is provided through the use of a current sense resistor, while overvoltage protection is provided internally. The RC5031 is a highly efficient switched-mode DC-DC converter that can select a 3.5V or user-adjustable output. With the appropriate external components, the RC5031 can be configured to implement a switchable power supply system for Pentium and K6 processors.
Preliminary Information
Applications
* Precision 2.xV CPU core regulator for Intel Pentium(R) MMXTM processors * Precision 2.xV or 3.xV CPU core regulator for AMD-K6TM MMX and Cyrix 6x86MXTM (M2) processors
Block Diagram
+12V +5V
SWITCHING REGULATOR
FEEDBACK CONTROL
OSCILLATOR
DIGITAL LOGIC SUPPLY VOLTAGE FOR CPU CORE
1.5V REFERENCE
RC5031
VREF
Pentium is a registered trademark of Intel Corporation. MMX is a trademark of Intel Corporation. K6 is a trademark of AMD Corporation. 6x86MX is a trademark of Cyrix Corporation.
65-5031-01
Rev. 0.9.3
PRELIMINARY INFORMATION describes products that are not in full production at the time of printing. Specifications are based on design goals and limited characterization. They may change without notice. Contact Fairchild Semiconductor for current information.
RC5031
PRODUCT SPECIFICATION
Functional Description
The RC5031 contains a precision trimmed zero TC voltage reference, a constant-on-time architecture controller, a high current switcher output driver, a low offset op-amp, and switches for selecting various output modes. The block diagram in Figure 1 shows how the RC5031 in combination with the external components achieves a switchable power supply.
High Current Output Drivers
The RC5031 switching high current output driver (SDRV) contains high speed bipolar power transistors configured in a push-pull configuration. The output driver is capable of supplying 0.5A of current in less than 100ns. The driver's power and ground are separated from the overall chip power and ground for added switching noise immunity.
Internal Reference
The reference in the RC5031 is a precision band-gap type reference. Its temperature coefficient is trimmed to provide a near zero TC. For guaranteed stable operation under all loading conditions, a 0.1mF capacitor is recommended on the VREF output pin.
Switch-Mode Control Loop
The main control loop for the switch-mode converter consists of a current conditioning amplifier and one of the two voltage conditioning amplifiers that take the raw voltage and current information from the regulator output, compare them against the precision reference and present the error signal to the input of the constant-on-time oscillator. The two voltage conditioning amplifiers act as an analog switch to select between the internal resistor divider network (set for 3.5V) or an external resistor divider network (adjustable for 1.5V to 3.6V.) The switch-mode select pin determines which of the two amplifiers is selected. The current feedback signals come across the Iout sense resistor to the IFBH and IFBL inputs of the RC5031. The error signals from both the current feedback loop and the voltage feedback loop are summed together and used to control the off-time duration of the oscillator. The current feedback error signal is also used as part of the RC5031 short-circuit protection.
Preliminary Information
Constant-On-Time Oscillator
The RC5031 switch-mode oscillator is designed as a fixed on-time, variable off-time oscillator. The constant-on-time oscillator consists of a comparator, an external capacitor, a fixed current source, a variable current source, and an analog switch that selects between two threshold voltages for the comparator. The external timing capacitor is alternately charged and discharged through the enabling and disabling of the fixed current source. The variable current source is controlled from the error inputs that are received from the current and voltage feedback signals. The oscillator off-time is controlled by the amount of current that is available from the variable current source to charge the external capacitor up to the high threshold level of the comparator. The on-time is set be the constant current source that discharges the external capacitor voltage down to the lower comparator threshold.
+5V +12V
gm gm
V/I
CONSTANT ON-TIME OSCILLATOR V/I gm IO ANALOG SWITCH VH VL VOSW ION VREF REF
To CPU Core
SWCTRL From CPU VCC2DET
SWITCHER SELECT
65-5031-07
Figure 1. RC5031 Block Diagram
2
PRODUCT SPECIFICATION
RC5031
Pin Assignments
NC VREF IFBH IFBL FBSW VCCA NC GNDP
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
65-5031-02
SWCTRL CEXT GNDA NC NC NC VCCP SDRV
Pin Descriptions
Preliminary Information
Pin Name NC VREF
Pin Number 1 2
Pin Function Description No connection. Voltage reference test point. This pin provides access to the internal precision 1.5V bandgap reference and should be decoupled to ground using a 0.1mF ceramic capacitor. No load should be connected to this pin. High side current feedback for switching regulator. Pins 3 and 4 are used as the inputs for the current feedback control loop and as the short circuit current sense points. Careful layout of the traces from these pins to the current sense resistor is critical for optimal performance of the short circuit protection scheme. See Applications Information for details. Low side current feedback for switching regulator. See Applications Information for details. Voltage feedback for switching regulator. This input is active when a logic level LOW is input on pin 16 (SWCTRL). Using two external resistors, it sets the output voltage level for the switching regulator. See Applications Information for details. Switching Regulator Vcc. Power supply for switching regulator control circuitry and voltage reference. Connect to system 5V supply and decouple to ground with 0.1mF ceramic capacitor. No connection. Power Ground. Return pin for high currents flowing in pins 9, 10 and 12 (SDRV, VCCP and LDRV). Connect to a low impedance ground. See Application Information for details. FET driver output for switching regulator. Connect this pin to the gate of the N-channel MOSFET M1 as shown in Figure 11. The trace from this pin to the MOSFET gate should be kept as short as possible (less than 0.5"). See Applications Information for details. Switching regulator gate drive Vcc. Power supply for SDRV output driver. Connect to system 12V supply with R-C filter shown in Figure 11. See Applications Information for details. No connection. Analog ground. All low power internal circuitry returns to this pin. This pin should be connected to system ground so that ground loops are avoided. See Applications Information for details. External capacitor. A 180pF capacitor is connected to this pin as part of the constant on-time pulse width circuit. Careful layout of this pin is critical to system performance. See Applications Information for details. Switching regulator control input. Accepts TTL/open collector input levels. A logic level HIGH on this pin presets the switching regulator output voltage at 3.5V using internal resistors. A logic level LOW on this pin will select the output voltage set by two external resistors and the voltage feedback control pin 5 (VFBSW). See Applications Information for details. 3
IFBH
3
IFBL FBSW
4 5
VCCA
6
NC GNDP SDRV
7 8 9
VCCP
10
NC GNDA
11-13 14
CEXT
15
SWCTRL
16
RC5031
PRODUCT SPECIFICATION
Absolute Maximum Ratings
Supply Voltages, VCCA, VCCP Junction Temperature, TJ Storage Temperature, TS Lead Soldering Temperature, 10 seconds 13V +150C -65 to +150C 300C
Note: 1. Functional operation under any of these conditions is not implied. Performance is guaranteed only if Operating Conditions are not exceeded.
Operating Conditions
Preliminary Information
Parameter Switching Regulator VCC, VCCA Logic Inputs, SWCTRL Ambient Operating Temperature, TA Drive Gate Supply, VCCP
Conditions Logic HIGH Logic LOW
Min. 4.75 2.4
Typ. 5
Max. 5.25 0.8
Units V V V C V
0 9 12
70 13
Electrical Characteristics
(VCCA = 5V, VCCP = 12V, TA = 25C using circuit of Figure 11, unless otherwise noted) The * denotes specifications which apply over the full ambient operating temperature range. Parameter Output Voltage, VOUT Output Voltage, VOUT1 Setpoint Accuracy2 Output Temperature Drift Output Current, ISW Line Regulation Load Regulation Output Ripple, peak-peak Cumulative DC Efficiency Output Driver Current Short Circuit Threshold Voltage On Time Pulse Width VREF PSRR Thermal Impedance, qJA VCCA Supply Current Independent of load * *
4
Conditions SWCTRL = High SWCTRL = Low Set by external resistors ISW = 5A, using 0.1% resistors * VCCA = 4.75 to 5.25V, ISW= 5A ISW = 0 to 5A or 5A to 10A 20MHz BW, ISW = 5A * ISW = 5A, VOSW = 2.8V Open Loop CEXT = 180pF
1
Min. * * 1.5 -1.2
Typ. 3.5
Max. 3.6 +1.2
Units V V % ppm A %Vo %Vo mV mV % A
40 13 0.10 0.9 15 55 80 0.5 80 1.485 60 150 5 10 90 3.5 1.5 1.515 100 85 100 * * * 0.15 1.3
Accuracy3
mV ms V dB C/W mA
Reference Voltage, VREF
4
PRODUCT SPECIFICATION
RC5031
Parameter VCCP Supply Current Internal Power Dissipation
Conditions ISW = 5A ISW = 5A, using Figure 11 * *
Min.
Typ. 20 125
Max. 25
Units mA mW
Notes: 1. When the SWCTRL pin is HIGH or left open, the switch-mode regulator output will be preset at 3.5V using internal precision resistors. When the SWCTRL pin is LOW, the output voltage may be programmed with external resistors. Please refer to the Applications Section for output voltage selection information. 2. Setpoint accuracy is the initial output voltage variability under the specified conditions. When SWCTRL is LOW, the matching of the external resistors will have a major influence on this parameter. 3. Cumulative DC accuracy includes setpoint accuracy, temperature drift, line and load regulation, and output ripple. 4. The on-time pulse width of the oscillator is preset via external capacitor CEXT. See Typical Operating Characteristics curves.
Typical Operating Characteristics
(VCCA = 5V, and TA = +25C using circuit in Figure 11, unless otherwise noted)
100 +1.5 +1.0 90 3.5V 2.8V 80
Preliminary Information
Efficiency (%)
VOUT (%)
+0.5 Nom -0.5 -1.0 3.5V 2.8V 0 2 4 6 8 10
70 0 2 4 6 8 10
-1.5
Output Current (A) Figure 2. Switcher Efficiency vs. Output Current
4 3
Output Current (A) Figure 3. Switcher Output Voltage vs. Load
+0.50
Output Voltage (%)
8 10 12 14 16
VOUT (V)
+0.25 Nom. -0.25 -0.50 0 25 50 75 100 125
2 1 0
Output Current, ISW (A) Figure 4. Switcher Output vs Output Current
Figure 5. Output Voltage vs. Temperature (ISW or IL = 5A)
ISW(2A/div) VOUT (50mV/div)
Time (100ms/division) Figure 6. Switcher Transient Response (0.5 to 5.5A Load Step)
VOUT (10mV/division)
Time (2ms/division) Figure 7. Switcher Output Ripple (BW = 20MHz, I SW = 5A)
5
RC5031
PRODUCT SPECIFICATION
Typical Operating Characteristics (continued)
VCCA(2V/div) SDRV Output Voltage (2V/div)
VOUT(2V/div)
Time (5ms/division)
Time (1s/division) Figure 9. Pin 9 (SDRV) at a 5 Amp Load
Preliminary Information
Figure 8. Switcher Turn-on Response
SDRV Output Voltage (2V/div)
Time (1s/division) Figure 10. Pin 9 (SDRV) at a 0.1 Amp Load
6
+12V 0.1F R6 471/2
PRODUCT SPECIFICATION
C7
+5V L2 CIN C9 0.1F
Test Circuit Configurations
C8
0.1uF
C14 1F M1 L1 101/2 4.7H 5m1/2 R11 1.74K1/2 1-2 2.8V 3-4 2.9V R7 2.00K1/2 9 8 DS1 7 6 5 10 11 12 13 R10 1.87K1/2 R1 R12
VCORE R9 2.26K1/2 5-6 3.2V R8 0.80K1/2 7-8 2.1V R7 2.53K1/2 9 - 10 3.4V COUT
RC5031
4 3 2 1
14 15 16 C13 180pF
R5
0.01/2
GND
SWCTRL
J7
Open = 3.5 V
VREF C10 0.1F
Figure 11. P54/P55C, K6, or M2 Switching Power Supply Application Schematic
RC5031
Preliminary Information
7
RC5031
PRODUCT SPECIFICATION
Table 1. Bill of Materials for a RC5031 P55C, K6, or M2 Application
Qty. 4 1 1 Reference C7, C8, C9, C10 C13 C14 Manufacturer Part Order # Panasonic ECU-V1H104ZFX Panasonic ECU-V1H181JCG Panasonic ECSH1CY105R Sanyo 6MV1500GX Sanyo 10MB1200GX Motorola MBR1545CT Pulse Engineering PE-53682 Beads Inductor IRL3103 Description 0.1mF 50V SMT 0805 capacitors 180pF 50V SMT0805 capacitor 1mF 16V SMT 0805 Capacitor 1500mF 6.3V electrolitic capacitor, 10mm x 20mm 1200mF 10 B electrolytic capacitor, 10mm x 20mm Schottky Diode 4.7mH inductor 2 Beads, 3.5 x 8mm wire, diameter = 0.6mm N-Channel Logic Level Enhancement Mode MOSFET 5mW MnCu or Copel resistor 0.80KW 1% resistor 2.26KW 1% resistor 1.87KW 1% resistor 1.74KW 1% resistor 2.00KW 1% resistor 0W 5% resistor 47W 5% resistor Adjustable Switching Regulator 0.1% resistor desirable for accuracy 0.1% resistor desirable for accuracy 0.1% resistor desirable for accuracy 0.1% resistor desirable for accuracy 0.1% resistor desirable for accuracy Resistor raises VOUT 25mV/5W Optional--Helps reduce ripple on the 5V line RDS(ON) < 20mW, VGS < 4.5V, ID > 20A Vf < 0.57V at If = 7.5A ESR < 0.044W Requirements and Comments
See COUT Table 2 See CIN Table 2
Preliminary Information
1 1 1 1
DS1 L1 L2 M1
1 1 1 1 1 1 1 1 1
R1 R8 R9 R10 R11 R7 R5 R6 U1
RSENSE (SW) Panasonic ERJ-6ENF 0.80KV Panasonic ERJ-6ENF2.26KV Panasonic ERJ-6ENF1.87KV Panasonic ERJ-6ENF1.74KV Panasonic ERJ-6ENF2.00KV Panasonic ERJ-6GEY000V Panasonic ERJ-6GEY047V Fairchild Semiconductor RC5031M
Table 2. Switching Regulator Components Selection Table
Output Voltage 3.5 2.8 2.9 2.9 3.2 3.2 2.1 3.3 8 Output Current 8 6 6.25 7.5 9.5 13 5.6 3 CIN Sanyo 10MV1200GX 1x 1x 1x 1x 2x 3x 1x N/A COUT Sanyo 6M1500GX 2x 2x 2x 2x 4x 6x 2x 1x Power MOSFET (M1) IRL3103 IRL3103 IRL3103 IRL3103 IRL3103 IRL3103 IRL3103 MJE15028
PRODUCT SPECIFICATION
RC5031
Applications Information
The following discussion is intended to be an abbreviated list of design considerations regarding the RC5031 as used in a typical voltage processor motherboard application. For a more thorough discussion of applicable specifications relating to the Intel Pentium P55C processor, please refer to Application Note 48.
Output Voltage Selection
Feedback Voltage Divider
The RC5031 precision reference is trimmed to be 1.5V nominally. When using the RC5031, the system designer has complete flexibility in choosing the output voltage for each regulator from 1.5V to 3.6V. This is done by appropriately selecting the feedback resistors. These should be 0.1% resistors to realize optimum output accuracy. The following equations determine the output voltages of the two regulators: Switching Regulator
R2 + R3 V OUT = 1.5 ae -------------------- o e R3 o
exceeds the short circuit comparator threshold voltage (Vth). When this happens the output voltage will temporarily go out of regulation. As the voltage across the sense resistor becomes larger, the top-side MOSFET will continue to turn off until the current limit value is reached. At this point, the RC5031 will continuously deliver the limit current at a reduced output voltage level. The short circuit comparator threshold voltage is typically 90mV, with a variability of 10mV. The ripple current flowing through the inductor is typically 0.5A. There needs to be a 29% margin for the sense resistor when using a motherboard PC trace resistor. Refer to Application Note 48 for detailed discussions. The sense resistor value can be approximated as follows:
V th,min V th,min R SENSE = --------------- ( 1 - TF ) = --------------------------------------------- ( 1 - TF ) I PK 1.5A + I LOAD,MAX
Preliminary Information
Where TF = Tolerance Factor for the sense resistor and 1.5A accounts for the inductor ripple current. There are several different types of sense resistors. Table 3 describes the tolerance, size, power capability, temperature coefficient and cost of various types of sense resistors. Based on the Tolerance in Table 3:
where: R2 > 1.5kW and (R2 + R3) 25kW For an embedded PC trace resistor: Example: For 2.8V,
R2 + R3 1.6k + 1.85k V OUT = 1.5 ae -------------------- o = 1.5 ae ------------------------------ o = 2.8V e R3 o e 1.85k o V th,min R SENSE = ---------------------------------------- ( 1 - TF ) 1.5 + I LOAD,MAX 80mV ( 1 - TF ) = ---------------------------- ( 1 - 29% ) = 4.9mW 1.5A + 10A
Short Circuit Considerations
The RC5031 uses a current sensing scheme to limit the load current if an output fault condition occurs. The current sense resistor carries the peak current of the inductor, which is greater than the maximum load current due to ripple currents flowing in the inductor. The RC5031 will begin to limit the output current to the load by turning off the top-side FET driver when the voltage across the current-sense resistor
For a discrete resistor:
V th,min R SENSE = ---------------------------------------- ( 1 - TF ) 1.5 + I LOAD,MAX 80mV ( 1 - TF ) = ---------------------------- ( 1 - 5% ) = 6.6mW 1.5A + 10A
Table 3. Comparison of Sense Resistors
Discrete Iron Alloy resistor (IRC) 5% (1% available) 0.45" x 0.065" x 0.2" 1 watt (3 and 5 watts available) +30 ppm $0.31 Discrete Metal Strip surface mount resistor (Dale) 1% 0.25" x 0.125" x 0.025" 1 watt (3 and 5 watts available) 75 ppm $0.47 Discrete MnCu Alloy wire resistor 10% 0.2" x 0.04" x 0.16" 1 watt 30 ppm $0.09 Discrete CuNi Alloy wire resistor (Copel) 10% 0.2" x 0.04" x 0.1" 1 watt 20ppm $0.09
Motherboard Trace Resistor Tolerance Factor (TF) Size (L x W x H) Power capability Temperature Coefficient Cost@10,000 piece quantity 29% 2" x 0.2" x 0.001" (1 oz Cu trace) >50A/in +4,000 ppm Low; included in motherboard
9
RC5031
PRODUCT SPECIFICATION
Table 4 lists recommended values for sense resistors for various load currents using an embedded PC trace resistor or a discrete resistor.
Using the above formula, for Vout = 2.8V, ILOAD = 6A
2.8 + 0.57 Duty Cycle = --------------------------------------------------------- = 61.8% 2.8 + 0.57 - ( 6 0.019 ) 5V 6A 2 P MOSFET = 6A 0.019W 61.8% + -------------------- 6 ( 210ns + 54ns ) 300KHz P MOSFET = 0.82W
Table 4. RSENSE for Various Load Currents, Switching Regulator
RSENSE ILOAD, MAX PC Trace Resistor (A) (mW) 5 6 7 8 8.7 7.6 6.7 6.0 5.4 4.9 RSENSE Discrete Resistor (mW) 11.7 10.1 8.9 8.0 7.0 6.6
Since the power at 6A is within the thermal guideline, a heat sink is not required other than the PCB.
Schottky Diode
In Figure 11, MOSFET M1 and flyback diode DS1 are used as complementary switches in order to maintain a constant current through the output inductor L1. As a result, DS1 will have to carry the full current of the output load when the power MOSFET is turned off. The power in the diode is a direct function of the forward voltage at the rated load current during the off time of the FET. The following equation can be used to estimate the diode power:
P DIODE = I D V D ( 1 - DutyCycle ) where ID is the forward current of the diode, VD is the forward voltage of the diode, and DutyCycle is defined the same as above.
Preliminary Information
9 10
Since the value of the sense resistor is often less than 10mW, care should be taken in the layout of the PCB. Trace resistance can contribute significant errors. The traces to the IFBH and IFBL pins of the RC5031 should be Kelvin connected to the pads of the current-sense resistor. To minimize the influence of noise, the two traces should be run next to each other.
Thermal Design Considerations
Good thermal management is critical in the design of high current regulators. System reliability will be degraded if the component temperatures become excessive. The following guide should serve as a reference for proper thermal management.
MOSFET Temperature
For the Motorola MBR2030CTL Rectifier in Figure 11,
P DIODE = 10A 0.57 ( 1 - 64.8% ) = 2.0W
The maximum power dissipation of the MOSFET can be calculated by using the following formula:
T J ( MAX ) - T A P D = --------------------------------Q JA
It is recommended that the diode T0-220 package be placed down on the motherboard to utilize the power plane as a heatsink and achieve a thermal resistance of 40C/W.
Board Design Considerations
RC5031 Placement
For IR 3103, QJA is 42C/W. For reliability the junction temperature of the MOSFET should not exceed 120C. Assuming that the ambient temperature is 40C, then the maximum power dissipation is calculated as:
120 - 40 P D = -------------------- = 1.905W 42
The RC5031 should be placed as close to the core voltage supply pins of the P55C as possible, preferably to have the PC layer directly underneath the RC5031 for ground layer. This serves as extra isolation from noisy power planes.
MOSFET Placement
The power that the MOSFET dissipates at the rated 6A load is calculated as follows:
P MOSFET = I LOAD R DS ( ON ) ( Duty Cycle ) + V IN I LOAD ------------------------------- ( t r + t f ) f 6 V OUT + V D Duty Cycle = -----------------------------------------------------------------------------V IN + V D - ( I LOAD R DS ( ON ) )
2
where VD is the forward voltage of the Schottky diode used.
Placement of the power MOSFET is critical in the design of the switch-mode regulator. The FET should be placed in such a way as to minimize the length of the gate drive path from the RC5031 SDRV pin. This trace should be kept under 0.5" for optimal performance. Excessive lead length on this trace will cause high frequency noise resulting from the parasitic inductance and capacitance of the trace. Since this voltage can transition nearly 12V in around 100nsec, the resultant ringing and noise will be very difficult to suppress. This trace should be routed on one layer only and kept well away from the "quiet" analog pins of the device; VREF, CEXT, FBSW, IFBH, IFBL, and VFBL. A10W resistor in series with the MOSFET gate can decrease this layout critically. Refer to Figure 12.
10
PRODUCT SPECIFICATION
RC5031
Example of a Good layout
SDRV 9 10 11 12 Noisy Signal is routed away from quiet pins and trace length is kept under 0.5 CEXT in. 13 14 15 16 8 7 6 5 4 3 2 1
Example of a Problem layout
SWDRV 9 10 11 12 13 8 7 6 5 4 3 2 1
IFBL IFBH VREF
VREF CEXT
14 15 16
= "Quiet" Pins
Noisy Signal radiates onto quiet pins and trace is
Preliminary Information
too long.
Figure 12. Examples of good and poor layouts Inductor and Schottky Diode Placement Power and Ground Connections
The inductor and fly-back Schottky diode need to be placed close to the source of the power MOSFET for the same reasons stated above. The node connecting the inductor and Schottky diode will swing between the drain voltage of the FET and the forward voltage of the Schottky diode. It is recommended that this node be converted to a plane if possible. This node will be part of the high current path in the design, and as such it is best treated as a plane in order to minimize the parasitic resistance and inductance on that node. Since most PC board manufacturers utilize 1/2 oz copper on the top and bottom signal layers of the PCB, it is not recommended to use these layers to rout the high current portions of the regulator design. Since it is more common to use 1 oz. copper on the PCB inner layers, it is recommended to use those layers to route the high current paths in the design.
Capacitor Placement
The connection of VCCA to the 5V power supply plane should be short and bypassed with a 0.1mF directly at the VCCA pin of the RC5031. The ideal connection would be a via down to the 5V power plane. A similar arrangement should be made for the VCCL pin that connects to +12V, though this one is somewhat less critical since it powers only the linear op-amp. Each ground should have a separate via connection to the ground plane below. A 12V power supply is used to bias the VCCP. A 47W resistor is used to limit the transient current into VCCP. A 1uF capacitor filter is used to filter the VCCP supply and source the transient current required to charge the MOSFET gate capacitance. This method provides sufficiently high gate bias voltage to the MOSFET (VGS), and therefore reduces RDS(ON) of the MOSFET and its power loss. Figure 13 provides about 5V of gate bias which works well when using typical logic-level MOSFETs, as shown in Figure 14. Non-logic-level MOSFETs should not be used because of their higher RDS(ON).
One of the keys to a successful switch-mode power supply design is correct placement of the low ESR capacitors. Decoupling capacitors serve two purposes; first there must be enough bulk capacitance to support the expected transient current of the CPU, and second, there must be a variety of values and capacitor types to provide noise supression over a wide range of frequencies. The low ESR capacitors on the input side (5V) of the FET must be located close to the drain of the power FET. Minimizing parasitic inductance and resistance is critical in supressing the ringing and noise spikes on the power supply. The output low ESR capacitors need to be placed close to the output sense resistor to provide good decoupling at the voltage sense point. One of the characteristics of good low ESR capacitors is that the impedance gradually increases as the frequency increases. Thus for high frequency noise supression, good quality low inductance ceramic capacitors need to be placed in parallel with the low ESR bulk capacitors. These can usually be 0.1mF 1206 surface mount capacitors.
MOSFET Gate Bias
+5V 47 W
+12V
VCCP SDRV 1uF
M1
L1 RSENSE DS1
VO
CBULK
GNDP
Figure 13. 12V Gate Bias Configuration
11
RC5031
PRODUCT SPECIFICATION
0.1 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 1.5 2 2.5 3 3.5 4 VGS 5 6 7
RDS(ON) Ohms
2SK1388 NDP7060 NDP706A NDP706AEL
8
9
10
11
Preliminary Information
Figure 14. RDS(ON) vs. VGS for Selected Logic-Level MOSFETs
12
PRODUCT SPECIFICATION
RC5031
Notes:
Preliminary Information
13
RC5031
PRODUCT SPECIFICATION
Notes:
Preliminary Information
14
PRODUCT SPECIFICATION
RC5031
Mechanical Dimensions
16-Lead SOIC Package
Inches Min. A A1 B C D E e H h L N a ccc Max. Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
Symbol
.053 .069 .004 .010 .013 .020 .008 .010 .386 .394 .150 .158 .050 BSC .228 .010 .016 16 0 -- 8 .004 .244 .020 .050
1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 9.80 10.00 3.81 4.00 1.27 BSC 5.80 0.25 0.40 16 0 -- 8 0.10 6.20 0.50 1.27
Preliminary Information
3 6
16
9
E
H
1
8
D A1 A SEATING PLANE -C- LEAD COPLANARITY ccc C a
h x 45 C
e
B
L
15
RC5031
PRODUCT SPECIFICATION
Ordering Information
Product Number RC5031M Package 16 pin SOIC
Preliminary Information
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS30005031 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
Application Circuit for P55C, K6, and M2
Figure 1. P54/P55C, K6 or M2 Single/Dual Power Supply Application Schematic
Table 1. Bill of Materials for a RC5031 P55C, K6, or M2 Application
Qty. 4 1 1 Reference C7, C8, C9, C10 C13 C14 Manufacturer Part Order # Panasonic ECU-V1H104ZFX Panasonic ECU-V1H181JCG Panasonic ECSH1CY105R Sanyo 6MV1500GX Sanyo 10MB1200GX Motorola MBR1545CT Pulse Engineering PE-53682 Beads Inductor IRL3103 Description 0.1mF 50V SMT 0805 capacitors 180pF 50V SMT0805 capacitor 1mF 16V SMT 0805 Capacitor 1500mF 6.3V electrolitic capacitor, 10mm x 20mm 1200mF 10 B electrolytic capacitor, 10mm x 20mm Schottky Diode 4.7mH inductor 2 Beads, 3.5 x 8mm wire, diameter = 0.6mm N-Channel Logic Level Enhancement Mode MOSFET 5mW MnCu or Copel resistor 0.80KW 1% resistor 2.26KW 1% resistor 1.87KW 1% resistor 1.74KW 1% resistor 2.00KW 1% resistor 0W 5% resistor 47W 5% resistor Adjustable Switching Regulator 0.1% resistor desirable for accuracy 0.1% resistor desirable for accuracy 0.1% resistor desirable for accuracy 0.1% resistor desirable for accuracy 0.1% resistor desirable for accuracy Resistor raises VOUT 25mV/5W Optional--Helps reduce ripple on the 5V line RDS(ON) < 20mW, VGS < 4.5V, ID > 20A Vf < 0.57V at If = 7.5A ESR < 0.044W Requirements and Comments
See COUT Table 2 See CIN Table 2 1 1 1 1 DS1 L1 L2 M1
1 1 1 1 1 1 1 1 1
R1 R8 R9 R10 R11 R7 R5 R6 U1
RSENSE (SW) Panasonic ERJ-6ENF 0.80KV Panasonic ERJ-6ENF2.26KV Panasonic ERJ-6ENF1.87KV Panasonic ERJ-6ENF1.74KV Panasonic ERJ-6ENF2.00KV Panasonic ERJ-6GEY000V Panasonic ERJ-6GEY047V Fairchild Semiconductor RC5031M
Table 2. Switching Regulator Components Selection Table
Output Voltage 3.5 2.8 2.9 2.9 3.2 3.2 2.1 3.3 Output Current 8 6 6.25 7.5 9.5 13 5.6 3 CIN Sanyo 10MV1200GX 1x 1x 1x 1x 2x 3x 1x N/A COUT Sanyo 6M1500GX 2x 2x 2x 2x 4x 6x 2x 1x Power MOSFET (M1) IRL3103 IRL3103 IRL3103 IRL3103 IRL3103 IRL3103 IRL3103 MJE15028
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RC5032
5V to 3.3V Step-Down DC-DC Converter
Features
* * * * * * * * * >85% Efficiency Fast transient response Soft control power-up Short circuit protection Output voltage fixed 3.3V Low TC reference voltage Adjustable oscillator frequency Drives N-Channel MOSFET 8 pin SOIC, 8 pin DIP package
Applications
* 3.3V power supply for PentiumTM based desktop CPU motherboards * Minimum component DC-DC converters
Preliminary Information
Description
The RC5032 is a step-down DC-DC controller IC dedicated to providing a 5V to 3.3V conversion for various types of CPU power. It can be configured with the proper applications circuitry to deliver load currents greater than 10 Amps. The RC5032 is designed to operate in a standard PWM control mode under heavy load conditions and as a PFM controller in light load conditions. Its highly accurate low TC reference eliminates the need for precision external components in order to achieve tight tolerance voltage regulation. The programmable oscillator can operate from 200KHz to greater than 1MHz to provide for flexibility in choosing external components such as inductors, capacitors, and Power MOSFETs.
Block Diagram
OSC
+ - I + - + - +
VIN
+12V
I
- +
- + - + - I + - I
VO DIGITAL CONTROL
VREF
65-5032-01
Rev. 0.9.6
PRELIMINARY INFORMATION describes products that are not in full production at the time of printing. Specifications are based on design goals and limited characterization. They may change without notice. Contact Fairchild Semiconductor for current information.
PRODUCT SPECIFICATION
RC5032
Pin Assignments
GND CEXT IFB VFB
1 2 3 4 8 7 6 5
65-5032-02
VCCP DRV GNDP VCCA
Pin Definitions
Pin Name Pin Number 1 2 3 4 5 6 7 8 Ground External capacitor for setting oscillator frequency Current Feedback Input Voltage Feedback Input Analog VCC Power ground for high current driver FET Driver Output VCC for FET output drivers Pin Function Description
Preliminary Information
GND CEXT IFB VFB VCCA GNDP DRV VCCP
Absolute Maximum Ratings
(beyond which the device may be damaged)1 Parameter VCCP Driver Supply Conditions Min Typ Max 13 Units V
Note: 1. Functional operation under any of these conditions is NOT implied. Performance is guaranteed only if Operating Conditions are not exceeded.
Operating Conditions
Parameter VCC VCCP VIH VIL Supply Voltage Driver Supply Input Voltage, Logic HIGH Input Voltage, Logic LOW Ambient Temp 0 Conditions Min 4.5 9 2 0.8 70 Typ 5 Max 7 13 Units V V V V C
2
RC5032
PRODUCT SPECIFICATION
DC Electrical Characteristics
(VCC = 5V, Fosc = 650 KHz, and TA = 0-70C) Parameter VO IO Vref Acc VTC LDR LIR VR Cum Acc Eff Iodr Pd Output Voltage Output Current Reference Accuracy Output Voltage TC Load Regulation Line Regulation Output Voltage Ripple Cumulative Efficiency Output Driver I Power Dissipation Accuracy1 TA = 0-70C Iload > 4A Open Loop 85 0.5 0.5 to 7A VCC = 5% See Figure 1 for application Conditions Min 3.1 Typ 3.4 7 1 40 0.5 0.07 30 3 88 0.7 0.1 5 3 Max 3.6 Units V A % ppm %VO %VO mV %
Preliminary Information
% A W
Notes: 1. Output Voltage accuracy, Tempco, load regulation, ripple, and transient performance determine the Cumulative Accuracy.
AC Electrical Characteristics
(VCC = 5V, Fosc = 650 KHz, and TA = 25C) Parameter Tr Fosc Osc Acc Dtc Dtcm Iscp Trimax Tssp Response Time Oscillator Range Fosc Accuracy Max Duty Cycle Min Duty Cycle Short Circuit Prot Response to Imax Soft start response PWM mode PFM mode 250 15 1 30 90 Conditions Il=0.5A to 7A 0.2 10 95 100 Min Typ 10 1.2 Max Units ms MHz % % ns mV ms ms
3
PRODUCT SPECIFICATION
RC5032
Test Circuit
6.2V ZENER VCC C3 220F C5 0.1F D1
R2 100 +12V C2 1F
M1 MTD20N03HDL CDRH127-1R3NC L1 VO 1.5H R1 0.012 C4 660F
Preliminary Information
5 6 7 8
RC5032
4 3 2 1 C1 47F
GND
DS1 MBRB1545CT
65-5032-03
Figure 1. RC5032 7A Schematic
Table 1. Components for RC5032
RC5032 Standard Application Circuit Bill of Materials Ref Designator L1 M1 DS1 D1 R1 C3 C4 C2 C1 C5 R2 Quantity 1 1 1 1 1 1 2 1 1 1 1 Part No. CDRH127-1R3NC MTD20N03HDL MBRB1545CT 6.2V Zener LRC-2512 OS-CON 10SA220M OS-CON 10SA330M 1uF 47pF 0.1uF 100W Manufacturer Sumida Motorola Motorola any IRC Sanyo Sanyo Monolithic ceramic Cap SMD Cap SMD Cap SMD Res
4
RC5032
PRODUCT SPECIFICATION
Notes:
Preliminary Information
5
PRODUCT SPECIFICATION
RC5032
Mechanical Dimensions
8 Lead Ceramic DIP Package
Inches Min. A b1 b2 c1 D E e eA L Q s1 a Max. Millimeters Min. Max. 8 2, 8 8 4 4 5, 9 7 3 6 Notes: Notes 1. Index area: a notch or a pin one identification mark shall be located adjacent to pin one. The manufacturer's identification shall not be used as pin one identification mark. 2. The minimum limit for dimension "b2" may be .023 (.58mm) for leads number 1, 4, 5 and 8 only. 3. Dimension "Q" shall be measured from the seating plane to the base plane. 4. This dimension allows for off-center lid, meniscus and glass overrun. 5. The basic pin spacing is .100 (2.54mm) between centerlines. Each pin centerline shall be located within .010 (.25mm) of its exact longitudinal position relative to pins 1 and 8. 6. Applies to all four corners (leads number 1, 4, 5, and 8). 7. "eA" shall be measured at the center of the lead bends or at the centerline of the leads when "a" is 90. 8. All leads - Increase maximum limit by .003 (.08mm) measured at the center of the flat, when lead finish applied. 9. Six spaces. D 4 1 Note 1 E
Symbol
Preliminary Information
-- .200 .014 .023 .045 .065 .008 .015 -- .405 .220 .310 .100 BSC .300 BSC .125 .200 .015 .060 .005 -- 90 105
-- 5.08 .36 .58 1.14 1.65 .20 .38 -- 10.29 5.59 7.87 2.54 BSC 7.62 BSC 3.18 5.08 .38 1.52 .13 -- 90 105
5 s1
8
e
eA
A Q L b2 b1 a c1
6
RC5032
PRODUCT SPECIFICATION
Mechanical Dimensions (continued)
8 Lead SOIC Package
Inches Min. A A1 B C D E e H h L N a ccc Max. Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
Symbol
.053 .069 .004 .010 .013 .020 .008 .010 .189 .197 .150 .158 .050 BSC .228 .010 .016 8 0 -- 8 .004 .244 .020 .050
1.35 1.75 0.10 0.25 0.33 0.51 0.20 0.25 4.80 5.00 3.81 4.01 1.27 BSC 5.79 0.25 0.40 8 0 -- 8 0.10 6.20 0.50 1.27
Preliminary Information
3 6
8
5
E
H
1
4
D A1 A SEATING PLANE B -C- LEAD COPLANARITY ccc C a
h x 45 C
e
L
7
PRODUCT SPECIFICATION
RC5032
Ordering Information
Product Number RC5032M Package 8 SOIC qJA 85C/W
Preliminary Information
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS30005032 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC5033
Adjustable Synchronous DC-DC Converter
Features
* * * * * * * * * * >85% Efficiency 350uA quiescent current in shutdown Fast transient response Soft control power-up Over-Voltage Protection Output voltage range from 2.0V to 3.6V Factory trimmed low TC reference voltage Adjustable oscillator frequency Drives N-Channel MOSFETs 16 pin SOIC package
Applications
* 3.3V power supply for PentiumTM based CPU motherboards * 3.45V power supply for AMD-K5TM CPU * 2.5V or 3.6V power supply for PowerPCTM
Preliminary Information
Description
The RC5033 is a synchronous mode DC-DC controller IC dedicated to providing a 5V to 2.0V up to 3.6V conversion for various types of CPU power . It can be configured in both the synchronous and non-synchronous modes and with the proper applications circuitry can be used to deliver load current greater than 10 Amps. The RC5033 is designed to operate in a standard PWM control mode under heavy load conditions and as a PFM controller in light load conditions. Its highly accurate low TC reference eliminates the need for precision external components in order to achieve tight tolerance voltage regulation. Through the use of external resistors, the RC5033 can generate accurate output voltages from 2.0V up to 3.6V. An integrated Over-Voltage protection function constantly monitors the output voltage and shuts down the power to the CPU in the event of a out-oftolerance voltage situation, thereby protecting the CPU. The programmable oscillator can operate from 200KHz to greater than 1MHz to provide for flexibility in choosing external components such as inductors, capacitors, and Power MOSFETs.
Block Diagram
OSC
+ - I + - I - + + - + - + I + - +
VIN
VO
I
-
-
DIGITAL CONTROL
VREF
VREF
65-5033-01
Rev. 0.9.5
PRELIMINARY INFORMATION describes products that are not in full production at the time of printing. Specifications are based on design goals and limited characterization. They may change without notice. Contact Fairchild Semiconductor for current information.
PRODUCT SPECIFICATION
RC5033
Pin Assignments
ON/OFF IFB VFB VCCA VCCD VCCP LODRV GNDP
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
65-5033-02
CEXT GNDA ADJ3 GNDD ADJ2 ADJ1 VCCQP HIDRV
Pin Definitions
Preliminary Information
Pin Name On/Off IFB VFB VCCA VCCD VCCP LODRV GNDP HIDRV VCCQP ADJ1 ADJ2 GNDD ADJ3 GNDA CEXT
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Current Feedback Input. Voltage Feedback Input. Analog VCC. Digital VCC.
Pin Function Description A low level on this pin will power down; tie to VCCD if not used.
VCC for synchronous FET output drivers. Synchronous FET driver output. Power ground for high current drivers. High side FET driver output. VCC for High side FET output driver VREF adjust pin.1 VREF adjust pin.1 Digital ground. VREF adjust pin.1 Analog ground. External capacitor for setting oscillator frequency.
Note: 1. See voltage adjust table for function
Output Voltage Selection Table
VOUT 3.5V 3.35V 3.3V 2.9V1 2.5V1 2.0V1 ADJ1 N/C N/C
2
ADJ2 N/C
2
ADJ3 N/C
2 2
N/C N/C N/C N/C
3.9K 2K 39W
N/C N/C N/C
Note: 1. See Figure 3 for resistor connection. 2. Indicated short pins together.
2
RC5033
PRODUCT SPECIFICATION
Absolute Maximum Ratings
(beyond which the device may be damaged)1 Parameter VCCP VCCQP TJ TA TS TL Driver Voltage High Driver Supply Junction Temperature Ambient Operating Temperature Storage Temperature Lead Soldering Temperature (10 seconds) 0 -65 Conditions Min Typ Max 13 13 175 70 150 300 Units V V C C C C
Note: 1. Functional operation under any of these conditions is NOT implied.
Preliminary Information
Operating Conditions
Parameter VCC VCCP VCCQP VIH VIL Supply Voltage Low Driver Supply High Driver Supply Input Voltage, Logic HIGH Input Voltage, Logic LOW Conditions Min 4.5 4.5 9 2 0.8 Typ 5 5 Max 7 12 13 Units V V V V V
DC Electrical Characteristics
(VCC = 5V, fosc = 650 KHz, and TA = +25C unless otherwise noted) Parameter VO IO Vref Acc VTC LDR LIR VR Cum Acc Eff Iodr PD Output Voltage Output Current Voltage Reference Accuracy Output Voltage Tempco Load Regulation Line Regulation Output Voltage Ripple Cumulative Efficiency Output Driver I Power Dissipation Accuracy2 TA = 0-70C Synchronous mode > 1A Open Loop 80 0.5 0.5 to 7A VCC = 5% Conditions Nominal, Pin 12 conn. Pin 14, TA = 0-70C See Figure for application Min 3.135 Typ 3.3 5 1 -40 1 0.14 30 3 85 0.7 0.1 0.2 Max 3.465 Units V A % ppm %Vo %Vo mV % % A W
Notes: 1. Functional operation under any of these conditions is not implied. Performance is guaranteed only if Operating Conditions are not exceeded. 2. Output Voltage accuracy, Tempco, load regulation, ripple, and transient performance determine the Cumulative Accuracy.
3
PRODUCT SPECIFICATION
RC5033
AC Electrical Characteristics1
(TA = +25C unless otherwise noted) Parameter Tr Fosc Osc Acc Dtc Dtcm Imax Iscp Ovp Response Time Oscillator Range Fosc Accuracy Max Duty Cycle Min Duty Cycle Imax Threshold Short Circuit Prot Over Voltage Prot Response to Imax Soft start response PWM mode PFM mode 30 80 20 15 10 30 90 Conditions Il=0.5A to 5.5A 0.2 10 95 100 Min Typ 10 1.2 Max Units ms MHz % % ns mV mV %Vo ns ms
Preliminary Information
Trimax Tssp
Note: 1. Guaranteed by design, not 100% total.
4
RC5033
PRODUCT SPECIFICATION
Typical Operating Characteristics1
Load Regulation (FOSC = 400 KHz) Efficiency vs Output Current (FOSC = 400 KHz)
100 3.38 3.37 3.36 3.35
Efficiency (%)
90 80 70 60 50 0 2 4 6
VOUT
3.34 3.33 3.32 3.31 3.3 0 2 4 6 8
Output Current (A) Output Current (A) Load Regulation (FOSC = 650 KHz) Efficiency vs Output Current (FOSC = 650 KHz)
100 3.37 3.36 3.35
Preliminary Information
Efficiency (%)
90
VOUT
80 70 60 50 0 2 4 6
3.34 3.33 3.32 3.31 3.3 0 2 4 6 8
Output Current (A)
Output Current (A)
Load Regulation (FOSC = 1 MHz) Efficiency vs Output Current (FOSC = 1 MHz)
100 3.36 3.35 3.34
Efficiency (%)
90
VOUT
0 2 4 6
80 70 60 50
3.33 3.32 3.31 3.3 0 2 4 6 8
65-5033-03
Output Current (A) Note: 1. Data taken with circuit of Figure 1.
Output Current (A)
5
PRODUCT SPECIFICATION
RC5033
Typical Operating Characteristics (continued)
Line Regulation vs. Output Load (FOSC = 400 KHz)
0.3 3.5 3.495
Reference Tempco
Line Reg (%)
0.25 0.2 0.15 0.1 0.05 0 0 2 4 6 8
VREF
3.49 3.485 3.48 3.475 3.47 0 50 100
Preliminary Information
Output Current (A)
Temp
Line Regulation vs. Output Load (FOSC = 650 KHz)
0.3
CEXT vs. Oscillator Frequency
200
Line Reg (%)
0.25 0.2 0.15 0.1 0.05 0 0 2 4 6 8
CEXT (pF)
150 100 50 0 0 4 4 8
Output Current (A)
Frequency (Hz)
Line Regulation vs. Output Load (FOSC = 1 MHz)
0.25 0.2
Line Reg (%)
0.15 0.1 0.05 0 -0.05 -0.1 0 2 4 6 8
65-5033-04
Output Current (A)
6
RC5033
PRODUCT SPECIFICATION
Typical Operating Characteristics (continued)
VOUT (50mV/division) VOUT (50mV/division) Hidrv (5V/division)
Hidrv (5V/division)
Preliminary Information
TIME ( 1ms/division)
TIME ( 1ms/division)
AC Ripple response .2A Load
AC Ripple response 5A Load
VOUT (50mV/division)
IOUT (2A/division)
TIME ( 200ms/division)
IOUT (2A/division)
VOUT (50mV/division)
TIME ( 20ms/division)
Transient Response .2A to 5A Load
Transient Response Magnified
VCC C5 200F C4 0.1F DS2 EC10QS02 M1 MTD20N03HDL 9 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1 C2 1F L1 1.5H R1 0.0121/2 VO C9 330F
RC5033
GND
M2 MTD20N03HDL
DS1 MBRB1545CT
C1 47pF
C13 4.7F
65-5033-05
Figure 1. Standard 7A Application Schematic
7
PRODUCT SPECIFICATION
RC5033
VCC C5 200F C4 0.1F DS2 EC10QS02 M1 MTD20N03HDL 9 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1 C2 1F L1 R1 CDRH127-1R3NC 0.0121/2 VO C9 330F
RC5033
DS1 MBRB1545CT
GND
Preliminary Information
C1 47pF
C13 4.7F
65-5033-06
Figure 2. Non-Synchronous 7A Application Circuit
VCC C5 200F C4 0.1F DS2 EC10QS02 M1 MTD20N03HDL 9 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1 C2 1F L1 1.5H R1 0.0121/2 VO C9 330F
RC5033
R2 GND
M2 MTD20N03HDL
DS1 MBRB1545CT
C1 47pF
C13 4.7F
65-5033-07
Figure 3. Adjustable Voltage DC-DC Converter
8
RC5033
PRODUCT SPECIFICATION
RC5033 Standard Application Circuit Bill of Materials Ref Designator L1 M1,M2 DS1 DS2 R1 C5 C9 C2 C1 C4 Quantity 1 2 1 1 1 1 1 1 1 2 Part No. CDRH127-1R3NC MTD20N03HDL MBRB1545CT EC10QS02L LRC-2512 OS-CON 10SA220M OS-CON 10SA330M 1uF 47pF 0.1uF
Table 1. Components for RC5033
Manufacturer Sumida Motorola Motorola Nihon IRC Sanyo Sanyo Monolithic ceramic Cap SMD Cap
Preliminary Information
SMD Cap
RC5033 Alternate Suppliers of Components Ref Designator L1 M1,M2 Quantity 1 2 Alternate Part No. PE-53680 2SK1388 IRLZ44N Si4410DY DS1 DS2 R1 C5 C9 1 1 1 1 1
Table 2. Alternate Components Selection
Alternate Manufacturer Pulse Engineering Fuji International Rectifier Temic (Siliconix) Nihon Rectron Motorola DALE
C10T02QL SR1620C MBRS140T3 WSL-2512
9
PRODUCT SPECIFICATION
RC5033
Applications Discussion
VCCP C5 200F C4 0.1F DS2 EC10QS02 M1 MTD20N03HDL 9 +12V 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1 C2 1F L1 1.5H R1 0.0121/2 VO C9 330F
RC5033
DS1 MBRB1545CT
GND
Preliminary Information
C1 47pF
C13 4.7F C1 47pF
R2 12K
- +
+ -
LM308A M2 MTD20N03HDL VO2 2.9V
R3 88K
65-5033-08
Dual Power Supply Application
In some CPU power applications there may be a need for a split voltage converter. The circuit in Figure 4 addresses this need with only minimal component count. The basic RC5033 non-synchronous DC-DC converter is augmented with an op-amp, a power MOSFET, and some 1% resistors to provide a dual power supply with one voltage set to 3.3V and the other, slaved off of the 3.3V, set to 2.9V. In this configuration, the RC5033 converts the 5V to 3..3V with high efficiency. By using the op-amp, power FET, and the resistors, a low-dropout linear regulator is realized that can be run off of the 3.3V. The 2.9V linear regulator has a relatively high efficiency just due to the fact that the ratio of 2.9V/3.3V is close to 88%. The power FET is a low Rdson n-channel MOSFET, and thus it is reasonably inexpensive. The opamp can be a garden variety, though the input bias current and output slew rate need to be considered to optimize accuracy and transient response. The overall efficiency of this power supply system will very much depend upon the percentage of power used on each power output. Overall, the efficiency of this system will be lower than if both supplies were implemented as switchers; however, the added savings of the part count reduction may more than compensate for the overall lower efficiency.
Standard Application Circuit
The circuit shown in Figure 1 along with its components and values has been designed as representative of the typical application involving the RC5033 for a PentiumTM CPU. Use of the standard application circuit will deliver the performance curves shown under the Typical Operating Characteristics section of the data sheet. Many users will want to develop their own DC-DC converter solution that is uniquely tailored to a specific application requirement. In that case, the users should review the detailed information in the Design Procedure and Applications Information section of the data sheet.
Detailed Description
The RC5033 is a programmable voltage synchronous controller. When designed around the appropriate external components, it can be configured to deliver more than 10A of output current. During heavy loading conditions the RC5033 functions as a current-mode PWM step down regulator. Under light loading conditions, the regulator functions in the PFM or pulse skipping mode, thereby increasing its efficiency under light loads.
10
RC5033
PRODUCT SPECIFICATION
Main Control Loop
Internal Reference
The main control loop of the regulator (see Block Diagram) contains two main blocks, the analog control block and the digital control block. The analog control block consists of signal conditioning amplifiers that feed into a set of fast comparators which provide the inputs to the digital control block. The signal conditioning block takes inputs from the IFB(current feedback) and VFB(voltage feedback) pins and then sets up two controlling signal paths. The voltage control path gains up the VFB signal and presents that signal to one of the summing amplifier inputs. The current control path takes the difference between the IFB and VFB pins and presents that signal to another input of the summing amplifier. These two signals are then summed together with the slope compensation input from the oscillator and the output is then presented to a comparator. This comparator provides the main PWM control signal to the digital control block. There are three other comparators in the analog control block. The first two control the thresholds of where the RC5033 goes into its pulse skipping mode during light loads and the second controls the point at which the max current comparator disables the output drive signal to the upper power MOSFET. The third comparator determines when the synchronous mode bottom side power MOSFET will be enabled and disabled. The digital controller section is designed to take the comparator inputs along with the main clock signal from the oscillator and provide the appropriate pulses to the HIDRV and LODRV output pins that will in turn control the external power MOSFETs. This digital section was designed in high speed schottky transistor logic which allows the RC5033 to clock up to speeds greater then 1MHz. This section is responsible for providing the break-before-make timing that ensures that both external FETs will not be on at the same time.
High Current Output Drivers
The reference in the RC5033 is a precision band-gap type reference. Its temperature coefficient is trimmed to provide a near zero TC. For applications that require a voltage other than the voltages provided by the fixed jumper connections, an external resistor will change the reference voltage from 2.0V up to 3.6V. For a guaranteed stable operation under all loading conditions, a 0.1mF capacitor is recommended on the VREF output pin.
Over -Voltage Protection
The RC5033 provides a constant monitor of the output voltage for over-voltage protection. Should the voltage at the VFB pin exceed 20% of the selected program voltage, then an overvoltage condition will be assumed to exist and the RC5033 will shut down the output drive signals to the power FETs.
Oscillator
Preliminary Information
The RC5033 oscillator is designed as a fixed current capacitor charging oscillator. An external capacitor allows for maximum flexibility in choosing the associated external components for the RC5033. The oscillator frequency con be set from less than 200KHz to over 1MHz depending on the application requirements.
Design Procedure and Applications Information
Simple Step-Down Converter
The RC5033 contains two identical high current output drivers. These drivers contain high speed bipolar transistors configured in a push-pull configuration. Each output driver is capable of pumping out 1A of current in less than 100ns. Each driver's power and ground are separated from the overall chip power and ground for added switching noise immunity. The HIDRV driver has a power supply, VCCQP, which can be either derived from an external voltage source or can be boot-strapped from a flying-capacitor as is shown in Figure 1. In the boot-strapped mode, C2 is alternately charged from VCC via the schottky diode DS2 and then boosted up when M1 is turned on. This provides a VCCQP voltage equal to 2*VCC - Vds(DS2); or about 9.5V with VCC=5V. This voltage is sufficient to provide the 9V gate drive to the external MOSFET that will be needed for achieving a low Rdson. Since the low side synchronous FET is referenced to ground, there is no need to boost the gate drive voltage and its VCCP power pin can just be tied to VCC.
Figure 4 shows a step-down DC-to-DC Converter with no feedback controller. The derivation of the basic step-down converter will serve as a basis for the design equations for the RC5033 in Figure 1. In Figure 5, the basic operation begins by closing the switch, S1. When S1 is closed the input voltage VB is impressed across the inductor L1. The current flowing in the inductor is given by the following equation: IL=(VB- Vo)Ton/L; where Ton is the time duration for S1 to be closed. When S1 is open, the diode will conduct the inductor current and the output current will be delivered to the load according to the equation: IL=Vo(T - Ton)/L; where T- Ton is the time duration for S1 to be off. By solving these two equations we can arrive at the basic relationship for the output voltage of a step-down converter: Vo= VB(Ton/T).
S1 L1 +
2
Vb
1
1
1
D1
2
C1
2
RL Vout -
65-5033-09
Figure 5. Simple Buck DC-DC Converter
11
PRODUCT SPECIFICATION
RC5033
Selecting the Inductor
Preliminary Information
The inductor is one of the most critical components to be selected in the DC-to-DC converter application. The critical parameters are inductance (L), max DC current (Imax), and the coil resistance (Rl). The inductor core material is a critical factor in determining the amount of current that the inductor will be able to handle. As with all engineering designs there are trade- offs for various types of inductor core materials. In general, Ferrites are popular because of their low cost, low EMI, and high frequency (>500kHz) characteristics. Molypermalloy powder (MPP) materials have good saturation characteristics and low EMI with low hysteresis losses; however they tend to be expensive and are more efficiently utilized at frequencies below 400kHz. DC winding resistance is another critical parameter. In general, the DC resistance should be kept as low as possible. The power loss in the DC resistance will degrade the efficiency of the converter by the relationship: Power Loss = (Io)2*Rl. The value of the inductor is a function of the switching frequency (Ton) and the maximum inductor current. The max inductor current can be calculated from the relationship:
2I L I MAX = --------------------------------------------------------------V IN - V OUTo ae ----------------------------- + 1 F O T ON e V OUT - V D o
Since the value of the sense resistor is generally in the miliohm region, care should be taken in the layout of the PCB. Trace resistance can contribute significant errors. The traces to the IFB and VFB pins of the RC5033 should be Kelvin connected to the pads of the current-sense resistor as shown in the sample layout Figure 5. To minimize the influence of noise the two traces should be run next to each other and the pins should be bypassed with a .1uF to GND as close to the device pins as possible.
Filter Capacitors
Good ripple performance and transient response are functions of the filter capacitors. Since the 5V input for a PC motherboard can be located several inches away from the DC-to-DC converter, input capacitance can play an important role in the load transient response of the RC5033. In general, the higher the input capacitance, the more charge storage is available for improving the current transfer through the top-side FET. A good rule of thumb is that for each watt of output power that you wish to deliver, there should be around 10uF of input capacitance. Low "ESR" capacitors are best suited for this application and can have an influence on the converter's efficiency. The input capacitor should be placed as close to the drain of the top-side FET as possible to reduce the effect of ringing that can be caused by large trace lengths. The ESR rating of a capacitor is a difficult number to pin down. ESR or Equivalent Series Resistance, is defined at the resonant impedance of that capacitor. Since the capacitor is actually a complex impedance device having resistance, inductance and capacitance, it is quite natural for it to have an associated resonant frequency. As a rule, the lower the ESR, the better suited the capacitor is for use in switching power supply applications. Many capacitor manufacturers do not supply ESR data. A useful estimate of the ESR can be obtained with the following equation: ESR = Pd/2pfC. Where Pd is the capacitor's dissipation factor and f is the frequency of measure and C is the capacitance in farads. With this in mind, calculating the output capacitance correctly is crucial to the performance of the DC-to-DC converter. The output capacitor determines the overall loop stability, output voltage ripple, and the transient load response. The calculation uses the following equation:
( V IN - V OUT )I MAX T ON ae ------------------------------------------------- + ILo e o V OUT C ( mF ) = ----------------------------------------------------------------------------Vr
Where: Fo is the desired clock frequency Ton is the max on time of the M1 FET Vd is the forward voltage of the schottky diode D1 Then the inductor value can be calculated with the relationship:
V IN - V DSON L = --------------------------------- ( T ON ) I MAX
Where: Vdson is the voltage across the drain-source of the M1 FET when switched on. (this can be calculated by RDSon * Imax)
Current-Sense Resistor
The current sense resistor will carry all of the peak current of the inductor. This current will be more than the designed for load current. The RC5033 will begin to limit the output current to the load by turning off the top-side FET driver when the voltage across the current-sense resistor exceeds 100mV. When this happens the output voltage will temporarily go out of regulation. As the voltage across the resistor becomes larger, the top-side FET will turn off more and more until the current limit value is reached and then the RC5033 will continuously deliver the limit current at a reduced output voltage level. To insure that load transient conditions do not momentarily cause deregulation of the output voltage, a 20% margin in the limit voltage is advisable. Thus the resistor should be set by the relationship: R = 100 mV/ Ipeak Where: Ipeak = Imax * 1.33 12
Where: Vr is the desired output ripple voltage
Schottky Diode Selection
The application circuit diagram shows two schottky diodes, DS1 and DS2. DS1 is used in parallel of M2 in order to prevent the lossy body diode in the FET from turning on. DS2 serves a dual purpose. As it is configured, it allows the VCCQP supply pin of the RC5033 to be bootstrapped up to
RC5033
PRODUCT SPECIFICATION
9V by using the bootstrap capacitor C2. When the lower FET M2 is turned on, one side of the capacitor C2 is connected to GND while the other side of the cap is being charged up through D2 to a voltage that is Vin - Vd. When the lower FET turns off and the upper one turns on, the voltage that is supplied to the VCCQP pin is 2Vin - Vd. The voltage then that is applied to the gate of the FET is VCCQP - Vsat, typically around 9V. It is important in the selection of DS1 and DS2 that they have a low forward voltage drop as this directly affects the regulator efficiency. The other job that DS2 performs is that of bootstrapping VCCQP during startup. It is possible to cause the output stage to latchup if the VCCQP supply is brought up before the other VCC supplies of the RC5033. It is therefore advisable that DS2 be connected even in applications that do not utilize the bootstrapping technique for VCCQP. An alternate application could tie the VCCQP supply pin to the +12V power supply in the PC, thus eliminating the need for C2 and forcing the Rdson of M1 even lower by increasing its Vgs.
MOSFET Switches
the FET is going to lower the overall efficiency. In higher current applications, the upper FET can be paralleled to provide greater current capability; however, the lower FET doesn't necessarily have to be doubled since it is on only a fraction of the time that the upper FET is on.
PCB Layout and Grounding
As is the case with most analog circuitry, good layout practices are necessary to achieve the optimum in the overall performance of the DC-to-DC converter. In general, it is always a good practice to have a tight layout that attempts to minimize short low inductance wiring to the RC5033. The use of multilayer PCB is recommended. In particular, it is recommended to have a continuos ground plane beneath the circuit, 2oz copper would be preferred in high current applications. As was stated previously, the current-sense resistor, R1, should be located as close to the RC5033 as possible and the IFB and VFB traces should be Kelvin connected to the pads of R1. To minimize switching losses and noise, place M1, M2, L and DS2 as close together as possible. Also try to keep the HIDRV and LODRV gate drive signal traces as short as possible. It is recommended that the noisy switching part of the circuit be kept away from the low current pins on the chip such as IFB, VFB, ADJ3, ADJ1, and CEXT. Keep the 0.1uF bypass capacitors as close to the chip pins as possible. All of the ground pins should be connected to the ground plane directly under the chip. A sample layout is provided in Figure 6.
Preliminary Information
The MOSFET switches in the RC5033 applications circuit are N-channel "logic-level" FETs. This means that they will be fully on with a Vgs of 4V. Many manufacturers make logic-level FETs and the trick is to choose the one with the lowest RDSon at the given Imax current level. The value of RDSon directly enters into the efficiency equation as a power loss. Also influencing the efficiency is the gate charge of the FET and the clock frequency of the RC5033. At higher clocking rates the amount of charge needed to be delivered to
13
PRODUCT SPECIFICATION
RC5033
Preliminary Information
Figure 6. Sample PCB Layout
14
RC5033
PRODUCT SPECIFICATION
Mechanical Dimensions - 16-Lead SOIC Package
Symbol A A1 B C D E e H h L N a ccc Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
.093 .104 .004 .012 .013 .020 .009 .013 .398 .413 .291 .299 .050 BSC .394 .010 .016 16 0 -- 8 .004 .419 .020 .050
2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 10.10 10.50 7.40 7.60 1.27 BSC 10.00 0.25 0.40 16 0 -- 8 0.10 10.65 0.51 1.27
3 6
Preliminary Information
16
9
E
H
1
8
D A e B A1 SEATING PLANE -C- LEAD COPLANARITY ccc C a
h x 45 C
L
15
PRODUCT SPECIFICATION
RC5033
Ordering Information
Product Number RC5033M Package 16 SOIC qJA 85C/W
Preliminary Information
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS30005033 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC5034
High Accuracy Synchronous DC-DC Converter
Features
* * * * * * * * * * PentiumTM VREF; 2% accuracy >85% Efficiency 350uA quiescent current in shutdown Fast transient response Soft control power-up Over-Voltage Protection Factory trimmed low TC reference voltage Adjustable oscillator frequency Drives N-Channel MOSFETs; to 1 MHz 16 pin SOIC package
Applications
* 3.3V power supply for PentiumTM based CPUs requiring 2% VRE specification motherboards
Preliminary Information
Description
The RC5034 is a synchronous mode DC-DC controller IC dedicated to providing a 5V to 3.52V conversion for PentiumTM CPUs that require the 2% VRE voltage specification. It can be configured in both the synchronous and nonsynchronous modes and with the proper applications circuitry can be used to deliver load current greater than 10 Amps. The RC5034 is designed to operate in a standard PWM control mode under heavy load conditions and as a PFM controller in light load conditions. Its highly accurate low TC reference eliminates the need for precision external components in order to achieve tight tolerance voltage regulation. An integrated Over-Voltage protection function constantly monitors the output voltage and shuts down the power to the CPU in the event of a out-of-tolerance voltage situation, thereby protecting the CPU. The programmable oscillator can operate from 200KHz to greater than 1MHz to provide for flexibility in choosing external components such as inductors, capacitors, and Power MOSFETs.
Block Diagram
OSC
+ - I + - I - + + - + - + I + - +
VIN
-
I
-
DIGITAL CONTROL
VO
VREF
VREF
65-5034-01
Rev. 0.9.6
PRELIMINARY INFORMATION describes products that are not in full production at the time of printing. Specifications are based on design goals and limited characterization. They may change without notice. Contact Fairchild Semiconductor for current information.
PRODUCT SPECIFICATION
RC5034
Pin Assignments
ON/OFF IFB VFB VCCA VCCD VCCP LODRV GNDP
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
65-5034-02
CEXT GNDA ADJ3 GNDD NC NC VCCQP HIDRV
Pin Definitions
Preliminary Information
Pin Name On/Off IFB VFB VCCA VCCD VCCP LODRV GNDP HIDRV VCCQP NC GNDD ADJ3 GNDA CEXT
Pin Number 1 2 3 4 5 6 7 8 9 10 11, 12 13 14 15 16 Current Feedback Input. Voltage Feedback Input. Analog VCC. Digital VCC.
Pin Function Description A low level on this pin will power down; tie to VCCD if not used.
VCC for synchronous FET output drivers. Synchronous FET driver output. Power ground for high current drivers. High side FET driver output. VCC for High side FET output driver No Connections leave open Digital ground. VREF Analog ground. External capacitor for setting oscillator frequency.
Absolute Maximum Ratings
(beyond which the device may be damaged)1 Parameter VCCP VCCQP TJ TA TS TL Low Driver Supply High Driver Supply Junction Temperature Ambient Operating Temperature Storage Temperature Lead Soldering Temperature (10 seconds) 0 -65 Conditions Min Typ Max 13 13 175 70 150 300 Units V V C C C C
Note: 1. Functional operation under any of these conditions is NOT implied.
2
RC5034
PRODUCT SPECIFICATION
Operating Conditions
Parameter VCC VCCP VCCQP VIH VIL Supply Voltage Low Driver Supply High Driver Supply Input Voltage, Logic HIGH Input Voltage, Logic LOW Conditions Min 4.5 4.5 9 2 0.8 Typ 5 5 Max 7 7 13 Units V V V V V
DC Electrical Characteristics
(VCC = 5V, fosc = 650 KHz, and TA = +25C unless otherwise noted)
Preliminary Information
Parameter VO IO Vref Acc VTC LDR LIR VR Cum Acc Eff Iodr Pd Output Voltage Output Current Reference Acc Output Voltage TC Load Regulation Line Regulation Output Voltage Ripple Cumulative Efficiency Output Driver I Power Dissipation Accuracy2
Conditions TA = 0-70C See Figure 1 for application
Min 3.45
Typ 3.52 5 .15 -40
Max 3.6 1
Units V A % ppm %Vo %Vo mV
0.5 to 7A VCC = 5% TA = 0-70C Synchronous mode > 2A Open Loop 85 0.5
0.25 0.1 15 1 88 0.7 0.1 0.2 2.1
% % A W
Notes: 1. Functional operation under any of these conditions is not implied. Performance is guaranteed only if Operating Conditions are not exceeded. 2. Output Voltage accuracy, Tempco, load regulation, ripple, and transient performance determine the Cumulative Accuracy.
AC Electrical Characteristics1
(VCC = 5V, fosc = 650 KHz, and TA = +25C unless otherwise noted) Parameter Tr Fosc Osc Acc Dtc Dtcm Imax Iscp Ovp Trimax Tssp Response Time Oscillator Range Fosc Accuracy Max Duty Cycle Min Duty Cycle Imax Threshold Short Circuit Prot Over Voltage Prot Response to Imax Soft start response PWM mode PFM mode 30 80 20 15 10 30 90 Conditions Il=0.5A to 5.5A 0.2 10 95 100 Min Typ 10 1.2 Max Units ms MHz % % ns mV mV %Vo ns ms
3
PRODUCT SPECIFICATION
RC5034
Typical Operating Characteristics1
Efficiency vs Output Current (FOSC = 400 KHz)
100 3.6
Load Regulation (FOSC = 300 KHz)
Efficiency (%)
90
70 60 50 0 2 4 6
VOUT
80
3.55
3.5
3.45
0
2
4
6
8
Output Current (A)
Output Current (A)
Preliminary Information
Efficiency vs Output Current (FOSC = 650 KHz)
100 3.6
Load Regulation (FOSC = 650 KHz)
Efficiency (%)
90 80 70 60 50 0 2 4 6 3.45 3.55
VOUT
3.5
0
2
4
6
8
Output Current (A)
Output Current (A)
Efficiency vs Output Current (FOSC = 1 MHz)
100 3.6
Load Regulation (FOSC = 1 MHz)
Efficiency (%)
90
70 60 50 0 2 4 6
VOUT
80
3.55
3.5
3.45 0 2 4 6 8
Output Current (A)
Output Current (A)
65-5034-03
Note: 1. Data taken with circuit of Figure 1.
4
RC5034
PRODUCT SPECIFICATION
Typical Operating Characteristics (continued)
Line Regulation vs. Output Load (FOSC = 400 KHz)
0.3
Line Reg (%)
0.25 0.2 0.15 0.1 0.05 0 0 2 4 6 8
Reference Tempco VREF
3.57 3.56 3.55 3.54 3.53 0 20 40 60 80
Output Current (A)
Temp
Preliminary Information
Line Regulation vs. Output Load (FOSC = 650 KHz)
0.3
CEXT vs. Oscillator Frequency
200
Line Reg (%)
0.25 0.2 0.15 0.1 0.05 0 0 2 4 6 8
CEXT (pF)
150 100 50 0 0 4 4 8
Output Current (A)
Frequency (Hz)
Line Regulation vs. Output Load (FOSC = 1 MHz)
0.25 0.2
Line Reg (%)
0.15 0.1 0.05 0 -0.05 -0.1 0 2 4 6 8
65-5034-04
Output Current (A)
5
PRODUCT SPECIFICATION
RC5034
Typical Operating Characteristics (continued)
VOUT (50mV/division) VOUT (50mV/division) Hidrv (5V/division)
Preliminary Information
Hidrv (5V/division)
TIME ( 1ms/division)
TIME ( 1ms/division)
AC Ripple response .2A Load
AC Ripple response 5A Load
IOUT (2A/division)
VOUT (50mV/division)
TIME ( 200ms/division)
IOUT (2A/division)
VOUT (50mV/division)
TIME ( 20ms/division)
Transient Response .2A to 5A Load
Transient Response Magnified
VCC C5 220F DS2 EC10QS02 M1 MTD20N03HDL 9 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1 C2 1F L1 1.3H R1 0.0121/2 VO C9 660F
RC5034
GND
M2 MTD20N03HDL
DS1 MBRB1545CT
C1 47pF
C13 4.7F
65-5034-05
Figure 1. Synchronous 7A Schematic
6
RC5034
PRODUCT SPECIFICATION
VCCP C5 220F DS2 EC10QS02 M1 MTD20N03HDL 9 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1 C2 1F L1 R1 CDRH127-1R3NC 0.0121/2 VO C9 330F C8 660F
+12V
RC5034
DS1 MBRB1545CT
GND
C1 47pF
C13 4.7F
65-5034-06
Preliminary Information
Figure 2. Non-Synchronous 7A Circuit
RC5034 Standard Application Circuit Bill of Materials Ref Designator L1 M1,M2 DS1 DS2 R1 C5 C9 C2 C1 C4 C13 Quantity 1 2 1 1 1 1 2 1 1 2 1 Part No. 1.3 mH CDRH127-1R3NC MTD20N03HDL MBRB1545CT EC10QS02L .012W LRC-2512 220 mF OS-CON 10SA220M 330 mF OS-CON 10SA330M 1uF 47pF 0.1uF 4.7uF
Table 1. Components for RC5034
Manufacturer Sumida Motorola Motorola Nihon IRC Sanyo Sanyo Monolithic ceramic Cap SMD Cap SMD Cap SMD Cap
RC5034 Alternate Suppliers of Components Ref Designator L1 M1,M2 Quantity 1 2 Alternate Part No. 1.3 mH PE-53680 2SK1388 IRLZ44N Si4410DY DS1 DS2 R1 1 1 1 C10T02QL SR1620C MBRS140T3 .012W WSL-2512
Table 2. Alternate Components Selection
Alternate Manufacturer Pulse Engineering Fuji International Rectifier Temic (Siliconix) Nihon Rectron Motorola DALE
7
PRODUCT SPECIFICATION
RC5034
Applications Discussion
VCCP C5 200F DS2 EC10QS02 M1 Si9410 9 +12V 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1 C2 1F L1 1.5H R1 0.0121/2 3.54V VO C9 660F
RC5034
DS1 MBRB1545CT
GND
Preliminary Information
C1 47pF
C13 4.7F C1 47pF
R2 18K
- +
+ -
LM308A I M2 2SK1388 VO2 2.9V
R3 82K
65-5034-07
Figure 3. Dual Regulator Applications Circuit
Dual Power Supply Application
In some CPU power applications there may be a need for a split voltage converter. The circuit in Figure 3 addresses this need with only minimal component count. The basic RC5034 non-synchronous DC-DC converter is augmented with an op-amp, a power MOSFET, and some 1% resistors to provide a dual power supply with one voltage set to 3.5V and the other, slaved off of the 3.5V, set to 2.9V. In this configuration, the RC5034 converts the 5V to 3.5V with high efficiency. By using the op-amp, power FET, and the resistors, a low-dropout linear regulator is realized that can be run off of the 3.5V. The 2.9V linear regulator has a relatively high efficiency just due to the fact that the ratio of 2.9V/3.5V is close to 88%. The power FET is a low Rdson n-channel MOSFET, and thus it is reasonably inexpensive. The opamp can be a garden variety, though the input bias current and output slew rate need to be considered to optimize accuracy and transient response. The overall efficiency of this power supply system will very much depend upon the percentage of power used on each power output. Overall, the efficiency of this system will be lower than if both supplies were implemented as switchers; however, the added savings of the part count reduction may more than compensate for the overall lower efficiency.
Standard Application Circuit
The circuit shown in Figure 1 along with its components and values has been designed as representative of the typical application involving the RC5034 for a PentiumTM CPU. Use of the standard application circuit will deliver the performance curves shown under the Typical Operating Characteristics section of the data sheet. Many users will want to develop their own DC-DC converter solution that is uniquely tailored to a specific application requirement. In that case, the users should review the detailed information in the Design Procedure and Applications Information section of the data sheet.
Detailed Description
The RC5034 is a programmable voltage synchronous controller. When designed around the appropriate external components, it can be configured to deliver more than 10A of output current. During heavy loading conditions the RC5034 functions as a current-mode PWM step down regulator. Under light loading conditions, the regulator functions in the PFM or pulse skipping mode, thereby increasing its efficiency under light loads.
8
RC5034
PRODUCT SPECIFICATION
Main Control Loop
Internal Reference
The main control loop of the regulator (see Block Diagram) contains two main blocks, the analog control block and the digital control block. The analog control block consists of signal conditioning amplifiers that feed into a set of fast comparators which provide the inputs to the digital control block. The signal conditioning block takes inputs from the IFB(current feedback) and VFB(voltage feedback) pins and then sets up two controlling signal paths. The voltage control path gains up the VFB signal and presents that signal to one of the summing amplifier inputs. The current control path takes the difference between the IFB and VFB pins and presents that signal to another input of the summing amplifier. These two signals are then summed together with the slope compensation input from the oscillator and the output is then presented to a comparator. This comparator provides the main PWM control signal to the digital control block. There are three other comparators in the analog control block. The first two control the thresholds of where the RC5034 goes into its pulse skipping mode during light loads and the second controls the point at which the max current comparator disables the output drive signal to the upper power MOSFET. The third comparator determines when the synchronous mode bottom side power MOSFET will be enabled and disabled. The digital controller section is designed to take the comparator inputs along with the main clock signal from the oscillator and provide the appropriate pulses to the HIDRV and LODRV output pins that will in turn control the external power MOSFETs. This digital section was designed in high speed schottky transistor logic which allows the RC5034 to clock up to speeds greater then 1MHz. This section is responsible for providing the break-before-make timing that ensures that both external FETs will not be on at the same time.
High Current Output Drivers
The reference in the RC5034 is a precision band-gap type reference. Its temperature coefficient is trimmed to provide a near zero TC. For a guaranteed stable operation under all loading conditions, a 0.1mF capacitor is recommended on the VREF output pin.
Over -Voltage Protection
The RC5034 provides a constant monitor of the output voltage for over-voltage protection. Should the voltage at the VFB pin exceed 20% of the selected program voltage, then an overvoltage condition will be assumed to exist and the RC5034 will shut down the output drive signals to the power FETs.
Oscillator
Preliminary Information
The RC5034 oscillator is designed as a fixed current capacitor charging oscillator. An external capacitor allows for maximum flexibility in choosing the associated external components for the RC5034. The oscillator frequency can be set from less than 200KHz to over 1MHz depending on the application requirements.
Design Procedure and Applications Information
Simple Step-Down Converter
The RC5034 contains two identical high current output drivers. These drivers contain high speed bipolar transistors configured in a push-pull configuration. Each output driver is capable of pumping out 1A of current in less than 100ns. Each driver's power and ground are separated from the overall chip power and ground for added switching noise immunity. The HIDRV driver has a power supply, VCCQP, which can be either derived from an external voltage source or can be boot-strapped from a flying-capacitor as is shown in Figure 1. In the boot-strapped mode, C2 is alternately charged from VCC via the schottky diode DS2 and then boosted up when M1 is turned on. This provides a VCCQP voltage equal to 2*VCC - Vds(DS2); or about 9.5V with VCC=5V. This voltage is sufficient to provide the 9V gate drive to the external MOSFET that will be needed for achieving a low Rdson. Since the low side synchronous FET is referenced to ground, there is no need to boost the gate drive voltage and its VCCP power pin can just be tied to VCC.
Figure 4 shows a step-down DC-to-DC Converter with no feedback controller. The derivation of the basic step-down converter will serve as a basis for the design equations for the RC5034 in Figure 1. In Figure 4, the basic operation begins by closing the switch, S1. When S1 is closed the input voltage VB is impressed across the inductor L1. The current flowing in the inductor is given by the following equation: IL=(VB- Vo)Ton/L; where Ton is the time duration for S1 to be closed. When S1 is open, the diode will conduct the inductor current and the output current will be delivered to the load according to the equation: IL=Vo(T - Ton)/L; where T- Ton is the time duration for S1 to be off. By solving these two equations we can arrive at the basic relationship for the output voltage of a step-down converter: Vo=VB(Ton/T).
S1 L1 +
2
Vb
1
1
1
D1
2
C1
2
RL Vout -
65-5034-08
Figure 4. Simple Buck DC-DC Converter
9
PRODUCT SPECIFICATION
RC5034
Selecting the Inductor
Preliminary Information
The inductor is one of the most critical components to be selected in the DC-to-DC converter application. The critical parameters are inductance (L), max DC current (Imax), and the coil resistance (Rl). The inductor core material is a critical factor in determining the amount of current that the inductor will be able to handle. As with all engineering designs there are trade- offs for various types of inductor core materials. In general, Ferrites are popular because of their low cost, low EMI, and high frequency (>500kHz) characteristics. Molypermalloy powder (MPP) materials have good saturation characteristics and low EMI with low hysteresis losses; however they tend to be expensive and are more efficiently utilized at frequencies below 400kHz. DC winding resistance is another critical parameter. In general, the DC resistance should be kept as low as possible. The power loss in the DC resistance will degrade the efficiency of the converter by the relationship: Power Loss = (Io)2*Rl. The value of the inductor is a function of the switching frequency (Ton) and the maximum inductor current. The max inductor current can be calculated from the relationship:
2I L I MAX = --------------------------------------------------------------V IN - V OUTo ae ----------------------------- + 1 F O T ON e V OUT - V D o
Since the value of the sense resistor is generally in the miliohm region, care should be taken in the layout of the PCB. Trace resistance can contribute significant errors. The traces to the IFB and VFB pins of the RC5034 should be Kelvin connected to the pads of the current-sense resistor as shown in the sample layout Figure 5. To minimize the influence of noise the two traces should be run next to each other and the pins should be bypassed with a .1uF to GND as close to the device pins as possible.
Filter Capacitors
Good ripple performance and transient response are functions of the filter capacitors. Since the 5V input for a PC motherboard can be located several inches away from the DC-to-DC converter, input capacitance can play an important role in the load transient response of the RC5034. In general, the higher the input capacitance, the more charge storage is available for improving the current transfer through the top-side FET. A good rule of thumb is that for each watt of output power that you wish to deliver, there should be around 10uF of input capacitance. Low "ESR" capacitors are best suited for this application and can have an influence on the converter's efficiency. The input capacitor should be placed as close to the drain of the top-side FET as possible to reduce the effect of ringing that can be caused by large trace lengths. The ESR rating of a capacitor is a difficult number to pin down. ESR or Equivalent Series Resistance, is defined at the resonant impedance of that capacitor. Since the capacitor is actually a complex impedance device having resistance, inductance and capacitance, it is quite natural for it to have an associated resonant frequency. As a rule, the lower the ESR, the better suited the capacitor is for use in switching power supply applications. Many capacitor manufacturers do not supply ESR data. A useful estimate of the ESR can be obtained with the following equation: ESR = Pd/2pfC. Where Pd is the capacitor's dissipation factor and f is the frequency of measure and C is the capacitance in farads. With this in mind, calculating the output capacitance correctly is crucial to the performance of the DC-to-DC converter. The output capacitor determines the overall loop stability, output voltage ripple, and the transient load response. The calculation uses the following equation:
( V IN - V OUT )I MAX T ON ae ------------------------------------------------- + ILo e o V OUT C ( mF ) = ----------------------------------------------------------------------------Vr
Where: Fo is the desired clock frequency Ton is the max on time of the M1 FET Vd is the forward voltage of the schottky diode D1 Then the inductor value can be calculated with the relationship:
V IN - V DSON L = --------------------------------- ( T ON ) I MAX
Where: Vdson is the voltage across the drain-source of the M1 FET when switched on. (this can be calculated by RDSon * Imax)
Current-Sense Resistor
The current sense resistor will carry all of the peak current of the inductor. This current will be more than the designed for load current. The RC5034 will begin to limit the output current to the load by turning off the top-side FET driver when the voltage across the current-sense resistor exceeds 100mV. When this happens the output voltage will temporarily go out of regulation. As the voltage across the resistor becomes larger, the top-side FET will turn off more and more until the current limit value is reached and then the RC5034 will continuously deliver the limit current at a reduced output voltage level. To insure that load transient conditions do not momentarily cause deregulation of the output voltage, a 20% margin in the limit voltage is advisable. Thus the resistor should be set by the relationship: R = 100 mV/ Ipeak Where: Ipeak = Imax * 1.33 10
Where: Vr is the desired output ripple voltage
Schottky Diode Selection
The application circuit diagram shows two schottky diodes, DS1 and DS2. DS1 is used in parallel of M2 in order to prevent the lossy body diode in the FET from turning on. DS2 serves a dual purpose. As it is configured, it allows the VCCQP supply pin of the RC5034 to be bootstrapped up to 9V by using the bootstrap capacitor C2. When the lower FET
RC5034
PRODUCT SPECIFICATION
M2 is turned on, one side of the capacitor C2 is connected to GND while the other side of the cap is being charged up through D2 to a voltage that is Vin - Vd. When the lower FET turns off and the upper one turns on, the voltage that is supplied to the VCCQP pin is 2Vin - Vd. The voltage then that is applied to the gate of the FET is VCCQP - Vsat, typically around 9V. It is important in the selection of DS1 and DS2 that they have a low forward voltage drop as this directly affects the regulator efficiency. The other job that DS2 performs is that of bootstrapping VCCQP during startup. It is possible to cause the output stage to latchup if the VCCQP supply is brought up before the other VCC supplies of the RC5034. It is therefore advisable that DS2 be connected even in applications that do not utilize the bootstrapping technique for VCCQP. An alternate application could tie the VCCQP supply pin to the +12V power supply in the PC, thus eliminating the need for C2 and forcing the Rdson of M1 even lower by increasing its Vgs.
MOSFET Switches
delivered to the FET is going to lower the overall efficiency. In higher current applications, the upper FET can be paralleled to provide greater current capability; however, the lower FET doesn't necessarily have to be doubled since it is on only a fraction of the time that the upper FET is on.
PCB Layout and Grounding
As is the case with most analog circuitry, good layout practices are necessary to achieve the optimum in the overall performance of the DC-to-DC converter. In general, it is always a good practice to have a tight layout that attempts to minimize short low inductance wiring to the RC5034. The use of multilayer PCB is recommended. In particular, it is recommended to have a continuos ground plane beneath the circuit, 2oz copper would be preferred in high current applications. As was stated previously, the current-sense resistor, R1, should be located as close to the RC5034 as possible and the IFB and VFB traces should be Kelvin connected to the pads of R1. To minimize switching losses and noise, place M1, M2, L and DS2 as close together as possible. Also try to keep the HIDRV and LODRV gate drive signal traces as short as possible. It is recommended that the noisy switching part of the circuit be kept away from the low current pins on the chip such as IFB, VFB, ADJ3, ADJ1, and CEXT. Keep the 0.1uF bypass capacitors as close to the chip pins as possible. All of the ground pins should be connected to the ground plane directly under the chip. A sample layout is provided in Figure 5.
Preliminary Information
The MOSFET switches in the RC5034 applications circuit are N-channel "logic-level" FETs. This means that they will be fully on with a Vgs of 4V. Many manufacturers make logic-level FETs and the trick is to choose the one with the lowest RDSon at the given Imax current level. The value of RDSon directly enters into the efficiency equation as a power loss. Also influencing the efficiency is the gate charge of the FET and the clock frequency of the RC5034. At higher clocking rates the amount of charge needed to be
11
PRODUCT SPECIFICATION
RC5034
Preliminary Information
Figure 5. Sample PCB Layout
12
RC5034
PRODUCT SPECIFICATION
Notes:
Preliminary Information
13
PRODUCT SPECIFICATION
RC5034
Notes:
Preliminary Information
14
RC5034
PRODUCT SPECIFICATION
Mechanical Dimensions - 16 Lead SOIC Package
Symbol A A1 B C D E e H h L N a ccc Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
.093 .104 .004 .012 .013 .020 .009 .013 .398 .413 .291 .299 .050 BSC .394 .010 .016 16 0 -- 8 .004 .419 .020 .050
2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 10.10 10.50 7.40 7.60 1.27 BSC 10.00 0.25 0.40 16 0 -- 8 0.10 10.65 0.51 1.27
3 6
Preliminary Information
16
9
E
H
1
8
D A e B A1 SEATING PLANE -C- LEAD COPLANARITY ccc C a
h x 45 C
L
15
PRODUCT SPECIFICATION
RC5034
Ordering Information
Product Number RC5034M Package 16 SOIC qJA 85C/W
Preliminary Information
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS30005034 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
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RC5035A
Dual Precision Voltage Regulators
Features
* Combines switching regulator and low dropout linear regulator in single chip * Enable function switches from single to dual output mode * Overvoltage and short circuit protection * Drives N-Channel MOSFETs * Precision trimmed low TC voltage reference * Soft start control during power-up * 88% Efficiency for switching regulator * 16 pin SOIC package
Applications
* Switchable single/dual power supply for Pentium(R) P54C/ P55C flexible motherboard implementation
Advanced Information
Description
The RC5035 combines a switch-mode DC-DC converter with a low-drop-out linear regulator providing a 5V to 3.3V and 2.8V conversion for CPUs that require split power supplies. It can be configured with the proper applications circuitry to deliver load currents greater than 10 Amps. The RC5035 is designed to operate in a "constant on-time" (patent pending) control mode under all load conditions. Its highly accurate low TC reference eliminates the need for precision external components in order to achieve tight tolerance voltage regulation. Using on-chip precision resistors, the RC5035A can generate the accurate output voltages required by Intel and Cyrix processors. The programmable oscillator can operate up to1MHz for flexibility in choosing external components such as inductors, capacitors, and Power MOSFETs. Short circuit current protection is provided on both the switch mode as well as the linear regulator.
Block Diagram
+12V VIN
gm gm
V/I
CONSTANT ON-TIME OSCILLATOR V/I gm IO ANALOG SWITCH VH VL VOSW ION
VREF
REF
+ - Iset
VOL
RC5035A
FBSW ENABLE
65-5035-01
Rev. 0.5.0
ADVANCED INFORMATION data sheets provide specification for products not yet complete or characterized. They provide design target information for customer planning purposes.
RC5035
PRODUCT SPECIFICATION
Pin Assignments
ENABLE VREF IFBH IFBL VFBSW VCCA VFBL GNDP
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
65-5035-02
VFBSW2 CEXT GNDA VSCL VOL VCCL VCCP VOSW
Pin Function Description
Advanced Information
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Pin Name ENABLE VREF IFBH IFBL VFBSW VCCA VFBL GNDP VOSW VCCP VCCL VOL VSCL GNDA CEXT VFBSW2
Pin Function Description Linear regulator enable/VOSW voltage selection Voltage reference output High side current feedback for switching regulator Low side current feedback for switching regulator Voltage feedback for switching regulator Analog Input supply; Nominally 5V Voltage feedback for linear regulator Power ground for high current drivers FET driver output for switching regulator Input supply for FET output driver; see figures 1,2 for typical connection Input supply for linear regulator; Nominally 12V Linear regulator op-amp output Short circuit current sense input for linear regulator Analog ground External capacitor for setting oscillator frequency of switching regulator Secondary voltage feedback for switching regulator
Absolute Maximum Ratings
Parameter Control Supply Voltages, VCCA, VCCL Output Driver Supply Voltage, VCCP Junction Temperature, TJ Storage Temperature, TS Lead Soldering Temperature, 10 seconds -65 Min Typ Max 13 13 +175 +150 300 Units V V C C C
Note: 1. Functional operation under any of these conditions is not implied. Performance is guaranteed only if Operating Conditions are not exceeded.
2
PRODUCT SPECIFICATION
RC5035
Operating Conditions
Parameter Analog Supply Voltage, VCCA Linear Supply Voltage, VCCL Driver Supply Voltage, VCCP ENABLE HIGH threshold ENABLE LOW theshold Ambient Temperature, TA Linear Regulator OFF Linear regulator ON 0 2.0 0.8 70 Conditions Min 4.75 Typ 5 12 9 12 Max 5.25 Units V V V V V C
DC Electrical Characteristics - Switch-Mode Regulator
Advanced Information
(VCCA = 5V, VCCL = 12V, TA = 0-70C using circuit of figure 1, unless otherwise noted) Parameter Output Voltage, VOSW Output Current, ISW Setpoint Accuracy Output Temperature Drift, TC Load Regulation Load Regulation Line Regulation Output Ripple, peak-peak Cumulative Efficiency Output Driver Current Short Circuit Protection Threshold Power Dissipation Thermal Impedance, qJA Accuracy1 Vref = 1.5V, ISW=3.5A TA = 0-70C ISW = 0.5A to 3.5A or 3.5A to 7A ISW = 0.5A to 3.5A or 3.5A to 8.5A VCCA = 5V 5% 20MHz BW, ISW=8A TA = 0-70C ISW = 3.5A Open Loop Rsense = .006W No external components Conditions Min 1.5 8 0.5 24 0.6 1.0 0.03 20 2.0 88 0.7 18 0.1 80 2.9 Typ Max 3.6 10 1 Units V A % ppm %Vo %Vo %Vo mV % % A A W C/W
Note: 1. Cumulative accuracy includes Setpoint Accuracy, Temperature drift, line and load regulation, ripple and transient performance.
3
RC5035
PRODUCT SPECIFICATION
DC Electrical Characteristics - Linear Regulator
(VCCA = 5V,VCCL = 12V, TA = 0-70C using circuit in figure 1, unless otherwise noted) Parameter Output Voltage, VOL Output Current, IL Setpoint Accuracy Output Temperature Drift, TC Load Regulation Line Regulation Output Noise Cumulative Accuracy1 ISW=5A Rsense = .005W No external components Crosstalk2 Short Circuit Current Op-amp Output Current Power Dissipation Vref = 1.5V, IL=0.5A TA = 0-70C IL = 0.5A to 3A VCCL = 5V 5% 0.1 to 20KHz Conditions Min 1.5 3 0.5 24 0.3 0.03 1 2 35 5 10 110 Typ Max 3.6 5 1 Units V A % ppm %Vo %Vo mV % mV A mA mW
Advanced Information
Note: 1. Cumulative accuracy includes Setpoint Accuracy, Temperature drift, line and load regulation, ripple and transient performance. 2. Crosstalk is defined as the amount of switching noise from the switched-mode regulator that appears on the output of the linear regulator when both outputs are in a static load condition.
AC Electrical Characteristics Switch Mode Regulator
(VCCA = 5V, VCCL = 12V, TA = 0-70C using circuit of figure 1, unless otherwise noted) Parameter Response Time Oscillator Range Minimum On Time Response time to short circuit Soft start response time Conditions ISW = 0.5A to 8A CEXT = 50pF 0.2 2 15 100 30 Min Typ 10 1 Max Units ms MHz us us us
4
PRODUCT SPECIFICATION
RC5035
Application Information
+5V
C38 100nF 2K L2 2.6uH R45 R21 5m W
+12V
C55 1uF C53 100nF 120pF M3 2SK1388 Cext
C5 2 x 1200uF
C9
C8 R2 R49 390 DS2 1N5817 M1 2SK1388 1500uF
VREF
C25 22uF C1 100nF
1 2 3 4 5 6 7 8 RC5035
16 15 14 13 12 11 10 9
VOL P54C = No Output P55C = 3.3V @ 3A
10nF
11.3K
R3 10K
DS2 L1 4.7uH R1 6m W
P54C = 3.5V @ 8.6A P55C = 2.8V @ 5A VOSW
Advanced Information
DS1 MBRB1545CT
C10 3 x 1500uF
GND
R5 22K R4
R6 22K
R7 53K
CPU SELECT 0 = P55C 1 = P54C
18.8K
Figure 1: P54C/P55C Single/Dual Output Application Schematic
Table 1. RC5035 P54C/P55C Application Bill of Materials
Ref 1 2 1 1 3 3 1 3 1 1 1 1 1 1 2 1 1 1 Quantity L1 M1, M3 DS1 DS2 C1, C38, C53 C5, C8 C9 C10 C25 C55 Cext R1 R2 R3 R4, R4S R5 R21 L2 Part No. 4.7mF 2SK1388 MBRB1545CT 1N5817 100nF 6MV1500GX 10nF 6MV1500GX 22mF 1mF 120pF 0.006 22K 18.33K 33K 22K 0.005K 2.6mH Inductor N-Channel Power MOSFET Schottky-Motorola, 10A Schottky-General Instruments Chip Cap Sanyo 1500mF Electrolytic, ESR=44mW Chip Cap Sanyo 1500mF Electrolytic, ESR=44mW Tantalum Cap Tantalum Cap Chip Cap MnCu Jumper 1% Resistor 1% Resistor 0.1% Resistor 0.1% Resistor MnCu Jumper Inductor Manufacturer
5
RC5035
PRODUCT SPECIFICATION
+5V
C38 R45 100nF 2K L2 2.6uH R21 5m W
+12V
C53 100nF 120pF M3 2SK1388 Cext
C5
VOL
C9 1 16 15 14 RC5035 13 12 11 10 9 4.7uH DS1 MBRB1545CT R3 1N5817 M1 2SK1388 DS2 L1 R1 6m W R2 10nF C8 R49 390 DS2
VREF
C1 100nF
2 3 4 5 6 7
Advanced Information
8
VOSW
C10
GND
R5
R4
Figure 2. Dual Power Supply Application Schematic
6
PRODUCT SPECIFICATION
RC5035
Dual Power Supply Application
Some CPU power applications such as the Intel Pentium(R) P55C will require separate voltages for the CPU core and I/O circuitry. Currently, the voltage requirements for this processor are 2.8V for the CPU core and 3.3V for the I/O circuitry. The circuit in figure 1 addresses this requirement using a minimum of external components. The RC5035 includes an internal operational amplifier that can be combined with an external N-channel power MOSFET and 1% resistors (see Design Equations) to form a second power supply. In this configuration, both the switched-mode and linear power supplies can be programmed between 2.0V and 3.6V to meet a variety of dual voltage requirements. In the circuit configuration of figure 1, the switched-mode portion is used for the 5V to 2.8V conversion for the CPU core to realize the optimal package efficiency. The op-amp, power FET and resistors are combined to generate the 3.3V required by the I/O power plane. Analysis of the linear regulator portion from an efficiency standpoint reveals that for a 5V to 3.3V conversion, the efficiency is roughly 3.3/5, or 66%. For loads of 4A or lower, the power dissipation of the external MOSFET should not pose any thermal design problems if it is chosen wisely. The N-channel MOSFET must exhibit a low Rdson and should still be inexpensive and readily available. The overall efficiency of the dual power supply will vary depending upon the burden on each output. Therefore, the switchedmode supply should typically be utilized as the primary supply with the linear regulator portion being used to provide power for the output that is more lightly loaded.
For the lower performance models, a 3.3V 5% supply is acceptable. For improved compatibility, Intel has now respecified its 3.3V standard CPUs for operation at the new 3.5V VRE level. The P55C multimedia upgrade processor, due to be released in the latter part of 1996, requires separate voltages for the core and I/O circuitry. The nominal core voltage is currently 2.8V 100mV, while the I/O supply remains at a nominal 3.3V. It is therefore desirable to implement a power supply design that will automatically detect the CPU model present and program each output voltage accordingly. The circuit in figure 2 directly addresses this requirement. The basic purpose of this design is to provide an automatic switch between a single switched-mode power supply and a dual switching/linear power supply depending upon which CPU occupies the socket.
Advanced Information
Design Equations
Linear Regulator R2 + R3 V OUT = V REF ae --------------------o e R3 o Switched-mode Regulator R4 + R5 V OUT = V REF ae --------------------o e R4 o
To ease the task of identifying the CPU, the P55C processor includes a single-bit identification pin, VCC2DET, at location AL1, to distinguish itself from the standard Pentium(R) P54C processor. This pin is always bonded to ground on the P55C CPU, while it is an internal no connect on the P54C. Therefore, the addition of an external pull-up resistor allows the user to easily identify which processor occupies the CPU socket. The circuit in figure 2 also uses the CPU identification pin to select the appropriate output voltage for the CPU core power island and switch off the linear regulator output when only a single output is necessary. To optimize the overall efficiency of the power supply, the switching converter should be used to power the load that is most heavily burdened. Therefore, the obvious choice is to assign the switching converter as the CPU core supply. Using this configuration, the switched-mode supply will always be loaded whereas the linear regulator portion will only be burdened when the dual voltages are required. Because the I/O circuitry will always operate from a nominal 3.3V supply, the linear regulator output is set at a fixed 3.3V output using resistors R2 and R3. The CPU core supply is thus switched between 2.8V and 3.5V using an external FET and the appropriate combination of resistors. Using this circuit configuration, the switched-mode supply can source up to 10A, while the linear regulator portion can be loaded to 5A. These current ranges will easily accomodate the standard Pentium(R) P54C/P54C and the P55C as well as other Pentium(R) compatible processors such as the Cyrix(R) 6x86.
Autodetecting Single/Dual Power Supply for a Flexible Motherboard Design
Further analysis of the Intel Pentium(R) processors reveals the requirement for an open-ended motherboard power supply design that can accomodate different CPUs in a single system. As an example, consider the Intel(R) P54C and P55C Pentium(R) processors. Although these two processors may occupy the same CPU socket, distinct differences exist in their power supply requirements. The present generation P54C uses a single supply for both the processor core and the I/O. For the higher performance devices, the supply voltage required is 3.5V 100mV (VRE s-specification).
Detailed Product Description
The RC5035 combines a programmable voltage step-down DC-DC controller with a similarily programmable low dropout linear regulator. When designed around the appropriate external components, it can be configured to deliver more than 5A of load current with both outputs loaded and up to 10A from the switched-mode regulator. During all loading conditions the switched-mode portion of the RC5035 functions as a constant-on-time PWM step-down regulator.
7
RC5035
PRODUCT SPECIFICATION
Main Control Loop
The main control loop of the regulator, see Block Diagram, contains one main control block. The analog control block consists of signal conditioning amplifiers that feed into a set of fast comparators which provide the inputs to control the clock VCO. The signal conditioning block takes inputs from the IFBH and IFBL (current feedback) and VFBSW (voltage feedback) pins and then sets up two controlling signal paths. The voltage control path gains up the VFBSW signal and presents that signal to one of the summing amplifier inputs. The current control path takes the difference between the IFBH and IFBL pins and presents that signal to another input of the summing amplifier. These two signals are then summed together with the slope compensation input from the oscillator and the output is then presented to a comparator. This comparator provides the main PWM control signal to the VCO control block. There are other comparators in the analog control block that control the point at which the max-current comparator disables the output drive signal to the power MOSFET. The VCO controller section is designed to take the comparator inputs along with the main clock signal from the oscillator and provide a constant-on-time set of pulses to the VOSW output pin that will in turn control the external power MOSFET. The high speed complementary bipolar process allows the RC5035 to clock at speeds greater then 1MHz.
Over-Voltage Protection
The RC5035 provides a constant monitor of the output voltage for over-voltage protection. Should the voltage at the VFB pin exceed 20% of the selected program voltage, then an overvoltage condition will be assumed to exist and the RC5035 will shut down the output drive signals to the power FETs.
Oscillator
The RC5035 oscillator is designed as a fixed on-time, variable off-time oscillator. It is comprised of a window comparator, a fixed current source, an analog switch and an external timing capacitor. The oscillator will exhibit a fixed on-time, where the off-time will vary proportional to the feedback current from the switched-mode regulator. Therefore, the overall switching frequency of the oscillator will vary with the load current. The window comparator is used to provide the constant on-time, where the analog switch opens when the upper comparator threshold limit is reached. A fixed current source then discharges the oscillator capacitor until the lower comparator threshold is reached. Therefore, the fixed on-time is derived from a constant current slewing a fixed capacitor through a constant voltage. The comparator output directly feeds the output driver circuitry, eliminating the need for logic circuitry in the PWM. Once the comparator input reaches the low threshold, the comparator output switches levels and enables the analog switch. The feedback current then forces the output to slew up to the comparator upper threshold. Using this implementation, lighter loads and/or smaller error voltages will increase the time to reach the upper comparator threshold and thus increase the overall switching frequency.
Advanced Information
High Current Output Drivers
The RC5035 high current output driver contains high speed bipolar power transistors configured in a push-pull configuration. Each output driver is capable of pumping out 1A of current in less than 100ns. Each driver's power and ground are separated from the overall chip power and ground for added switching noise immunity. The VOSW driver has a power supply, VCCP, which can be derived from an external 12V source or boot-strapped from a flying-capacitor. In the boot-strapped mode, C2 is connected to the source of M1 and is alternately charged from VCC via the schottky diode DS2 and then boosted up when M1 is turned on. This provides a VCCP voltage equal to 2*VCC - Vds(DS2); or about 9.5V with VCC=5V. This voltage is sufficient to provide the 9V gate drive to the external MOSFET that will be needed for achieving a low Rdson. If VCCP is derived from an external 12V source, the Rdson is assured of being low due to the increased gate drive voltage to the power FET M1 .
Output Enable/Voltage Select Function
The RC5035 includes an ENABLE pin in order to allow the user to enable or disable the linear regulator as well as change the output voltage of the switched-mode regulator using a single logic input. The ENABLE pin is an open collector compatible input. When the ENABLE pin is in the LOW state, the linear regulator is turned on and the RC5035 will operate as a dual output power supply. When the ENABLE pin is switched to the HIGH state, the op-amp portion of the linear regulator will turn off. In addition, an alternate voltage feedback loop from the switched-mode regulator output will be enabled that re-programs its output voltage according to a second set of precision resistors. Using this configuration, the RC5035 can read the VCC2DET output from a Pentium(R) CPU and program the outputs to deliver the appropriate voltage(s) to the CPU core and I/O circuitry depending upon the processor type. When using the RC5035 in a Flexible Motherboard application for the Pentium(R) P54C/P55C processors, a shorting bar must be inserted in the motherboard to join the CPU core and I/O power islands when a single output is
Internal Reference
The reference in the RC5035 is a precision band-gap type reference. Its temperature coefficient is trimmed to provide a near zero TC. For applications that require a different voltage, a pair external resistors can be used change the output voltage from 2.0V up to 3.6V. For a guaranteed stable operation under all loading conditions, a 0.1mF capacitor is recommended on the VREF output pin.
8
PRODUCT SPECIFICATION
RC5035
selected. If this shorting bar is not utilized, the two power islands will be joined solely via the internal bonding connections of the CPU and damage to the processor may result.
The max inductor current can be calculated from the relationship:
2I L I MAX = --------------------------------------------------------------V IN - V OUT F O T ON ae ----------------------------- o + 1 e V OUT - V D o
Design Procedure and Applications Information
Simple Step-Down Converter
Where: FO is the desired clock frequency TON is the max on time of the M1 FET VDd is the forward voltage of the schottky diode D1 Then the inductor value can be calculated with the relationship:
65-5035-04
Figure 2. Simple Buck DC-DC Converter
VIN - V DSON L = ae ---------------------------------o TON e o I MAX
Advanced Information
Figure 2 shows a step-down DC-to-DC Converter with no feedback controller. The derivation of the basic step-down converter will serve as a basis for the design equations for the RC5035 in Figure 1. In Figure 2, the basic operation begins by closing the switch, S1. When S1 is closed the input voltage VB is impressed across the inductor L1. The current flowing in the inductor is given by the following equation: IL=(VB- VO)Ton/L; where Ton is the time duration for S1 to be closed. When S1 is open, the diode will conduct the inductor current and the output current will be delivered to the load according to the equation: IL=VO(T - TON)/L; where T- TON is the time duration for S1 to be off. By solving these two equations we can arrive at the basic relationship for the output voltage of a step-down converter:
V O = VB ( T ON T )
Where: VDSON is the voltage across the drain-source of the M1 FET when switched on (calculated by RDSon * IMAX)
Current-Sense Resistor
The current sense resistor will carry all of the peak current of the inductor. This current will be more than the designed for load current. The RC5035 will begin to limit the output current to the load by turning off the top-side FET driver when the voltage across the current-sense resistor exceeds 100mV. When this happens the output voltage will temporarily go out of regulation. As the voltage across the resistor becomes larger, the top-side FET will turn off more and more until the current limit value is reached and then the RC5035 will continuously deliver the limit current at a reduced output voltage level. To insure that load transient conditions do not momentarily cause deregulation of the output voltage, a 20% margin in the limit voltage is advisable. Thus the resistor should be set by the relationship: R = 100 mV/Ipeak Where: Ipeak = Imax * 1.33 Since the value of the sense resistor is generally in the miliohm region, care should be taken in the layout of the PCB. Trace resistance can contribute significant errors. The traces to the IFBH and IFBL pins of the RC5035 should be Kelvin connected to the pads of the current-sense resistor as shown in the sample layout Figure 4. To minimize the influence of noise the two traces should be run next to each other and the pins should be bypassed with a .1uF to GND as close to the device pins as possible.
Selecting the Inductor
The inductor is one of the most critical components to be selected in the DC-to-DC converter application. The critical parameters are inductance (L), max DC current (Imax), and the coil resistance (Rl). The inductor core material is a critical factor in determining the amount of current that the inductor will be able to handle. As with all engineering designs there are trade- offs for various types of inductor core materials. In general, Ferrites are popular because of their low cost, low EMI, and high frequency (>500kHz) characteristics. Molypermalloy powder (MPP) materials have good saturation characteristics and low EMI with low hysteresis losses; however they tend to be expensive and are more efficiently utilized at frequencies below 400kHz. DC winding resistance is another critical parameter. In general, the DC resistance should be kept as low as possible. The power loss in the DC resistance will degrade the efficiency of the converter by the relationship: Power Loss = (Io)2*Rl. The value of the inductor is a function of the switching frequency (TON) and the maximum inductor current.
Filter Capacitors
Good ripple performance and transient response are functions of the filter capacitors. Since the 5V input for a PC motherboard can be located several inches away from the 9
RC5035
PRODUCT SPECIFICATION
DC-to-DC converter, input capacitance can play an important role in the load transient response of the RC5035. In general, the higher the input capacitance, the more charge storage is available for improving the current transfer through the top-side FET. A good rule of thumb is that for each watt of output power that you wish to deliver, there should be around 10uF of input capacitance. Low "ESR" capacitors are best suited for this application and can have an influence on the converter's efficiency. The input capacitor should be placed as close to the drain of the top-side FET as possible to reduce the effect of ringing that can be caused by large trace lengths. The ESR rating of a capacitor is a difficult number to pin down. ESR or Equivalent Series Resistance, is defined at the resonant impedance of that capacitor. Since the capacitor is actually a complex impedance device having resistance, inductance and capacitance, it is quite natural for it to have an associated resonant frequency. As a rule, the lower the ESR, the better suited the capacitor is for use in switching power supply applications. Many capacitor manufacturers do not supply ESR data. A useful estimate of the ESR can be obtained with the following equation: ESR = DF/2pfC. Where DF is the capacitor's dissipation factor, f is the frequency of measure and C is the capacitance in farads. With this in mind, calculating the output capacitance correctly is crucial to the performance of the DC-to-DC converter. The output capacitor determines the overall loop stability, output voltage ripple, and the transient load response. The calculation uses the following equation:
( V IN - V OUT ) T ae ---------------------------------- + ILo e o V OUT C (mF) = -------------------------------------------------------VR
tant in the selection of DS1 and DS2 that they have a low forward voltage drop as this directly affects the regulator efficiency. During the off time of the power FET, M1, the voltage on the inductor will drop until the diode DS1 clamps and conducts the full current in the inductor. The power in DS1, Vf*IL, is a direct subtraction from the overall efficiency of the DC-DC converter; therefore, it is important for DS1 to have a low Vf in order to minimize the power loss term.
MOSFET Switches
The MOSFET switch in the RC5035 applications circuit is an N-channel "logic-level" FET. This means that it will be fully on with a Vgs of 4V. Many manufacturers make logiclevel FETs and the trick is to choose the one with the lowest Rdson at the given Imax current level. The value of Rdson directly enters into the efficiency equation as a power loss. Also influencing the efficiency is the gate charge of the FET and the clock frequency of the RC5035. At higher clocking rates the amount of charge needed to be delivered to the FET is going to lower the overall efficiency.
Advanced Information
PCB Layout and Grounding
As is the case with most analog circuitry, good layout practices are necessary to achieve the optimum in the overall performance of the DC-to-DC converter. In general, it is always a good practice to have a tight layout that attempts to minimize short low inductance wiring to the RC5035. The use of multilayer PCB is recommended. In particular, it is recommended to have a continuos ground plane beneath the circuit, 2oz copper would be preferred in high current applications. As was stated previously, the current-sense resistor, R1, should be located as close to the RC5035 as possible and all voltage and current feedback traces should be Kelvin connected to the pads of R1. To minimize switching losses and noise, place M1, M2, L1 and DS2 as close together as possible. Also try to keep the VOSW and VOL gate drive signal traces as short as possible. It is recommended that the noisy switching part of the circuit be kept away from the low current pins on the chip such as IFBH, IFBL, VFBSW, VFBSW2 and CEXT. Keep the 0.1uF bypass capacitors as close to the chip pins as possible. All of the ground pins should be connected to the ground plane directly under the chip. A sample layout is provided in Figure 4.
Where: VR is the desired output ripple voltage
Schottky Diode Selection
The application circuit diagram shows two schottky diodes, DS1 and DS2. As it is configured, DS2 provides the function of bootstrapping the VCCP node during startup. It is possible to cause the output stage to latchup if the VCCP supply is brought up before the other VCC supplies of the RC5035. It is therefore advisable that DS2 be connected. It is impor-
10
PRODUCT SPECIFICATION
RC5035
Mechanical Dimensions - 16-Lead SOIC Package
Symbol A A1 B C D E e H h L N a ccc Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
.053 .069 .004 .010 .013 .020 .008 .010 .386 .394 .150 .158 .050 BSC .228 .010 .016 16 0 -- 8 .004 .244 .020 .050
1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 9.80 10.00 3.81 4.00 1.27 BSC 5.80 0.25 0.40 16 0 -- 8 0.10 6.20 0.50 1.27
3 6
Advanced Information
16
9
E
H
1
8
D A1 A SEATING PLANE -C- LEAD COPLANARITY ccc C 16 Lead Small Outline IC (SOIC) - .150" Body Width Rev 1.0 11/28/95 a
h x 45 C
e
B
L
11
RC5035
PRODUCT SPECIFICATION
Ordering Information
Product Number RC5035M Package 16 pin SOIC
Advanced Information
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RC5036
Dual Adjustable Voltage Regulator Controller
Features
* Combines switching regulator and low dropout linear regulator in single chip * Linear regulator on/off control * Each output voltage adjustable from 1.5V to 3.6V * Built-in soft start * Switcher can be configured for 13A loads, linear for 5A * Precision trimmed low TC voltage reference * Constant On-Time oscillator * Small footprint 16 lead SOIC package
Description
The RC5036 combines a switch-mode DC-DC converter with a low-dropout linear regulator. In addition, it integrates the circuitry required to switch the DC-DC converter output between 3.5V and a user-selectable voltage from 1.5V to 3.6V as well as an enable function to allow the linear regulator to be turned off when not required. RC5036 has built-in soft start feature which offers system protection during power-up by reducing both inrush current and output overshoot. With the appropriate external components, the DC-DC converter can deliver load current as high as 13A and the linear regulator can provide 5A. The DC-DC converter and the linear regulator can be set independently using two external resistors each to any value between 1.5V and 3.6V. The factory trimmed internal reference achieves tight tolerance voltage regulation on both outputs. Independent short circuit protection is also provided.
Applications
* * * * RAMBUS or SDRAM power with ACPI support I/O and AGP power High efficiency power for DSPs Programmable dual power supply for high current loads
Block Diagram
+12V +5V
SWITCHING REGULATOR
SWITCHER SELECT OSCILLATOR
FEEDBACK CONTROL
DIGITAL LOGIC
LINEAR ENABLE
LINEAR REGULATOR
1.5V REFERENCE + -
RC5036
REV. 2.0.0
RC5036
PRODUCT SPECIFICATION
Pin Assignments
LIN_EN VREF IFBH IFBL FBSW VCCA VFBL GNDP 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SWCTRL CEXT GNDA VSCL LDRV VCCL VCCP SDRV
Pin Descriptions
Pin Name LIN_EN VREF Pin Number 1 2 Pin Function Description Linear regulator enable input. Accepts TTL/open collector input levels. A logic level HIGH on this pin disables the output of the linear regulator. Voltage reference test point. This pin provides access to the internal precision 1.5V bandgap reference and should be decoupled to ground using a 0.1F ceramic capacitor. No load should be connected to this pin. High side current feedback for switching regulator. Pins 3 and 4 are used as the inputs for the current feedback control loop and as the short circuit current sense points. Careful layout of the traces from these pins to the current sense resistor is critical for optimal performance of the short circuit protection scheme. See Applications Discussion for details. Low side current feedback for switching regulator. See Applications Discussion for details. Voltage feedback for switching regulator. This input is active when a logic level LOW is input on pin 16 (SWCTRL). Using two external resistors, it sets the output voltage level for the switching regulator. See Applications Discussion for details. Switching Regulator Vcc. Power supply for switching regulator control circuitry and voltage reference. Connect to system 5V supply and decouple to ground with 0.1F ceramic capacitor. Voltage feedback for linear regulator. Using two external resistors, this pin sets the output voltage level for the linear regulator. See Applications Discussion for details. Power Ground. Return pin for high currents flowing in pins 9, 10 and 12 (SDRV, VCCP and LDRV). Connect to a low impedance ground. See Applications Discussion for details. FET driver output for switching regulator. Connect this pin to the gate of the N-channel MOSFET Q1 as shown in Figure 1. The trace from this pin to the MOSFET gate should be kept as short as possible (less than 0.5"). See Applications Discussion for details. Switching regulator gate drive Vcc. Power supply for SDRV output driver. Connect to system 12V supply with R-C filter shown in Figure 1. See Applications Discussion for details. Linear Regulator Vcc. Power supply for LDRV output op-amp. Connect to system 12V supply and decouple to ground with 0.1F ceramic capacitor. Output driver for linear regulator. Connect this pin to the base of an NPN transistor. When pin 1 (LIN_EN) is pulled HIGH, the linear regulator is disabled and pin 12 will be pulled low internally. Low side current sense for linear regulator. Connect this pin between the sense resistor and the collector of the power transistor. The high side current sense is internally connected to pin 6 (VCCA). Layout is critical to optimal performance of the linear regulator short circuit protection scheme. See Applications Discussion for details.
IFBH
3
IFBL FBSW
4 5
VCCA
6
VFBL GNDP SDRV
7 8 9
VCCP
10
VCCL LDRV
11 12
VSCL
13
2
RC5036
PRODUCT SPECIFICATION
Pin Descriptions (continued)
Pin Name GNDA Pin Number 14 Pin Function Description Analog ground. All low power internal circuitry returns to this pin. This pin should be connected to system ground so that ground loops are avoided. See Applications Discussion for details. External capacitor. A 180pF capacitor is connected to this pin as part of the constant on-time pulse width circuit. Careful layout of this pin is critical to system performance. See Applications Discussion for details. Switching regulator control input. Accepts TTL/open collector input levels. A logic level HIGH on this pin presets the switching regulator output voltage at 3.5V using internal resistors. A logic level LOW on this pin will select the output voltage set by two external resistors and the voltage feedback control pin 5 (VFBSW). See Applications Discussion for details.
CEXT
15
SWCTRL
16
Absolute Maximum Ratings
Supply Voltages, VCCA, VCCL, VCCP Junction Temperature, TJ Storage Temperature, TS Lead Soldering Temperature, 10 seconds Thermal Resistance Junction-to-Ambient, JA 13V +150C -65 to +150C 300C 112C/W
Note: 1. Functional operation under any of these conditions is not implied. Performance is guaranteed only if Operating Conditions are not exceeded.
Operating Conditions
Parameter Switching Regulator VCC, VCCA Linear Regulator VCC, VCCL Logic Inputs, SWCTRL, LIN_EN Ambient Operating Temperature, TA Drive Gate Supply, VCCP Logic HIGH Logic LOW Conditions Min. 4.75 11.4 2.4 0.8 0 9.5 12 70 12.6 Typ. 5 12 Max. 5.25 12.6 Units V V V V C V
3
PRODUCT SPECIFICATION
RC5036
Electrical Characteristics--Switch-Mode Regulator
(VCCA = 5V, VCCL = 12V, TA = 25C using circuit of Figure 1, unless otherwise noted) The * denotes specifications which apply over the full ambient operating temperature range. Parameter Output Voltage, VOSW1 Conditions SWCTRL = HIGH Set by internal resistors SWCTRL = LOW Set by external resistors ISW = 5A TA = 0C-70C VCCA = 4.75 to 5.25V ISW = 5A ISW = 0 to 5A or 5A to 10A 20MHz BW, ISW = 5A * ISW = 5A Open Loop * * CEXT = 180pF 80 0.5 70 90 3.5 100 * * * 1.5 -1.2 40 0.10 0.9 15 55 87 100 0.15 1.3 Min. Typ. 3.5 3.6 +1.2 Max. Units V V %Vo ppm %Vo %Vo mV mV % A mV s
Output Voltage, VOSW1 Setpoint Accuracy2 Output Temperature Drift Line Regulation Load Regulation Output Ripple, peak-peak Cumulative DC Efficiency Output Driver Current Short Circuit Threshold Voltage On Time Pulse Width4 Accuracy3
Notes: 1. When the SWCTRL pin is HIGH or left open, the switch-mode regulator output will be preset at 3.5V using internal precision resistors. When the SWCTRL pin is LOW, the output voltage may be programmed with external resistors. Please refer to the Applications Section for output voltage selection information. 2. Setpoint accuracy is the initial output voltage variability under the specified conditions. When SWCTRL is LOW, the matching of the external resistors will have a major influence on this parameter. 3. Cumulative DC accuracy includes setpoint accuracy, temperature drift, line and load regulation, and output ripple. 4. The on-time pulse width of the oscillator is preset using external capacitor CEXT. See Typical Operating Characteristics curves.
4
RC5036
PRODUCT SPECIFICATION
Electrical Characteristics--Linear Regulator
(VCCA = 5V, VCCL = 12V, TA = 25C using circuit in Figure 1, unless otherwise noted) The * denotes specifications which apply over the full ambient operating temperature range. Parameter Output Voltage, Setpoint VOL1 Accuracy2 Conditions Set by external resistors IL=0.5A, using 0.1% resistors * VCCL = 11.4V to 12.6V, IL = 3A IL = 0 to 5A 0.1 to 20KHz Accuracy3 ISW = 5A * Open Loop 40 50 * * Min 1.5 -1.5 40 0.1 0.7 1 1.7 35 50 70 60 3 0.15 1 Typ Max 3.6 +1.5 Units V % ppm %Vo %Vo mV % mVpp mV mA
Output Temperature Drift Line Regulation Load Regulation Output Noise Cumulative DC Crosstalk4 Short Circuit Comparator Threshold Op-amp Output Current
Notes: 1. When the LIN_EN pin is LOW, the linear regulator output is set with external resistors. When the LIN_EN pin is HIGH, the linear regulator is disabled and will exhibit no output voltage. Please refer to the Application Section for output voltage selection information. 2. Setpoint accuracy is the initial output voltage variability under the specified conditions. The matching of the external resistors will have a major influence on this parameter. 3. Cumulative DC accuracy includes setpoint accuracy, temperature drift, line and load regulation. 4. Crosstalk is defined as the amount of switching noise from the switch-mode regulator that appears on the output of the linear regulator when both outputs are in a static load condition.
Electrical Characteristics--Common
(VCCA = 5V, VCCL = 12V, TA = 25C using circuit of Figure 1, unless otherwise noted) The * denotes specifications which apply over the full ambient operating temperature range. Parameter Reference Voltage, VREF VREF PSRR VCCA Supply Current VCCP Supply Current VCCL Supply Current Independent of load ISW = 5A IL = 2A * * * Conditions Min 1.485 60 5 20 5 15 25 Typ 1.5 Max 1.515 Units V dB mA mA mA
5
RC5036
PRODUCT SPECIFICATION
Typical Operating Characteristics (VCCA = 5V, VCCL = 12V and TA = +25C using circuit in Figure 1, unless otherwise noted)
Switcher Efficiency vs. Output Current 95 94 93 92 91 90 89 88 87 86 85 1 2 3 4 5 6 7 8 9 10 Output Current +1.5 +1.0 VOSW (%) +0.5 Nom -0.5 -1.0 -1.5 0 2 4 6 8 10 Output Current (A) 3.5V 2.8V Switcher Output Voltage vs. Load
Efficiency (%)
Switcher Output vs. Output Current 4 3 VOSW (V) 2 1 0 8 10 12 14 16 Output Current, ISW (A) Output Voltage (V) 4 3 2 1 0
Linear Regulator Output vs. Output Current, Rsense = 7m
0
1
2
3
4
5
6
Output Current (A)
Output Voltage vs. Temperature, ISW = 5A or ILR = 5A ISW (2A/div) VOSW (50mV/div) +0.50 Output Voltage (%) +0.25 Nom. -0.25 -0.50 0 25 50 75 100 125
Switcher Transient Response, 0.5A to 5.5A
Temperature (C)
Time (100s/division)
6
PRODUCT SPECIFICATION
RC5036
Typical Operating Characteristics (continued)
Switcher Output Ripple, IOUT = 10A Linear Output Startup, System Power-Up
Time (2s/division)
Time (5ms/division)
Switcher Output Startup, System Power-Up
Linear Output Startup, Using LIM_EN Pin
Time (5ms/division)
Time (5ms/division)
Pin 9 (SDRV), 10A Load
Pin 9 (SDRV), 0.1A Load
Time (1s/division)
Time (1s/division)
7
8
C1 Optional L1 0.1F C6 0.1F C3 1F Q1 L2 4.7 4.7H 5m R6 6.65K COUT D1 R2 7m 9 10 11 U1 12 13 RC5036 14 15 16 8 7 6 5 4 3 2 1 R4 VCORE R3 CIN R1 47
RC5036
+12V 0.1F
Application Circuit
+5V
C2
R5 10K
C4 180pF
GND Q4 Q2 C7 10nF Standby Q3 C5 0.1F R8 6.65K PRODUCT SPECIFICATION R7 10K
Figure 1. RAMBUS Power with ACPI support, 10A Main, 100mA Standby
RC5036
PRODUCT SPECIFICATION
Table1. Bill of Materials for a RC5036 RAMBUS Application
Qty. 4 1 1 1 3 1 1 1 1 1 2 2 1 1 3 Reference C3 C4 C7 CIN COUT R1 R2 R3 R4 R5, R7 R6, R8 D1 Q1 Q2-4 Manufacturer Part Order # Any Any Any Sanyo 10MV1200GX Rubycon 6.3ZL1500M Any N/A Any N/A Any Any Motorola MBRB1545CT Fairchild FDB6030L Fairchild MMBT2222A Any Any Fairchild RC5036M Description 100nF, 25V Capacitor 1F, 25V Capacitor 180pF, 50V Capacitor 10nF, 25V Capacitor 1200F, 10V Aluminum Capacitor 1500F, 6.3V Aluminum Capacitor 47.5 300m 4.75 5m PCB Trace Resistor, 1W 10K 6.65K 15A, 45V Schottky 30V, 14m Logic Level MOSFET 40V, 1A NPN 2.5H Inductor 4.7H Inductor PWM Controller ISAT > 8A ISAT > 13A PCB Trace Resistor, see Applications PCB Trace Resistor, see Applications IRMS = 2A , See Equation (2) in Applications ESR = 23m C0G Requirements and Comments
C1-2, C5-6 Any
Optional L1 1 1 L2 U1
Application Information
The RC5036 contains a precision trimmed zero TC voltage reference, a constant-on-time architecture controller, a high current switcher output driver, a low offset op-amp, and switches for selecting various output modes. The block diagram in Figure 2 shows how the RC5036 in combination with the external components achieves a switchable dual power supply.
Switch-Mode Control Loop
The main control loop for the switch-mode converter consists of a current conditioning amplifier and one of the two voltage conditioning amplifiers that take the raw voltage and current information from the regulator output, compare them against the precision reference and present the error signal to the input of the constant-on-time oscillator. The two voltage conditioning amplifiers act as an analog switch to select
between the internal resistor divider network (set for 3.5V) or an external resistor divider network (adjustable for 1.5V to 3.6V.) The switch-mode select pin determines which of the two amplifiers is selected. The current feedback signals come across the Iout sense resistor to the IFBH and IFBL inputs of the RC5036. The error signals from both the current feedback loop and the voltage feedback loop are summed together and used to control the off-time duration of the oscillator. The current feedback error signal is also used as part of the RC5036 short-circuit protection.
Linear Control Loop
The low-offset op-amp is configured to be the controlling element in a precision low-drop-out linear regulator. As can be seen from Figure 2, the op-amp is used to compare the divided down output of the linear regulator to the precision reference. The error signal is used to control either an N-channel MOSFET or a power NPN transistor.
9
RC5036
PRODUCT SPECIFICATION
High Current Output Drivers
The RC5036 switching high current output driver (SDRV) contains high speed bipolar power transistors configured in a push-pull configuration. The output driver is capable of supplying 0.5A of current in less than 100ns. The driver's power and ground are separated from the overall chip power and ground for added switching noise immunity.
Internal Reference
The reference in the RC5036 is a precision band-gap type reference. Its temperature coefficient is trimmed to provide a near zero TC. For guaranteed stable operation under all conditions, a 0.1F capacitor is recommended on the VREF output pin. No load may be attached to this pin.
charged and discharged through the enabling and disabling of the fixed current source. The variable current source is controlled from the error inputs that are received from the current and voltage feedback signals. The oscillator off-time is controlled by the amount of current that is available from the variable current source to charge the external capacitor up to the high threshold level of the comparator. The on-time is set be the constant current source that discharges the external capacitor voltage down to the lower comparator threshold.
Using SWCTRL and LIM_EN
When the SWCTRL pin is HIGH, the switching regulator will set its output at 3.5V using two internal precision resistors. When this pin is LOW, the switching regulator output can be set to any voltage between 1.5V and 3.6V using external precision resistors. The LIN_EN pin is used to enable or disable the linear regulator. When the LIN_EN pin is HIGH, the linear regulator will be disabled. If this pin is LOW, the linear regulator output can be set from 1.5V to 3.5V using external precision resistors. The linear regulator output can be left on to provide power to other 3.3V components.
Constant-On-Time Oscillator
The RC5036 switch-mode oscillator is designed as a fixed on-time, variable off-time oscillator. The constant-on-time oscillator consists of a comparator, an external capacitor, a fixed current source, a variable current source, and an analog switch that selects between two threshold voltages for the comparator. The external timing capacitor is alternately
+5V +12V
gm gm CONSTANT ON-TIME OSCILLATOR gm IO ANALOG SWITCH VH VL VOSW ION
+12V VREF REF + - VOL
RC5036
SWITCHER SELECT LINEAR ENABLE
SWCTRL
LIN_EN
Figure 2. RC5036 Block Diagram
10
PRODUCT SPECIFICATION
RC5036
Output Voltage Selection
The RC5036 precision reference is trimmed to be 1.5V nominally. When using the RC5036, the system designer has complete flexibility in choosing the output voltage for each regulator from 1.5V to 3.6V. This is done by appropriately selecting the feedback resistors. These could be 0.1% resistors to realize optimum output accuracy. The following equations determine the output voltages of the two regulators: Switching Regulator:
V OUT R6 + R5 = 1.5 x -------------------- R5
Linear Regulator Design Considerations
Figure 1 shows the application schematic for the RC5036 with an NPN used for the linear regulator. Careful consideration must be given to the base current of the power NPN device. The base current to the power NPN device is limited by: * The RC5036 op-amp output current (50mA) * The internal power dissipation of the RC5036 package * The of the power NPN device. The internal RC5036 power dissipation is the most severe limitation for this application. For optimum reliability, we require that the junction temperature not exceed 130C; thus we can calculate the maximum power dissipation allowable for this 16-lead SOIC package as follows:
T J ( max ) - T A P D = ------------------------------R JA
Linear Regulator:
R8 + R7 V OUT = 1.5 x -------------------- R7
where R6 > 1.5k and (R5 + R6) 25k and R8 > 1.5k and (R7 + R8) 25k Example: For 3.3V,
R6 + R5 6.65k + 10k V OUT = 1.5 x -------------------- = 1.5 x ---------------------------- = 3.3V R5 10k
If we assume that the ambient temperature TA is 70C and the thermal resistance of the 16-lead SOIC package is 112C/W, then the maximum power dissipation for the IC is:
130 - 70 P D = -------------------- 0.533W 112 P D = P SW + P LR = ( 35mA x 5.25V ) + ( 12.6V - V OUT - V BE ) x I OL 0.533W
Input Capacitors
The number of input capacitors required for the RC5036 is dependent on their ripple current rating, which assures their rated life. The number required may be determined by
I out * DC - DC No. Caps = --------------------------------------I rating
2
(2)
where PSW is the internal power dissipation of the switching regulator and PLN is the internal power dissipation of the linear regulator. IOL is the linear regulator op-amp output current. For VOUT = 3.3V nominal, the worst case output will be determined by the current used. For example, for a worst case VOUT = 3.135V, the maximum op-amp output current is:
0.533W - ( 35mA x 5.25V ) I OL = ------------------------------------------------------------------ 40mV ( 12.6V - 3.135V - 0.8V ) 3000mA -------------------- = 75 40mA
where the duty cycle DC = Vout/Vin. For example, with a 1.5V output at 10A, 5V input, and using the Sanyo capacitors specified in Table 1 which have a 2A ripple current rating, we have DC = 1.5/5 = 0.3, and
10* 0.03 - 0.3 No. Caps = ----------------------------------- = 2.29 2 2
so that we need 3 input capacitors.
The power NPN transistor must have a minimum of 75 at IL = 3A in order to meet the internal power dissipation limit of the 16-SOIC package.
11
RC5036
PRODUCT SPECIFICATION
Short Circuit Considerations
For the Switch-Mode Regulator
Schottky Diode
In Figure 1, MOSFET Q1 and flyback diode D1 are used as complementary switches in order to maintain a constant current through the output inductor L1. As a result, D1 will have to carry the full current of the output load when the power MOSFET is turned off. The power in the diode is a direct function of the forward voltage at the rated load current during the off time of the FET. The following equation can be used to estimate the diode power:
P DIODE = I D x V D x ( 1 - DutyCycle )
The RC5036 uses a current sensing scheme to limit the load current if an output fault condition occurs. The current sense resistor carries the peak current of the inductor, which is greater than the maximum load current due to ripple currents flowing in the inductor. The RC5036 will begin to limit the output current to the load by turning off the top-side FET driver when the voltage across the current-sense resistor exceeds the short circuit comparator threshold voltage (Vth). When this happens the output voltage will temporarily go out of regulation. As the voltage across the sense resistor becomes larger, the top-side MOSFET will continue to turn off until the current limit value is reached. At this point, the RC5036 will continuously deliver the limit current at a reduced output voltage level. The short circuit comparator threshold voltage is typically 90mV, with a variability of 10mV. The ripple current flowing through the inductor is typically 0.5A. Refer to Application Note AM-53 for detailed discussions. The sense resistor value can be approximated as follows:
V th,min V th,min R SENSE = --------------- x ( 1 - TF ) = --------------------------------------------- x ( 1 - TF ) I PK 0.5A + I LOAD,MAX
where ID is the forward current of the diode, VD is the forward voltage of the diode, and DutyCycle is defined the same as
Vout Duty Cycle = -----------Vin
For the Motorola MBRB1545CT Power Rectifier used in Figure 1,
P DIODE = 10A x 0.65 x ( 1 - 73.1% ) = 1.75W
where TF = Tolerance Factor for the sense resistor and 0.5A accounts for the inductor current ripple. Since the value of the sense resistor is often less than 10m, care should be taken in the layout of the PCB. Trace resistance can contribute significant errors. The traces to the IFBH and IFBL pins of the RC5036 should be Kelvin connected to the pads of the current-sense resistor. To minimize the influence of noise, the two traces should be run next to each other.
It is recommended that the diode T0-220 package be attached to a heatsink.
Board Design Considerations
RC5036 Placement
Preferably the PC layer directly underneath the RC5036 should be the ground layer. This serves as extra isolation from noisy power planes.
MOSFET Placement
For the Linear Regulator
The analysis for short circuit protection of the linear regulator is much simpler than that of the switching regulator. The formula for the inception point of short-circuit protection for the linear regulator is:
V th,min R SENSE = -------------------------- x ( 1 - TF ) I LOAD,MAX
Vth = 45mV 8mV and ILOAD,MAX = 5A,
37mV R SENSE = -------------- x ( 1 - 29% ) = 5.3m for using an 5A embedded PC trace resistor
Placement of the power MOSFET is critical in the design of the switch-mode regulator. The FET should be placed in such a way as to minimize the length of the gate drive path from the RC5036 SDRV pin. This trace should be kept under 0.5" for optimal performance. Excessive lead length on this trace causes high frequency noise resulting from the parasitic inductance and capacitance of the trace. Since this voltage can transition nearly 12V in around 100nsec, the resultant ringing and noise will be very difficult to suppress. This trace should be routed on one layer only and kept well away from the "quiet" analog pins of the device: VREF, CEXT, FBSW, IFBH, IFBL, and VFBL. Refer to Figure 3.
Inductor and Schottky Diode Placement
37mV R SENSE = -------------- x ( 1 - 5% ) = 7.0m for using a 5A discrete resistor
The inductor and fly-back Schottky diode must be placed close to the source of the power MOSFET. The node connecting the inductor and the diode swing between the drain voltage of the FET and the forward voltage of the Schottky diode. It is recommended that this node be converted to a plane if possible. This node is part of the high current path in the design, and is best treated as a plane to minimize the parasitic resistance and inductance on that node.
12
RC5036
PRODUCT SPECIFICATION
Most PC board manufacturers utilize 1/2oz copper on the top and bottom signal layers of the PCB; thus, it is not recommended to use these layers to rout the high current portions of the regulator design. Since it is more common to use 1 oz. copper on the PCB inner layers, it is recommended to use those layers to route the high current paths in the design.
Capacitor Placement
One of the keys to a successful switch-mode power supply design is correct placement of the low ESR capacitors. Decoupling capacitors serve two purposes; first there must be enough bulk capacitance to support the expected transient current, and second, there must be a variety of values and capacitor types to provide noise supression over a wide
Example of a Good layout
range of frequencies. The low ESR capacitors on the input side (5V) of the FET must be located close to the drain of the power FET. Minimizing parasitic inductance and resistance is critical in supressing the ringing and noise spikes on the power supply. The output low ESR capacitors need to be placed close to the output sense resistor to provide good decoupling at the voltage sense point. One of the characteristics of good low ESR capacitors is that the impedance gradually increases as the frequency increases. Thus for high frequency noise supression, good quality low inductance ceramic capacitors need to be placed in parallel with the low ESR bulk capacitors. These can usually be 0.1F 1206 surface mount capacitors.
Example of a Problem layout
SDRV 9 10 11 12 Noisy Signal is routed away from quiet pins and trace length is kept under 0.5 in. CEXT 13 14 15 16 8 7 6 5 4 3 2 1 IFBL IFBH VREF
SWDRV 9 10 11 12 13 14 CEXT 15 16 8 7 6 5 4 3 2 1 IFBL IFBH VREF
= "Quiet" Pins
Noisy Signal radiates onto quiet pins and trace is too long.
Figure 3. Examples of good and poor layouts
Power and Ground Connections
MOSFET Gate Bias
+5V 47 W
The connection of VCCA to the 5V power supply plane should be short and bypassed with a 0.1F directly at the VCCA pin of the RC5036. The ideal connection would be a via down to the 5V power plane. A similar arrangement should be made for the VCCL pin that connects to +12V, though this one is somewhat less critical since it powers only the linear op-amp. Each ground should have a separate via connection to the ground plane below.
+12V
VCCP Q1 SDRV 1uF D1 GNDP L1 RSENSE CBULK VO
Figure 4. 12V Gate Bias Configuration
13
RC5036
PRODUCT SPECIFICATION
A 12V power supply is used to bias the VCCP. A 47 resistor is used to limit the transient current into VCCP. A 1uF capacitor filter is used to filter the VCCP supply and source the transient current required to charge the MOSFET gate capacitance. This method provides sufficiently high gate bias voltage to the MOSFET (VGS), and therefore reduces RDS(ON) of the MOSFET and its power loss. Figure 4 provides about 5V of gate bias which works well when using typical logic-level MOSFETs.
RC5036 Evaluation Board
Fairchild Electronics Semiconductor Division provides an evaluation board for verifying the system level performance of the RC5036. The evaluation board provides a guide as to what can be expected in performance with the supplied external components and PCB layout. Please call your local Sales Office or Fairchild Electronics Semiconductor Division at 408-822-2550 for an evaluation board.
Layout Gerber File and Silk Screen
A reference design for motherboard implementation of the RC5036 along with the Layout Gerber File and the Silk Screen is available. Please call Fairchild Electronics Semiconductor Division's Marketing Departmentat 408-822-2550 to obtain this information.
14
PRODUCT SPECIFICATION
RC5036
Mechanical Dimensions
16-Lead SOIC Package
Inches Min. A A1 B C D E e H h L N ccc Max. Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
Symbol
.053 .069 .004 .010 .013 .020 .008 .010 .386 .394 .150 .158 .050 BSC .228 .010 .016 16 0 -- 8 .004 .244 .020 .050
1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 9.80 10.00 3.81 4.00 1.27 BSC 5.80 0.25 0.40 16 0 -- 8 0.10 6.20 0.50 1.27
3 6
16
9
E
H
1
8
D A1 A SEATING PLANE -C- LEAD COPLANARITY ccc C e B
h x 45 C
L
15
RC5036
PRODUCT SPECIFICATION
Ordering Information
Product Number RC5036M Package 16 pin SOIC
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
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2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
ACExTM CoolFETTM CROSSVOLTTM E2CMOSTM FACTTM FACT Quiet SeriesTM FAST(R) FASTrTM GTOTM HiSeCTM
DISCLAIMER
ISOPLANARTM MICROWIRETM POPTM PowerTrench QFETTM QSTM Quiet SeriesTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8
SyncFETTM TinyLogicTM UHCTM VCXTM
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Rev. D
+12V 0.1F R6 471/2
C7
+5V L2 CIN C9 0.1F
C8
0.1uF
C14 1F M1 L1 101/2 4.7H 5m1/2 R11 1.74K1/2 1-2 2.8V 3-4 2.9V R7 2.00K1/2 9 8 DS1 7 6 5 10 11 12 13 R10 1.87K1/2 R1 R12
VCORE R9 2.26K1/2 5-6 3.2V R8 0.80K1/2 7-8 2.1V R7 2.53K1/2 9 - 10 3.4V COUT
R2
7m1/2
Application Circuit for P55C, K6, and M2
RC5036
4 3 2 1
14 15 16 C13 180pF
R5
0.01/2
GND Q1
Enable: 3.3V+/-5%@3A (J9 Closed) Disable: Off
SWCTRL VI/O C11 10nF VREF C10 0.1F R4 10K1/2 R3 12.1K1/2 C1 1500F
J7
Open = 3.5 V
Lin_EN
Figure 1. P54/P55C, K6 or M2 Single/Dual Power Supply Application Schematic
J9
Table 1. Bill of Materials for a RC5036 P55C, K6, or M2 Application
Qty. 4 1 1 1 Reference C7, C8, C9, C10 C11 C13 C14 Manufacturer Part Order # Panasonic ECU-V1H104ZFX Panasonic ECU-V1H103KBX Panasonic ECU-V1H181JCG Panasonic ECSH1CY105R Sanyo 6MV1500GX Sanyo 10MB1200GX Sanyo 6MV1500GX Motorola MBR1545CT Pulse Engineering PE-53682 Beads Inductor IRL3103 Description 0.1mF 50V SMT 0805 capacitors 10nF 50V SMT 0805 capacitor 180pF 50V SMT0805 capacitor 1mF 16V SMT 0805 Capacitor 1500mF 6.3V electrolitic capacitor, 10mm x 20mm 1200mF 10 B electrolytic capacitor, 10mm x 20mm 1500mF 6.3V electrolytic capacitor, 10mm x 20mm Schottky Diode 4.7mH inductor 2 Beads, 3.5 x 8mm wire, diameter = 0.6mm N-Channel Logic Level Enhancement Mode MOSFET NPN power transistor 5mW MnCu or Copel resistor 0.80KW 1% resistor 2.26KW 1% resistor 1.87KW 1% resistor 1.74KW 1% resistor 2.00KW 1% resistor 12.1KW 1% resistor 10.0KW 1% resistor 0W 5% resistor 47W 5% resistor 7mW MnCu or Copel resistor Dual Regulator for P55-- switching regulator + LDO linear regulator 0.1% resistor desirable for accuracy 0.1% resistor desirable for accuracy 0.1% resistor desirable for accuracy 0.1% resistor desirable for accuracy 0.1% resistor desirable for accuracy 0.1% resistor desirable for accuracy 0.1% resistor desirable for accuracy Resistor raises VOUT 25mV/5W Optional--Helps reduce ripple on the 5V line RDS(ON) < 20mW, VGS < 4.5V, ID > 20A > 80 at 3A Vf < 0.57V at If = 7.5A ESR < 0.044W Requirements and Comments
See COUT Table 2 See CIN Table 2 1 1 1 1 1 C1 DS1 L1 L2 M1
1 1 1 1 1 1 1 1 1 1 1 1 1
Q1 R1 R8 R9 R10 R11 R7 R3 R4 R5 R6 R2 U1
Motorola MJE15028 RSENSE (SW) Panasonic ERJ-6ENF 0.80KV Panasonic ERJ-6ENF2.26KV Panasonic ERJ-6ENF1.87KV Panasonic ERJ-6ENF1.74KV Panasonic ERJ-6ENF2.00KV Panasonic ERJ-6ENF12.1KV Panasonic ERJ-6ENF10.0KV Panasonic ERJ-6GEY000V Panasonic ERJ-6GEY047V RSENSE (Lin) Fairchild Semiconductor RC5036M
Table 2. Switching Regulator Components Selection Table
Output Voltage 3.5 2.8 2.9 2.9 3.2 3.2 2.1 3.3 Output Current 8 6 6.25 7.5 9.5 13 5.6 3 CIN Sanyo 10MV1200GX 1x 1x 1x 1x 2x 3x 1x N/A COUT Sanyo 6M1500GX 2x 2x 2x 2x 4x 6x 2x 1x Power MOSFET (M1) IRL3103 IRL3103 IRL3103 IRL3103 IRL3103 IRL3103 IRL3103 MJE15028
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RC5037
Adjustable Switching Regulator Controller
Features
* High power switch-mode DC-DC controller can provide in excess of 13A * Output voltage adjustable from 1.5V to 3.6V * 85% efficiency * Cumulative accuracy < 3% over line, load, and temperature variations * Overvoltage and short circuit protection * Built-in soft start
Description
The RC5037 is a high power, switch-mode DC-DC controller that provides efficient power for all low-voltage applications. This controller has a built-in Soft Start feature which offers system protection during power-up by reducing both inrush current and output overshoot. When combined with the appropriate external circuitry, the RC5037 can deliver load currents as high as 13A at efficiencies as high as 88%. The RC5037 can generate output voltages from 1.5V up to 3.6V using external resistors. The RC5037 is designed to operate in a constant on-time control mode under all load conditions. Its accurate low TC reference eliminates the need for precision external components in order to achieve the tight tolerance voltage regulation required by many applications. Short circuit current protection is provided through the use of a current sense resistor, while overvoltage protection is provided internally.
Applications
* * * * I/O and AGP power for desktop computers High efficiency power for ASICs High efficiency power for DSPs Adjustable step-down power supplies
Block Diagram
5V
2
+12V
4
+5V
RC5037
Feedback Control
3 8
1
Oscillator
Digital Logic
7
Vout 1.5V Reference
5 6
REV. 1.0.1
RC5037
PRODUCT SPECIFICATION
Pin Assignments
CEXT VCCA IFBH IFBL 1 2 3 4 8 7 6 5 VCCP DRV GNDP VFB
RC5037
Pin Descriptions
Pin Name CEXT Pin Number 1 Pin Function Description External capacitor. A 180pF capacitor is connected to this pin as part of the constant ontime pulse width circuit. Careful layout of this pin is critical to system performance. See Applications Information for details. Analog Vcc. Power supply for regulator control circuitry and voltage reference. Connect to system 5V supply and decouple to ground with 0.1F ceramic capacitor. High side current feedback. Pins 3 and 4 are used as the inputs for the current feedback control loop and as the short circuit current sense points. Careful layout of the traces from these pins to the current sense resistor is critical for optimal performance of the short circuit protection scheme. See Applications Information for details. Low side current feedback. See Applications Information for details. Voltage feedback. Using two external resistors, this pin sets the output voltage level for the switching regulator. Power Ground. Connect to a low impedance ground. See Application Information for details. MOSFET driver output. Connect this pin to the gate of the N-channel MOSFET Q1 as shown in Figure 12. The trace from this pin to the MOSFET gate should be kept as short as possible (less than 0.5"). See Applications Information for details. Power Vcc. Power supply for DRV output driver. Connect to system 12V supply with R-C filter shown in Figure 12. See Applications Information for details.
VCCA IFBH
2 3
IFBL VFB GNDP DRV
4 5 6 7
VCCP
8
Absolute Maximum Ratings
Supply Voltages, VCCA Supply Voltages, VCCP Junction Temperature, TJ Storage Temperature, TS Lead Soldering Temperature, 10 seconds Thermal Resistance Junction-to-Ambient, JA 7V 13V +150C -65 to +150C 300C 163C/W
Note: 1. Functional operation under any of these conditions is not implied. Performance is guaranteed only if Operating Conditions are not exceeded.
Operating Conditions
Parameter Switching Regulator Supply, VCCA Ambient Operating Temperature, TA Gate Drive Supply, VCCP Conditions Min. 4.75 0 9.5 12 Typ. 5 Max. 5.25 70 12.6 Units V C V
2
PRODUCT SPECIFICATION
RC5037
Electrical Characteristics (VCCA = 5V, VCCP = 12V, TA = 25C using circuit of Figure 1, unless otherwise noted)
The * denotes specifications which apply over the full ambient operating temperature range. Parameter Output Voltage Output Temperature Drift Line Regulation Load Regulation VOUT PSRR Output Ripple, peak-peak Total DC Accuracy1 ILOAD = 5A Open Loop CEXT = 180pF Independent of load ILOAD = 13A * * * * Efficiency Output Driver Current Short Circuit Threshold Voltage On Time Pulse Width2 VCCA Supply Current VCCP Supply Current TA = 0C-70C VCCA = 4.75 to 5.25V, ILOAD = 13A ILOAD = 0 to 5A or 5A to 13A VCCA = 4.75 to 5.25V 20MHz BW, ILOAD = 13A * 80 0.5 70 90 3.5 5 20 15 25 100 60 15 55 85 100 Conditions Min. 1.5 40 3 30 5 43 Typ. Max. 3.6 Units V ppm/C mV mV dB mV mV % A mV s mA mA
Notes: 1. Total DC accuracy includes setpoint accuracy, temperature drift, line and load regulation. 2. The on-time pulse width of the oscillator is set via external capacitor CEXT.
3
RC5037
PRODUCT SPECIFICATION
Typical Operating Characteristics (VCCA = 5V, and TA = +25C using circuit in Figure 1, unless otherwise noted)
Efficiency vs. Output Current 95 94 93 92 91 90 89 88 87 86 85 1 2 3 4 5 6 7 8 9 10 Output Current +1.5 +1.0 VOUT (%) +0.5 Nom -0.5 -1.0 -1.5 0 2 4 6 8 10 Output Current (A) Output Voltage vs. Load
Efficiency (%)
Output Voltage vs. Temperature, IOUT = 10A +0.50 Output Voltage (%) +0.25 Nom. -0.25 -0.50 0 25 50 75 100 125
Transient Response, 0.5 to 5.5A ISW (2A/div) VOUT (50mV/div)
Output Ripple, IOUT = 10A)
Time (100s/division)
VOUT (10mV/division)
Time (2s/division)
4
PRODUCT SPECIFICATION
RC5037
Typical Operating Characteristics (continued)
Output Startup, System Power-Up Pin 7 (DRV), 10A Load
Time (5ms/division)
Time (1s/division)
Pin 7 (DRV), 0.1A Load
Time (1s/division)
Application Circuit
Optional L1 +5V 2.5H +C2 +C4 + C3 1200F 1200F 1200F C8 0.1F
+12V C1 0.1F
R1 47 C5
D2 MMBD4148 D3 1N4735A 1F
FDB6030L Q1 R2 4.7 D1 L2 4.7H R3 5.2m R4 2.43K + VCORE
C7 0.1uF C6 180pF
8 1 7 2 U1 3 RC5037 6 5 4
...
MBRB1545CT
+ C14 1500F
R5 2K
Figure 1. 13A at 3.3V Application Schematic
5
RC5037
PRODUCT SPECIFICATION
Table1. Bill of Materials for a RC5037 3.3V, 13A Application
Qty. 3 3 1 1 6 1 1 1 1 1 1 1 1 1 Reference C1, C7-8 C2-4
C5 C6
Manufacturer Part Order # Any Sanyo 10MV1200GX Any Any Sanyo 6MV1500GX Any Any N/A Any Any Motorola MBRB1545CT Fairchild MMBD4148 Motorola 1N4735A Fairchild FDB6030L Any Any Fairchild RC5037M
Description 100nF, 25V Capacitor 1200F, 10V Aluminum Capacitor 1F, 25V Capacitor 180pF, 50V Capacitor 1500F, 6.3V Aluminum Capacitor 47.5 4.75 5.2m, 1W Resistor 2.43K 2K 15A, 45V Schottky Signal Diode 6.2V Zener 30V, 14m Logic Level MOSFET 2.5H Inductor 4.7H Inductor PWM Controller C0G
Requirements and Comments IRMS = 2A , See Equation (2) in Applications
C9-14 R1 R2 R3 R4 R5 D1 D2 D3 Q1
ESR = 44m
PCB Trace Resistor, see Eauation (3) Applications
Optional L1 1 1 L2 U1
ISAT > 8A ISAT > 13A
Application Information
The RC5037 contains a precision trimmed zero TC voltage reference, a constant-on-time architecture controller, a high current output driver, and a low offset error amp. The detailed block diagram in Figure 1 shows how the RC5037 works together with external components to achieve a highperformance switching power supply.
High Current Output Drivers
The RC5037 high current output driver (DRV) contains high speed bipolar power transistors configured in a push-pull configuration. The output driver is capable of supplying 0.5A of current in less than 100ns. The driver's power and ground are separated from the overall chip power and ground for added switching noise immunity.
Switch-Mode Control Loop
The main control loop for the switch-mode converter consists of a current conditioning amplifier and a voltage conditioning amplifier. The voltage amplifier compares the voltage from the internal reference with the converter's output voltage divided by an external resistor divider. The current amplifier senses the current by comparing the voltages at the IFBH and IFBL pins, which are attached to either side of the current sense resistor. The signals from the voltage and current amplifiers are summed together, the result being used to control the off-time of the oscillator. The current feedback signal is also used as part of the RC5037 short-circuit protection.
Internal Reference
The reference in the RC5037 is a precision band-gap type reference. Its temperature coefficient is trimmed to provide a near zero TC.
Constant-On-Time Oscillator
The RC5037 switch-mode oscillator is designed as a fixed on-time, variable off-time oscillator. The constant-on-time oscillator consists of a comparator, an external capacitor, a fixed current source, a variable current source, and an analog switch that selects between two threshold voltages for the comparator. The external timing capacitor is alternately
6
PRODUCT SPECIFICATION
RC5037
charged and discharged through the enabling and disabling of the fixed current source. The variable current source is controlled from the error inputs that are received from the current and voltage feedback signals. The oscillator off-time is controlled by the amount of current that is available from
the variable current source to charge the external capacitor up to the high threshold level of the comparator. The on-time is set by the constant current source that discharges the external capacitor voltage down to the lower comparator threshold.
+5V +12V VCCA
2
4 IFBL
gm
3 IFBH
Constant On-Time Oscillator
gm CEXT IO
8 VCCP
VH
1
7 SDRV
VL ION REF
5 FBSW 6
VOUT
GNDP
65-5037-07
Figure 2. RC5037 Detailed Block Diagram
Output Voltage Selection
The RC5037 precision reference is trimmed to be 1.5V nominally. When using the RC5037, the system designer has complete flexibility in choosing the output voltage for one regulator from 1.5V to 3.6V. This is done by appropriately selecting the feedback resistors. These could be 0.1% resistors to realize optimum output accuracy. The following equations determines the output voltage of the regulator:
R4 + R5 V OUT = 1.5 x -------------------- R5
ing, we have DC = 1.5/5 = 0.3, and
10* 0.03 - 0.3 No. Caps = ----------------------------------- = 2.29 2 2
so that we need 3 input capacitors.
Short Circuit Considerations
The RC5037 uses a current sensing scheme to limit the load current if an output fault condition occurs. The current sense resistor carries the peak current of the inductor, which is greater than the maximum load current due to ripple current flowing in the inductor. The RC5037 will begin to limit the output current to the load by reducing the duty cycle of the top-side MOSFET driver when the voltage across the current-sense resistor exceeds the short circuit comparator threshold voltage (Vth). When this happens the output voltage will temporarily go out of regulation. As the voltage across the sense resistor becomes larger, the duty cycle of the top-side MOSFET will continue to be reduced until the current limit value is reached. At this point, the RC5037 will continuously deliver the limit current at a reduced output voltage level. The short circuit comparator threshold voltage is typically 90mV, with a tolerance of 10mV. The ripple current flowing through the inductor in Figure 1 is 0.6A. Refer to Application Note AM-53 for detailed discussions. The sense resistor value can be approximated as follows:
V th,min V th,min R SENSE = --------------- x ( 1 - TF ) = --------------------------------------------- x ( 1 - TF ) (3) I PK 0.6A + I LOAD,MAX
(1)
For example, for 3.3V:
R4 + R5 2.43k + 2.0k V OUT = 1.5 x -------------------- = 1.5 x ------------------------------ = 3.3V R5 2.0k
Input Capacitors
The number of input capacitors required for the RC5037 is dependent on their ripple current rating, which assures their rated life. The number required may be determined by
I out * DC - DC No. Caps = --------------------------------------I rating
2
(2)
where the duty cycle DC = Vout/Vin. For example, with a 1.5V output at 10A, 5V input, and using the Sanyo capacitors specified in Table 1 which have a 2A ripple current rat-
7
RC5037
PRODUCT SPECIFICATION
where TF = Tolerance Factor for the sense resistor and 0.6A accounts for the inductor ripple current. Since the value of the sense resistor is often less than 10m, care should be taken in the layout of the PCB. Trace resistance can contribute significant errors. The traces to the IFBH and IFBL pins of the RC5037 should be Kelvin connected to the pads of the current-sense resistor. To minimize the influence of noise, the two traces should be run next to each other.
Board Design Considerations
MOSFET Placement
Schottky Diode
In Figure 1, MOSFET Q1 and flyback diode D1 are used as complementary switches in order to maintain a constant current through the output inductor L2. As a result, D1 will have to carry the full current of the output load when the power MOSFET is turned off. The power in the diode is a direct function of the forward voltage at the rated load current during the off time of the FET. The following equation can be used to estimate the diode power:
P DIODE = I D x V D x ( 1 - DutyCycle )
Placement of the power MOSFET is critical in the design of the switch-mode regulator. The MOSFET should be placed in such a way as to minimize the length of the gate drive path from the RC5037 SDRV pin. This trace should be kept under 0.5" for optimal performance. Excessive lead length on this trace will cause high frequency noise resulting from the parasitic inductance and capacitance of the trace. Since this voltage can transition nearly 12V in around 100nsec, the resultant ringing and noise would be very difficult to suppress. This trace should be routed on one layer only and kept well away from the "quiet" analog pins of the device: CEXT, IFBH, IFBL, and GND. Refer to Figure 2. A 4.7 resistor in series with the MOSFET gate can decrease this layout criticality. Refer to Figure 1.
Inductor and Schottky Diode Placement
where ID is the forward current of the diode, VD is the forward voltage of the diode, and DutyCycle is defined the same as
Vout Duty Cycle = -----------Vin
For the Motorola MBRB1545CT Rectifier in Figure 1,
P DIODE = 10A x 0.65 x ( 1 - 73.1% ) = 1.75W
The inductor and fly-back Schottky diode need to be placed close to the source of the power MOSFET for the same reasons stated above. The node connecting the inductor and Schottky diode will swing between the drain voltage of the FET and the forward voltage of the Schottky diode. It is recommended that this node be converted to a plane if possible. This node will be part of the high current path in the design, and as such it is best treated as a plane in order to minimize the parasitic resistance and inductance on that node. Since most PC board manufacturers utilize 1/2 oz copper on the top and bottom signal layers of the PCB, it is not recommended to use these layers to route the high current portions of the regulator design. Since it is more common to use 1 oz. copper on the PCB inner layers, it is recommended to use those layers to route the high current paths in the design.
It is recommended that the diode T0-220 package be attached to a heatsink.
Example of a Good Layout
Example of a Problem Layout
5 6 7 Noisy signal is routed away from quiet pins and the trace length is kept under 0.5in. The gate resistor is as close as possible to the MOSFET. 8
4 3 2 1
5 6 7 8
4 3 2 1
Noisy signal radiates onto quiet pins and the trace is too long. Gate resistor is far away from the MOSFET.
= "Quiet" Pins
Figure 3. Examples of good and poor layouts
8
PRODUCT SPECIFICATION
RC5037
Power and Ground Connections
MOSFET Gate Bias
+5V +12V
The connection of VCCA to the 5V power supply plane should be short and bypassed with a 0.1F directly at the VCCA pin of the RC5037. The ideal connection would be a via down to the 5V power plane. A similar arrangement should be made for the VCCP pin that connects to +12V. Each ground should have a separate via connection to the ground plane below. A 12V power supply is used to bias the VCCP. A 47 resistor is used to limit the transient current into VCCP. A 1uF capacitor filter is used to filter the VCCP supply and source the transient current required to charge the MOSFET gate capacitance. This method provides sufficiently high gate bias voltage to the MOSFET (VGS), and therefore reduces RDS(ON) of the MOSFET and its power loss. Figure 4 provides about 5V of gate bias which works well when using typical logic-level MOSFETs. Non-logic-level MOSFETs should not be used because of their higher RDS(ON).
47
VCCP
Q1 L2 RSENSE VOUT CBULK
1F GNDP
D1
Figure 4. 12V Gate Bias Configuration
9
PRODUCT SPECIFICATION
RC5037
Mechanical Dimensions
8 Lead SOIC Package
Inches Min. A A1 B C D E e H h L N ccc Max. Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
Symbol
.053 .069 .004 .010 .013 .020 .008 .010 .189 .197 .150 .158 .050 BSC .228 .010 .016 8 0 -- 8 .004 .244 .020 .050
1.35 1.75 0.10 0.25 0.33 0.51 0.20 0.25 4.80 5.00 3.81 4.01 1.27 BSC 5.79 0.25 0.40 8 0 -- 8 0.10 6.20 0.50 1.27
3 6
8
5
E
H
1
4
D A1 A SEATING PLANE B -C- LEAD COPLANARITY ccc C e
h x 45 C
L
10
RC5037
PRODUCT SPECIFICATION
Ordering Information
Product Number RC5037M Package 8 pin SOIC
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 1/26/00 0.0m 001 Stock#DS30005037 (c) 1998 Fairchild Semiconductor Corporation
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DISCLAIMER
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LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Rev. D
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RC5037
Adjustable Switching Regulator
Features
* High power switched-mode DC-DC controller can control in excess of 13A * Output voltage adjustable from 1.5V to 3.6V * 85% efficiency * Cumulative accuracy < 3% over line, load, and temperature variations * Overvoltage and short circuit protection * Built-in soft start
Description
The RC5037 is a high power, switch-mode DC-DC controller that provides an accurate output for high-end microprocessors CPU voltage. This controller has a built-in Soft Start feature which offers system protection during power-up by reducing both inrush current and output overshoot. When combined with the appropriate external circuitry, the RC5037 can deliver load currents as high as 13A at efficiencies as high as 88%. The RC5037 can generate output voltages from 1.5V up to 3.6V using external resistors. The RC5037 is designed to operate in a "constant on-time" (patent pending) control mode under all load conditions. Its accurate low TC reference eliminates the need for precision external components in order to achieve the tight tolerance voltage regulation required by most CPU-based applications. Short circuit current protection is provided through the use of a current sense resistor, while overvoltage protection is provided internally.
Preliminary Information
Applications
* Precision 2.xV CPU core regulator for Pentium(R) MMXTM processes * Precision 2.xV or 3.xV CPU core regulator for AMD-K6TM MMX and Cyrix 6x86MXTM (M2) processors
Block Diagram
5V
2
+12V
4
+5V
RC5037
Feedback Control
3 8
1
Oscillator
Digital Logic
7
Vout for CPU Core
1.5V Reference
5 6 65-5037-01
Pentium is a registered trademark of Intel Corporation. MMX is a trademark of Intel Corporation. K6 is a trademark of AMD Corporation. 6x86MX is a trademark of Cyrix Corporation.
Rev. A.9.4
PRELIMINARY INFORMATION describes products that are not in full production at the time of printing. Specifications are based on design goals and limited characterization. They may change without notice. Contact Fairchild Semiconductor for current information.
RC5037
PRODUCT SPECIFICATION
Functional Description
The RC5037 contains a precision trimmed zero TC voltage reference, a constant-on-time architecture controller, a high current output driver, and a low offset op-amp. The detailed block diagram in Figure 1 shows how the RC5037 works together with external components to achieve a high-performance switching power supply.
High Current Output Drivers
The RC5037 high current output driver (SDRV) contains high speed bipolar power transistors configured in a push-pull configuration. The output driver is capable of supplying 0.5A of current in less than 100ns. The driver's power and ground are separated from the overall chip power and ground for added switching noise immunity.
Switch-Mode Control Loop
The main control loop for the switch-mode converter consists of a current conditioning amplifier and a voltage conditioning amplifier. The voltage amplifier compares the voltage from the internal reference with the converter's output voltage divided by an internal resistor divider. The current amplifier senses the current by comparing the voltages at the IFBH and IFBL pins, which are attached to either side of the current sense resistor. The signals from the voltage and current amplifiers are summed together, the result being use to control the off-time of the oscillator. The current feedback signal is also used as part of the RC5037 short-circuit protection.
Internal Reference
The reference in the RC5037 is a precision band-gap type reference. Its temperature coefficient is trimmed to provide a near zero TC.
Constant-On-Time Oscillator
The RC5037 switch-mode oscillator is designed as a fixed on-time, variable off-time oscillator. The constant-on-time oscillator consists of a comparator, an external capacitor, a fixed current source, a variable current source, and an analog switch that selects between two threshold voltages for the comparator. The external timing capacitor is alternately charged and discharged through the enabling and disabling of the fixed current source. The variable current source is controlled from the error inputs that are received from the current and voltage feedback signals. The oscillator off-time is controlled by the amount of current that is available from the variable current source to charge the external capacitor up to the high threshold level of the comparator. The on-time is set by the constant current source that discharges the external capacitor voltage down to the lower comparator threshold.
Preliminary Information
+5V +12V VCCA
2
4 IFBL
gm
V/I
3 IFBH
Constant On-Time Oscillator
V/I gm CEXT 1 IO
8 VCCP
VH VL ION REF
7 SDRV
VOUT
6
5
FBSW
GNDP
65-5037-07
Figure 1. RC5037 Detailed Block Diagram
2
PRODUCT SPECIFICATION
RC5037
Pin Assignments
CEXT VCCA IFBH IFBL
1 2 3 4 8 7 6 5
VCCP SDRV GNDP FBSW
RC5037
Pin Descriptions
Pin Name CEXT Pin Number 1 Pin Function Description
Preliminary Information
External capacitor. A 180pF capacitor is connected to this pin as part of the constant on-time pulse width circuit. Careful layout of this pin is critical to system performance. See Applications Information for details. Switching Regulator Vcc. Power supply for switching regulator control circuitry and voltage reference. Connect to system 5V supply and decouple to ground with 0.1mF ceramic capacitor. High side current feedback for switching regulator. Pins 3 and 4 are used as the inputs for the current feedback control loop and as the short circuit current sense points. Careful layout of the traces from these pins to the current sense resistor is critical for optimal performance of the short circuit protection scheme. See Applications Information for details. Low side current feedback for switching regulator. See Applications Information for details. Voltage feedback for switching regulator. Using two external resistors, this pin sets the output voltage level for the switching regulator. Power Ground. Connect to a low impedance ground. See Application Information for details. FET driver output for switching regulator. Connect this pin to the gate of the N-channel MOSFET Q1 as shown in Figure 12. The trace from this pin to the MOSFET gate should be kept as short as possible (less than 0.5"). See Applications Information for details. Switching regulator gate drive Vcc. Power supply for SDRV output driver. Connect to system 12V supply with R-C filter shown in Figure 12. See Applications Information for details.
VCCA
2
IFBH
3
IFBL FBSW GNDP SDRV
4 5 6 7
VCCP
8
Absolute Maximum Ratings
Supply Voltages, VCCA Supply Voltages, VCCP Junction Temperature, TJ Storage Temperature, TS Lead Soldering Temperature, 10 seconds 7V 13V +150C -65 to +150C 300C
Note: 1. Functional operation under any of these conditions is not implied. Performance is guaranteed only if Operating Conditions are not exceeded.
3
RC5037
PRODUCT SPECIFICATION
Operating Conditions
Parameter Switching Regulator Supply, VCCA Ambient Operating Temperature, TA Gate Drive Supply, VCCP Conditions Min. 4.75 0 9.5 12 Typ. 5 Max. 5.25 70 12.6 Units V C V
Electrical Characteristics
(VCCA = 5V, VCCP = 12V, TA = 25C using circuit of Figure 10, unless otherwise noted) The * denotes specifications which apply over the full ambient operating temperature range.
Preliminary Information
Parameter Initial Accuracy1 Output Temperature Drift Line Regulation Load Regulation VOUT PSRR Output Ripple, peak-peak Cumulative DC Efficiency Output Driver Current Short Circuit Threshold Voltage On Time Pulse Width3 Accuracy2
Conditions ILOAD = 13A TA = 0C-70C VCCA = 4.75 to 5.25V, ILOAD = 13A ILOAD = 0 to 5A or 5A to 13A
Min. 1.5
Typ. 40 3 30
Max. 3.6 5 43
Units V ppm/C mV mV dB mV
60 20MHz BW, ILOAD = 13A * ILOAD = 5A Open Loop CEXT = 180pF * Independent of load ILOAD = 13A ILOAD = 13A * * * * * * 80 0.5 80 90 3.5 140 5 20 125 10 25 100 15 55 85 100
mV % A mV ms C/W mA mA mW
Thermal Impedance, qJA VCCA Supply Current VCCP Supply Current Internal Power Dissipation
Notes: 1. Initial accuracy is the initial output voltage variability under the specified conditions. 2. Cumulative DC accuracy includes setpoint accuracy, temperature drift, line and load regulation. 3. The on-time pulse width of the oscillator is set via external capacitor CEXT.
4
PRODUCT SPECIFICATION
RC5037
Typical Operating Characteristics
(VCCA = 5V, and TA = +25C using circuit in Figure 10, unless otherwise noted)
100 +1.5 +1.0 90
Efficiency (%)
VOUT (%)
0 2 4 6 8 10
+0.5 Nom -0.5 -1.0
80
70
-1.5 0 2 4 6 8 10
Output Current (A) Figure 2. Switcher Efficiency vs. Output Current
+0.50
Output Current (A) Figure 3. Switcher Output Voltage vs. Load
Preliminary Information
Output Voltage (%)
+0.25 Nom. -0.25 -0.50 0 25 50 75 100 125
Figure 4. Output Voltage vs. Temperature (II/O = 10A)
ISW(2A/div) VOUT (50mV/div)
Time (100ms/division) Figure 5. Switcher Transient Response (0.5 to 5.5A Load Step)
VOUT (10mV/division)
Time (2ms/division) Figure 6. Switcher Output Ripple (BW = 20MHz, I I/O = 10A)
65-5037-03
5
RC5037
PRODUCT SPECIFICATION
Typical Operating Characteristics (continued)
VCCA(2V/div) SDRV Output Voltage (2V/div)
VOUT(2V/div)
Time (5ms/division)
Time (1s/division) Figure 8. Pin 7 (SDRV) at a 10 Amp Load
Preliminary Information
Figure 7. Switcher Turn-on Response
SDRV Output Voltage (2V/div)
Time (1s/division) Figure 9. Pin 7 (SDRV) at a 0.1 Amp Load
Test Circuit Configurations
L1 +5V 2.5H D2 1N4148 D3 1N4735A 1F R2 4.71/2 D1 1 2 C7 0.1uF C6 180pF
65-5037-11
+ C2 1200F
+ C3 1200F
+ C4 1200F
C8
0.1F
R1 +12V 471/2 C5 C1 0.1F
Q1
IRL3103 L2 4.7H R3 5.2m1/2
VCORE R11 1.74K1/2 1-2 2.8V R10 1.87K1/2 R9 2.26K1/2 R8 0.80K1/2 C8 1500F
8 U1 RC5037 7 6 5 MBR1545CT
3-4 2.9V
5-6 3.2V
7-8
+
...
+
C14 1500F
3 4
2.1V
R7 2.00K1/2
Figure 10. 13A Application Schematic
6
PRODUCT SPECIFICATION
RC5037
Table 1. Bill of Materials for a RC5037 13A Application
Qty. 3 2 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reference C1, C7, C8 C2, C3, C4 C5 C6 C9, C10, C11, C12, C13, C14 R1 R2 R3 R7 R8 R9 R10 R11 D1 D2 D3 Q1 L1 L2 U1 Manufacturer Rohm Sanyo Rohm Rohm Sanyo Panasonic Panasonic Fairchild Semiconductor Panasonic Panasonic Panasonic Panasonic Panasonic Motorola Any Motorola IR Panasonic Pulse Fairchild Semiconductor Part Number MCH212F104ZP 10MV1200GX MCH312F105ZP MCH215A181JK 6MV1500GX ERJ-6GEYJ470 ERJ-6GEYJ4R7 RC10-52 ERJ-ENF 2.0 0KV ERJ-ENF 0.80KV ERJ-ENF 2.26KV ERJ-ENF 1.87KV ERJ-ENF 1.74KV MBR1545CT 1N4148 1N4735A IRL3103 EXC-ELDR35V PE-53682 RC5037M Description 100nF +80/-20%, 25V Z5U Ceramic Capacitor 1200mF, 10V 44mW Aluminum Capacitor 1mF +80/-20%, 25V Z5U Ceramic Capacitor 180pF 5%, 50V COG Ceramic Capacitor 1500mF, 6.3V, 44mW Aluminum Capacitor 47W 5%, 1/10W Resistor 4.7W 5%, 1/10W Resistor 5.2mW, 1W Resistor
Preliminary Information
0.1% resistor desirable for accuracy 0.1% resistor desirable for accuracy 0.1% resistor desirable for accuracy 0.1% resistor desirable for accuracy 0.1% resistor desirable for accuracy 15A, 45V Schottky Diode Small Signal Diode 6.2V 5%, 1W, Zener Diode 30V, 14mW Logic Level MOSFET 2.5mH Bead Inductor 4.7mH, ISAT > 10A Inductor Adjustable Switching Regulator
Table 2. Switching Regulator Components Selection Table
Output Voltage 3.5 2.8 2.9 2.9 3.2 3.2 2.1 3.3 Output Current 8 6 6.25 7.5 9.5 13 5.6 3 CIN Sanyo 10MV1200GX 1x 1x 1x 1x 2x 3x 1x N/A COUT Sanyo 6M1500GX 2x 2x 2x 2x 4x 6x 2x 1x Power MOSFET (M1) IRL3103 IRL3103 IRL3103 IRL3103 IRL3103 IRL3103 IRL3103 Si9936
Applications Information
The following discussion is intended to be an abbreviated list of design considerations regarding the RC5037 as used in a typical processor motherboard application. For a more thorough discussion of applicable specifications and layout considerations relating to the Intel Pentium P55C processor, please refer to Application Note 48.
Output Voltage Selection
Feedback Voltage Divider
The RC5037 precision reference is trimmed to be 1.5V nominally. When using the RC5037, the system designer has complete flexibility in choosing the output voltage for each regulator from 1.5V to 3.6V. This is done by appropriately selecting the feedback resistors. These should be 0.1% resis tors to realize optimum output accuracy. The following equations determine the output voltages of the two regulators: 7
RC5037
PRODUCT SPECIFICATION
Switching Regulator
Rx + R7 V OUT = 1.5 ae --------------------o e R7 o
V th,min V th,min R SENSE = --------------- ( 1 - TF ) = --------------------------------------------- ( 1 - TF ) I PK 0.6A + I LOAD,MAX
Where TF = Tolerance Factor for the sense resistor and 0.6A accounts for the inductor ripple current. There are several different types of sense resistors. Table 3 describes the tolerance, size, power capability, temperature coefficient and cost of various types of sense resistors. Based on the Tolerance in Table 3: For an embedded PC trace resistor:
0.08 RSENSE = ---------------------------------------- .71 0.6 + I LOAD,MAX
where Rx: R8, R9, R10, and R11. For example, for 2.8V:
R11 + R7 1.74k + 2.0k V OUT = 1.5 ae -----------------------o = 1.5 ae ------------------------------o = 2.8V e R7 o e o 2.0k
Short Circuit Considerations
Preliminary Information
The RC5037 uses a current sensing scheme to limit the load current if an output fault condition occurs. The current sense resistor carries the peak current of the inductor, which is greater than the maximum load current due to ripple current flowing in the inductor. The RC5037 will begin to limit the output current to the load by reducing the duty cycle of the top-side FET driver when the voltage across the currentsense resistor exceeds the short circuit comparator threshold voltage (Vth). When this happens the output voltage will temporarily go out of regulation. As the voltage across the sense resistor becomes larger, the duty cycle of the top-side MOSFET will continue to be reduced until the current limit value is reached. At this point, the RC5037 will continuously deliver the limit current at a reduced output voltage level. The short circuit comparator threshold voltage is typically 90mV, with a tolerance of 10mV. The ripple current flowing through the inductor in Figure 10 is 0.6A. There needs to be a 29% margin for the sense resistor when using a motherboard PC trace resistor. Refer to Application Note 48 for detailed discussions. The sense resistor value can be approximated as follows:
For a discrete Copel resistor:
0.08 RSENSE = ---------------------------------------- .90 0.6 + I LOAD,MAX
Table 4 lists recommended values for sense resistors for various load currents using an embedded PC trace resistor or a discrete resistor. If the calculated value is not available, round down.
Table 4. RSENSE for Various Load Currents, Switching Regulator
RSENSE ILOAD, MAX PC Trace Resistor (mW) (A) 3 15.8 RSENSE Discrete Resistor (mW) 20.0
Table 3. Comparison of Sense Resistors
Discrete Iron Alloy resistor (IRC) 5% (1% available) 0.45" x 0.065" x 0.2" 1 watt (3 and 5 watts available) +30 ppm $0.31 Discrete Metal Strip surface mount resistor (Dale) 1% 0.25" x 0.125" x 0.025" 1 watt (3 and 5 watts available) 75 ppm $0.47 Discrete MnCu Alloy wire resistor 10% 0.2" x 0.04" x 0.16" 1 watt 30 ppm $0.09 Discrete CuNi Alloy wire resistor (Copel) 10% 0.2" x 0.04" x 0.1" 1 watt 20ppm $0.09
Motherboard Trace Resistor Tolerance Factor (TF) Size (L x W x H) Power capability Temperature Coefficient Cost@10,000 piece quantity 29% 2" x 0.2" x 0.001" (1 oz Cu trace) >50A/in +4,000 ppm Low; included in motherboard
8
PRODUCT SPECIFICATION
RC5037
5 6 7 8 9 10 13
10.1 8.6 7.5 6.6 5.9 5.4 4.2
12.9 10.9 9.5 8.4 7.5 6.8 5.3
PMOSFET = 2.49W
Since the power at 10A is higher than the thermal guideline, a heat sink is required.
Schottky Diode
In Figure 10, MOSFET Q1 and flyback diode D1 are used as complementary switches in order to maintain a constant current through the output inductor L2. As a result, D1 will have to carry the full current of the output load when the power MOSFET is turned off. The power in the diode is a direct function of the forward voltage at the rated load current during the off time of the FET. The following equation can be used to estimate the diode power:
P DIODE = I D V D ( 1 - DutyCycle )
Since the value of the sense resistor is often less than 10mW, care should be taken in the layout of the PCB. Trace resistance can contribute significant errors. The traces to the IFBH and IFBL pins of the RC5037 should be Kelvin connected to the pads of the current-sense resistor. To minimize the influence of noise, the two traces should be run next to each other.
Preliminary Information
Thermal Design Considerations
Good thermal management is critical in the design of high current regulators. System reliability will be degraded if the component temperatures become excessive. The following guide should serve as a reference for proper thermal management.
MOSFET Temperature
where ID is the forward current of the diode, VD is the forward voltage of the diode, and DutyCycle is defined the same as above. For the Motorola MBR1545CT Rectifier in Figure 10,
P DIODE = 10A 0.65 ( 1 - 73.1% ) = 1.75W
The maximum power dissipation of the MOSFET can be calculated by using the following formula:
T J ( MAX ) - T A P D = --------------------------------Q JA
It is recommended that the diode T0-220 package be attached to a heatsink.
Board Design Considerations
MOSFET Placement
For IRL3103, QJA is 62C/W. For reliability the junction temperature of the MOSFET should not exceed 120C. Assuming that the ambient temperature is 40C, then the maximum power dissipation without heat sink is calculated as:
120 - 40 P D = -------------------- = 1.29W 62
The power that the MOSFET dissipates at 10A load is calculated as follows:
P MOSFET = I LOAD R DS ( ON ) ( Duty Cycle ) + V IN I LOAD ------------------------------- ( tr + t f ) f 6 V OUT + V D Duty Cycle = -----------------------------------------------------------------------------V IN + V D - ( I LOAD R DS ( ON ) )
2
Placement of the power MOSFET is critical in the design of the switch-mode regulator. The FET should be placed in such a way as to minimize the length of the gate drive path from the RC5037 SDRV pin. This trace should be kept under 0.5" for optimal performance. Excessive lead length on this trace will cause high frequency noise resulting from the parasitic inductance and capacitance of the trace. Since this voltage can transition nearly 12V in around 100nsec, the resultant ringing and noise would be very difficult to suppress. This trace should be routed on one layer only and kept well away from the "quiet" analog pins of the device: CEXT, IFBH, IFBL, and GND. A 4.7W resistor in series with the MOSFET gate can decrease this layout criticality. Refer to Figure 10.
Inductor and Schottky Diode Placement
where VD is the forward voltage of the Schottky diode used. Using the above formula, for Vout = 3.3V, ILOAD = 10A
3.3 + 0.65 Duty Cycle = ------------------------------------------------------- = 73.1% 5 + 0.65 - ( 10 0.023 ) 5V 10A 2 PMOSFET = ( 10A ) 0.025W 73.1% + ----------------------- 6 ( 210ns + 54ns ) 300KHz
The inductor and fly-back Schottky diode need to be placed close to the source of the power MOSFET for the same reasons stated above. The node connecting the inductor and Schottky diode will swing between the drain voltage of the FET and the forward voltage of the Schottky diode. It is recommended that this node be converted to a plane if possible. This node will be part of the high current path in the design, and as such it is best treated as a plane in order to minimize the parasitic resistance and inductance on that node. Since most PC board manufacturers utilize 1/2 oz copper on the
9
RC5037
PRODUCT SPECIFICATION
Example of a Good Layout
Example of a Problem Layout
5 6 7 Noisy signal is routed away from quiet pins and the trace length is kept under 0.5in. The gate resistor is as close as possible to the MOSFET. 8
4 3 2 1
5 6 7 8
4 3 2 1
Noisy signal radiates onto quiet pins and the trace is too long. Gate resistor is far away from the MOSFET.
= "Quiet" Pins
65-5037-10
Preliminary Information
Figure 11. Examples of good and poor layouts
top and bottom signal layers of the PCB, it is not recommended to use these layers to route the high current portions of the regulator design. Since it is more common to use 1 oz. copper on the PCB inner layers, it is recommended to use those layers to route the high current paths in the design.
Power and Ground Connections
Figure 12 provides about 5V of gate bias which works well when using typical logic-level MOSFETs, as shown in Figure 13. Non-logic-level MOSFETs should not be used because of their higher RDS(ON).
MOSFET Gate Bias
The connection of VCCA to the 5V power supply plane should be short and bypassed with a 0.1mF directly at the VCCA pin of the RC5037. The ideal connection would be a via down to the 5V power plane. A similar arrangement should be made for the VCCP pin that connects to +12V. Each ground should have a separate via connection to the ground plane below. A 12V power supply is used to bias the VCCP. A 47W resistor is used to limit the transient current into VCCP. A 1uF capacitor filter is used to filter the VCCP supply and source the transient current required to charge the MOSFET gate capacitance. This method provides sufficiently high gate bias voltage to the MOSFET (VGS), and therefore reduces RDS(ON) of the MOSFET and its power loss.
+5V +12V 471/2
VCCP Q1 L2 1F GNDP
65-5037-12
RSENSE
VI/O CBULK
D1
Figure 12. 12V Gate Bias Configuration
RDS(ON) Ohms
0.1 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 1.5 2 2.5 3 3.5 4 VGS 5 6 7
2SK1388 NDP7060 NDP706A NDP706AEL
8
9
10
11
Figure 13. RDS(ON) vs. VGS for Selected Logic-Level MOSFETs
10
PRODUCT SPECIFICATION
RC5037
Mechanical Dimensions
8 Lead SOIC Package
Inches Min. A A1 B C D E e H h L N a ccc Max. Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
Symbol
.053 .069 .004 .010 .013 .020 .008 .010 .189 .197 .150 .158 .050 BSC .228 .010 .016 8 0 -- 8 .004 .244 .020 .050
1.35 1.75 0.10 0.25 0.33 0.51 0.20 0.25 4.80 5.00 3.81 4.01 1.27 BSC 5.79 0.25 0.40 8 0 -- 8 0.10 6.20 0.50 1.27
Preliminary Information
3 6
8
5
E
H
1
4
D A1 A SEATING PLANE B -C- LEAD COPLANARITY ccc C a
h x 45 C
e
L
11
RC5037
PRODUCT SPECIFICATION
Ordering Information
Product Number RC5037M Package 8 pin SOIC
Preliminary Information
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonable expected to result in a significant injury of the user.
Fairchild Semiconductor Corporation Americas Customer Response Center Tel:1-888-522-5372 Fairchild Semiconductor Europe Fax: Email: Deutsch Tel: English Tel: Italy Tel: +49 (0) 1 80-530 85 86 europe.support@nsc.com +49 (0) 8 141-35-0 +44 (0) 1 793-85-68-56 +39 (0) 2 57 5631
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
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www.fairchildsemi.com 2/98 0.0m Stock#DS30005037A O 1998 Fairchild Semiconductor Corporation
www.fairchildsemi.com
RC5039
Programmable DC-DC Converter for P55C, K6, and M2 processors
Features
* * * * * Drives N-Channel MOSFET Operates From +5V or +12V VCC Bias Operates from +5V Power Input Simple Single-Loop Control Design - Voltage-Mode PWM Control Fast Transient Response - High-Bandwidth Error Amplifier - Full 0% to 100% Duty Ratio Excellent Output Voltage Regulation - 1.5% Over Line Voltage and Temperature 4 Bit Digital-to-Analog Output Voltage Selection - Wide Range - 2.0VDC to 3.5VDC - 0.1V Binary Steps Power-Good Output Voltage Monitor Over-Voltage and Over-Current Fault Monitors - Does Not Require Extra Current Sensing Element, uses MOSFET's RDS(ON) Small Converter Size - Constant Frequency Operation - 200kHz Free-Running Oscillator Programmable from 50kHz to 1MHz
Applications
* Power Supply for Pentium(R), Pentium(R) Pro, PowerPCTM and AlphaTM Microprocessors * High-Power 5V to 3.xV DC-DC Regulators * Low-Voltage Distributed Power Supplies
Preliminary Information
Description
The RC5039 provides complete control and protection for a DC-DC converter optimized for high-performance microprocessor applications. It is designed to drive an N-Channel MOSFET in a standard buck topology. The RC5039 integrates all of the control, output adjustment, monitoring and protection functions into a single package. The RC5039 includes a 4-Input Digital-to-Analog Converter (DAC) that adjusts the output voltage from 2.0VDC to 3.5VDC in 0.1V increments. The precision reference and voltage-mode regulator hold the selected output voltage to within 1.5% over temperature and line voltage variations.
* *
* *
*
Block Diagram
VCC VSEN 110% + 90% + 115% OVERVOLTAGE + + - OVERCURRENT REFERENCE 200A 4V SOFTSTART SS BOOT UGATE PHASE VID0 VID1 VID2 VID3 FB COMP OSCILLATOR RT/OVP D/A CONVERTER (DAC) DACOUT + ERROR AMP GND PWM COMPARATOR + INHIBIT PWM GATE CONTROL LOGIC 10A POWER-ON RESET (POR)
PGOOD
OCSET
Alpha is a trademark of Digital Equipment Corporation. Pentium is a registered trademark of Intel Corporation. PowerPC is a trademark of IBM.
Rev. 0.9.2
PRELIMINARY INFORMATION describes products that are not in full production at the time of printing. Specifications are based on design goals and limited characterization. They may change without notice. Contact Fairchild Semiconductor for current information.
RC5039
PRODUCT SPECIFICATION
The RC5039 provides simple, single feedback loop, voltagemode control with fast transient response. It includes a 200kHz free-running triangle-wave oscillator that is adjustable from 50kHz to 1MHz. The error amplifier features a 15MHz gain-bandwidth product and 6V/ms slew rate which enables high converter bandwidth for fast transient performance. The resulting PWM duty ratio ranges from 0% to 100%.
The RC5039 monitors the output voltage with a window comparator that tracks the DAC output and issues a Power Good signal when the output is within 10%. The RC5039 monitors the current by using the RDS(ON) of the upper MOSFET which eliminates the need for a current sensing resistor. The RC5039 protects against over-current conditions by inhibiting PWM operation. Built-in over-voltage protection triggers an exter-nal SCR to crowbar the input supply.
Pin Assignments
RC5039 (SOIC) TOP VIEW
OCSET 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VSEN RT/OVP VCC BOOT UGATE PHASE PGOOD GND
Preliminary Information
SS VID0 VID1 VID2 VID3 COMP FB
Pin Definitions
Pin Number 1 Pin Name OCSET Pin Function Description Connect a resistor (ROCSET) from this pin to the drain of the upper MOSFET. ROCSET , an internal 200mA current source (IOCS), and the upper MOSFET on-resistance. (RDS(ON)) set the converter over-current (OC) trip point according to the following equation:
I OCS * R OCSET I PEAK = --------------------------------------R DS ( ON )
An over-current trip cycles the soft-start function. 2 3-6 SS VID0-3 Connect a capacitor from this pin to ground. This capacitor, along with an internal 10mA current source, sets the soft-start interval of the converter. VID0-3 are the input pins to the 4-bit DAC. The states of these four pins program the internal voltage reference (DACOUT). The level of DACOUT sets the converter output voltage. It also sets the PGOOD and OVP thresholds. Table 1 specifies DACOUT for the 16 combinations of DAC inputs. COMP and FB are the available external pins of the error amplifier. The FB pin is the inverting input of the error amplifier and the COMP pin is the error amplifier output. These pins are used to compensate the voltage-control feedback loop of the converter. Signal ground for the IC. All voltage levels are measured with respect to this pin. PGOOD is an open collector output used to indicate the status of the converter output voltage. This pin is pulled low when the converter output is not within 10% of the DACOUT reference voltage. Connect the PHASE pin to the upper MOSFET source. This pin is used to monitor the voltage drop across the MOSFET for over-current protection. This pin also provides the return path for the upper gate drive. Connect UGATE to the upper MOSFET gate. This pin provides the gate drive for the upper MOSFET.
7 8
COMP FB
9 10
GND PGOOD
11
PHASE
12
UGATE
2
PRODUCT SPECIFICATION
RC5039
Pin Definitions (continued)
Pin Number 13 14 15 Pin Name BOOT VCC RT/OVP Pin Function Description This pin provides bias voltage to the upper MOSFET driver. A bootstrap circuit may be used to create a BOOT voltage suitable to drive a standard N-Channel MOSFET. Provide a 12V bias supply for the chip to this pin. This pin is multiplexed, providing two functions. The first function is oscillator switching frequency adjustment. By placing a resistor (RT) from this pin to GND, the nominal 200KHz switching frequency is increased according to the following equation:
5.6E3 [ KHz Kohm ] F S = 200kHz + ------------------------------------------------------R T [ Kohm ] ( R T to GND )
Conversely, connecting a pull-up resistor (RT) from this pin to VCC reduces the switching frequency according to the following equation:
30.0E3 [ KHz Kohm ] F S = 200kHz - ----------------------------------------------------------R T [ Kohm ] ( R T to 12V )
Preliminary Information
The second function for this pin is to drive an external SCR in the event of an overvoltage condition. 16 VSEN This pin is connected to the converters output voltage. The PGOOD and OVP comparator circuits use this signal to report output voltage status and for overvoltage protection.
Absolute Maximum Ratings
Power Input Voltage VIN Supply Voltage, VCC Boot Voltage, VBOOT - VPHASE VCC or I/O Voltage ESD Classification 6V +13.5V +13.5V GND -0.3V to VCC + 0.3V Class 2
Recommended Operating Conditions
Supply Voltage, VCC Ambient Temperature Range Junction Temperature Range +12V 10% 0C to 70C 0C to 100C
Thermal Information
Thermal Resistance (Typical, Note 1) SOIC Package SOIC Package (with 3 in2 of Copper) Maximum Junction Temperature (Plastic Package) Maximum Storage Temperature Range Maximum Lead Temperature (Soldering 10s) (SOIC - Lead Tips Only) qJA (C/W) 100 90 150C -65C to 150C 300C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Note: 1. qJA is measured with the component mounted on an evaluation PC board in free air.
3
RC5039
PRODUCT SPECIFICATION
Electrical Specifications (Recommended Operating Conditions, unless otherwise noted.)
Parameter VCC Supply Current ICC Nominal Supply Rising VCC Threshold Falling VCC Threshold Rising VOCSET Threshold Oscillator Free Running Frequency Total Variation RT = OPEN 6kW < RT to GND < 200kW RT = OPEN 180 -20 - -1.5 - - COMP = 10pF VBOOT - VPHASE = 12V, VUGATE = 6V VUGATE - VPHASE = 1V - 350 - - VOCSET = 4.5VDC VSEN = 5.5V; VOVP = 0V 170 60 - VSEN Rising VSEN Falling Upper and Lower Threshold IPGOOD = -5mA 106 89 - - 200 - 1.9 - 88 15 6 500 100 115 200 - 10 - - 2 0.5 220 +20 - +1.5 - - - - - 120 230 - - 111 94 - - kHz % VP-P % dB MHz V/ms mA mA % mA mA mA % % % V UGATE Open VOCSET = 4.5V VOCSET = 4.5V - - 8.8 - 22 - - 1.26 - 10.4 - - mA V V V Power-On Reset Test Conditions Min. Typ. Max. Units
Preliminary Information
DVOSC
Ramp Amplitude DACOUT Voltage Accuracy
Reference and DAC Error Amplifier DC Gain GBW SR IUGATE IUGATE Protection Over-Voltage Trip (VSEN/DACOUT) IOCSET IOVP ISS OCSET Current Source OVP Sourcing Current Soft Start Current Upper Threshold (VSEN /DACOUT) Lower Threshold (VSEN /DACOUT) Hysteresis (VSEN /DACOUT) VPGOOD PGOOD Voltage Low Gain-Bandwidth Product Slew Rate Upper Gate Source Upper Gate Sink
Gate Driver
Power Good
4
PRODUCT SPECIFICATION
RC5039
Typical Application
+12V VCC PGOOD SS RT/OVP MONITOR AND PROTECTION BOOT OCSET VIN = +5V OR +12V
OSC VID0 VID1 VID2 VID3 FB RC5039 D/A +
UGATE
PHASE
+VOUT
+ COMP
Preliminary Information
VSEN
GND
Functional Description
Initialization
The RC5039 automatically initializes upon receipt of power. Special sequencing of the input supplies is not necessary. The Power-On Reset (POR) function continually monitors the input supply voltages. The POR monitors the bias voltage at the VCC pin and the input voltage (VIN) on the OCSET pin. The level on OCSET is equal to VIN less a fixed voltage drop (see over-current protection). The POR function initiates soft start operation after both input supply voltages exceed their POR thresholds.
PGOOD (2V/DIV)
0V
SOFT-START (1V/DIV) OUTPUT VOLTAGE (1V/DIV)
Soft Start
The POR function initiates the soft start sequence. An internal 10mA current source charges an external capacitor (CSS) on the SS pin to 4V. Soft start clamps the error amplifier output (COMP pin) and reference input (+ terminal of error amp) to the SS pin voltage. Figure 1 shows the soft start interval with CSS = 0.1mF. Initially the clamp on the error amplifier (COMP pin) controls the converter's output voltage. At t1 in Figure 1, the SS voltage reaches the valley of the oscillator's triangle wave. The oscillator's triangular wave-form is compared to the ramping error amplifier voltage. This generates PHASE pulses of increasing width that charge the output capacitor(s). This interval of increasing pulse width continues to t2. With sufficient output voltage, the clamp on the reference input controls the output voltage. This is the interval between t2 and t3 in Figure 1. At t3 the SS voltage exceeds the DACOUT voltage and the output voltage is in regulation. This method provides a rapid and controlled output voltage rise. The PGOOD signal toggles `high' when the output voltage (VSEN pin) is within 5% of DACOUT. The 2% hysteresis built into the power good comparators prevents PGOOD oscillation due to nominal output voltage ripple.
0V 0V
t1 t2 t3
TIME (5ms/DIV)
Figure 1. Soft Start Interval
Over-Current Protection
The over-current function protects the converter from a shorted output by using the upper MOSFET's on-resistance, RDS(ON) to monitor the current. This method enhances the converter's efficiency and reduces cost by eliminating a current sensing resistor. The over-current function cycles the soft-start function in a hiccup mode to provide fault protection. A resistor (ROCSET) programs the over-current trip level. An internal 200mA current sink develops a voltage across ROCSET that is referenced to VIN. When the voltage across the upper MOSFET (also referenced to VIN) exceeds the voltage across ROCSET, 5
RC5039
PRODUCT SPECIFICATION
the over-current function initiates a soft-start sequence. The soft-start function discharges CSS with a 10mA current sink and inhibits PWM operation. The soft-start function recharges CSS, and PWM operation resumes with the error amplifier clamped to the SS voltage. Should an overload occur while recharging CSS, the soft start function inhibits PWM operation while fully charging CSS to 4V to complete its cycle. Figure 2 shows this operation with an overload condition. Note that the inductor current increases to over 15A during the CSS charging interval and causes an overcurrent trip. The converter dissipates very little power with this method. The measured input power for the conditions of Figure 2 is 2.5W.
A small ceramic capacitor should be placed in parallel with ROCSET to smooth the voltage across ROCSET in the presence of switching noise on the input voltage.
Output Voltage Program
The output voltage of a RC5039 converter is programmed to discrete levels between 2.0VDC and 3.5VDC. The voltage identification (VID) pins program an internal voltage reference (DACOUT) with a 4-bit digital-to-analog converter (DAC). The level of DACOUT also sets the PGOOD and OVP thresholds. Table 1 specifies the DACOUT voltage for the 16 combinations of open or short connections on the VID pins. The output voltage should not be adjusted while the converter is delivering power. Remove input power before changing the output voltage. Adjusting the output voltage during operation could toggle the PGOOD signal and exercise the over-voltage protection.
Preliminary Information
SOFT-START
4V 2V 0V
Table 1. Output Voltage Program
PIN NAME VID3 1 1 1
TIME (20ms/DIV)
OUTPUT INDUCTOR
15A 10A 5A 0A
VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
VID0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 0
NOMINAL DACOUT VOLTAGE 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5
1 1 1 1 1 0 0 0 0 0 0 0 0
Figure 2. Over-Current Operation
The over-current function will trip at a peak inductor current (IPEAK) determined by:
I OCSET * R OCSET I PEAK = ------------------------------------------r DS ( ON )
where IOCSET is the internal OCSET current source (200mA typical). The OC trip point varies mainly due to the MOSFET's RDS(ON) variations. To avoid over-current tripping in the normal operating load range, find the ROCSET resistor from the equation above with: 1. 2. 3. The maximum RDS(ON) at the highest junction temperature. The minimum IOCSET from the specification table. Determine IPEAK for IPEAK > IOUT(MAX) + (DI)/2, where DI is the output inductor ripple current.
Note: 1. 0 = Connected to GND or VSS, 1 = OPEN
For an equation for the ripple current see the section under component guidelines titled `Output Inductor Selection'.
The DAC function is a precision non-inverting summation amplifier shown in Figure 3. The resistor values shown are only approximations of the actual precision values used. Grounding any combination of the VID pins increases the DACOUT voltage. The `open' circuit voltage on the VID pins is the band gap reference voltage, 1.26V.
6
PRODUCT SPECIFICATION
RC5039
BAND GAP REFERENCE
VIN
RC5039
1.26V 21.5k1/2 VID0 10.7k1/2 VID1 5.4k1/2 VID2 2.7k1/2 VID3 D2 1.7k1/2 CO LOAD CIN + DACOUT + ERROR AMPLIFIER COMP UGATE PHASE Q1 LO VOUT
DAC
2.9k1/2
FB
RETURN
Figure 3. DAC Function Schematic
Figure 4. Printed Circuit Board Power and Ground planes or Islands
Preliminary Information
Application Guidelines
Layout Considerations
As in any high frequency switching converter, layout is very important. Switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. These interconnecting impedances should be minimized by using wide, short printed circuit traces. The critical components should be located as close together as possible using ground plane construction or single point grounding. Figure 4 shows the critical power components of the converter. To minimize the voltage overshoot the interconnecting wires indicated by heavy lines should be part of ground or power plane in a printed circuit board. The components shown in Figure 4 should be located as close together as possible. Please note that the capacitors CIN and CO each represent numerous physical capacitors. Locate the RC5039 within 3 inches of the MOSFET, Q1. The circuit traces for the MOSFET's gate and source connections from the RC5039 must be sized to handle up to 1A peak current.
Figure 5 shows the circuit traces that require additional lay-out consideration. Use single point and ground plane construction for the circuits shown. Minimize any leakage current paths on the SS PIN and locate the capacitor, CSS close to the SS pin because the internal current source is only 10mA. Provide local VCC decoupling between VCC and GND pins. Locate the capacitor, CBOOT as close as practical to the BOOT and PHASE pins.
+VIN BOOT CBOOT D1 Q1 LO VOUT LOAD
RC5039
SS
PHASE VCC +12V
D2
CO
CSS GND
CVCC
Figure 5. Printed Circuit Board Small Signal Layout Guidelines
7
RC5039
PRODUCT SPECIFICATION
Feedback Compensation
Figure 6 highlights the voltage-mode control loop for a buck converter. The output voltage (VOUT) is regulated to the reference voltage level. The error amplifier (Error Amp) output (VE/A) is compared with the oscillator (OSC) triangular wave to provide a pulse-width modulated (PWM) wave with an amplitude of VIN at the PHASE node. The PWM wave is smoothed by the output filter (LO and CO). The modulator transfer function is the small-signal transfer function of VOUT/VE/A. This function is dominated by a DC Gain and the output filter (LO and CO), with a double pole break frequency at FLC and a zero at FESR. The DC Gain of the modulator is simply the input voltage (VIN) divided by the peak-to-peak oscillator voltage DVOSC.
VIN OSC PWM COMPARATOR DVOSC + DRIVER LO PHASE CO ESR (PARASITIC) ZFB VE/A + ERROR AMP ZIN REFERENCE VOUT
is the difference between the closed loop phase at f0dB and 180. The equations below relate the compensation network's poles, zeros and gain to the components (R1, R2, R3, C1, C2, and C3) in Figure 6. Use these guidelines for locating the poles and zeros of the compensation network: 1. 2. 3. 4. 5. 6. 7. Pick Gain (R2/R1) for desired converter bandwidth Place 1ST Zero Below Filter's Double Pole (~75% FLC ) Place 2ND Zero at Filter's Double Pole Place 1ST Pole at the ESR Zero Place 2ND Pole at Half the Switching Frequency Check Gain against Error Amplifier's Open-Loop Gain Estimate Phase Margin - Repeat if Necessary
Preliminary Information
Compensation Break Frequency Equations
1 F Z1 = -------------------------------2p * R2 * C1 1 F P1 = --------------------------------------------------C1 * C2 2p * R2 * ae --------------------o e C1 + C2o 1 F P2 = -------------------------------2p * R3 * C3
1 F Z2 = -------------------------------------------------2p * ( R1 + R3 ) * C3
DETAILED COMPENSATION COMPONENTS ZFB C2 C1 R2 C3 R1 FB ZIN R3 VOUT
COMP +
Figure 7 shows an asymptotic plot of the DC-DC converter's gain vs. frequency. The actual Modulator Gain has a high gain peak due to the high Q factor of the output filter and is not shown in Figure 7. Using the above guidelines should give a Compensation Gain similar to the curve plotted. The open loop error amplifier gain bounds the compensation gain. Check the compensation gain at FP2 with the capabilities of the error amplifier. The Closed Loop Gain is constructed on the log-log graph of Figure 7 by adding the Modulator Gain (in dB) to the Compensation Gain (in dB). This is equivalent to multiplying the modulator transfer function to the compensation transfer function and plotting the gain.
100 80
RC5039
DACOUT
FZ1 FZ2
FP1
FP2 OPEN LOOP ERROR AMP GAIN
Figure 6. Voltage-Mode Buck Converter Compensation
GAIN (dB)
60 40 20 0 -20 -40
FLC MODULATOR GAIN FESR 20LOG (R2/R1)
Modulator Break Frequency Equations
1 F LC = -----------------------------------2p * L O * C O 1 F ESR = -----------------------------------2p * ESR * C O
20LOG (VIN /DVOSC) COMPENSATION GAIN CLOSED LOOP GAIN
The compensation network consists of the error amplifier (internal to the RC5039) and the impedance networks ZIN and ZFB. The goal of the compensation network is to provide a closed loop transfer function with the highest 0dB crossing frequency (f0dB) and adequate phase margin. Phase margin
-60
10
100
1K
10K 100K 1M FREQUENCY (Hz)
10M
Figure 7. Asymptotic Bode Plot of Converter Gain
8
PRODUCT SPECIFICATION
RC5039
The compensation gain uses external impedance networks ZFB and ZIN to provide a stable, high bandwidth (BW) overall loop. A stable control loop has a gain crossing with -20dB/decade slope and a phase margin greater than 45 degrees. Include worst case component variations when determining phase margin.
V IN - V OUT V OUT DI = ----------------------------- * -------------V IN FS L
DV RIPPLE = DI ESR
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply the load transient current. The filtering requirements are a function of the switching frequency and the ripple current. The load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. These requirements are generally met with a mix of capacitors and careful layout. Modern microprocessors produce transient load rates above 1A/ns. High frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (Effective Series Resistance) and voltage rating requirements rather than actual capacitance requirements. High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. Consult with the manufacturer of the load on specific decoupling requirements. For example, Intel recommends that the high frequency decoupling for the Pentium Pro be composed of at least forty (40) 1mF ceramic capacitors in the 1206 surface-mount package. Use only specialized low-ESR capacitors intended for switching-regulator applications for the bulk capacitors. The bulk capacitor's ESR will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. An aluminum electrolytic capacitor's ESR value is related to the case size with lower ESR available in larger case sizes. However, the equivalent series inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. Unfortunately, ESL is not a specified parameter. Work with your capacitor supplier and measure the capacitor's impedance with frequency to select a suitable component. In most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor.
Increasing the value of inductance reduces the ripple current and voltage. However, the large inductance values reduce the converter's response time to a load transient. One of the parameters limiting the converter's response to a load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, the RC5039 will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time required to slew the inductor current from an initial current value to the transient current level. During this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor. Minimizing the response time can minimize the output capacitance required. The response time to a transient is different for the application of load and the removal of load. The following equations give the approximate response time interval for application and removal of a transient load:
L O I TRAN t RISE = ----------------------------V IN - V OUT L O I TRAN t FALL = ---------------------------V OUT
Preliminary Information
where: ITRAN is the transient load current step, tRISE is the response time to the application of load, and tFALL is the response time to the removal of load. With a +5V input source, the worst case response time can be either at the application or removal of load and dependent upon the DACOUT setting. Be sure to check both of these equations at the minimum and maximum output levels for the worst case response time.
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage overshoot across the MOSFETs. Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time Q1 turns on. Place the small ceramic capacitors physically close to the MOSFETs and between the drain of Q1 and the anode of Schottky diode D2. The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. The RMS current rating requirement for the input capacitor of a buck regulator is approximately 1/2 the DC load current.
Output Inductor Selection
The output inductor is selected to meet the output voltage ripple requirements and minimize the converter's response time to the load transient. The inductor value determines the converter's ripple current and the ripple voltage is a function of the ripple current. The ripple voltage and current are approximated by the following equations:
9
RC5039
PRODUCT SPECIFICATION
For a through hole design, several electrolytic capacitors (Panasonic HFQ series or Nichicon PL series or Sanyo MVGX or equivalent) may be needed. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. These capacitors must be capable of handling the surge-current at power-up. The TPS series available from AVX, and the 593D series from Sprague are both surge current tested.
+12V DBOOT + VCC VD +5V
BOOT
RC5039
UGATE PHASE
CBOOT Q1 NOTE: VG-S VCC -VD D2
MOSFET Selection/Considerations
The RC5039 requires an N-channel power MOSFET. It should be selected based upon RDS(ON), gate supply requirements, and thermal management requirements.
+
GND
Preliminary Information
In high-current applications, the MOSFET power dissipation, package selection and heatsink are the dominant design factors. The power dissipation includes two loss components; conduction loss and switching loss. The conduction losses are the largest component of power dissipation for the MOSFET. Switching losses also contribute to the overall MOSFET power loss (see the equations below). These equations assume linear voltage-current transitions and are approximations. The gate-charge losses are dissipated by the RC5039 and don't heat the MOSFET. However, large gate-charge increases the switching interval, tSW, which increases the upper MOSFET switching losses. Ensure that the MOSFET is within its maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. A separate heat-sink may be necessary depending upon MOSFET power, package type, ambient temperature and air flow.
P COND = P SW
2 IO
Figure 8. Upper Gate Drive - Bootstrap Option
Figure 9 shows the upper gate drive supplied by a direct connection to VCC . This option should only be used in converter systems where the main input voltage is + 5VDC or less. The peak upper gate-to-source voltage is approximately VCC less the input supply. For +5V main power and + 12VDC for the bias, the gate-to-source voltage of Q1 is 7V. A logic-level MOSFET is a good choice for Q1 under these conditions.
+12V +5V OR LESS VCC BOOT
RC5039
Q1 UGATE PHASE NOTE: VG-S VCC -5V D2
R DS ( ON ) D
1 = -- I O V IN t SW Fs 2
+
Where: D is the duty cycle = VOUT/VIN, tSW is the switching interval, and Fs is the switching frequency Standard-gate MOSFETs are normally recommended for use with the RC5039. However, logic-level gate MOSFETs can be used under special circumstances. The input voltage, upper gate drive level, and the MOSFET's absolute gate-tosource voltage rating determine whether logic-level MOSFETs are appropriate. Figure 8 shows the upper gate drive (BOOT pin) supplied by a bootstrap circuit from VCC. The boot capacitor, CBOOT, develops a floating supply voltage referenced to the PHASE pin. This supply is refreshed each cycle to a voltage of VCC less the boot diode drop (VD) when the Schottky diode, D2, conducts. Logic-level MOSFETs can only be used if the MOSFET's absolute gate-to-source voltage rating exceeds the maximum voltage applied to VCC.
GND
Figure 9. Upper Gate Drive - Direct VCC Drive Option
Schottky Selection
Rectifier D2 conducts when the upper MOSFET Q1 is off. The diode should be a Schottky type for low power losses. The power dissipation in the Schottky rectifier is approximated by:
PD = IO Vf ( 1 - D )
Where: D is the duty cycle = VO/VIN, and Vf is the Schottky forward voltage drop In addition to power dissipation, package selection and heatsink requirements are the main design tradeoffs in choosing the Schottky rectifier. Since the three factors are interrelated,
10
PRODUCT SPECIFICATION
RC5039
the selection process is an iterative procedure. The maximum junction temperature of the rectifier must remain below the manufacturer's specified value, typically 125C. By using the package thermal resistance specification and the Schottky power dissipation equation (shown above), the junction temperature of the rectifier can be estimated. Be sure to use the available airflow and ambient temperature to determine the junction temperature rise.
RC5039 DC-DC Converter Application Circuit
The figure below shows an application circuit of a DC-DC Converter for an Intel Pentium Pro microprocessor.
F1 VIN = +5V 15A
L1 1.5 H C1-C4 4x 330F C19-C20 2x 1F CR1
Q2 2N6394 R6
+12V
VSS VR1 5.1V R9 10K C14 0.1F VCC 14 SS 2 C13 0.1F RT/OVP 15 OSC U1 VID0 VID1 VID2 VID3 VID0 VID1 VID2 VID3 3 4 5 D/A 6 +
10
Preliminary Information
C18 1F
IN4148
C21 1000pF R7 1.1K Q1 C22 0.1F L2 7H CR2 VOUT PWRGD
1 OCSET 10 PGOOD 13 BOOT 12 UGATE 11 PHASE 16 VSEN
MONITOR AND PROTECTION
+
RC5039
7 9 GND R8 20K C5-C12 8x 1000F VSS
FB 8 R2 750k
-
C15 33pF C16 R5
COMP
1000pF 90.9K R10 R3 3.01K 15K C24 0.1F
Component Selection Notes: C5-C12 - 8 each 1000F 6.3W VDC, Sanyo MV-GX or Equivalent C1-C4 - 4 each 330F 25W VDC, Sanyo MV-GX or Equivalent L1 - Core: Micrometals T60-52; Each Winding: 14 Turns of 17AWG L2 - Core: Micrometals T44-52; Winding: 7 Turns of 18AWG CR1 - 1N4148 or Equivalent CR2 - 25A, 35V Schottky, Motorola MBR2535CTL or Equivalent Q1 - Fairchild NDP6030L, heatsink with thermal resistance qSA<20C/W should be used
Figure 10. Pentium Pro DC-DC Converter
11
RC5039
PRODUCT SPECIFICATION
Notes:
Preliminary Information
12
PRODUCT SPECIFICATION
RC5039
Notes:
Preliminary Information
13
RC5039
PRODUCT SPECIFICATION
Notes:
Preliminary Information
14
PRODUCT SPECIFICATION
RC5039
Mechanical Dimensions
16 Lead SOIC
Symbol A A1 B C D E e H h L N a ccc Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
.053 .069 .004 .010 .013 .020 .008 .010 .386 .394 .150 .158 .050 BSC .228 .010 .016 16 0 -- 8 .004 .244 .020 .050
1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 9.80 10.00 3.81 4.00 1.27 BSC 5.80 0.25 0.40 16 0 -- 8 0.10 6.20 0.50 1.27
Preliminary Information
3 6
16
9
E
H
1
8
D A1 A SEATING PLANE -C- LEAD COPLANARITY ccc C a
h x 45 C
e
B
L
15
RC5039
PRODUCT SPECIFICATION
Ordering Information
Part Number RC5039CB Temperature Range (C) 0 to 70 Package 16 Lead SOIC Pkg. No. M16.15
Preliminary Information
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 7/1/98 0.0m 002 Stock#DS30005039 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC5040
Programmable Synchronous DC-DC Converter
Features
* Programmable output from 2.1V to 3.5V using integrated 4-bit DAC * 87% efficiency * Oscillator frequency adjustable from 200KHz to 1MHz * On-chip Power Good and Output Enable functions * Excellent transient response * Over-Voltage Protection * Short Circuit Protection * Precision trimmed low TC voltage reference * 20 pin SOIC package * Meets Intel Pentium(R) Pro VRM specifications using minimum number of external components
Description
The RC5040 is a synchronous mode DC-DC controller IC which provides an accurate, programmable output for Pentium(R) Pro CPU applications. Using an integrated 4-bit DAC to accept a voltage identification (VID) code directly from the CPU, the RC5040 can generate precise output voltages between 2.1V and 3.5V in 100mV increments. Output load currents in excess of 12A can be delivered using minimal external circuitry. The RC5040 is designed to operate in a standard PWM control mode under heavy load conditions and in PFM control mode while supplying light loads for optimal efficiency. An on-board precision low TC voltage reference eliminates the requirement for external components in order to achieve tight voltage regulation. The Pentium Pro(R) CPU is continuously protected by an integrated Power Good function, which sends an active-low interrupt signal to the CPU in the event that the output voltage is out of tolerance. The internal oscillator can be programmed to operate over a range of 200KHz to 1MHz to allow flexibility in choosing external components.
Applications
* Programmable power supply for Pentium(R) Pro and Pentium(R) based CPU motherboards * VRM module for Pentium(R) Pro CPU * Programmable power supply for high current microprocessors
Block Diagram
RC5040
OSCILLATOR
- +
+5V VIN
- +
- +
- +
VO DIGITAL CONTROL
VREF
4-BIT DAC
1.24V REFERENCE
POWER GOOD
PWRGD
VID0 VID1 VID2 VID3
65-5040-01
ENABLE
Rev. 1.3.1
RC5040
PRODUCT SPECIFICATION
Pin Assignments
CEXT ENABLE PWRGD IFB VFB VCCA VCCD VCCP LODRV GNDP
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
65-5040-02
VID0 VID1 VID2 VID3 VREF GNDA GNDD VCCQP HIDRV GNDP
Pin Definitions
Pin Number 1 Pin Name CEXT Pin Function Description Oscillator capacitor connection. Connecting an external capacitor to this pin sets the internal oscillator frequency from 200 KHz to 1 MHz. Layout of this pin is critical to system performance. See Application Information for details. Output Enable. Open collector/TTL input. Logic LOW will disable output. A 10KW internal pull-up resistor assures correct operation if pin is left unconnected. Power Good output flag. Open collector output will be at logic HIGH under normal operation. Logic LOW indicates output voltage is not within 10% of nominal. High side current feedback. Pins short 4 and 5 are used as the inputs for the current feedback control loop and as the short circuit current sense points. Layout of these traces is critical to system performance. See Application Information for details. Voltage feedback. Pin 5 is used as the input for the voltage feedback control loop and as the low side current feedback input. Layout of this trace is critical to system performance. See Application Information for details. Analog VCC. Connect to system 5V supply and decouple to ground with 0.1mF ceramic capacitor. Digital VCC. Connect to system 5V supply and decouple to ground with 4.7mF tantalum capacitor. Power VCC for low side FET driver. Connect to system 5V supply. Low side FET driver output. Connect this pin to the gate of the N-channel MOSFET M3 in Figure 2. The trace from this pin to the MOSFET gate should be as short as possible (less than 0.5"). See Application Information for details. Power ground. Return pin for high currents flowing in pins 12 and 13 (HIDRV and VCCQP). Connect to low impedance ground. See Application Information for details. High side FET driver output. Connect this pin to the gate of the N-channel MOSFETs M1 and M2 in Figures 1 and 2. The trace from this pin to the MOSFET gates should be kept as short as possible (less than 0.5"). See Application Information for details. Power VCC for high side FET driver. VCCQP must be connected to a voltage of at least VCCA + VGS,ON (M1). See Application Information for details. Digital ground. Return path for digital logic. This pin should be connected to system ground so that ground loops are avoided. See Application Information for details.
2 3 4
ENABLE PWRGD IFB
5
VFB
6 7 8 9
VCCA VCCD VCCP LODRV
10, 11
GNDP
12
HIDRV
13 14
VCCQP GNDD
2
PRODUCT SPECIFICATION
RC5040
Pin Definitions (continued)
Pin Number 15 16 Pin Name GNDA VREF Pin Function Description Analog ground. Return path for low power analog circuitry. Connect to system ground so that ground loops are avoided. See Application Information for details. Reference voltage test point. This pin provides access to the DAC output and should be decoupled to ground using a 0.1mF capacitor. No load should be connected to this pin. Voltage identification (VID) code inputs. These open collector/TTL compatible inputs will program the output voltage over the ranges specified in Table 1. Internal 10KW pull-up resistors assure correct operation if pins are left unconnected.
17-20
VID3 - VID0
Absolute Maximum Ratings1
Supply Voltages, VCCA, VCCD, VCCP Supply Voltage for high side FET, VCCQP Voltage Identification Code Inputs, VID3-VID0 Junction Temperature, TJ Storage Temperature, TS Lead Soldering Temperature, 10 seconds 13V 13V 13V 150C -65 to 150C 300C
Notes: 1. Functional operation under any of these conditions is not implied. Permanent damage may occur if the device is subjected to conditions outside these ratings.
Operating Conditions
Parameter Supply Voltages, VCCA, VCCD, VCCP1 High side FET supply, VCCQP VID Code Input Voltage, Logic HIGH VID Code Input Voltage, Logic LOW PWRGD HIGH Threshold PWRGD LOW Threshold Operating Ambient Temperature, TA Conditions Min. 4.5 9 2 Typ. 5 10 Max. 7 12 0.8 +7 -7 0 70 Units V V V V %VREF %VREF C
Notes: 1. In non-synchronous operation, VCCP must be connected to GND.
Electrical Specifications
(VCCA, VCCD = 5V, fosc = 650 KHz, and TA = +25C using circuit in Figure 1, unless otherwise noted) The * denotes specifications which apply over the full operating temperature range. Parameter Output Voltage Output Current1 Setpoint Accuracy2 Output Temperature Drift Load Regulation Line Regulation Output Ripple/Noise, pk-pk Cumulative Accuracy3 Efficiency Conditions TA = 0-70C, See Table 1. ILOAD = 5.25A TA = 0-70C ILOAD = 0.5 to 12.5A VIN = 4.75-5.25V, ILOAD = 12.5A VOUT = 2.1-3.5V, 20MHz BW TA = 0-70C ILOAD = 12.5A, VOUT = 3.3V * Min. 2.0 Typ. 12.5 1.0 +40 -1.0 +0.14 30 3.3 85 Max. 3.5 14.5 1.5 Units V A % ppm/ %Vo %Vo mV % % 3
* * * * * *
5.0
80
RC5040
PRODUCT SPECIFICATION
Electrical Specifications (continued) (VCCA, VCCD = 5V, fosc = 650 KHz, and TA = +25C using circuit in Figure 1, unless otherwise noted) The * denotes specifications which apply over the full operating temperature range.
Parameter Short Circuit Detect Threshold Output Current Driver Power Dissipation Thermal Impedance, qJA Response Time, Sleep to Full Load Oscillator Frequency Range4 excludes tolerance of CEXT 90 0.2 10 95 100 15 10 Slew rate = 30A/ms 100 30 Oscillator Frequency Accuracy Maximum Duty Cycle in PWM Mode Minimum Pulse Width in PFM Mode Response Time to Short Circuit Soft Start Duration at Power-Up Load Transient, 0.5 to 12.5A step Conditions Internal comparator offset No load * Min. 100 0.5 Typ. 120 1.0 0.1 80 10 1 Max. 140 0.2 Units mV A W C/W ms MHz % % ns ns ms mV
Notes: 1. The maximum output current is limited only by the external components used and their thermal limitations. For loads greater than 12.5A, adequate thermal management is required to achieve optimal performance and reliability. 2. Setpoint Accuracy includes Output Ripple/Noise. 3. Cumulative Accuracy is determined by Setpoint Accuracy, Line and Load Regulation, Output Ripple/Noise, Transient Performance and Temperature Drift. 4. See Typical Operating Characteristics.
Table 1. Voltage Identification Codes1
Pentium ProTM Processor Pins VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 VID Setpoint 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 Setpoint Accuracy2 (mV) -- 31 33 34 36 37 39 40 42 43 45 46 48 49 51 60 Cumulative Accuracy3 (mV) -- 105 110 115 120 125 130 135 140 145 150 155 160 165 170 175
Notes: 1. 0 = processor pin connected to VSS. 1 = Open. 2. Setpoint Accuracy includes Output Ripple/Noise. 3. Cumulative Accuracy includes Setpoint Accuracy, Line & Load Regulation, Transient Effects and Temperature Drift.
4
PRODUCT SPECIFICATION
RC5040
Typical Operating Characteristics
(VCCA, VCCD = 5V, fosc = 650 KHz, and TA = +25C using circuit in Figure 1, unless otherwise noted)
Efficiency vs. Output Current, 650 KHz
100 95 90 Efficiency (%) 85 80 75
65-5040-03
Load Regulation, 650 KHz
3.36 3.34 3.32 3.30 3.28 3.26 3.24 3.22 3.20 3.18 3.16 3.14 0.5 1 2 3.3V
3.1V
65 60 0.5 1 2 3 4 5 6 7 8 9 IOUT (Amps)
3.1V 3 4 5 6 7 8
10 11 12.5
9 10 11 12.5
IOUT (Amps)
Reference Tempco
3.162 3.160 3.158 Vref (V) 3.156 3.154
65-5040-05
VREF Programming
3.50 3.25 VREF pin (V) 3.00 2.75 2.50 2.25 2.00 2 2.5 3 VID Set Point (V)
65-5040-06
3.152 3.150 0 25 50 Temperature (C)
70
3.5
Oscillator Frequency vs. CEXT
1250 1050 Frequency (kHz)
Output Voltage vs. Output Current, RSENSE = 6m1/2
3.5 3.0
Output Voltage
850 650 450 250 50 18 39 75 150 CEXT (pf) 300
65-5040-07
2.5 2.0 1.5 1.0 0.5 0 0 5 10 15 20 65-5040-15 25
561
Output Current
65-5040-04
70
VOUT (Volts)
3.3V
5
RC5040
PRODUCT SPECIFICATION
Typical Operating Characteristics (continued)
Switching Waveforms, 12.5A Load FET Driver Supply, VCCQP (ILOAD = 12.5A using charge pump)
1V/div
CEXT pin VOUT (5V/div)
5V/div
HIDRV pin
Time (500ns/division)
Time (1s/division)
Transient Response, 0.5A to 12.5A Step
AC Ripple Response, 12.5A Load
VOUT (50mV/div)
Time (200s/division)
VOUT (50mV/div)
Time (1s/division)
Output Startup, System Power-Up
VOUT (2V/div) VOUT (2V/div)
Output Startup from Re-Enable
Time (50ms/division)
ON/OFF (2V/div)
VIN (2V/div)
Time (20ms/division)
65-5040-08
6
PRODUCT SPECIFICATION
RC5040
Test Circuits
L2 VCC C4 0.1F 2.5H C1 C2 C3 C5 0.1F DS2 1N5817 0.1F C8 C9 0.1F
1000F 1000F 1000F
M1 11 12 R7 10K VREF C7 0.1F GND 13 14 15 16 17 18 19 20 10 9 8 7 6 5 4 3 2 1 CEXT 39pF SS32 C6 4.7F DS1 C12 1F 2SK1388
M2 2SK1388 L1 1.3H RSENSE 1500F 6m1/2 1500F 1500F VO
RC5040
VID3 VID2 VID1 VID0
R1 R2 R3 R4
10K VCC 10K 10K 10K R5 VCC R6 10K PWRGD C11 0.22F 65-5040-09
OUTEN C10 0.1F 10K
Figure 1. Non-Synchronous DC-DC Converter Application Schematic
L2 VCC C4 0.1F 2.5H C1 1000F C2 C3 C5 0.1F DS2 1N5817 0.1F C8 C9 0.1F
1000F 1000F
M1 11 12 R7 10K VREF C7 0.1F GND 13 14 15 16 17 18 19 20 10 9 8 7 C12 1F 2SK1388
M2 2SK1388 L1 1.3H RSENSE 1500F 1500F 6m1/2 1500F VO
RC5040
6 5 4 3 2 1
C6 4.7F M3 2SK1388 DS1
C13
C14
C14
C13
SS32
CEXT 39pF
VID3 VID2 VID1 VID0
R1 R2 R3 R4
10K VCC 10K 10K 10K R5 VCC R6 10K PWRGD C11 0.22F 65-5040-10
OUTEN C10 0.1F 10K
Figure 2. Synchronous DC-DC Converter Application Schematic
C15
C15
7
RC5040
PRODUCT SPECIFICATION
Table 2. RC5040 Bill of Materials
Reference C6 CEXT C12 C1, C2, C3 C11 C13-C15 DS1 DS2 8 L21 M1, M22 Part Number Panasonic ECSH1CY475R Panasonic ECU-V1H121JCG Panasonic ECSH1CY105R Sanyo 6MV1000GX Panasonic ECU-V1H224ZFX Sanyo 6MV1500GX General Instrument SS32 General Instrument IN5817 Skynet 320-8107 Skynet 320-6110 Fuji 2SK1388 Copel A.W.G #18 Panasonic ERJ-6ENF10.0KV Description 0.1mF 50V capacitor 4.7mF 16V capacitor 39pF capacitor 1mF 16V capacitor 1000mF 6.3V electrolytic capacitor 0.22mF 50V capacitor 1500mF 6.3 electrolytic capacitor Schottky Diode 7 1.3mH inductor 2.5mH inductor N-Channel Logic Level Enhancement Mode MOSFET 6 mW CuNi Alloy Wire Resistor 10K 5% Resistors RDS(ON) < 37mW VGS < 4V, ID > 20A ESR < 0.047 W 3A, 20V 8 Relevant Spec. C4, C5, C7-C10 Panasonic ECU-V1H104ZFX
RSENSE R1-R4, R6, R7
Notes: 1. The inductor L2 is recommended to isolate the 5V input supply from current surges caused by MOSFET switching. L2 is not required for normal operation and may be omitted if desired. 2. A total of 3 MOSFETs are recommended only for the synchronous DC-DC converter application. For the non-synchronous application, the low side MOSFET M3 is not used.
Application Information
Simple Step-Down Converter
S1 L1 + VIN D1 C1 RL Vout -
65-5040-11
V OUT ( T S - T ON ) I L = -----------------------------------------L1
where: TS is the overall switching period. (TS - TON) is the time during which S1 is open. By solving these two equations, we can arrive at the basic relationship for the output voltage of a step-down converter:
T ON V OUT = V IN ae ----------o e TS o
Figure 3. Simple Buck DC-DC Converter
Figure 3 illustrates a step-down DC-DC converter with no feedback control. The derivation of the basic step-down converter will serve as a basis for the design equations for the RC5040. Referring to Figure 3, the basic operation begins by closing the switch S1. When S1 is closed, the input voltage VIN is impressed across inductor L1. The current flowing in this inductor is given by the following equation:
( V IN - V OUT )T ON I L = ---------------------------------------------L1
In order to obtain a more accurate approximation for VOUT, we must also include the forward voltage VD across diode D1 and the switching loss, Vsw. After taking into account these factors, the new relationship becomes:
T ON V OUT = ( V IN + V D - V SW ) ---------- - V D TS
Overview
The RC5040 is a programmable synchronous DC-DC controller IC. When designed around the appropriate external components, the RC5040 can be configured to deliver more than 14.5A of output current. During heavy loading conditions, the RC5040 functions as a current-mode PWM stepdown regulator. Under light loads, the regulator functions in the PFM (pulse frequency modulation), or pulse skipping mode. The controller will sense the load level and switch between the two operating modes automatically, thus optimizing its efficiency under all loading conditions.
where TON is the duty cycle (the time when S1 is closed). When S1 opens, the diode D1 will conduct the inductor current and the output current will be delivered to the load according to the equation:
8
PRODUCT SPECIFICATION
RC5040
+5V OSCILLATOR VCCQP D HIDRV B VO C LODRV GNDP
65-5040-12
A
CEXT
pin that controls the external power MOSFET. The digital section was designed utilizing high speed Schottky transistor logic, thus allowing the RC5040 to operate at clock speeds as high as 1MHz.
High Current Output Drivers
The RC5040 contains two identical high current output drivers which utilize high speed bipolar transistors arranged in a push-pull configuration. Each driver is capable of delivering 1A of current in less than 100ns. Each driver's power and ground are separated from the overall chip power and ground for additional switching noise immunity. The HIDRV driver has a power supply, VCCQP, which is boot-strapped from a flying capacitor as illustrated in Figure 2. Using this configuration, C12 is alternately charged from VCC via the Schottky diode DS2 and then boosted up when the FET is turned on. This scheme provides a VCCQP voltage equal to 2*VCC - VDS(DS2), or approximately 9.5V with VCC = 5V. This voltage is sufficient to provide the 9V gate drive to the external MOSFET required in order to achieve a low RDS(ON). Since the low side synchronous FET is referenced to ground (refer to Figure 4), there is no need to boost the gate drive voltage and its VCCP power pin can be tied to VCC. See Typical Operating Characteristics for typical full load VCCQP waveform.
PWM/PFM Control E
A B C D E
CEXT HIDRV ILOAD
Figure 4. Typical Switching Waveforms
Main Control Loop
Refer to the Block Diagram on page 1. The control loop of the regulator contains two main sections; the analog control block and the digital control block. The analog block consists of signal conditioning amplifiers feeding into a set of comparators which provide the inputs to the digital block. The signal conditioning section accepts inputs from the IFB (current feedback) and VFB (voltage feedback) pins and sets up two controlling signal paths. The voltage control path amplifies the VFB signal and presents the output to one of the summing amplifier inputs. The current control path takes the difference between the IFB and VFB pins and presents the resulting signal to another input of the summing amplifier. These two signals are then summed together with the slope compensation input from the oscillator. This output is then presented to a comparator, which provides the main PWM control signal to the digital control block. The additional comparators in the analog control section set the thresholds of where the RC5040 enters its pulse skipping mode during light loads as well as the point at which the maximum current comparator disables the output drive signals to the external power MOSFETs. The digital control block is designed to take the comparator inputs along with the main clock signal from the oscillator and provide the appropriate pulses to the HIDRV output
Internal Voltage Reference
The reference included in the RC5040 is a 1.24V precision band-gap voltage reference. The internal resistors are precisely trimmed to provide a near zero temperature coefficient (TC). Added to the reference input is the resulting output from an integrated 4-bit DAC. The DAC is provided in accordance with the Pentium Pro specification guideline, which requires the DC-DC converter output to be directly programmable via a 4-bit voltage identification (VID) code. This code will scale the reference voltage from 2.0V (no CPU) to 3.5V in 100mV increments. For guaranteed stable operation under all loading conditions, a 10KW pull-up resistor and 0.1mF of decoupling capacitance should be connected to the VREF pin.
Power Good
The RC5040 Power Good function is designed in accordance with the Pentium Pro DC-DC converter specification and provides a constant voltage monitor on the VFB pin. The circuit compares the VFB signal to the VREF voltage and outputs an active-low interrupt signal to the CPU should the power supply voltage exceed 7% of its nominal setpoint. The Power Good flag provides no other control function to the RC5040.
9
RC5040
PRODUCT SPECIFICATION
Output Enable (OUTEN)
The DC-DC converter accepts an open collector signal for controlling the output voltage. A logic low on the ENABLE pin disables the output voltage. When disabled, the PWRGD output is in the low state. This feature is available for the RC5040 only.
In general, a lower operating frequency will increase the peak ripple current flowing in the output inductor, and thus require the use of a larger inductor value. Operation at lower frequencies also increases the amount of energy storage that must be provided by the bulk output capacitors during load transients due to the slower loop response of the controller. As the operating frequency is increased, the user should note that the efficiency losses due to switching are relatively fixed per switching cycle. Therefore, as the switching frequency is increased, so is the contribution toward efficiency due to switching losses. Careful analysis of the RC5040 DC-DC controller has resulted in an optimal operating frequency of 650KHz, which allows the use of smaller inductive and capacitive components while maximizing peak efficiency under all operating conditions.
Upgrade Present (UP#)
Intel's specifications state that the DC-DC converter must accept an open collector signal, used to indicate the presence of an upgrade processor. The typical state is high (standard CPU). When in the low or ground state (OverDrive processor present), the output voltage must be disabled unless the converter can supply the OverDrive processor's specifications. When disabled, the PWRGD output must be in the low state. Since the RC5040 can supply the OverDrive processor specifications, the UP# signal is not required.
Over-Voltage Protection
The RC5040 provides a constant monitor of the output voltage for protection against overvoltage conditions. If the voltage at the VFB pin exceeds 20% of the selected program voltage, an overvoltage condition will be assumed, and the RC5040 will disable the output drive signal to the MOSFET(s).
Design Considerations and Component Selection
MOSFET Selection
This application requires N-channel Logic Level Enhancement Mode Field Effect Transistors. Desired characteristics are as follows: * Low Static Drain-Source On-Resistance, RDS(on) < 37 mW (lower is better) * Low gate drive voltage, VGS < 4V * Power package with low thermal resistance * Drain current rating of 20A minimum * Drain-Source voltage > 15V The on-resistance (RDS(ON)) is the primary parameter for MOSFET selection. The on-resistance determines the power dissipation of the MOSFET and therefore significantly affects the efficiency of the DC-DC Converter. Table 5 presents a list of suitable MOSFETs for this application.
Short Circuit Protection
A current sense methodology is implemented to disable the output drive signal to the MOSFET(s) when an over-current condition is detected. The voltage drop created by the output current flowing across a sense resistor is presented to an internal comparator. When voltage developed across the sense resistor exceeds the comparator threshold voltage, the RC5040 will disable the output drive signal to the MOSFET(s). The DC-DC converter returns to normal operation after the fault has been removed, for either an overvoltage or a short circuit condition.
Oscillator
The RC5040 oscillator section is implemented using a fixed current capacitor charging configuration. An external capacitor (CEXT) is used to preset the oscillator frequency between 200KHz and 1MHz. This scheme allows maximum flexibility in setting the switching frequency as well as choosing external components.
10
PRODUCT SPECIFICATION
RC5040
Table 5. MOSFET Selection Table
RDS,ON(mW) Manufacturer & Model # Fuji 2SK1388 Siliconix SI4410DY National Semiconductor NDP706AL NDP706AEL National Semiconductor NDP603AL National Semiconductor NDP606AL Motorola MTB75N03HDL Int. Rectifier IRLZ44 Int. Rectifier IRL3103S VGS = 4.5V, ID = 10A VGS = 5V, ID = 24A VGS = 5V, ID = 37.5A VGS = 5V, ID = 31A VGS = 4.5V, ID = 28A VGS = 4V, ID = 17.5A VGS = 4.5V, ID = 5A VGS = 5V, ID = 40A Conditions1 TJ = 25C TJ = 125C TJ = 25C TJ = 125C TJ = 25C TJ = 125C TJ = 25C TJ = 125C TJ = 25C TJ = 125C TJ = 25C TJ = 125C TJ = 25C TJ = 125C TJ = 25C TJ = 125C Typ. 25 37 16.5 28 13 20 31 42 22 33 6 9.3 -- -- -- Max. 37 -- 20 34 15 24 40 54 25 40 9 14 28 46 19 31 TO-220 TO-263 (D2 PAK) TO-220 TO-220 TO-220 FJA = 62.5 FJC = 2.5 FJA = 62.5 FJC = 1.5 FJA = 62.5 FJC = 1.0 FJA = 62.5 FJC = 1.0 FJA = 62.5 FJC = 1.0 SO-8 (SMD) TO-220 FJA = 50 FJA = 62.5 FJC =1.5 Package TO-220 Thermal Resistance FJA = 75
Note: RDS(ON) values at TJ = 125C for most devices were extrapolated from the typical operating curves supplied by the manufacturers and are approximations only. Only National Semiconductor offers maximum values at TJ = 125C.
Two MOSFETs in Parallel
We recommend that two MOSFETs be used in parallel instead of one single MOSFET. Significant advantages are realized using two MOSFETs in parallel: * Significant reduction of power dissipation. Maximum current of 14A with one MOSFET: PMOSFET = (I2 RDS(ON))(Duty Cycle) = (14)2(0.050*)(3.3+0.4)/(5+0.4-0.35) = 7.2 W With two MOSFETs in parallel: PMOSFET = (I2 RDS(ON))(Duty Cycle) = (14/ 2)2(0.037*)(3.3+0.4)/(5+0.4-0.35) = 1.3W/FET
* *Note: RDS(on) increases with temperature. Assume RDS(on)=25mW at 25C. RDS(on) can easily increase to 50mW at high temperature when using a single MOSFET. When using two MOSFETs in parallel, the temperature effects should not cause the RDS(on) to rise above the listed maximum value of 37mW.
* Higher current capability. With thermal management under control, this on-board DC-DC converter is able to deliver load currents up to 14.5A with no problem at all.
MOSFET Gate Bias
Figure 5 employs a charge pump to provide gate bias. Capacitor CP is the charge pump deployed to boost the voltage of the RC5040 output driver. When the MOSFET switches off, the source of the MOSFET is at -0.6V. VCCQP is charged through the Schottky diode to 4.5V. Thus, the capacitor CP is charged to 5V. When the MOSFET turns on, the source of the MOSFET voltage is equal to 5V. The capacitor voltage follows, and hence provides a voltage at VCCQP equal to 10V. The Schottky is required to provide the charge path when the MOSFET is off. The Schottky reverses bias when the VCCQP goes to 10V. The charge pump capacitor, CP, needs to be a high Q and high frequency capacitor. A 1mF ceramic capacitor is recommended here.
* Less heat sink required. With power dissipation down to around one watt and with MOSFETs mounted flat on the motherboard, there will be considerably less heat sink required. The junction-to-case thermal resistance for the MOSFET package (TO-220) is typically at 2C/W and the motherboard serves as an excellent heat sink.
11
RC5040
PRODUCT SPECIFICATION
.
+5V DS2
VCCQP M1 HIDRV CP PWM/PFM Control LODRV GNDP
65-5040-13
L1
RS VO
DS1
CB
0.1 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 1.5 2 2.5 3 3.5 4 5 6 VGS
R(DS)Fuji R(DS)Fuji R(DS)706A R(DS)-706AEL
RDS(ON) Ohms
7
8
9
10 11
Figure 5. Charge Pump Configuration
Figure 6. R(DS) vs. VGS for Selected MOSFETs
Converter Efficiency
Losses due to parasitic resistance in the switches, coil, and sense resistor dominate at high load-current level. The major loss mechanisms under heavy loads, in usual order of importance, are: * * * * * * * * MOSFET I2R Losses Inductor Coil Losses Sense Resistor Losses gate-charge losses diode-conduction losses transition losses Input Capacitor losses losses due to the operating supply current of the IC.
Efficiency of the converter under heavy loads can be calculated as follows:
P OUT I OUT V OUT Efficiency = ------------- = ------------------------------------------------------- , I OUT V OUT + P LOSS p IN
where P LOSS = PD MOSFET + PD INDUCTOR + PD RSENSE + PD GATE + PD DIODE + PD TRAN + PD CAP + PD IC
Design Equations: (1) PD MOSFET = I OUT R DS ( ON ) DutyCycle
OUT D where DutyCycle = ----------------------------------------2
+V V V IN + V D - V SW
(2) PD INDUCTOR = I OUT R INDUCTOR (3) PD RSENSE = I OUT R SENSE (4) PD GATE = q GATE f 5V , where qGATE is the gate charge and f is the switching frequency (5) PD DIODE = V f I OUT ( 1 - Dutycycle ) V IN C RSS I LOAD f (6) PD TRAN = ------------------------------------------------------------ , where CRSS is the reverse transfer capacitance of the high-side MOSFET. I DRIVE
2 2
2
12
PRODUCT SPECIFICATION
RC5040
(7) PD CAP = I RMS ESR (8) PD IC = V CC I CC Example: 3.3 + 0.5 DutyCycle = ----------------------------- = 0.73 5 + 0.5 - 0.3 PD MOSFET = 10 0.030 0.73 = 2.19W PD INDUCTOR = 10 0.010 = 1W PD RSENSE = 10 0.0065 = 0.65W PD GATE = CV f 5V = 1.75nf ( 9 - 1 )V 650Khz 5V = 0.045W PD DIODE = 0.5 10 ( 1 - 0.73 ) = 1.35W 5 400pf 10 650khz PD TRAN = --------------------------------------------------------------- ~ 0.010W 0.7A PD CAP = ( 7.5 - 2.5 ) 0.015 = 0.37W PD IC = 0.2W PD LOSS = 2.19W + 1.0W + 0.65W + 0.045W + 1.35W + 0.010W + 0.37W + 0.2W = 5.815W 3.3 10 \ Efficiency = -------------------------------------- ~ 85% 3.3 10 + 5.815
2 2 2 2 2
2
Selecting the Inductor
The inductor is one of the most critical components to be selected in the DC-DC converter application.. The critical parameters are inductance (L), maximum DC current (Io) and the coil resistance (R1). The inductor core material is a crucial factor in determining the amount of current the inductor will be able to withstand. As with all engineering designs, tradeoffs exist between various types of core materials. In general, Ferrites are popular due to their low cost, low EMI properties and high frequency (>500KHz) characteristics. Molypermalloy powder (MPP) materials exhibit good saturation characteristics, low EMI and low hysteresis losses; however, they tend to be expensive and more effectively utilized at operating frequencies below 400KHz. Another critical parameter is the DC winding resistance of the inductor. This value should typically be reduced as much as possible, as the power loss in the DC resistance will degrade the efficiency of the converter by the relationship: PLOSS = IO2 x R1. The value of the inductor is a function of the oscillator duty cycle (TON) and the maximum inductor current (IPK). IPK can be calculated from the relationship:
V IN - V SW - V D I PK = I MIN + ae ---------------------------------------- o T ON e o L
Then the inductor value can be calculated using the relationship:
V IN - V SW - V O L = ae ---------------------------------------- o T ON e I PK - I MIN o
Where VSW (RDSON x IO) is the drain-to-source voltage of M1 when it is switched on.
Implementing Short Circuit Protection
Intel currently requires all power supply manufacturers to provide continuous protection against short circuit conditions that may damage the CPU. To address this requirement, Fairchild Semiconductor has implemented a current sense methodology to disable the output drive signal to the MOSFET(s) when an over current condition is detected. The voltage drop created by the output current flowing across a sense resistor is presented to one terminal of an internal comparator with hysterisis. The other comparator terminal has the threshold voltage, nominally of 120mV. Table 6 states the limits for the comparator threshold of the Switching Regulator.
Where TON is the maximum duty cycle and VD is the forward voltage of diode DS1.
13
RC5040
PRODUCT SPECIFICATION
Table 6. RC5040 Short Circuit Comparator Threshold Voltage
Short Circuit Comparator Vthreshold (mV) Typical Minimum Maximum 120 100 140
The calculation of this ripple current is as follows:
( V IN - V SW - V OUT ) ( V OUT + V D ) ( I pk - I min ) --------------------------- = ---------------------------------------------------- ----------------------------------------------T L ( V IN - V SW + V D ) 2
When designing the external current sense circuitry, the designer must pay careful attention to the output limitations during normal operation and during a fault condition. If the short circuit protection threshold current is set too low, the DC-DC converter may not be able to continuously deliver the maximum CPU load current. If the threshold level is too high, the output driver may not be disabled at a safe limit and the resulting power dissipation within the MOSFET(s) may rise to destructive levels. The design equation used to set the short circuit threshold limit is as follows:
R SENSE V th = ------- , where: I SC = Output short circuit current I SC
where: * Vin= input voltage to Converter * VSW=voltage across Switcher (MOSFET) =ILOAD x RDS(ON) * VD= Forward Voltage of the Schottky diode * T = the switching period of the converter = 1/fS, where fS = switching frequency. For an input voltage of 5V, an output voltage of 3.3V, an inductor value of 1.3mH and a switching frequency of 650KHz (using CEXT = 39pF), the inductor current can be calculated as follows:
( I pk - I min ) ( 5.0 - 14.5 0.037 - 3.3 ) --------------------------- = ------------------------------------------------------------- -6 2 1.3 10 ( 3.3 + 0.5 ) 1 ------------------------------------------------------------- ----------------------- = 1.048A ( 5.0 - 14.5 0.037 + 0.5 ) 650 10 3
( I PK - I min ) I SC I inductor = I Load, max + ---------------------------2
Therefore, the peak current, IPK, through the inductor for a 14.5A load is found to be:
( I PK - I min ) I SC I inductor = I Load, max + ---------------------------- = 14.5 + 1 = 15.5A 2
Where Ipk and Imin are peak ripple current and Iload, max = maximum output load current The designer must also take into account the current (IPK -Imin), or the ripple current flowing through the inductor under normal operation. Figure 7 illustrates the inductor current waveform for the RC5040 DC-DC converter at maximum load.
Ipk
As a result, the short circuit detection threshold must be at least 15.5A. The next step is to determine the value of the sense resistor. Including sense resistor tolerance, the sense resistor value can be approximated as follows
V th,min V th,min R SENSE = --------------- ( 1 - TF ) = ---------------------------------- ( 1 - TF ) I SC 1.0 + I Load,max
I
(Ipk-imin)/2 ILOAD TOFF T=1/f s t
Where TF = Tolerance Factor for the sense resistor. There are several different type of sense resistors. Table 7 describes tolerance, size, power capability, temperature coefficient and cost of various type of sense resistors.
Imin TON
Figure 7. Typical DC-DC Converter Inductor Current Waveform
14
PRODUCT SPECIFICATION
RC5040
Table 7. Comparison of Sense Resistors1
Discrete Iron Alloy resistor (IRC) Discrete Metal Strip surface mount resistor (Dale) Discrete MnCu Alloy wire resistor 10% 0.200" x 0.04" x 0.160" 1 watt Discrete CuNi Alloy wire resistor (Copel) 10% 0.200" x 0.04" x 0.100" 1 watt
Description Tolerance Factor (TF) Size (L x W x H)
Motherboard Trace Resistor 29% 2" x 0.2" x 0.001" (1 oz Cu trace)
5% 1% (1% available) 0.45" x 0.065" x 0.25" x 0.125" x 0.200" 0.025" 1 watt (3W and 5W available) +30 ppm $0.31 1 watt
Power capability >50A/in
Temperature Coefficient Cost @10,000 piece
+4,000 ppm Low included in motherboard
75 ppm $0.47
30 ppm $0.09
20 ppm $0.09
Notes: 1. Refer to Appendix A for Directory of component suppliers
Based on the Tolerance in the above table, For Embedded PC Trace Resistor and for Iload,max=14.5A:
V th,min R SENSE = ---------------------------------------- ( 1 - TF ) 1.0A + I Load, max 100mV = --------------------------------- ( 1 - 29% ) = 4.6mW 1.0A + 14.5A
Table 8. Rsense for various load currents
ILoad,max (A) 10.00 11.20 12.40 13.90 14.00 14.50 RSENSE PC Trace Resistor (mW) 6.5 5.8 5.3 4.8 4.7 4.6 RSENSE Discrete Resistor (mW) 8.6 7.8 7.1 6.4 6.3 6.1
For discrete resistor and Iload, max = 14.5A:
V th,min R SENSE = ---------------------------------------- ( 1 - TF ) 1.0A + I Load, max 100mV = --------------------------------- ( 1 - 5% ) = 6.1mW 1.0A + 14.5A
RC5040 Short Circuit Current Characteristics
The RC5040 has a short circuit current characteristic that includes a hysteresis function that prevents the DC-DC converter from oscillating in the event of a short circuit. A typical V-I characteristic of the DC-DC converter output with a sense resistor of 6 mW is presented in the Typical Operating Characteristics section, page 5. The converter performs with a normal load regulation characteristic until the voltage across the resistor reaches the internal short circuit threshold of 120mV. At this point, the internal comparator trips and sends a signal to the controller to turn off the gate drive to the power MOSFET. This causes a drastic reduction in the output voltage as the load regulation collapses into the short circuit mode of control. The output voltage will not return to the normal load characteristic until the output short circuit current is reduced to within the safe range for the DC-DC converter.
For user convenience, Table 8 lists recommended Value for sense resistor for various load current using Embedded PC Trace Resistor or Discrete Resistor.
15
RC5040
PRODUCT SPECIFICATION
Schottky Diode Selection
The application circuit diagrams of Figures 1 and 2 show two Schottky diodes, DS1 and DS2. In synchronous mode, DS1 is used in parallel with M3 to prevent the lossy diode in the FET from turning on. DS2 serves a dual purpose. As configured, it allows the VCCQP supply pin of the RC5040 to be bootstrapped up to 9V using capacitor C12. When the lower MOSFET M3 is turned on, one side of capacitor C12 is connected to ground while the other side of the capacitor is being charged up to voltage VIN - VD through DS2. The voltage that is then applied to the gate of the MOSFET is VCCQP - VSAT, or typically around 9V. A vital selection criteria for DS1 and DS2 is that they exhibit a very low forward voltage drop, as this parameter can directly affect the regulator efficiency. In non-synchronous mode, DS1 is used as a flyback diode to provide a constant current path for the inductor when M1 is turned off. Table 9 lists several suitable Schottky diodes. Note that the MBR2015CTL has a very low forward voltage drop. This diode is most ideal for application where output voltage is required to be less than 2.8V.
supply ESR data. A useful estimate of the ESR can be obtained using the following equation:
DF ESR = -----------2pfC
Where: * DF is the dissipation factor of the capacitor * f is the operating frequency * C is the capacitance in farads With this in mind, correct calculation of the output capacitance is crucial to the performance of the DC-DC converter. The output capacitor determines the overall loop stability, output voltage ripple and load transient response. The calculation is as follows:
I O DT C ( mF ) = ------------------------------------DV - I O ESR
Where DV is the maximum voltage deviation due load transient DT is reaction time of the power source (Loop response time of the RC5040) and it is approximately 8ms IO is the output load current For IO = 10A, and DV = 75mV, the bulk capacitor required can be approximated as follows:
I O DT 10A 8ms C ( mF ) = ------------------------------------- = -------------------------------------------------- = 3200mF DV - I O ESR 75mV - 10A 5mW
Table 9. Schottky Diode Selection Table
Manufacturer Model # Philips PBYR1035 Motorola MBR2035CT Motorola MBR1545CT Conditions IF = 20A; Tj = 25C IF = 20A; Tj = 125C IF = 20A; Tj = 25C IF = 20A; Tj = 125C IF = 15A; Tj = 25C IF = 15A; Tj = 125C Forward Voltage VF < 0.84V < 0.72V < 0.84V < 0.72V < 0.84V < 0.72V < 0.58V < 0.48V
Motorola IF = 20A; Tj = 25C MBR2015CTL IF = 20A; Tj = 150C
Input filter
We recommend that the design include an input inductor between the system +5V supply and the DC-DC converter input described below. This inductor will serve to isolate the +5V supply from noise occurring in the switching portion of the DC-DC converter and to also limit the inrush current into the input capacitors on power up. A value of around 2.5mH is recommended.
5V 2.5H Vin
Output Filter Capacitors
Optimal ripple performance and transient response are functions of the filter capacitors used. Since the 5V supply of a PC motherboard may be located several inches away from the DC-DC converter, input capacitance can play an important role in the load transient response of the RC5040. The higher the input capacitance, the more charge storage is available for improving the current transfer through the FET. Low "ESR" capacitors are best suited for this type of application and can influence the converter's efficiency if not chosen carefully. The input capacitor should be placed as close to the drain of the FET as possible to reduce the effect of ringing caused by long trace lengths. The ESR rating of a capacitor is a difficult number to quantify. ESR or Equivalent Series Resistance, is defined as the resonant impedance of the capacitor. Since the capacitor is actually a complex impedance device having resistance, inductance and capacitance, it is quite natural for this device to have a resonant frequency. As a rule, the lower the ESR, the better suited the capacitor is for use in switching power supply applications. Many capacitor manufacturers do not
0.1F
1000F, 10V Electrolytic
65-5040-16
Figure 8. Input Filter
16
PRODUCT SPECIFICATION
RC5040
PCB Layout Guidelines and Considerations
PCB Layout Guidelines
1. Placement of the MOSFETs relative to the RC5040 is critical. The MOSFETs (M1 & M2), should be placed such that the trace length of the HIDRV pin from the RC5040 to the FET gates is minimized. A long lead length on this pin will cause high amounts of ringing due to the inductance of the trace combined with the large gate capacitance of the FET. This noise will radiate all over the board, and because it is switching at such a high voltage and frequency, it will be very difficult to suppress. Figure 9 below depicts an example of good placement for the MOSFETs in relation to the RC5040 and also an example of problematic placement for the MOSFETs. In general, all of the noisy switching lines should be kept away from the quiet analog section of the RC5040. That is to say, traces that connect to pins 12 and 13 (HIDRV and VCCQP) should be kept far away from the traces that connect to pins 1 through 5, and pin 16. 2. Place decoupling capacitors (.1mF) as close to the RC5040 pins as possible. Extra lead length on these will negate their ability to suppress noise.
3.
Each VCC and GND pin should have its own via down to the appropriate plane underneath. This will help give isolation between pins. Surround the CEXT timing capacitor with a ground trace as much as possible. Also be sure to keep a ground or power plane underneath the capacitor for further noise isolation. This will help to shield the oscillator pin 1 from the noise on the PCB. Place this capacitor as close to the RC5040 pin 1 as possible. Place MOSFETs, inductor and Schottky as close together as possible for the same reasons as #1 above. Place the input bulk capacitors as close to the drains of MOSFETs as possible. In addition, placement of a 0.1mF decoupling cap right on the drain of each MOSFET will help to suppress some of the high frequency switching noise on the input of the DC-DC converter. The traces that run from the RC5040 IFB (pin 4) and VFB (pin 5) pins should be run together next to each other and be Kelvin connected to the sense resistor. Running these lines together will help in rejecting some of the common noise that is presented to the RC5040 feedback input. Try as much as possible to run the noisy switching signals (HIDRV & VCCQP) on one layer; and use the inner layers for only power and ground. If the top layer is being used to route all of the noisy switching signals, use the bottom layer to route the analog sensing signals VFB and IFB.
4.
5.
6.
Correct layout
11 12 13 14 15 16 17 18 19 20 RC5040 10 9 8 7 6 5 4 3 2 1
Poor layout
11 12 13 14 15 16 17 18 19 20 RC5040 10 9 8 7 6 5 4 3 2 1
= "Quiet" Pins
65-5040-17
Figure 9. MOSFET Layout Guidelines
17
RC5040
PRODUCT SPECIFICATION
Example of a Layout on a PC Motherboard and Gerber File
A reference design for motherboard implementation of the RC5040 along with Layout Gerber File and Silk Screen are presented below. The actual Gerber File can be obtained from a Fairchild Semiconductor local Sales Rep Office or from Fairchild Semiconductor Marketing Department at 415-966-7819.
Semiconductor local Sales Rep Office or Fairchild Semiconductor Marketing department at 415-966-7819 for an evaluation board.
Additional Application Information
A comprehensive Application Note providing implementation guidelines for the RC5040 and RC5042 DC-DC Converters for Pentium(R) Pro processors (AP-42) is available from your local Fairchild Semiconductor Sales Rep or from Fairchild Semiconductor Marketing at 415-966-7819. Most application notes and data sheets can also be obtained by calling Fairchild Semiconductor's RAYFAX line at 415-988-2123.
RC5040 Evaluation Board
Fairchild Semiconductor provides an evaluation board for the purpose of verifying the system level performance of the RC5040. The evaluation board serves as a guide as to what can be expected in performance with the supplied external components and PCB layout. Please call your Fairchild
18
PRODUCT SPECIFICATION
RC5040
Mechanical Dimensions - 20 Lead SOIC
Symbol A A1 B C D E e H h L N a ccc Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
.093 .104 .004 .012 .013 .020 .009 .013 .496 .512 .291 .299 .050 BSC .394 .010 .016 20 0 -- 8 .004 .419 .029 .050
2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 12.60 13.00 7.40 7.60 1.27 BSC 10.00 0.25 0.40 20 0 -- 8 0.10 10.65 0.75 1.27
3 6
20
11
E
H
1
10
D A e B A1 SEATING PLANE -C- LEAD COPLANARITY ccc C a
h x 45 C
L
19
RC5040
PRODUCT SPECIFICATION
Ordering Information
Product Number RC5040M Package 20 pin SOIC
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS30005040 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC5041
Programmable DC-DC Converter for Pentium(R) P55C, K6TM, and 6x86MXTM (M2) Processors
Features
* Programmable output from 2.1V to 3.5V using integrated 4-bit DAC * 87% efficiency * Oscillator frequency adjustable from 200KHz to 1MHz * On-chip Power Good function * Excellent transient response * Over-Voltage Protection * Short Circuit Protection * Power Good Function * Precision trimmed low TC voltage reference * 16 pin SOIC package * Meets Intel Pentium VRM specifications using minimum number of external components
Description
The RC5041 is a non-synchronous DC-DC controller IC which provides an accurate, programmable output for Pentium CPU applications. Using an integrated 4-bit DAC to accept a voltage identification (VID), the RC5041 can generate precise output voltages between 2.1V and 3.5V in 100mV increments. Output load currents in excess of 10A can be delivered using minimal external circuitry. The RC5041 is designed to operate in a standard PWM control mode under heavy load conditions and in PFM control mode while supplying light loads for optimal efficiency. An onboard precision low TC voltage reference eliminates the requirement for external components in order to achieve tight voltage regulation. The Pentium CPU is continuously protected by an integrated Power Good function, which sends an active-low interrupt signal to the CPU in the event that the output voltage is out of tolerance. The internal oscillator can be programmed to operate over a range of 200KHz to 1MHz to allow flexibility in choosing external components.
Preliminary Information
Applications
* Programmable power supply for P54C, P55C, K6, and M2 based CPU motherboards * VRM module for Pentium and equivalent CPU's * Programmable power supply for high current microprocessors
Block Diagram
RC5041
OSCILLATOR
- +
+12V
+5V VIN
- +
- - + +
VO DIGITAL CONTROL
VREF
4-BIT DAC
1.24V REFERENCE
POWER GOOD
PWRGD
VID0 VID1 VID2 VID3
65-5041-01
Pentium is a registered trademark of Intel Corporation. K6 is a trademark of AMD Corporation. 6x86MX is a trademark of Cyrix Corporation.
Rev. 0.9.6
PRELIMINARY INFORMATION describes products that are not in full production at the time of printing. Specifications are based on design goals and limited characterization. They may change without notice. Contact Fairchild Semiconductor for current information.
RC5041
PRODUCT SPECIFICATION
Pin Assignments
CEXT PWRGD IFB VFB VCCA VCCD GNDP HIDRV
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
65-5041-02
VID0 VID1 VID2 VID3 VREF GNDA GNDD VCCQP
Pin Definitions
Preliminary Information
Pin Number Pin Name 1 CEXT
Pin Function Description Oscillator capacitor connection. Connecting an external capacitor to this pin sets the internal oscillator frequency from 200 KHz to 1 MHz. Layout of this pin is critical to system performance. See Application Information for details. Power Good output flag. Open collector output will be at logic HIGH under normal operation. Logic LOW indicates output voltage is not within 10% of nominal. High side current feedback. Pins short 4 and 5 are used as the inputs for the current feedback control loop and as the short circuit current sense points. Layout of these traces is critical to system performance. See Application Information for details. Voltage feedback. Pin 5 is used as the input for the voltage feedback control loop and as the low side current feedback input. Layout of this trace is critical to system performance. See Application Information for details. Analog VCC. Connect to system 5V supply and decouple to ground with 0.1mF ceramic capacitor. Digital VCC. Connect to system 5V supply and decouple to ground with 4.7mF tantalum capacitor. Power ground. Return pin for high currents flowing in pins 8 and 9 (HIDRV and VCCQP). Connect to low impedance ground. See Application Information for details. FET driver output. Connect this pin to the gate of the N-channel MOSFETs M1 and M2 in Figures 1 and 2. The trace from this pin to the MOSFET gates should be kept as short as possible (less than 0.5"). See Application Information for details. Power VCC for FET Driver. VCCQP must be connected to a voltage of at least VCCA + VGS,ON (M1). See Application Information for details. Digital ground. Return path for digital logic. This pin should be connected to system ground so that ground loops are avoided. See Application Information for details. Analog ground. Return path for low power analog circuitry. Connect to system ground so that ground loops are avoided. See Application Information for details. Reference voltage test point. This pin provides access to the DAC output and should be decoupled to ground using a 0.1mF capacitor. No load should be connected to this pin. Voltage identification (VID) code inputs. These open collector/TTL compatible inputs will program the output voltage over the ranges specified in Table 1.
2 3
PWRGD IFB
4
VFB
5 6 7 8
VCCA VCCD GNDP HIDRV
9 10 11 12
VCCQP GNDD GNDA VREF
13-16
VID3- VID0
2
PRODUCT SPECIFICATION
RC5041
Table 1. Voltage Identification Codes for P55/K6
Data Bits VID3 1 1 1 1 1 1 1 1 VID2 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 VCCP (VDC) No CPU 2.1 2.2 2.3 2.4 2.5 2.6 2.7 VID3 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 Data Bits VID2 VID1 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 VCCP (VDC) 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5
Preliminary Information
Absolute Maximum Ratings1
Control Supply Voltages, VCCA and VCCD FET Supply Voltage, VCCQP Voltage Identification Code Inputs, VID3-VID0 Junction Temperature, TJ Storage Temperature, TS Lead Soldering Temperature, 10 seconds 7V 13V 7V 150C -65 to 150C 300C
Notes: 1. Functional operation under any of these conditions is not implied. Permanent damage may occur if the device is subjected to conditions outside these ratings.
Operating Conditions
Parameter Control Supply Voltages, VCCA and VCCD Driver Supply Voltage, VCCQP VID Code Input Voltage, Logic HIGH VID Code Input Voltage, Logic LOW PWRGD HIGH Threshold PWRGD LOW Threshold Ambient Temperature, TA 0 7 10 70 Min. 4.75 9 2 0.8 Typ. 5 10 Max. 5.25 12 Units V V V V %VREF %VREF C
Electrical Specifications
(VCCA = 5V, VOUT = 2.8V, fosc = 300 KHz, and TA = +25C using circuit in Figure 1, unless otherwise noted) The * denotes specifications which apply over the full operating temperature range. Parameter Output Voltage Output Current Initial Voltage Setpoint Output Temperature Drift Load Regulation Line Regulation Output Ripple/Noise, pk-pk ILOAD = 0.8A TA = 0 to 60C ILOAD = 0.8A to 10A VIN = 4.75V to 5.25V 20MHz BW, ILOAD = 10A * * * Conditions See Table 1 * 13 20 +10 -20 2 20 Min. Typ. Max. 3.5 Units V A mV mV mV mV mV 3
RC5041
PRODUCT SPECIFICATION
Electrical Specifications (continued) (VCCA = 5V, VOUT = 2.8V, fosc = 300 KHz, and TA = +25C using circuit in Figure 1, unless otherwise noted) The * denotes specifications which apply over the full operating temperature range.
Parameter Output Voltage Regulation Steady State1 Transient2 Efficiency Output Driver Rise and Fall Time Turn-on Response Time Oscillator Range Oscillator Frequency Maximum Duty Cycle Conditions VOUT = 2.8V, ILOAD = 0 to 10A ILOAD = 0.8 to 9.5A, 30A/mS ILOAD = 10A, VOUT = 2.8V See Figure 2 ILOAD = 0A to 10A 80 CEXT = 100 pF 90 300 300 95 * * * Min. 2.74 2.70 80 Typ. 2.80 2.80 85 50 10 1000 Max. 2.90 2.90 Units V V % ns ms KHz KHz %
Preliminary Information
Notes: 1. Steady State Voltage Regulation includes Initial Voltage Setpoint, DC load regulation, outut ripple/noise and temperature drift. 2. These specifications assume a minimum of 20, 1mF ceramic capacitors are placed directly next to the CPU in order to provide adequate high-speed decoupling. For motherboard applications, the PCB layout must exhibit no more than 0.5mW parasitic resistance and 1nH parasitic inductance between the converter output and the CPU.
Test Circuits
L2 VCC 2.5mH C4 0.1mF CIN DS2 C8 0.1mF +12V
C12 1mF 9 10 11 VREF C7 GND 0.1mF 12 13 14 15 16 U1 RC5041 8 7 6 5 4 3 2 1 CEXT 100pF C6 1.0mF
M1 L1 1.0mH RSENSE VO 6mW COUT
DS1
VID3 VID2 VID1 VID0
R1 R2 R3 R4
10K 10K 10K 10K VCC C11 0.1mF R6 10K1/2
VCC
PWRGD
65-5041-03
Figure 1. Standard Test or Application Schematic
4
PRODUCT SPECIFICATION
RC5041
Table 2. Bill of Materials for a 4-Bit Non-Synchronous DC-DC Converter
Item C4 C12 C8 CEXT C6 C11 C7 CIN COUT DS1 DS2 L1 L2 RSENSE R1 R2 R3 R4 R6 M1 U1 Description Ceramic Capacitor, 0.1mF, X7R, SMT0805 Ceramic Capacitor, 1mF, X7R, SMT0805 Ceramic Capacitor, 0.1mF, X7R, SMT0805 Ceramic Capacitor, 100pF, X7R, SMT0805 Ceramic Capacitor, 1mF, X7R, SMT0805 Ceramic Capacitor, 0.1mF, X7R, SMT0805 Capacitor, 0.1mF, X7R, SMT0805 Capacitor, Al-Elect, 1200mF, 10v, 10 x 20 radial Capacitor, Al-Elect, 1500mF, 6.3v, 10 x 20 radial Schottky Diode, MBR2535CT Zener Diode, 1N5817 Output Inductor, 1.0mH, Toroid, 6 turns 17AWG Input Inductor, 2.5mH, Toroid, 10 turns 17AWG Sense Resistor, CuNi Allow Wire, 1W, 6mW, 10% 10KW Resistor, 1/8W, 5%, SMT0805 10KW Resistor, 1/8W, 5%, SMT0805 10KW Resistor, 1/8W, 5%, SMT0805 10KW Resistor, 1/8W, 5%, SMT0805 10KW Resistor, 1/8W, 5%, SMT0805 N-ch Power FET PWM Controller, Fairchild Semiconductor RC5041M See Table 2 See Note 1 See Table 3 See Table 3 Comments
Preliminary Information
Note: 1. The inductor L2 is recommended to isolate the 5V ipower supply from current surges caused by the MOSFET switching. This inductor is not required for the proper operation of the DC-DC converter and can be substituted with a ferrite beads inductor or omitter completely.
Table 3. Part Selection Table
Fairchild Semiconductor DC-DC Converter CIN Sanyo 10MV1200GX 1x 1x RC5041 2x 3x 1x COUT Sanyo 6MV1500GX 2x 2x 4x 6x 2x
K6 CPU 166 MHz 200 MHz 233 MHz 266 MHz 300 MHz+
Output Voltage 2.9V 2.9V 3.2V 3.2V 2.1V
IMAX 6.25A 7.5A 9.5A 13.0A 5.6A
MOSFET IRL3103 IRL3103 IRL3103 IRL2203 IRL3103
5
RC5041
PRODUCT SPECIFICATION
+12V 0.1F
471/2 1F VCCQP tR HIDRV RISE/FALL 10% 7000pF 90% 50% 90% 50% 10% tF
+5V 0.1F
VCCA
HIDRV RC5041
VCCD 4.7F GNDA GNDD GNDP
65-5041-04
Preliminary Information
Figure 2. Output Driver Test Circuit
Application Information
Simple Step-Down Converter
S1 L1 + VIN D1 C1 RL Vout -
65-5041-05
In order to obtain a more accurate approximation for VOUT, we must also include the forward voltage VD across diode D1 and the switching loss, Vsw. After taking into account these factors, the new relationship becomes:
T ON V OUT = ( V IN + V D - V SW ) ---------- - V D TS
Overview
The RC5041 is a programmable DC-DC controller IC. When designed around the appropriate external components, the RC5041 can be configured to deliver more than 14.5A of output current. During heavy loading conditions, the RC5041 functions as a current-mode PWM step-down regulator. Under light loads, the regulator functions in the PFM (pulse frequency modulation), or pulse skipping mode. The controller will sense the load level and switch between the two operating modes automatically, thus optimizing its efficiency under all loading conditions.
+5V
Figure 3. Simple Buck DC-DC Converter
Figure 3 illustrates a step-down DC-DC converter with no feedback control. The derivation of the basic step-down converter will serve as a basis for the design equations for the RC5041. Referring to Figure 3, the basic operation begins by closing the switch S1. When S1 is closed, the input voltage VIN is impressed across inductor L1. The current flowing in this inductor is given by the following equation:
( V IN - V OUT )T ON I L = ---------------------------------------------L1
A
CEXT
OSCILLATOR
VCCQP D HIDRV B VO C E GNDP
Where TON is the duty cycle (the time when S1 is closed). When S1 opens, the diode D1 will conduct the inductor current and the output current will be delivered to the load according to the equation:
V OUT ( T S - T ON ) I L = -----------------------------------------L1
PWM/PFM Control
A B C D
CEXT HIDRV ILOAD
Where TS is the overall switching period, and (TS - TON) is the time during which S1 is open. By solving these two equations, we can arrive at the basic relationship for the output voltage of a step-down converter:
T ON V OUT = V IN ae ----------o e TS o
65-5041-06
E
Figure 4. Typical Switching Waveforms
6
PRODUCT SPECIFICATION
RC5041
Main Control Loop
Refer to the Block Diagram on page 1. The control loop of the regulator contains two main sections, the analog control block and the digital control block. The analog block consists of signal conditioning amplifiers feeding into a set of comparators which provide the inputs to the digital block. The signal conditioning section accepts inputs from the IFB (current feedback) and VFB (voltage feedback) pins and sets up two controlling signal paths. The voltage control path amplifies the VFB signal and presents the output to one of the summing amplifier inputs. The current control path takes the difference between the IFB and VFB pins and presents the resulting signal to another input of the summing amplifier. These two signals are then summed together with the slope compensation input from the oscillator. This output is then presented to a comparator, which provides the main PWM control signal to the digital control block. The additional comparators in the analog control section set the thresholds of where the RC5041 enters its pulse skipping mode during light loads as well as the point at which the maximum current comparator disables the output drive signals to the external power MOSFETs. The digital control block is designed to take the comparator inputs along with the main clock signal from the oscillator and provide the appropriate pulses to the HIDRV output pin that controls the external power MOSFET. The digital section was designed utilizing high speed Schottky transistor logic, thus allowing the RC5041 to operate at clock speeds as high as 1MHz.
Power Good
The RC5041 Power Good function is designed in accordance with the Pentium Pro DC-DC converter specification and provides a constant voltage monitor on the VFB pin. The circuit compares the VFB signal to the VREF voltage and outputs an active-low interrupt signal to the CPU should the power supply voltage exceed 12% of its nominal setpoint. The Power Good flag provides no other control function to the RC5041.
Over-Voltage Protection
The RC5041 provides a constant monitor of the output voltage for protection against overvoltage conditions. If the voltage at the VFB pin exceeds 20% of the selected program voltage, an overvoltage condition will be assumed, and the RC5041 will disable the output drive signal to the MOSFET(s).
Preliminary Information
Short Circuit Protection
A current sense methodology is implemented to disable the output drive signal to the MOSFET(s) when an over-current condition is detected. The voltage drop created by the output current flowing across a sense resistor is presented to an internal comparator. When voltage developed across the sense resistor exceeds the comparator threshold voltage, the RC5041 will disable the output drive signal to the MOSFET(s). The DC-DC converter returns to normal operation after the fault has been removed, for either an overvoltage or a short circuit condition.
High Current Output Drivers
The RC5041 contains one high current output drivers which utilize high speed bipolar transistors arranged in a push-pull configuration. The driver is capable of delivering 1A of current in less than 100ns. The driver's power and ground are separated from the overall chip power and ground for additional switching noise immunity.
Oscillator
The RC5041 oscillator section is implemented using a fixed current capacitor charging configuration. An external capacitor (CEXT) is used to preset the oscillator frequency between 80KHz and 1MHz. This scheme allows maximum flexibility in setting the switching frequency as well as choosing external components. In general, a lower operating frequency will increase the peak ripple current flowing in the output inductor, and thus require the use of a larger inductor value. Operation at lower frequencies also increases the amount of energy storage that must be provided by the bulk output capacitors during load transients due to the slower loop response of the controller. The user should note that the efficiency losses due to switching are relatively fixed per switching cycle. Therefore, as the switching frequency is increased, so is the contribution toward efficiency due to switching losses. Careful analysis of the RC5041 DC-DC controller has resulted in an optimal operating frequency of 300KHz, which allows the use of smaller inductive and capacitive components while maximizing peak efficiency under all operating conditions. 7
Internal Voltage Reference
The reference included in the RC5041 is a 1.24V precision band-gap voltage reference. The internal resistors are precisely trimmed to provide a near zero temperature coefficient (TC). Added to the reference input is the resulting output from an integrated 4-bit DAC. The DAC is provided in accordance with the Pentium Pro specification guideline, which requires the DC-DC converter output to be directly programmable via a 4-bit voltage identification (VID) code. This code will scale the reference voltage from 2.0V (no CPU) to 3.5V in 100mV increments. For guaranteed stable operation under all loading conditions, a 10KW pull-up resistor and 0.1mF of decoupling capacitance should be connected to the VREF pin.
RC5041
PRODUCT SPECIFICATION
Design Considerations and Component Selection
MOSFET Selection
This application requires N-channel Logic Level Enhancement Mode Field Effect Transistors. Desired characteristics are as follows: * Low Static Drain-Source On-Resistance, RDS(on) < 20 mW (lower is better)
* * * *
Low gate drive voltage, VGS < 4V Power package with low thermal resistance Drain current rating of 20A minimum Drain-Source voltage > 15V.
The on-resistance (RDS(ON)) is the primary parameter for MOSFET selection. The on-resistance determines the power dissipation of the MOSFET and therefore significantly affects the efficiency of the DC-DC Converter. Table 3 provides a list of suitable MOSFETs for this application.
Table 3. MOSFET Selection Table
Preliminary Information
RDS,ON(mW) Manufacturer & Model # Megamos MiP30N03A Fuji 2SK1388 Int. Rectifier IRL3803 Int. Rectifier IRL2203 Int. Rectifier IRL3103 NS NDP706A NEC 2SK2941 NEC 2SK2984 NEC mPA1703 Int. Rectifier IRF7413A Int. Rectifier IRF7413 Int. Rectifier IRL3103A Conditions1 VGS = 4.5V, ID = 6A VGS = 4V, ID = 20A VGS = 4.5V, ID = 59A VGS = 4.5V, ID = 50A VGS = 4.5V, ID = 28A VGS = 5.0V, ID = 40A VGS = 4.0V, ID = 18A VGS = 4.0V, ID = 20A VGS = 4.0V, ID = 5A VGS = 4.5V, ID = 3.3A VGS = 4.5V, ID = 3.7A VGS = 4.5V, ID = 28A TJ = 25C TJ = 125C TJ = 25C TJ = 125C TJ = 25C TJ = 125C TJ = 25C TJ = 125C TJ = 25C TJ = 125C TJ = 25C TJ = 125C TJ = 25C TJ = 125C TJ = 25C TJ = 125C TJ = 25C TJ = 125C TJ = 25C TJ = 125C TJ = 25C TJ = 125C TJ = 25C TJ = 125C 8.2 -- 16 -- 13 20 22 -- 10.5 -- 12 -- -- -- -- -- -- -- Typ. 16 -- 25 37 6.1 Max. 25 38 37 56 9 14 10 16 19 29 15 24 33 50 15 23 17 26 20 30 18 27 19 29 D2 PAK SO-8 SO-8 SO-8 TO-220 TO-220 TO-220 TO-220 TO-220 TO-220 TO-220 Package TO-220
Thermal Resistance FJA = 62 FJA = 75 FJA = 62 FJA = 62 FJA = 62 FJA = 62 FJA = 83 FJA = 83 FJA = 125 FJA = 125 FJA = 125 FJA = 40
Note: 1. RDS(ON) values at TJ=125C for most devices were extrapolated from the typical operating curves supplied by the manufacturers and are approximations only. Only National Semiconductor offers maximum values at TJ = 125C.
8
PRODUCT SPECIFICATION
RC5041
Two MOSFETs in Parallel
For high current requirements, we recommend that two MOSFETs be used in parallel instead of one single MOSFET. Significant advantages are realized using two MOSFETs in parallel: * Significant reduction of power dissipation. Maximum current of 14A with one MOSFET: PMOSFET = (I2 RDS(ON))(Duty Cycle) = (14)2(0.050*)(3.3+0.4)/(5+0.4-0.35) = 7.2 W With two MOSFETs in parallel: PMOSFET = (I2 RDS(ON))(Duty Cycle) = (14/2)2(0.037*)(3.3+0.4)/(5+0.4-0.35) = 1.3W/FET
*Note: RDS(on) increases with temperature. Assume RDS(on) = 0.025 at 25C. RDS(on) can easily increase to 0.050W at high temperature when using a single MOSFET. When using two MOSFETs in parallel, the temperature effects should not cause the RDS(on) to rise above the listed maximum value of 37mW.
PWM/PFM Control DS1 +5V DS2 VCCQP M HIDRV CP L1 RS VO CB
65-5041-07
Figure 5. Charge Pump Configuration Method 2. 12V Gate Bias
Preliminary Information
+5V +12V 471/2 DS2 6.2V VCCQP M1 HIDRV L1 PWM/PFM Control DS1 RS VO CB
* Less heat sink required. With power dissipation down to around one watt and with MOSFETs mounted flat on the motherboard, there will be considerably less heat sink required. The junction-to-case thermal resistance for the MOSFET package (TO-220) is typically at 2C/W and the motherboard serves as an excellent heat sink. * Higher current capability. With thermal management under control, this on-board DC-DC converter is able to deliver load currents up to 14.5A with no problem at all.
65-5041-08
Figure 6. 12V Gate Bias Configuration
MOSFET Gate Bias
The MOSFET can be biased by one of two methods: Charge Pump and 12V Gate Bias.
Method 1. Charge pump (or Bootstrap) method
Figure 7 uses an external 12V source to bias VCCQP. A 47W resistor is used to limit the transient current into the VCCQP pin. A 1mF capacitor filter is used to filter the VCCQP supply. This method provides a higher gate bias voltage to the MOSFET, and therefore reduces the RSD(ON) and resulting power loss within the MOSFET. Figure 8 illustrates how RDS(ON) decreases dramatically as VGS increases. A 6.2V Zener (DS2) is used to clamp the voltage at VCCQP to a maximum of 12V and ensure that the absolute maximum voltage of the IC will not be exceeded.
0.1 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 1.5 2 2.5 3 3.5 4 5 6 7 8 9 VGS
Figure 5 employs a charge pump to provide gate bias. Capacitor CP is the charge pump deployed to boost the voltage of the RC5041 output driver. When the MOSFET switches off, the source of the MOSFET is at -0.6V. VCCQP is charged through the Schottky diode to 4.5V. Thus, the capacitor CP is charged to 5V. When the MOSFET turns on, the source of the MOSFET voltage is equal to 5V. The capacitor voltage follows, and hence provides a voltage at VCCQP equal to 10V. The Schottky is required to provide the charge path when the MOSFET is off. The Schottky reverses bias when the VCCQP goes to 10V. The charge pump capacitor, CP, needs to be a high Q and high frequency capacitor. A 1mF ceramic capacitor is recommended here.
RDS(ON) W
10 11
Figure 7. R(DS) vs. VGS for Typical MOSFETs
65-5041-09
9
RC5041
PRODUCT SPECIFICATION
Converter Efficiency
Losses due to parasitic resistance in the switches, coil, and sense resistor dominate at high load-current level. The major loss mechanisms under heavy loads, in usual order of importance, are: * MOSFET I2R Losses
* * * * * * *
Inductor coil losses Sense resistor losses Gate-charge losses Diode-conduction losses Transition losses Input capacitor losses Losses due to the operating supply current of the IC.
Efficiency of the converter under heavy loads can be calculated as follows:
P OUT I OUT V OUT Efficiency = ------------- = ------------------------------------------------------- , I OUT V OUT + P LOSS p IN
where P LOSS = PD MOSFET + PD INDUCTOR + PD RSENSE + PD GATE + PD DIODE + PD TRAN + PD CAP + PD IC
Preliminary Information
Design Equations:
(1) PD MOSFET = I OUT ( R DS ( ON ) 1.5 ) DutyCycle where 1.5 is the temperature multiplier
OUT D where DutyCycle = ----------------------------------------2
+V V V IN + V D - V SW
(2) PD INDUCTOR = I OUT R INDUCTOR (3) PD RSENSE = I OUT R SENSE (4) PD GATE = q GATE f 5V , where q GATE is the gate charge and f is the switching frequency (5) PD DIODE = V f I OUT ( 1 - Dutycycle ) V IN C RSS I LOAD f (6) PD TRAN = ------------------------------------------------------------ , where CRSS is the reverse transfer capacitance of the MOSFET. I DRIVE (7) PD CAP = I RMS ESR (8) PD IC = V CC I CC
2 2 2
2
Example:
3.3 + 0.5 DutyCycle = ----------------------------- = 0.70 5 + 0.5 - 0.1 PD INDUCTOR = 10 0.010 = 1W
2
PD MOSFET = 10 ( 0.010 1.5 ) 0.70 = 1.05W PD RSENSE = 10 0.0065 = 0.65W
2
2
PD GATE = CV f 5V = 1.75nf ( 9 - 1 )V 300Khz 5V = 0.021W PD DIODE = 0.5 10 ( 1 - 0.70 ) = 1.5W 5 400pf 10 300khz PD TRAN = --------------------------------------------------------------- ~ 0.074W 0.7A PD CAP = ( 7.5 - 2.5 ) 0.015 = 0.37W PD IC = 0.2W PD LOSS = 1.05W + 1.0W + 0.65W + 0.021W + 1.50W + 0.074W + 0.37W + 0.2W = 4.865W 3.3 10 \ Efficiency = -------------------------------------- ~ 87% 3.3 10 + 4.865
2 2
10
PRODUCT SPECIFICATION
RC5041
Selecting the Inductor
The inductor is one of the most critical components to be selected in the DC-DC converter application.. The critical parameters are inductance (L), maximum DC current (Io) and the coil resistance (R1). The inductor core material is a crucial factor in determining the amount of current the inductor will be able to withstand. As with all engineering designs, tradeoffs exist between various types of core materials. In general, Ferrites are popular due to their low cost, low EMI properties and high frequency (>500KHz) characteristics. Molypermalloy powder (MPP) materials exhibit good saturation characteristics, low EMI and low hysteresis losses; however, they tend to be expensive and more effectively utilized at operating frequencies below 400KHz. Another critical parameter is the DC winding resistance of the inductor. This value should typically be reduced as much as possible, as the power loss in the DC resistance will degrade the efficiency of the converter by the relationship: PLOSS = IO2 x R1. The value of the inductor is a function of the oscillator duty cycle (TON) and the maximum inductor current (IPK). IPK can be calculated from the relationship:
I PK V IN - V SW - V D = I MIN + ae ---------------------------------------- o T ON e o L
When designing the external current sense circuitry, pay careful attention to the output limitations during normal operation and during a fault condition. If the short circuit protection threshold current is set too low, the DC-DC converter may not be able to continuously deliver the maximum CPU load current. If the threshold level is too high, the output driver may not be disabled at a safe limit and the resulting power dissipation within the MOSFET(s) may rise to destructive levels. The design equation used to set the short circuit threshold limit is as follows:
V th R SENSE = ------- , where: I SC = Output short circuit current I SC
Preliminary Information
( I PK - I min ) I SC I inductor = I Load, max + ---------------------------2
Where Ipk and Imin are peak ripple current and Iload, max = maximum output load current. The designer must also take into account the current (IPK -Imin), or the ripple current flowing through the inductor under normal operation. Figure 8 illustrates the inductor current waveform for the RC5041 DC-DC converter at maximum load.
Ipk
Where TON is the maximum duty cycle and VD is the forward voltage of diode DS1. Then the inductor value can be calculated using the relationship:
V IN - V SW - V O L = ae ---------------------------------------- o T ON e I PK - I MIN o
I
(Ipk-imin)/2 ILOAD TOFF T=1/f s t
65-5041-10
Imin TON
Where VSW (RDSON x IO) is the drain-to-source voltage of M1 when it is switched on.
Implementing Short Circuit Protection
Intel currently requires all power supply manufacturers to provide continuous protection against short circuit conditions that may damage the CPU. To address this requirement, Fairchild Semiconductor has implemented a current sense methodology to disable the output drive signal to the MOSFET(s) when an over current condition is detected. The voltage drop created by the output current flowing across a sense resistor is presented to one terminal of an internal comparator with hysterisis. The other comparator terminal has the threshold voltage, nominally of 120mV. Table 4 states the limits for the comparator threshold of the Switching Regulator.
Figure 8. DC-DC Converter Inductor Current Waveform
The calculation of this ripple current is as follows:
( V IN - V SW - V OUT ) ( V OUT + V D ) ( I pk - I min ) --------------------------- = ---------------------------------------------------- ----------------------------------------------T L ( V IN - V SW + V D ) 2
Table 4. RC5041 Short Circuit Comparator Threshold Voltage
Short Circuit Comparator Vthreshold (mV) Typical Minimum Maximum 120 100 140
where: * Vin = input voltage to Converter * VSW = voltage across Switcher (MOSFET) = ILOAD x RDS(ON) * VD = Forward Voltage of the Schottky diode * T = the switching period of the converter = 1/fS, where fS = switching frequency. For an input voltage of 5V, an output voltage of 3.3V, an inductor value of 1.3mH and a switching frequency of 650KHz (using CEXT=39pF), the inductor current can be calculated as follows:
11
RC5041
PRODUCT SPECIFICATION
Table 5. Comparison of Sense Resistors1
Discrete Iron Alloy resistor (IRC) Discrete Metal Strip surface mount resistor (Dale) Discrete MnCu Alloy wire resistor 10% 0.200" x 0.04" x 0.160" 1 watt Discrete CuNi Alloy wire resistor (Copel) 10% 0.200" x 0.04" x 0.100" 1 watt
Description Tolerance Factor (TF) Size (L x W x H)
Motherboard Trace Resistor 29% 2" x 0.2" x 0.001" (1 oz Cu trace)
5% 1% (1% available) 0.45" x 0.065" x 0.25" x 0.125" x 0.200" 0.025" 1 watt (3W and 5W available) +30 ppm $0.31 1 watt
Power capability >50A/in
Preliminary Information
Temperature Coefficient Cost @10,000 piece
+4,000 ppm Low included in motherboard
75 ppm $0.47
30 ppm $0.09
20 ppm $0.09
Notes: 1.Refer to Appendix A for Directory of component suppliers. ( I pk - I min ) ( 5.0 - 14.5 0.037 - 3.3 ) --------------------------- = ------------------------------------------------------------- -6 2 1.3 10 ( 3.3 + 0.5 ) 1 ------------------------------------------------------------- ----------------------- = 1.048A ( 5.0 - 14.5 0.037 + 0.5 ) 650 10 3
* For discrete resistor and Iload, max = 14.5A:
V th,min R SENSE = --------------------------------------------------- ( 1 - TF ) 1.0A + I Load, max + I R 100mV = --------------------------------- ( 1 - 5% ) = 5.75mW 2.0A + 14.5A
Therefore, the peak current, IPK, through the inductor for a 14.5A load is found to be:
I SC I inductor ( I PK - I min ) = I Load, max + ---------------------------- = 14.5 + 1 = 15.5A 2
For user convenience, Table 6 lists recommended value for sense resistor for various load current using embedded PC trace resistor or discrete resistor.
As a result, the short circuit detection threshold must be at least 15.5A The next step is to determine the value of the sense resistor. Including sense resistor tolerance, the sense resistor value can be approximated as follows:
V th,min V th,min R SENSE = ---------------- ( 1 - TF ) = --------------------------------------------- ( 1 - TF ) 1 + I SC 1.0 + I Load,max + I R
Table 6. Rsense for Various Load Current
ILoad,max (A) 10.00 11.20 12.40 13.90 14.00 14.50 RSENSE PC Trace Resistor (mW) 5.9 5.4 4.9 4.5 4.4 4.3 RSENSE Discrete Resistor (mW) 7.9 7.2 6.6 6.0 5.9 5.7
Where TF = Tolerance Factor for the sense resistor. IR = Ripple Current = 1A There are several different type of sense resistors. Table 7 describes tolerance, size, power capability, temperature coefficient and cost of various type of sense resistors: Based on the Tolerance in Table 5, * For Embedded PC Trace Resistor and for Iload,max = 14.5A:
V th,min R SENSE = ---------------------------------------- ( 1 - TF ) 2.0A + I Load, max 100mV = --------------------------------- ( 1 - 29% ) = 4.3mW 2.0A + 14.5A
12
PRODUCT SPECIFICATION
RC5041
RC5041 Short Circuit Current Characteristics
The RC5041 has a short circuit current characteristic that includes a hysteresis function that prevents the DC-DC converter from oscillating in the event of a short circuit. A typical V-I characteristic of the DC-DC converter output is presented in the Operating Conditions table. The converter performs with a normal load regulation characteristic until the voltage across the resistor reaches the internal short circuit threshold of 120mV. At this point, the internal comparator trips and sends a signal to the controller to turn off the gate drive to the power MOSFET. This causes a drastic reduction in the output voltage as the load regulation collapses into the short circuit mode of control. The output voltage will not return to the normal load characteristic until the output short circuit current is reduced to within the safe range for the DC-DC converter.
The ESR rating of a capacitor is a difficult number to quantify. ESR or Equivalent Series Resistance, is defined as the resonant impedance of the capacitor. Since the capacitor is actually a complex impedance device having resistance, inductance and capacitance, it is quite natural for this device to have a resonant frequency. As a rule, the lower the ESR, the better suited the capacitor is for use in switching power supply applications. Many capacitor manufacturers do not supply ESR data. A useful estimate of the ESR can be obtained using the following equation:
DF ESR = -----------2pfC
Where DF is the dissipation factor of the capacitor, f is the operating frequency, and C is the capacitance in farads.
Preliminary Information
Schottky Diode Selection
The application circuit of Figure 1 shows a Schottky diode, DS1. DS1 is used as a flyback diode to provide a constant current path for the inductor when M1 is turned off. A vital selection criteria for DS1 is that it exhibits a very low forward voltage drop, as this parameter will directly impact the regulator efficiency as the output voltage is reduced. Table 7 presents several suitable Schottky diodes for this application. Note that the diode MBR2015CTL has a very low forward voltage drop. This diode is most ideal for applications where output voltages below 2.8V are required.
With this in mind, correct calculation of the output capacitance is crucial to the performance of the DC-DC converter. The output capacitor determines the overall loop stability, output voltage ripple and load transient response. The calculation is as follows:
I O DT C ( mF ) = ------------------------------------DV - I O ESR
Where DV is the maximum voltage deviation due load transient, DT is reaction time of the power source (Loop response time of the RC5041) and it is approximately 8ms), and IO is the output load current. For IO = 10A, and DV = 75mV, the bulk capacitor required can be approximated as follows:
I O DT 10A 8ms C ( mF ) = ------------------------------------- = -------------------------------------------------- = 3200mF DV - I O ESR 75mV - 10A 5mW
Table 7. Schottky Diode Selection Table
Manufacturer Model # Philips PBYR1035 Motorola MBR2035CT Motorola MBR1545CT Conditions IF = 20A; Tj = 25C IF = 20A; Tj = 125C IF = 20A; Tj = 25C IF = 20A; Tj = 125C IF = 15A; Tj = 25C IF = 15A; Tj = 125C Forward Voltage VF < 0.84V < 0.72V < 0.84V < 0.72V < 0.84V < 0.72V < 0.58V < 0.48V
Input filter
We recommend that the design include an input inductor between the system +5V supply and the DC-DC converter input described below. This inductor will serve to isolate the +5V supply from noise occurring in the switching portion of the DC-DC converter and to also limit the inrush current into the input capacitors on power up. We recommend a value of around 2.5mH.
5V 2.5H Vin
Motorola IF = 20A; Tj = 25C MBR2015CTL IF = 20A; Tj = 150C
Output Filter Capacitors
Optimal ripple performance and transient response are functions of the filter capacitors used. Since the 5V supply of a PC motherboard may be located several inches away from the DC-DC converter, input capacitance can play an important role in the load transient response of the RC5041. The higher the input capacitance, the more charge storage is available for improving the current transfer through the FET. Low "ESR" capacitors are best suited for this type of application and can influence the converter's efficiency if not chosen carefully. The input capacitor should be placed as close to the drain of the FET as possible to reduce the effect of ringing caused by long trace lengths.
0.1F
1000F, 10V Electrolytic
65-5041-11
Figure 9. Input Filter
13
RC5041
PRODUCT SPECIFICATION
PCB Layout Guidelines and Considerations
PCB Layout Guidelines
* Placement of the MOSFETs relative to the RC5041 is critical. The MOSFETs (M1 & M2), should be placed such that the trace length of the HIDRV pin from the RC5041 to the FET gates is minimized. A long lead length on this pin will cause high amounts of ringing due to the inductance of the trace combined with the large gate capacitance of the FET. This noise will radiate all over the board, and because it is switching at such a high voltage and frequency, it will be very difficult to suppress.
* Surround the CEXT timing capacitor with a ground trace as much as possible. Also be sure to keep a ground or power plane underneath the capacitor for further noise isolation. This will help to shield the oscillator pin 1 from the noise on the PCB. Place this capacitor as close to the RC5041 pin 1 as possible. * Place MOSFETs, inductor and Schottky as close together as possible for the same reasons as #1 above. Place the input bulk capacitors as close to the drains of MOSFETs as possible. In addition, placement of a 0.1mF decoupling cap right on the drain of each MOSFET will help to suppress some of the high frequency switching noise on the input of the DC-DC converter. * The traces that run from the RC5041 IFB (pin 3) and VFB (pin 4) pins should be run together next to each other and be Kelvin connected to the sense resistor. Running these lines together will help in rejecting some of the common noise that is presented to the RC5041 feedback input. Try as much as possible to run the noisy switching signals (HIDRV & VCCQP) on one layer; and use the inner layers for only power and ground. If the top layer is being used to route all of the noisy switching signals, use the bottom layer to route the analog sensing signals VFB and IFB.
Preliminary Information
The drawing below depicts an example of good placement for the MOSFETs in relation to the RC5041 and also an example of problematic placement for the MOSFETs. In general, all of the noisy switching lines should be kept away from the quiet analog section of the RC5041. That is to say, traces that connect to pins 8 and 9 (HIDRV and VCCQP) should be kept far away from the traces that connect to pins 1 through 4, and pin 12. * Place decoupling capacitors (.1mF) as close to the RC5041 pins as possible. Extra lead length on these will negate their ability to suppress noise. * Each VCC and GND pin should have its own via down to the appropriate plane underneath. This will help give isolation between pins.
M1
M2
Correct layout
9 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1
Poor layout
9 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1
= "Quiet" Pins
M1
65-5041-12
M2
Figure 10. MOSFET Layout Guidelines
14
PRODUCT SPECIFICATION
RC5041
Mechanical Dimensions - 16 Lead SOIC
Symbol A A1 B C D E e H h L N a ccc Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
.053 .069 .004 .010 .013 .020 .008 .010 .386 .394 .150 .158 .050 BSC .228 .010 .016 16 0 -- 8 .004 .244 .020 .050
1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 9.80 10.00 3.81 4.00 1.27 BSC 5.80 0.25 0.40 16 0 -- 8 0.10 6.20 0.50 1.27
3 6
Preliminary Information
16
9
E
H
1
8
D A1 A SEATING PLANE -C- LEAD COPLANARITY ccc C a
h x 45 C
e
B
L
15
RC5041
PRODUCT SPECIFICATION
Ordering Information
Product Number RC5041M Package 16 pin SOIC
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS30005041 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC5042
Programmable DC-DC Converter
Features
* Programmable output from 2.1V to 3.5V using integrated 4-bit DAC * 87% efficiency * Oscillator frequency adjustable from 200KHz to 1MHz * On-chip Power Good function * Excellent transient response * Over-Voltage Protection * Short Circuit Protection * Precision trimmed low TC voltage reference * 16 pin SOIC package * Meets Intel Pentium(R) Pro VRM specifications using minimum number of external components
Description
The RC5042 is a non-synchronous DC-DC controller IC which provides an accurate, programmable output for Pentium Pro CPU applications. Using an integrated 4-bit DAC to accept a voltage identification (VID) code directly from the CPU, the RC5042 can generate precise output voltages between 2.1V and 3.5V in 100mV increments. Output load currents in excess of 12A can be delivered using minimal external circuitry. The RC5042 is designed to operate in a standard PWM control mode under heavy load conditions and in PFM control mode while supplying light loads for optimal efficiency. An on-board precision low TC voltage reference eliminates the requirement for external components in order to achieve tight voltage regulation. The Pentium Pro CPU is continuously protected by an integrated Power Good function, which sends an active-low interrupt signal to the CPU in the event that the output voltage is out of tolerance. The internal oscillator can be programmed to operate over a range of 200KHz to 1MHz to allow flexibility in choosing external components.
Applications
* Programmable power supply for Pentium Pro and Pentium-based CPU motherboards * VRM module for Pentium Pro CPU * Programmable power supply for high current microprocessors
Block Diagram
RC5042
OSCILLATOR
- +
+5V VIN
- +
- - + +
VO DIGITAL CONTROL
VREF
4-BIT DAC
1.24V REFERENCE
POWER GOOD
PWRGD
VID0 VID1 VID2 VID3
65-5042-01
Rev. 1.3.1
RC5042
PRODUCT SPECIFICATION
Pin Assignments
CEXT PWRGD IFB VFB VCCA VCCD GNDP HIDRV
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
65-5042-02
VID0 VID1 VID2 VID3 VREF GNDA GNDD VCCQP
Pin Definitions
Pin Number Pin Name 1 CEXT Pin Function Description Oscillator capacitor connection. Connecting an external capacitor to this pin sets the internal oscillator frequency from 200 KHz to 1 MHz. Layout of this pin is critical to system performance. See Application Information for details. Power Good output flag. Open collector output will be at logic HIGH under normal operation. Logic LOW indicates output voltage is not within 10% of nominal. High side current feedback. Pins short 4 and 5 are used as the inputs for the current feedback control loop and as the short circuit current sense points. Layout of these traces is critical to system performance. See Application Information for details. Voltage feedback. Pin 5 is used as the input for the voltage feedback control loop and as the low side current feedback input. Layout of this trace is critical to system performance. See Application Information for details. Analog VCC. Connect to system 5V supply and decouple to ground with 0.1mF ceramic capacitor. Digital VCC. Connect to system 5V supply and decouple to ground with 4.7mF tantalum capacitor. Power ground. Return pin for high currents flowing in pins 8 and 9 (HIDRV and VCCQP). Connect to low impedance ground. See Application Information for details. FET driver output. Connect this pin to the gate of the N-channel MOSFETs M1 and M2 in Figures 1 and 2. The trace from this pin to the MOSFET gates should be kept as short as possible (less than 0.5"). See Application Information for details. Power VCC for FET Driver. VCCQP must be connected to a voltage of at least VCCA + VGS,ON (M1). See Application Information for details. Digital ground. Return path for digital logic. This pin should be connected to system ground so that ground loops are avoided. See Application Information for details. Analog ground. Return path for low power analog circuitry. Connect to system ground so that ground loops are avoided. See Application Information for details. Reference voltage test point. This pin provides access to the DAC output and should be decoupled to ground using a 0.1mF capacitor. No load should be connected to this pin. Voltage identification (VID) code inputs. These open collector/TTL compatible inputs will program the output voltage over the ranges specified in Table 1. Internal 10KW pull-up resistors assure correct operation if pins are left unconnected.
2 3
PWRGD IFB
4
VFB
5 6 7 8
VCCA VCCD GNDP HIDRV
9 10 11 12
VCCQP GNDD GNDA VREF
13-16
VID3- VID0
2
PRODUCT SPECIFICATION
RC5042
Absolute Maximum Ratings1
Control Supply Voltages, VCCA and VCCD FET Supply Voltage, VCCQP Voltage Identification Code Inputs, VID3-VID0 Junction Temperature, TJ Storage Temperature, TS Lead Soldering Temperature, 10 seconds 13V 13V 13V 150C -65 to 150C 300C
Notes: 1. Functional operation under any of these conditions is not implied. Permanent damage may occur if the device is subjected to conditions outside these ratings.
Operating Conditions
Parameter Control Supply Voltages, VCCA and VCCD Driver Supply Voltage, VCCQP VID Code Input Voltage, Logic HIGH VID Code Input Voltage, Logic LOW PWRGD HIGH Threshold PWRGD LOW Threshold Ambient Temperature, TA -7 0 70 Conditions Min. 4.5 9 2 0.8 +7 Typ. 5 10 Max. 7 12 Units V V V V %VREF %VREF C
Electrical Specifications
(VCCA, VCCD = 5V, fosc = 650 KHz, and TA = +25C using circuit in Figure 1, unless otherwise noted) The * denotes specifications which apply over the full operating temperature range. Parameter Output Voltage Output Current1 Accuracy2 ILOAD = 5.25A TA = 0-70C ILOAD = 0.5 to 12.5A VIN = 4.75-5.25V, ILOAD = 12.5A VOUT = 2.1-3.5V, 20MHz BW TA = 0-70C ILOAD = 12.5A, VOUT = 3.3V Internal comparator offset No load * * * * * * * 80 100 0.5 Setpoint Conditions TA = 0-70C, See Table 1. * Min. 2.0 12.5 1.0 +100 -0.5 +0.14 30 3.3 85 120 1.0 0.1 150 10 0.2 Excluding tolerance of CEXT 90 10 95 100 1 0.2 140 5.0 Typ. Max. 3.5 14.5 1.5 Units V A % ppm/C %Vo %Vo mV % % mV A W C/W ms MHz % % ns
Output Temperature Drift Load Regulation Line Regulation Output Ripple/Noise, pk-pk Cumulative Efficiency Short Circuit Detect Threshold Output Current Driver Power Dissipation Thermal Impedance, qJA Response Time, Sleep to Full Load Oscillator Frequency Range4 Oscillator Frequency Accuracy Maximum Duty Cycle in PWM Mode Minimum Duty Cycle in PFM Mode Accuracy3
3
RC5042
PRODUCT SPECIFICATION
Electrical Specifications (continued) (VCCA, VCCD = 5V, fosc = 650 KHz, and TA = +25C using circuit in Figure 1, unless otherwise noted) The * denotes specifications which apply over the full operating temperature range.
Parameter Response Time to Short Circuit Soft Start Duration at Power-Up Load Transient, 0.5A to 12.5A step Slew rate = 30A/ms Conditions Min. Typ. 15 10 100 Max. 30 Units ns ms mV
Notes: 1. The maximum output current is limited only by the external components used and their thermal limitations. For loads greater than 12.5A, adequate thermal management is required to achieve optimal performance and reliability. 2. Setpoint Accuracy includes Output Ripple/Noise. 3. Cumulative Accuracy is determined by Setpoint Accuracy, Line and Load Regulation, Output Ripple/Noise, Transient Performance and Temperature Drift. 4. See Typical Operating Characteristics.
Table 1. Voltage Identification Codes1
Pentium Pro Processor Pins VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 VID Setpoint 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 Setpoint Accuracy2 (mV) -- 31 33 34 36 37 39 40 42 43 45 46 48 49 51 60 Cumulative Accuracy3 (mV) -- 105 110 115 120 125 130 135 140 145 150 155 160 165 170 175
Notes: 1. 0 Indicates Processor pin is tied to VSS. 1 = Open. 2. Setpoint Accuracy includes Output Ripple/Noise. 3. Cumulative Accuracy includes Setpoint Accuracy, Line & Load Regulation, Transient Effects and Temperature Drift.
4
PRODUCT SPECIFICATION
RC5042
Typical Operating Characteristics
(VCCA, VCCD = 5V, fOSC = 650 kHz and TA = +25C using circuit in Figure 1, unless otherwise noted)
Efficiency vs. Output Current, 650 KHz
100 95 90 Efficiency (%) 85 80 75
65-5042-03
Load Regulation, 650 KHz
3.35 3.3V 3.30
3.3V VOUT (V) 3.1V 3.25 3.20
65-5042-04
70 65 60 0.5 1 2 3 4 5 6 7 8 9
3.15 3.1V 3.10 0.5 1 2 3 4 5 6 7 8 IOUT (A)
10 11 12.5
9 10 11 12.5
IOUT (A)
Reference Tempco 3.150 1250 1050 VREF (V) 3.125 Frequency (kHz) 850 650 450 250 50 18
Oscillator Frequency vs CEXT
3.100
65-5042-05
3.075 0 25 50 Temperature (C)
70
39
75 150 CEXT (pf)
300
561
VREF Programming
3.50 3.25
Output Voltage vs. Output Current, RSENSE = 6m1/2
3.5 3.0
Output Voltage
VREF pin (V)
3.00 2.75 2.50
65-5042-07
2.5 2.0 1.5 1.0 0.5 0 0 5 10 15 20
65-5042-13
2.25 2.00 2 2.5 3 VID Set Point (V)
3.5
25
Output Current
65-5042-06
5
RC5042
PRODUCT SPECIFICATION
Typical Operating Characteristics (continued)
Switching Waveforms, 12.5A Load FET Driver Supply, VCCQP (ILOAD = 12.5A using charge pump)
1V/div
CEXT pin VOUT (5V/div)
5V/div
HIDRV pin
Time (500ns/division)
Time (1s/division)
Transient Response, 0.5A to 12.5A Step
AC Ripple Response, 12.5A Load
VOUT (50mV/div)
Time (200ns/division)
VOUT (50mV/div)
Time (1s/division)
65-5042-08
6
PRODUCT SPECIFICATION
RC5042
Test Circuits
L2 VCC C4 0.1 m F 2.5 mH C1 1000 mF C2 C3 C5 0.1 m F DS2 1N5817 C8 0.1 m F C9 0.1 m F
1000 m F 1000 m F
C12 1mF 9 R7 10K VREF C7 0.1 mF GND 10 11 12 13 14 15 16 C EXT 39pF 8 7 6 C6 4.7 mF DS1 5 4 3 2 1 M1 2SK1388
M2 2SK1388 L1 1.3 m H
R SENSE VO 1500 mF 6m W 1500 mF C14 1500 m F C15
RC5042
MBR1545CT
VID3 VID2 VID1 VID0
R1 R2 R3 R4 10K
10K VCC 10K 10K VCC C10 0.1 m F C11 0.22 m F R6 10K PWRGD
65-5042-09
Figure 1. Standard Test or Application Schematic
Table 2. RC5042 Bill of Materials
Reference C6 CEXT C12 C1, C2, C3 C11 C13, C14, C15 DS1 DS2 L1 L21 M1, M2 RSENSE R1-R4, R6, R7 Part Number Panasonic ECSH1CY475R Panasonic ECU-V1H121JCG Panasonic ECSH1CY105R Sanyo 6MV1000GX Panasonic ECU-V1H224ZFX Sanyo 6MV1500GX Motorola MBR1545CT General Instruments 1N5817 Skynet 320-8107 Skynet 320-6110 Fuji 2SK1388 Copel AWG #18 Panasonic ERJ-6ENF10.0KV Description 0.1mF 50V capacitor 4.7mF 16V capacitor 39pF capacitor 1mF 16V capacitor 1000mF 6.3V electrolytic capacitor 0.22mF 50V capacitor 1500mF 6.3 electrolytic capacitor Schottky Diode Schottky Diode 1.3mH inductor 2.5mH inductor N-Channel Logic Level Enhancement Mode MOSFET 6 mW CuNi Alloy Wire Resistor 10K 5% Resistors RDS(ON) < 37mW VGS < 4V, ID > 20A ESR < 0.047 W Vf < 0.72V @ If = 15A Relevant Specification C4, C5, C7-C10 Panasonic ECU-V1H104ZFX
Note: 1. The inductor L2 is recommended to isolate the 5V input supply from current surges caused by MOSFET switching. L2 is not required for normal operation and may be omitted if desired.
C13
7
RC5042
PRODUCT SPECIFICATION
Application Information
Simple Step-Down Converter
S1 L1 + VIN D1 C1 RL Vout -
65-AP42-01
controller will sense the load level and switch between the two operating modes automatically, thus optimizing its efficiency under all loading conditions.
+5V
A
CEXT
OSCILLATOR
VCCQP D HIDRV B VO C E
Figure 2. Simple Buck DC-DC Converter
PWM/PFM Control
Figure 2 illustrates a step-down DC-DC converter with no feedback control. The derivation of the basic step-down converter will serve as a basis for the design equations for the RC5042. Referring to Figure 1, the basic operation begins by closing the switch S1. When S1 is closed, the input voltage VIN is impressed across inductor L1. The current flowing in this inductor is given by the following equation:
( V IN - V OUT )T ON I L = ---------------------------------------------L1
GNDP
A B C D E
CEXT HIDRV ILOAD
Where TON is the duty cycle (the time when S1 is closed). When S1 opens, the diode D1 will conduct the inductor current and the output current will be delivered to the load according to the equation:
V OUT ( T S - T ON ) I L = -----------------------------------------L1
Figure 3. Typical Switching Waveforms
Main Control Loop
Refer to the Block Diagram on page 1. The control loop of the regulator contains two main sections, the analog control block and the digital control block. The analog block consists of signal conditioning amplifiers feeding into a set of comparators which provide the inputs to the digital block. The signal conditioning section accepts inputs from the IFB (current feedback) and VFB (voltage feedback) pins and sets up two controlling signal paths. The voltage control path amplifies the VFB signal and presents the output to one of the summing amplifier inputs. The current control path takes the difference between the IFB and VFB pins and presents the resulting signal to another input of the summing amplifier. These two signals are then summed together with the slope compensation input from the oscillator. This output is then presented to a comparator, which provides the main PWM control signal to the digital control block. The additional comparators in the analog control section set the thresholds of where the RC5042 enters its pulse skipping mode during light loads as well as the point at which the maximum current comparator disables the output drive signals to the external power MOSFETs. The digital control block is designed to take the comparator inputs along with the main clock signal from the oscillator and provide the appropriate pulses to the HIDRV output pin that controls the external power MOSFET. The digital section was designed utilizing high speed Schottky transistor logic, thus allowing the RC5042 to operate at clock speeds as high as 1MHz.
Where TS is the overall switching period, and (TS - TON) is the time during which S1 is open. By solving these two equations, we can arrive at the basic relationship for the output voltage of a step-down converter:
T ON V OUT = V IN ae ----------o e TS o
In order to obtain a more accurate approximation for VOUT, we must also include the forward voltage VD across diode D1 and the switching loss, Vsw. After taking into account these factors, the new relationship becomes:
T ON V OUT = ( V IN + V D - V SW ) ---------- - V D TS
Overview
The RC5042 is a programmable DC-DC controller IC. When designed around the appropriate external components, the RC5042 can be configured to deliver more than 14.5A of output current. During heavy loading conditions, the RC5042 functions as a current-mode PWM step-down regulator. Under light loads, the regulator functions in the PFM (pulse frequency modulation), or pulse skipping mode. The
8
PRODUCT SPECIFICATION
RC5042
High Current Output Drivers
The RC5042 contains two identical high current output drivers which utilize high speed bipolar transistors arranged in a push-pull configuration. Each driver is capable of delivering 1A of current in less than 100ns. Each driver's power and ground are separated from the overall chip power and ground for additional switching noise immunity. The HIDRV driver has a power supply, VCCQP, which is boot-strapped from a flying capacitor as illustrated in Figure 2. Using this configuration, C12 is alternately charged from VCC via the Schottky diode DS2 and then boosted up when the FET is turned on. This scheme provides a VCCQP voltage equal to 2*VCC - VDS(DS2), or approximately 9.5V with VCC = 5V. This voltage is sufficient to provide the 9V gate drive to the external MOSFET required in order to achieve a low RDS(ON). Since the low side synchronous FET is referenced to ground (refer to Figure 3), there is no need to boost the gate drive voltage and its VCCP power pin can be tied to VCC. See Typical Operating Characteristics for typical full load VCCQP waveform.
When disabled, the PWRGD output must be in the low state. Since the RC5042 can supply the OverDrive processor specifications, the UP# signal is not required.
Over-Voltage Protection
The RC5042 provides a constant monitor of the output voltage for protection against overvoltage conditions. If the voltage at the VFB pin exceeds 20% of the selected program voltage, an overvoltage condition will be assumed, and the RC5042 will disable the output drive signal to the MOSFET(s).
Short Circuit Protection
A current sense methodology is implemented to disable the output drive signal to the MOSFET(s) when an over-current condition is detected. The voltage drop created by the output current flowing across a sense resistor is presented to an internal comparator. When voltage developed across the sense resistor exceeds the comparator threshold voltage, the RC5042 will disable the output drive signal to the MOSFET(s). The DC-DC converter returns to normal operation after the fault has been removed, for either an overvoltage or a short circuit condition.
Internal Voltage Reference
The reference included in the RC5042 is a 1.24V precision band-gap voltage reference. The internal resistors are precisely trimmed to provide a near zero temperature coefficient (TC). Added to the reference input is the resulting output from an integrated 4-bit DAC. The DAC is provided in accordance with the Pentium Pro specification guideline, which requires the DC-DC converter output to be directly programmable via a 4-bit voltage identification (VID) code. This code will scale the reference voltage from 2.0V (no CPU) to 3.5V in 100mV increments. For guaranteed stable operation under all loading conditions, a 10KW pull-up resistor and 0.1mF of decoupling capacitance should be connected to the VREF pin.
Oscillator
The RC5042 oscillator section is implemented using a fixed current capacitor charging configuration. An external capacitor (CEXT) is used to preset the oscillator frequency between 200KHz and 1MHz. This scheme allows maximum flexibility in setting the switching frequency as well as choosing external components. In general, a lower operating frequency will increase the peak ripple current flowing in the output inductor, and thus require the use of a larger inductor value. Operation at lower frequencies also increases the amount of energy storage that must be provided by the bulk output capacitors during load transients due to the slower loop response of the controller. As the operating frequency is increased, the user should note that the efficiency losses due to switching are relatively fixed per switching cycle. Therefore, as the switching frequency is increased, so is the contribution toward efficiency due to switching losses. Careful analysis of the RC5042 DC-DC controller has resulted in an optimal operating frequency of 650KHz, which allows the use of smaller inductive and capacitive components while maximizing peak efficiency under all operating conditions.
Power Good
The RC5042 Power Good function is designed in accordance with the Pentium Pro DC-DC converter specification and provides a constant voltage monitor on the VFB pin. The circuit compares the VFB signal to the VREF voltage and outputs an active-low interrupt signal to the CPU should the power supply voltage exceed 7% of its nominal setpoint. The Power Good flag provides no other control function to the RC5042.
Upgrade Present (UP#)
Intel's specifications state that the DC-DC converter must accept an open collector signal, used to indicate the presence of an upgrade processor. The typical state is high (standard CPU). When in the low or ground state (OverDrive processor present), the output voltage must be disabled unless the converter can supply the OverDrive processor's specifications.
9
RC5042
PRODUCT SPECIFICATION
Design Considerations and Component Selection
MOSFET Selection
This application requires N-channel Logic Level Enhancement Mode Field Effect Transistors. Desired characteristics are as follows: * Low Static Drain-Source On-Resistance, RDS(on) < 37 mW (lower is better) * Low gate drive voltage, VGS < 4V * Power package with low thermal resistance * Drain current rating of 20A minimum * Drain-Source voltage > 15V.
The on-resistance (RDS(ON)) is the primary parameter for MOSFET selection. The on-resistance determines the power dissipation of the MOSFET and therefore significantly affects the efficiency of the DC-DC Converter. Table 5 presents a list of suitable MOSFETs for this application.
Table 5. MOSFET Selection Table
RDS,ON(mW) Manufacturer & Model # Fuji 2SK1388 Siliconix SI4410DY National Semiconductor NDP706AL NDP706AEL National Semiconductor NDP603AL National Semiconductor NDP606AL Motorola MTB75N03HDL Int. Rectifier IRLZ44 Int. Rectifier IRL3103S VGS = 4.5V, ID = 10A VGS = 5V, ID = 24A VGS = 5V, ID = 37.5A VGS = 5V, ID = 31A VGS = 4.5V, ID = 28A VGS = 4V, ID = 17.5A VGS = 4.5V, ID = 5A VGS = 5V, ID = 40A Conditions1 TJ = 25C TJ = 125C TJ = 25C TJ = 125C TJ = 25C TJ = 125C TJ = 25C TJ = 125C TJ = 25C TJ = 125C TJ = 25C TJ = 125C TJ = 25C TJ = 125C TJ = 25C TJ = 125C Typ. 25 37 16.5 28 13 20 31 42 22 33 6 9.3 -- -- -- Max. 37 -- 20 34 15 24 40 54 25 40 9 14 28 46 19 31 TO-220 TO-263 (D2 PAK) TO-220 TO-220 TO-220 FJA = 62.5 FJC = 2.5 FJA = 62.5 FJC = 1.5 FJA = 62.5 FJC = 1.0 FJA = 62.5 FJC = 1.0 FJA = 62.5 FJC = 1.0 SO-8 (SMD) TO-220 FJA = 50 FJA = 62.5 FJC = 1.5 Package TO-220 Thermal Resistance FJA = 75
Note: 1. RDS(ON) values at TJ=125C for most devices were extrapolated from the typical operating curves supplied by the manufacturers and are approximations only. Only National Semiconductor offers maximum values at TJ = 125C.
10
PRODUCT SPECIFICATION
RC5042
Two MOSFETs in Parallel
We recommend that two MOSFETs be used in parallel instead of one single MOSFET. Significant advantages are realized using two MOSFETs in parallel: * Significant reduction of power dissipation. Maximum current of 14A with one MOSFET: PMOSFET = (I RDS(ON))(Duty Cycle) = (14)2(0.050*)(3.3+0.4)/(5+0.4-0.35) = 7.2 W With two MOSFETs in parallel: PMOSFET = RDS(ON))(Duty Cycle) 2(0.037*)(3.3+0.4)/(5+0.4-0.35) = 1.3W/FET = (14/2)
*Note: RDS(on) increases with temperature. Assume RDS(on) = 0.025 at 25C. RDS(on) can easily increase to 0.050W at high temperature when using a single MOSFET. When using two MOSFETs in parallel, the temperature effects should not cause the RDS(on) to rise above the listed maximum value of 37mW. 2
PWM/PFM Control DS1 +5V DS2 VCCQP M HIDRV CP L1 RS VO CB
65-5040-13
(I2
Figure 4. Charge Pump Configuration Method 2. 12V Gate Bias
+5V +12V 471/2 DS2 6.2V VCCQP M1 HIDRV L1 PWM/PFM Control DS1 RS VO CB
* Less heat sink required. With power dissipation down to around one watt and with MOSFETs mounted flat on the motherboard, there will be considerably less heat sink required. The junction-to-case thermal resistance for the MOSFET package (TO-220) is typically at 2C/W and the motherboard serves as an excellent heat sink. * Higher current capability. With thermal management under control, this on-board DC-DC converter is able to deliver load currents up to 14.5A with no problem at all.
65-5040-14
Figure 5. 12V Gate Bias Configuration
MOSFET Gate Bias
The MOSFET can be biased by one of two methods-- Charge Pump or 12V Gate Bias.
Charge pump (or Bootstrap) method
Figure 4 employs a charge pump to provide gate bias. Capacitor CP is the charge pump deployed to boost the voltage of the RC5042 output driver. When the MOSFET switches off, the source of the MOSFET is at -0.6V. VCCQP is charged through the Schottky diode to 4.5V. Thus, the capacitor CP is charged to 5V. When the MOSFET turns on, the source of the MOSFET voltage is equal to 5V. The capacitor voltage follows, and hence provides a voltage at VCCQP equal to 10V. The Schottky is required to provide the charge path when the MOSFET is off. The Schottky reverses bias when the VCCQP goes to 10V. The charge pump capacitor, CP, needs to be a high Q and high frequency capacitor. A 1mF ceramic capacitor is recommended here.
Figure 6 uses an external 12V source to bias VCCQP. A 47 W resistor is used to limit the transient current into the VCCQP pin. A 1mF capacitor filter is used to filter the VCCQP supply. This method provides a higher gate bias voltage to the MOSFET, and therefore reduces the RSD(ON) and resulting power loss within the MOSFET. Figure 7 illustrates how RDS(ON) decreases dramatically as VGS increases. A 6.2V Zener (DS2) is used to clamp the voltage at VCCQP to a maximum of 12V and ensure that the absolute maximum voltage of the IC will not be exceeded.
0.1 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 1.5 2 2.5 3 3.5 4 5 6 VGS
R(DS)Fuji R(DS)Fuji R(DS)706A R(DS)-706AEL
RDS(ON) Ohms
7
8
9
10 11
Figure 6. R(DS) vs. VGS for Selected MOSFETs
11
RC5042
PRODUCT SPECIFICATION
Converter Efficiency
Losses due to parasitic resistance in the switches, coil, and sense resistor dominate at high load-current level. The major loss mechanisms under heavy loads, in usual order of importance, are: * MOSFET I2R Losses * Inductor Coil Losses
* * * * * *
Sense Resistor Losses gate-charge losses diode-conduction losses transition losses Input Capacitor losses losses due to the operating supply current of the IC
Efficiency of the converter under heavy loads can be calculated as follows:
P OUT I OUT V OUT Efficiency = ------------- = ------------------------------------------------------- , I OUT V OUT + P LOSS p IN
where P LOSS = PD MOSFET + PD INDUCTOR + PD RSENSE + PD GATE + PD DIODE + PD TRAN + PD CAP + PD IC Design Equations:
(1) PD MOSFET = I OUT R DS ( ON ) DutyCycle
OUT D where DutyCycle = ----------------------------------------2
+V V IN + V D - V SW V
(2) PD INDUCTOR = I OUT R INDUCTOR (3) PD RSENSE = I OUT R SENSE (4) PD GATE = q GATE f 5V , where q GATE is the gate charge and f is the switching frequency (5) PD DIODE = V f I OUT ( 1 - Dutycycle ) V IN C RSS I LOAD f (6) PD TRAN = ------------------------------------------------------------ , where CRSS is the reverse transfer capacitance of the high-side MOSFET. I DRIVE (7) PD CAP = I RMS ESR (8) PD IC = V CC I CC
2 2 2
2
Example:
3.3 + 0.5 DutyCycle = ----------------------------- = 0.73 5 + 0.5 - 0.3 PD MOSFET = 10 0.030 0.73 = 2.19W PD INDUCTOR = 10 0.010 = 1W PD RSENSE = 10 0.0065 = 0.65W PD GATE = CV f 5V = 1.75nf ( 9 - 1 )V 650Khz 5V = 0.045W PD DIODE = 0.5 10 ( 1 - 0.73 ) = 1.35W 5 400pf 10 650khz PD TRAN = --------------------------------------------------------------- ~ 0.010W 0.7A PD CAP = ( 7.5 - 2.5 ) 0.015 = 0.37W PD IC = 0.2W
2 2 2 2 2
12
PRODUCT SPECIFICATION
RC5042
PD LOSS = 2.19W + 1.0W + 0.65W + 0.045W + 1.35W + 0.010W + 0.37W + 0.2W = 5.815W 3.3 10 \ Efficiency = -------------------------------------- ~ 85% 3.3 10 + 5.815
Selecting the Inductor
The inductor is one of the most critical components to be selected in the DC-DC converter application.. The critical parameters are inductance (L), maximum DC current (Io) and the coil resistance (R1). The inductor core material is a crucial factor in determining the amount of current the inductor will be able to withstand. As with all engineering designs, tradeoffs exist between various types of core materials. In general, Ferrites are popular due to their low cost, low EMI properties and high frequency (>500KHz) characteristics. Molypermalloy powder (MPP) materials exhibit good saturation characteristics, low EMI and low hysteresis losses; however, they tend to be expensive and more effectively utilized at operating frequencies below 400KHz. Another critical parameter is the DC winding resistance of the inductor. This value should typically be reduced as much as possible, as the power loss in the DC resistance will degrade the efficiency of the converter by the relationship: PLOSS = IO2 x R1. The value of the inductor is a function of the oscillator duty cycle (TON) and the maximum inductor current (IPK). IPK can be calculated from the relationship:
V IN - V SW - V D = I MIN + ae ---------------------------------------- o T ON e o L
Table 6. RC5042 Short Circuit Comparator Threshold Voltage
Short Circuit Comparator Vthreshold (mV) Typical Minimum Maximum 120 100 140
When designing the external current sense circuitry, the designer must pay careful attention to the output limitations during normal operation and during a fault condition. If the short circuit protection threshold current is set too low, the DC-DC converter may not be able to continuously deliver the maximum CPU load current. If the threshold level is too high, the output driver may not be disabled at a safe limit and the resulting power dissipation within the MOSFET(s) may rise to destructive levels. The design equation used to set the short circuit threshold limit is as follows:
V th R SENSE = ------- , where: I SC = Output short circuit current I SC ( I PK - I min ) I SC I inductor = I Load, max + ---------------------------2
I PK
Where TON is the maximum duty cycle and VD is the forward voltage of diode DS1. Then the inductor value can be calculated using the relationship:
V IN - V SW - V O L = ae ---------------------------------------- o T ON e I PK - I MIN o
Where Ipk and Imin are peak ripple current and Iload, max = maximum output load current. The designer must also take into account the current (IPK -Imin), or the ripple current flowing through the inductor under normal operation. Figure 7 illustrates the inductor current waveform for the RC5042/42 DC-DC converter at maximum load.
Ipk
Where VSW (RDSON x IO) is the drain-to-source voltage of M1 when it is switched on.
Implementing Short Circuit Protection
Intel currently requires all power supply manufacturers to provide continuous protection against short circuit conditions that may damage the CPU. To address this requirement, Fairchild Semiconductor has implemented a current sense methodology to disable the output drive signal to the MOSFET(s) when an over current condition is detected. The voltage drop created by the output current flowing across a sense resistor is presented to one terminal of an internal comparator with hysterisis. The other comparator terminal has the threshold voltage, nominally of 120mV. Table 6 states the limits for the comparator threshold of the Switching Regulator:
I
(Ipk-imin)/2 ILOAD TOFF T=1/f s t
Imin TON
Figure 7. Typical DC-DC Converter Inductor Current Waveform
The calculation of this ripple current is as follows:
( V IN - V SW - V OUT ) ( V OUT + V D ) ( I pk - I min ) --------------------------- = ---------------------------------------------------- ----------------------------------------------T L ( V IN - V SW + V D ) 2
13
RC5042
PRODUCT SPECIFICATION
where: * Vin = input voltage to Converter * VSW = voltage across Switcher (MOSFET) = ILOAD x RDS(ON) * VD = Forward Voltage of the Schottky diode * T = the switching period of the converter = 1/fS, where fS = switching frequency. For an input voltage of 5V, an output voltage of 3.3V, an inductor value of 1.3mH and a switching frequency of 650KHz (using CEXT=39pF), the inductor current can be calculated as follows:
( I pk - I min ) ( 5.0 - 14.5 0.037 - 3.3 ) --------------------------- = ------------------------------------------------------------- -6 2 1.3 10 ( 3.3 + 0.5 ) 1 ------------------------------------------------------------- ----------------------- = 1.048A ( 5.0 - 14.5 0.037 + 0.5 ) 650 10 3
Therefore, the peak current, IPK, through the inductor for a 14.5A load is found to be:
( I PK - I min ) I SC I inductor = I Load, max + ---------------------------- = 14.5 + 1 = 15.5A 2
As a result, the short circuit detection threshold must be at least 15.5A. The next step is to determine the value of the sense resistor. Including sense resistor tolerance, the sense resistor value can be approximated as follows:
V th,min V th,min R SENSE = --------------- ( 1 - TF ) = ---------------------------------- ( 1 - TF ) I SC 1.0 + I Load,max
Where TF = Tolerance Factor for the sense resistor. There are several different type of sense resistors. Table 7 describes tolerance, size, power capability, temperature coefficient and cost of various type of sense resistors:
Table 7. Comparison of Sense Resistors1
Discrete Iron Alloy resistor (IRC) 5% (1% available) Discrete Metal Strip surface mount resistor (Dale) 1% Discrete MnCu Alloy wire resistor 10% Discrete CuNi Alloy wire resistor (Copel) 10%
Description Tolerance Factor (TF) Size (L x W x H)
Motherboard Trace Resistor 29%
2" x 0.2" x 0.001" (1 oz Cu trace)
0.45" x 0.065" x 0.25" x 0.125" x 0.200" 0.025" 1 watt (3W and 5W available) +30 ppm $0.31 1 watt
0.200" x 0.04" x 0.160" 1 watt
0.200" x 0.04" x 0.100" 1 watt
Power capability >50A/in
Temperature Coefficient Cost @10,000 piece
+4,000 ppm Low included in motherboard
75 ppm $0.47
30 ppm $0.09
20 ppm $0.09
Notes: 1. Refer to Appendix A for Directory of component suppliers
Based on the Tolerance in the above table, For Embedded PC Trace Resistor and for Iload,max = 14.5A:
V th,min R SENSE = ---------------------------------------- ( 1 - TF ) 1.0A + I Load, max 100mV = --------------------------------- ( 1 - 29% ) = 4.6mW 1.0A + 14.5A
For user convenience, Table 8 lists recommended value for sense resistor for various load current using embedded PC trace resistor or discrete resistor.
Table 8. Rsense for Various Load Current
ILoad,max (A) 10.00 11.20 12.40 13.90 14.00 14.50 RSENSE PC Trace Resistor (mW) 6.5 5.8 5.3 4.8 4.7 4.6 RSENSE Discrete Resistor (mW) 8.6 7.8 7.1 6.4 6.3 6.1
For discrete resistor and Iload, max = 14.5A:
R SENSE V th,min = ---------------------------------------- ( 1 - TF ) 1.0A + I Load, max
100mV = --------------------------------- ( 1 - 5% ) = 6.1mW 1.0A + 14.5A
14
PRODUCT SPECIFICATION
RC5042
RC5042 Short Circuit Current Characteristics
The RC5042 has a short circuit current characteristic that includes a hysteresis function that prevents the DC-DC converter from oscillating in the event of a short circuit. A typical V-I characteristic of the DC-DC converter output is presented in the Typical Operating Characteristics section, page 5. The converter performs with a normal load regulation characteristic until the voltage across the resistor reaches the internal short circuit threshold of 120mV. At this point, the internal comparator trips and sends a signal to the controller to turn off the gate drive to the power MOSFET. This causes a drastic reduction in the output voltage as the load regulation collapses into the short circuit mode of control. The output voltage will not return to the normal load characteristic until the output short circuit current is reduced to within the safe range for the DC-DC converter.
The higher the input capacitance, the more charge storage is available for improving the current transfer through the FET. Low "ESR" capacitors are best suited for this type of application and can influence the converter's efficiency if not chosen carefully. The input capacitor should be placed as close to the drain of the FET as possible to reduce the effect of ringing caused by long trace lengths. The ESR rating of a capacitor is a difficult number to quantify. ESR or Equivalent Series Resistance, is defined as the resonant impedance of the capacitor. Since the capacitor is actually a complex impedance device having resistance, inductance and capacitance, it is quite natural for this device to have a resonant frequency. As a rule, the lower the ESR, the better suited the capacitor is for use in switching power supply applications. Many capacitor manufacturers do not supply ESR data. A useful estimate of the ESR can be obtained using the following equation:
DF ESR = -----------2pfC
Schottky Diode Selection
The application circuit diagram of Figure 1 shows two Schottky diodes, DS1 and DS2. In synchronous mode, DS1 is used in parallel with M3 to prevent the lossy diode in the FET from turning on. DS2 serves a dual purpose. As configured, it allows the VCCQP supply pin of the RC5042 to be bootstrapped up to 9V using capacitor C12. When the lower MOSFET M3 is turned on, one side of capacitor C12 is connected to ground while the other side of the capacitor is being charged up to voltage VIN - VD through DS2. The voltage that is then applied to the gate of the MOSFET is VCCQP - VSAT, or typically around 9V. A vital selection criteria for DS1 and DS2 is that they exhibit a very low forward voltage drop, as this parameter can directly affect the regulator efficiency. In non-synchronous mode, DS1 is used as a flyback diode to provide a constant current path for the inductor when M1 is turned off. Table 9 lists several suitable Schottky diodes. Note that the MBR2015CTL has a very low forward voltage drop. This diode is most ideal for application where output voltage is required to be less than 2.8V.
Where: * DF is the dissipation factor of the capacitor * f is the operating frequency * C is the capacitance in farads With this in mind, correct calculation of the output capacitance is crucial to the performance of the DC-DC converter. The output capacitor determines the overall loop stability, output voltage ripple and load transient response. The calculation is as follows:
I O DT C ( mF ) = ------------------------------------DV - I O ESR
Where DV is the maximum voltage deviation due load transient DT is reaction time of the power source (Loop response time of the RC5042) and it is approximately 8ms IO is the output load current For IO = 10A, and DV = 75mV, the bulk capacitor required can be approximated as follows:
I O DT 10A 8ms C ( mF ) = ------------------------------------- = -------------------------------------------------- = 3200mF DV - I O ESR 75mV - 10A 5mW
Table 9. Schottky Diode Selection Table
Manufacturer Model # Philips PBYR1035 Motorola MBR2035CT Motorola MBR1545CT Conditions IF = 20A; Tj = 25C IF = 20A; Tj = 125C IF = 20A; Tj = 25C IF = 20A; Tj = 125C IF = 15A; Tj = 25C IF = 15A; Tj = 125C Forward Voltage VF < 0.84V < 0.72V < 0.84V < 0.72V < 0.84V < 0.72V < 0.58V < 0.48V
Input filter
We recommend that the design include an input inductor between the system +5V supply and the DC-DC converter input described below. This inductor will serve to isolate the +5V supply from noise occurring in the switching portion of the DC-DC converter and to also limit the inrush current into the input capacitors on power up. We recommend a value of around 2.5mH.
Motorola IF = 20A; Tj = 25C MBR2015CTL IF = 20A; Tj = 150C
Output Filter Capacitors
Optimal ripple performance and transient response are functions of the filter capacitors used. Since the 5V supply of a PC motherboard may be located several inches away from the DC-DC converter, input capacitance can play an important role in the load transient response of the RC5042.
15
RC5042
PRODUCT SPECIFICATION
5V
2.5H
Vin
0.1F
1000F, 10V Electrolytic
In general, all of the noisy switching lines should be kept away from the quiet analog section of the RC5042. That is to say, traces that connect to pins 8 and 9 (HIDRV and VCCQP) should be kept far away from the traces that connect to pins 1 through 4, and pin 12. 2. Place decoupling capacitors (.1mF) as close to the RC5042 pins as possible. Extra lead length on these will negate their ability to suppress noise. Each VCC and GND pin should have its own via down to the appropriate plane underneath. This will help give isolation between pins. Surround the CEXT timing capacitor with a ground trace as much as possible. Also be sure to keep a ground or power plane underneath the capacitor for further noise isolation. This will help to shield the oscillator pin 1 from the noise on the PCB. Place this capacitor as close to the RC5042 pin 1 as possible. Place MOSFETs, inductor and Schottky as close together as possible for the same reasons as #1 above. Place the input bulk capacitors as close to the drains of MOSFETs as possible. In addition, placement of a 0.1mF decoupling cap right on the drain of each MOSFET will help to suppress some of the high frequency switching noise on the input of the DC-DC converter. The traces that run from the RC5042 IFB (pin 3) and VFB (pin 4) pins should be run together next to each other and be Kelvin connected to the sense resistor. Running these lines together will help in rejecting some of the common noise that is presented to the RC5042 feed-
65-AP42-17
Figure 8. Input Filter
3.
PCB Layout Guidelines and Considerations
4.
PCB Layout Guidelines
1. Placement of the MOSFETs relative to the RC5042 is critical. The MOSFETs (M1 & M2), should be placed such that the trace length of the HIDRV pin from the RC5042 to the FET gates is minimized. A long lead length on this pin will cause high amounts of ringing due to the inductance of the trace combined with the large gate capacitance of the FET. This noise will radiate all over the board, and because it is switching at such a high voltage and frequency, it will be very difficult to suppress. The drawing below depicts an example of good placement for the MOSFETs in relation to the RC5042 and also an example of problematic placement for the MOSFETs.
5.
6.
M1
M2
Correct layout
9 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1
Poor layout
9 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1
= "Quiet" Pins
M1
M2
Figure 9. MOSFET Layout Guidelines
16
PRODUCT SPECIFICATION
RC5042
back input. Try as much as possible to run the noisy switching signals (HIDRV & VCCQP) on one layer; and use the inner layers for only power and ground. If the top layer is being used to route all of the noisy switching signals, use the bottom layer to route the analog sensing signals VFB and IFB.
Example of a Layout on a PC Motherboard and Gerber File
A reference design for motherboard implementation of the RC5042 along with Layout Gerber File and Silk Screen are presented here. The actual Gerber File can be obtained from a Fairchild Semiconductor local Sales Rep Office or from Fairchild Semiconductor Marketing Department at (415) 966-7819.
17
RC5042
PRODUCT SPECIFICATION
RC5042 Evaluation Board
Fairchild Semiconductor provides an evaluation board for the purpose of verifying the system level performance of the RC5042. The evaluation board serves as a guide as to what can be expected in performance with the supplied external components and PCB layout. Please call your Fairchild Semiconductor local Sales Rep Office or Fairchild Semiconductor Marketing Department at (650) 966-7819 for an evaluation board.
Additional Application Information
A comprehensive Application Note providing implementation guidelines for the RC5040 and RC5042 DC-DC Converters for Pentium(R) Pro processors (AP-42) is available from your local Fairchild Semiconductor Sales Rep or from Fairchild Semiconductor Marketing at 650-966-7819. Most application notes and data sheets can also be obtained by calling Fairchild Semiconductor's fax-on-demand system at 650-988-2123.
18
PRODUCT SPECIFICATION
RC5042
Mechanical Dimensions - 16 Lead SOIC
Symbol A A1 B C D E e H h L N a ccc Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
.053 .069 .004 .010 .013 .020 .008 .010 .386 .394 .150 .158 .050 BSC .228 .010 .016 16 0 -- 8 .004 .244 .020 .050
1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 9.80 10.00 3.81 4.00 1.27 BSC 5.80 0.25 0.40 16 0 -- 8 0.10 6.20 0.50 1.27
3 6
16
9
E
H
1
8
D A1 A SEATING PLANE -C- LEAD COPLANARITY ccc C a
h x 45 C
e
B
L
19
RC5042
PRODUCT SPECIFICATION
Ordering Information
Product Number RC5042M Package 16 pin SOIC
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 7/24/98 0.0m 002 Stock#DS30005042 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
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RC5050
Programmable DC-DC Converter for Low Voltage Microprocessors
Features
* * * * * * * * * * Programmable output from 1.3V to 3.5V 85% efficiency typical 1% output accuracy Oscillator frequency adjustable from 80KHz to 1MHz On-chip Power Good and Enable functions Over-Voltage Protection Foldback current limiting Precision trimmed low TC voltage reference 20 pin SOIC package Meets Intel Pentium(R) II specifications using minimum number of external components
Description
The RC5050 is a DC-DC controller IC which provides an accurate, programmable output for all Pentium II CPU applications. The RC5050 uses a 5-bit D/A converter to program the output voltage from 1.3V to 3.5V. The RC5050 uses a high level of integration to deliver load currents in excess of 15A from a 5V source with minimal external circuitry. Nonsynchronous operation allows a low cost solution for most CPU power supply applications. The internal oscillator can be programmed from 80KHz to 1MHz for additional flexibility in choosing external components. An on-board precision low TC reference achieves tight tolerance voltage regulation without expensive external components. The RC5050 also offers integrated functions including Power Good, Output Enable, over-voltage protection and current limiting.
Applications
* Programmable power supply for Pentium II * Voltage Regulator Module (VRM) for Pentium II processors * Programmable step-down power supply
Block Diagram
+12V RC5050 OSC
- +
+5V
- +
- +
- +
DIGITAL CONTROL
VO
VREF
5-BIT DAC
1.24V REFERENCE
POWER GOOD
PWRGD
65-5050-01
VID0 VID2 VID4 VID1 VID3
ENABLE
Pentium is a registered trademark of Intel Corporation.
Rev. 1.2.1
RC5050
PRODUCT SPECIFICATION
Pin Assignments
CEXT ENABLE PWRGD IFB VFB VCCA VCCD VID4 NC GNDP
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
65-5050-02
VID0 VID1 VID2 VID3 VREF GNDA GNDD VCCQP HIDRV NC
Pin Definitions
Pin Number 1 Pin Name CEXT Pin Function Description Oscillator Capacitor Connection. Connecting an external capacitor to this pin sets the internal oscillator frequency. Layout of this pin is critical to system performance. See Application Information for details. Output Enable. Open collector/TTL input. Logic LOW will disable output. A 10KW internal pull-up resistor assures correct operation if pin is left unconnected.
2 3 4
ENABLE
PWRGD Power Good Flag. Open collector output will be at logic HIGH under normal operation. Logic LOW indicates output voltage is not within 12% of nominal. IFB High Side Current Feedback. Pins 4 and 5 are used as the inputs for the current feedback control loop and as the short circuit current sense points. Layout of these traces is critical to system performance. See Application Information for details. Voltage Feedback. Pin 5 is used as the input for the voltage feedback control loop and as the low side current feedback input. Layout of this trace is critical to system performance. See Application Information for details. Analog Vcc. Connect to system 5V supply and decouple to ground with 0.1mF ceramic capacitor. Digital Vcc. Connect to system 5V supply and decouple to ground with 4.7mF tantalum capacitor. VID4 Input. A logic 1 on this open collector/TTL input will enable the VID3-VID0 inputs to set the output from 2.1V to 3.5V, and a logic 0 on this pin will set the output from 1.3V to 2.05V, as shown in Table 1. Pullup resistors are internal to the controller. No Internal Connection. Connection of these pins to system ground will improve the thermal dissipation characteristics of the package. Power Ground. Return pin for high currents flowing in pins 12 and 13 (HIDRV and VCCQP). Connect to low impedance ground. FET Driver Output. Connect this pin to the gates of N-channel MOSFETs M1 and M2 in Figure 1. The trace from this pin to the MOSFET gates should be < 0.5". Power Vcc. This is the power supply for the FET driver. VCCQP must be connected to a voltage of at least VCCA + VGS,ON (M1). See Application Information for details. Digital Ground. Return path for digital logic. This pin should be connected to system ground to minimize ground loops. Analog Ground. Return path for low power analog circuitry. Connect to system ground to minimize ground loops. Reference Voltage Test Point. This pin provides access to the DAC output and should be decoupled to ground using a 0.1mF capacitor. No load should be connected. Voltage Identification (VID) Code Inputs. These open collector/TTL compatible inputs will program the output voltage over the ranges specified in Table 1. Pullup resistors are internal to the controller.
5
VFB
6 7 8
VCCA VCCD VID4
9, 11 10 12 13 14 15 16 17-20
NC GNDP HIDRV VCCQP GNDD GNDA VREF VID3- VID0
2
PRODUCT SPECIFICATION
RC5050
Absolute Maximum Ratings
Supply Voltages, VCCA, VCCD, VCCQP Voltage Identification Code Inputs, VID4-VID0 Junction Temperature, TJ Storage Temperature Lead Soldering Temperature, 10 seconds 13V 13V 150C -65 to 150C 300C
Operating Conditions
Parameter Supply Voltages, VCCA and VCCD Output Driver Supply, VCCQP Input Logic HIGH Input Logic LOW PWRGD Threshold Ambient Operating Temperature Logic HIGH Logic LOW 93 88 0 Conditions Min. 4.5 8.5 2.0 0.8 107 112 70 Typ. 5 Max. 7 12 Units V V V V %VO %VO C
Electrical Characteristics
(VCCA, VCCD = 5V, VOUT = 2.8V, Fosc = 300 KHz, and TA = +25C using Figure 1, unless otherwise specified) The * denotes specifications which apply over the full operating temperature range. Parameter Output Voltage Output Current Initial Voltage Setpoint Output Temperature Drift Load Regulation Line Regulation Output Ripple Output Voltage Regulation Steady State1 Transient2 Short Circuit Detect Threshold Efficiency Output Driver Rise and Fall Time Turn-on Response Time Oscillator Range Oscillator Frequency Max Duty Cycle CEXT = 100 pF PWM mode ILOAD = 13A, VOUT = 2.8V See Figure 2 ILOAD = 0 to 13A 80 270 90 300 300 95 ILOAD = 0.8A TA = 0 to 60C ILOAD = 0.8A to 13A VIN = 4.75 to 5.25V 20MHz BW, ILOAD = 13A VOUT = 2.8V, ILOAD = 0.8 - 15A ILOAD = 0.8 to 14.2A, 30A/ms * * * * 2.74 2.67 100 80 * * * Conditions See Table 1 * Min. 1.3 13 20 +10 -25 2 11 2.80 2.80 120 85 50 10 1000 330 2.90 2.93 140 Typ. Max. 3.5 Units V A mV mV mV mV mV V V mV % ns ms KHz KHz %
Notes: 1. Steady State Voltage Regulation includes Initial Voltage Setpoint, DC load regulation, output ripple/noise and temperature drift. 2. These specifications assume a minimum of 20, 1mF ceramic capacitors are placed directly next to the CPU in order to provide adequate high-speed decoupling. For motherboard applications, the PCB layout must exhibit no more than 0.5mW parasitic resistance and 1nH parasitic inductance between the converter output and the CPU.
3
RC5050
PRODUCT SPECIFICATION
Table 1. Output Voltage Programming Codes
VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 VOUT to CPU 1.30V 1.35V 1.40V 1.45V 1.50V 1.55V 1.60V 1.65V 1.70V 1.75V 1.80V 1.85V 1.90V 1.95V 2.00V 2.05V No CPU 2.1V 2.2V 2.3V 2.4V 2.5V 2.6V 2.7V 2.8V 2.9V 3.0V 3.1V 3.2V 3.3V 3.4V 3.5V
Note: 1. 0 = processor pin is tied to GND 1 = processor pin is open.
4
PRODUCT SPECIFICATION
RC5050
Typical Operating Characteristics
(VCCA, VCCD = 5V, fosc = 280 KHz, and TA = +25C using circuit in Figure 1, unless otherwise noted)
Efficiency vs. Output Current
92.0 90.0 VOUT = 3.3V 2.83 2.82 2.81 2.80 2.79 2.78 2.77 2.76 2.75 2.74 2.73
Load Regulation, VOUT = 2.8 V
Efficiency (%)
88.0 84.0 82.0 80.0 78.0 76.0 74.0 1 3 5 7 9 11 13 14.5
VOUT = 2.5V
VOUT (V)
86.0
VOUT = 2.8V
1
3
5
7
9
11
13
14.5
Output Current (A) Output Voltage vs. Output Current, RSENSE = 6m1/2
3.5 1250 3.0 2.5 1050 850 650 450 250 50 0 5 10 15 20 25 18 39
Output Current (A)
Oscillator Frequency vs. CEXT
2.0 1.5 1.0 0.5 0
Frequency (KHz)
VOUT (V)
75
150
300
561
Output Current (A)
CEXT (pf)
Output Programming, VID4 = 0
3.5 3.0 3.5 3.0
Output Programming, VID4 = 1
VOUT (V)
2.5 2.0 1.5 1.0 1.30
VOUT (V)
1.40 1.50 1.60 1.70 1.80 1.90 2.0
2.5 2.0 1.5 1.0
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5
DAC Set Point
DAC Set Point
65-5050-03
5
RC5050
PRODUCT SPECIFICATION
Typical Operating Characteristics (continued)
Output Ripple, 2.8V @ 13A Transient Response, 0.5A to 13A
VOUT (20mV/div)
VOUT (50mV/div)
Time (2s/division)
Time (50s/division)
Switching Waveforms, 0.5A Load
Switching Waveforms, 13A Load
500mV/div
500mV/div
CEXT pin
CEXT pin
20mV/div
HDRV pin
20mV/div
HIDRV pin
Time (2s/division)
Time (2s/division)
Output Startup, System Power-up
Output Startup from Re-enable
VOUT (1V/div)
ENABLE (1V/div)
VIN (1V/div )
VOUT (1V/div)
Time (10ms/division)
Time (10ms/division)
65-5050-04
6
PRODUCT SPECIFICATION
RC5050
Test Circuit
+12V L2 +5V 2.5H C4 0.1F CIN C5 0.1F R5 471/2 D1 1N4735A C8 0.1F C9 0.1F
M1 11 12 13 14 15 16 17 18 19 20 10 9 8 7 6 5 4 3 2 1 IRL3103
M2 IRL3103 L1 RSENSE* VO
C6 1F
C12 1F
1.3H DS1 MBR2015CTL
RC5050
VREF C7 GND 0.1F
COUT*
CEXT 100pF
VID4 VID3 VID2 VID1 VID0 C10 0.1F ENABLE C11 0.1F R6 10K1/2
VCC
PWRGD
*Refer to Table 2 for value of RSENSE, COUT, and CIN.
65-5050-12
Figure 1. 15A Application Circuit for Pentium II Processor
+12V 0.1F 471/2 1F VCCQP +5V 0.1F VCCA HIDRV RC5050 VCCD 4.7F GNDA GNDD GNDP
65-5050-11
tR HIDRV RISE/FALL 7000pF 10% 90% 50% 90% 50%
tF
10%
Figure 2. Output Driver Test Circuit
Table 2. Recommended Bulk Capacitors for CPU-based Applications
Application Motorola PowerPC 603/604 Motherboard Intel Pentium II Klamath Motherboard Intel Pentium II Motherboard (All versions including next generation) Output Current 7A CIN 2 x 1500mF, 6V Sanyo 6MV1500CX 3 x 1200mF, 10V Sayno 10MV1200EG 3 x 1200mF, 10V Sayno 10MV1200EG COUT 2 x 1500mF, 6V Sanyo 6MV1500SX 5 x 1500mF, 6.3V Sanyo 6MV1500GX 7 x 1500mF, 6.3V Sanyo 6MV1500GX COUT Maximum ESR 22mW RSENSE 10.5mW
14.2
9.0mW
5.5mW
15A
6.0mW
5.0mW
7
RC5050
PRODUCT SPECIFICATION
Table 3. RC5050 Application Bill of Materials for Intel Pentium II Processors
Reference C4, C5, C7-C11 Cext C12, C6 CIN COUT DS1 D1 L1 L2 M1, M2 Manufacturer Part # Panasonic ECU-V1H104ZFX Panasonic ECU-V1H121JCG Panasonic ECSH1CY105R Sanyo 10MV1200EG Sanyo 6MV1500GX Motorola MBR2015CT 1N4735A Skynet 320-8107 Skynet 320-6110 International Rectifier IRL3103 Copel AWG#18 Panasonic ERJ-6GEY050Y Panasonic ERJ-6ENF10.0KV Description 0.1mF 50V capacitor 100pF capacitor 1mF 16V capacitor 1200mF 10V electrolytic capacitor 10mm x 20mm 1500mF 6.3V electrolytic capacitor 10mm x 20mm Schottky Diode 6.2V Zener Diode, Motorola 1.3mH, 14A inductor DCR ~ 2.5mW 2.5mH, 11A inductor DCR ~ 6mW N-Channel Logic Level Enhancement Mode MOSFET 5.5mW CuNi Alloy Wire Resistor 47W 5% resistor 10KW 5% resistor See Note 2 See Note 3 RDS(ON) < 19mW VGS < 4.5V, ID = 15A See Note 4 ESR < 62mW See Table 2 ESR < 44mW See Note 1 and Table 2 Vf < 0.52 at If = 10A Requirements/Comments
RSENSE R5 R6
Notes: 1. In order to meet the voltage transient requirements for the Intel Pentium II Motherboard application, the equivalent ESR of the output capacitors must not exceed 7.5mW. In order to satisfy the specified Output Voltage Regulation requirements for VOUT = 1.8V at 15A for next generation processors, the output capacitors must exhibit no more than 6.0mW equivalent ESR for a motherboard application. The use of the capacitors recommended in Table 1 will address this and other voltage specifications without significant added cost, although it is left up to the user to specify the components used. Please refer to Application Bulletin 5 for additional considerations required to meet the Intel Pentium II voltage transient specifications. 2. To optimize a converter for 15A at 1.8V output, fSW = 300 kHz, change the value of L1 to 1.24mH. 3. Inductor L2 is recommended to isolate the 5V input supply from current surges caused by MOSFET switching. L2 is not required for normal operation and may be omitted if desired. 4. For 15A designs using IR3103 MOSFETs, heat sinks with thermal resistance QSA < 50C/W should be used.
Application Information
Simple Step-Down Converter
S1 L1 + VIN D1 C1 RL Vout -
65-5050-06
Figure 3 illustrates a step-down DC-DC converter with no feedback control. The derivation of the basic step-down converter will serve as a basis for the design equations for the RC5050. Referring to Figure 3, the basic operation begins by closing the switch S1. When S1 is closed, the input voltage VIN is impressed across inductor L1. The current flowing in this inductor is given by the following equation: ( V IN - V OUT )T ON I L = ---------------------------------------------L1 where TON is the duty cycle (the time when S1 is closed).
Figure 3. Simple Buck DC-DC Converter
8
PRODUCT SPECIFICATION
RC5050
When S1 opens, the diode D1 will conduct the inductor current and the output current will be delivered to the load according to the equation: V OUT ( T S - T ON ) I L = ------------------------------------------L1 where TS is the overall switching period and (TS - TON) is the time during which S1 is open. By solving these two equations, we can arrive at the basic relationship for the output voltage of a step-down converter: T ON V OUT = V IN ae ----------o e TS o In order to obtain a more accurate approximation for VOUT, we must also include the forward voltage VD across diode D1 and the switching loss, Vsw. After taking into account these factors, the new relationship becomes: T ON V OUT = ( V IN + V D - V SW ) ---------- - V D TS where VSW = MOSFET switching loss = IL * RDS,ON
The additional comparators in the analog control section set the point at which the max current comparator disables the output drive signals to the external power MOSFETs. The digital control block is designed to take the comparator inputs along with the main clock signal from the oscillator and provide the appropriate pulses to the HIDRV output pin that controls the external power MOSFET(s). The digital section was designed utilizing high speed Schottky transistor logic, thus allowing the RC5050 to operate at clock speeds as high as 1MHz.
High Current Output Drivers
The RC5050 contains a high current output driver which utilizes high speed bipolar transistors arranged in a push-pull configuration. This driver is capable of delivering 1A of current in less than 100ns. The driver's power and ground are separated from the overall chip power and ground for additional switching noise immunity. The output driver power supply, VCCQP, is derived from an external 12V supply through a 47W series resistor. The resulting voltage is sufficient to provide the gate-source voltage to the external MOSFET required in order to achieve a low RDS,ON.
Internal Voltage Reference
The reference included in the RC5050 is a precision bandgap voltage reference. The internal resistors are precisely trimmed to provide a near zero temperature coefficient (TC). Added to the reference output is the resulting output from an integrated 5-bit DAC. The DAC is provided in order to allow the DC-DC converter output to be directly programmable via a 5-bit digital input. When the VID4 pin is in the HIGH state, pins VID3-VID0 will scale the output voltage from 2V to 3.5V in 100mV increments. When the VID4 pin is pulled LOW, the output can be programmed from 1.3V to 2.05V in 50mV steps. For guaranteed stable operation under all operating conditions, a 0.1mF decoupling capacitor should be connected to the VREF pin. No load should be imposed upon this pin.
The RC5050 Controller
The RC5050 is a programmable DC-DC controller IC. When designed around the appropriate external components, The RC5050 can be configured to deliver more than 14.5A of output current. The RC5050 utilizes both current-mode and voltage-mode control to create an integrated step-down voltage regulator. During heavy loading conditions, the RC5050 functions as a PWM step down regulator. Under light loads, the controller goes into Pulse Frequency Modulation (PFM) or pulse-skipping mode. The controller will sense the load level and switch between the two modes automatically, thus optimizing its efficiency under all conditions.
Main Control Loop
For this discussion, refer to the Block Diagram on page 1 of the data sheet. The control loop of the regulator contains two main sections; the analog control block and the digital control block. The analog block consists of signal conditioning amplifiers feeding into a set of comparators which provide the inputs to the digital block. The signal conditioning section accepts inputs from the IFB (current feedback) and VFB (voltage feedback) pins and sets up two controlling signal paths. The voltage control path amplifies the VFB signal and presents the output to one of the summing amplifier inputs. The current control path takes the difference between the IFB and VFB pins and presents the resulting signal to another input of the summing amplifier. These two signals are then summed together with the slope compensation input from the oscillator. This output is then presented to a comparator, which provides the main PWM control signal to the digital control block.
Power Good (PWRGD)
The RC5050 Power Good function is designed in accordance with the Pentium II DC-DC converter specifications and provides a constant voltage monitor on the VFB pin. The internal circuitry compares the VFB signal to the VREF voltage and outputs an active-low interrupt signal to the CPU should the power supply voltage exceed 10% of its nominal setpoint. The Power Good flag provides no other control function to the RC5050.
Output Enable (ENABLE)
Intel specifications state that the DC-DC converter should accept an open collector signal for controlling the output voltage; a logic LOW on the ENABLE pin disables the output voltage. When disabled, the PWRGD output is in the low state.
9
RC5050
PRODUCT SPECIFICATION
Upgrade Present
Intel specifications state that the DC-DC converter should accept an open collector signal (UP#), used to indicate the presence of an upgrade processor. The typical state is high (standard processor). When in the low or ground state (OverDrive processor present), the output voltage must be disabled unless the converter can supply the OverDrive processor's power requirements. Because the RC5050 can supply the OverDrive processor requirements, the UP# signal is not required.
Design Considerations and Component Selection
MOSFET Selection
This application requires the use of N-channel, Logic Level Enhancement Mode Field Effect Transistors. Desired characteristics are as follows: * Low Static Drain-Source On-Resistance, RDS,ON< 37 mW (lower is better). * Low gate drive voltage, VGS 4.5V. * Power package with low Thermal Resistance. * Drain current rating of 20A minimum. * Drain-Source voltage > 15V The on-resistance (RDS,ON) is the primary parameter for MOSFET selection. The on-resistance determines the power dissipation of the MOSFET and therefore significantly affects the efficiency of the DC-DC Converter. Table 4 presents a list of suitable MOSFETs for this application.
Over-Voltage Protection
The RC5050 provides a constant monitor of the output voltage for protection against over voltage conditions. If the voltage at the VFB pin exceeds 20% of the selected program voltage, an over-voltage condition will be assumed and the RC5050 will disable the output drive signal to the external MOSFET(s).
Short Circuit Protection
A current sense methodology is implemented to disable the output drive signal to the MOSFET(s) when an over-current condition is detected. The voltage drop created by the output current flowing across a sense resistor is presented to an internal comparator. When the voltage developed across the sense resistor exceeds the 120 mV comparator threshold voltage, the RC5050 will reduce the output duty cycle to protect the power devices.
Two MOSFETs in Parallel
At higher load currents, it is recommend that two MOSFETs be used in parallel instead of a single MOSFET. Significant advantages are realized using two MOSFETs in parallel: * Significant reduction of power dissipation. Maximum current of 15A with one MOSFET: PMOSFET = (I2 RDS,ON)(Duty Cycle) = (15)2(0.050*)(2.8+0.4)/(5+0.4-0.35) = 7.1 W With two MOSFETs in parallel:
The DC-DC converter will return to normal operation after the fault has been removed, for either an over voltage or a short circuit condition.
Oscillator
The RC5050 oscillator section is implemented using a fixed current capacitor charging configuration. An external capacitor (CEXT) is used to preset the oscillator frequency between 80KHz and 1MHz. This scheme allows maximum flexibility in setting the switching frequency as well as in choosing external components. In general, a lower operating frequency will increase the peak ripple current flowing in the output inductor and thus require the use of a larger inductor value. Operation at lower frequencies also increases the amount of energy storage that must be provided by the bulk output capacitors during load transients due to the slower loop response of the controller. Additionally, the efficiency losses due to switching of the MOSFETs will increase as the operating frequency is increased. Therefore, efficiency will be optimized at lower operating frequencies. Due to the trend of increasing load current at lower supply voltages, an operating frequency of 300 KHz has been chosen to optimize efficiency while maintaining excellent output regulation and transient performance. 10
PMOSFET = (I2 RDS,ON)(Duty Cycle) = (15/2)2(0.037*)(2.8+0.4)/(5+0.4-0.35) = 1.3W/FET
* Note: RDS,ON increases with temperature. Assume RDS,ON = 25mW at 25C. RDS,ON can easily increase to 50mW at high temperature when using a single MOSFET. When using two MOSFETs in parallel, the temperature effects should not cause the RDS,ON to rise above the listed maximum value of 37mW.
* No added heat sink required. With power dissipation down to around one watt and with MOSFETs mounted flat on the motherboard, no external heat sink is required. The junction-to-case thermal resistance for the MOSFET package (TO-220) is typically at 2C/W and the motherboard serves as an excellent heat sink. * Higher current capability. With thermal management under control, this on-board DC-DC circuit is able to deliver load currents up to 15A with no performance or reliability concerns.
PRODUCT SPECIFICATION
RC5050
Table 4. MOSFET Selection Table
RDS, ON (mW) Manufacturer & Model # Fuji 2SK1388 Siliconix SI4410DY National Semiconductor NDP706AL NDP706AEL National Semiconductor NDP603AL National Semiconductor NDP606AL Motorola MTB75N03HDL Int. Rectifier IRLZ44 Int. Rectifier IRL3103S VGS=4.5V, ID=28A VGS=5V, ID=31A VGS=5V, ID=37.5A VGS=5V, ID=24A VGS=4.5V, ID=10A Conditions1 VGS=4V, ID=17.5A VGS=4.5V, ID=5A VGS=5V, ID=40A TJ =25C TJ =125C TJ =25C TJ =125C TJ =25C TJ =125C TJ =25C TJ =125C TJ =25C TJ =125C TJ =25C TJ =125C TJ =25C TJ =125C TJ =25C TJ =125C Typ. 25 37 16.5 28 13 20 31 42 22 33 6 9.3 -- -- -- Max. 37 -- 20 34 15 24 40 54 25 40 9 14 28 46 19 31 TO-220 TO-263 (D PAK)
2
Package TO-220 SO-8 (SMD) TO-220
Thermal Resistance FJA=75 FJA=50 FJA=62.5 FJC=1.5 FJA=62.5 FJC=2.5 FJA=62.5 FJC=1.5 FJA=62.5 FJC=1.0 FJA=62.5 FJC=1.0 FJA=62.5 FJC=1.0
TO-220 TO-220
TO-220
Note: 1. RDS,ON values at Tj = 125C for most devices were extrapolated from the typical operating curves supplied by the manufacturers and are approximations only.
MOSFET Gate Bias
Figure 4 illustrates how an external 12V supply is used to bias the output driver supply, VCCQP. A 47W resistor is used to limit the transient current into the VCCQP pin and a 1mF capacitor filter is used to filter the VCCQP supply. This method provides a sufficient gate-to-source bias voltage (VGS ) to the MOSFET, and therefore reduces the RDS,ON and the resulting power loss within the MOSFET. Figure 5 illustrates how the RDS,ON decreases dramatically as VGS increases. A 6.2V Zener (D1) is used to clamp the voltage at VCCQP to a maximum of 12V, thus ensuring that the absolute maximum voltage limit of the IC will not be exceeded.
+12V
+5V 471/2 D1 6.2V M1 HIDRV 1F PWM/PFM Control DS1 L1 RS VO CB
VCCQP
65-5050-07
Figure 4. MOSFET Gate Bias Configuration
11
RC5050
PRODUCT SPECIFICATION
0.1 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 1.5 2 2.5 3 3.5 4 5 6
Fuji Fuji 706A 706AEL
RDS,ON (W)
Choosing the value of the inductor is a tradeoff between allowable ripple voltage and required transient response. The system designer can choose any value within the allowed range in order to maximize either ripple or transient performance. The first order equation (close approximation) for minimum inductance is: ( V OUT - V IN ) V OUT ESR L min = ----------------------------------- -------------- ---------V IN Vr f where: * * * * VIN = Input Power Supply VOUT = Output Voltage f = DC/DC converter switching frequency ESR = Equivalent series resistance of all output capacitors in parallel * Vr = Peak to peak output ripple voltage budget.
7
8
9
10 11
Gate-Source Voltage, VGS (V)
Figure 5. RDS,ON vs. VGS for Selected MOSFETs
Converter Efficiency
Losses due to parasitic resistance in the switches, inductor coil and sense resistor dominate at high load current levels. The major loss mechanisms under heavy loads, in usual order of importance, are: * * * * * * * * MOSFET I2R losses Inductor coil losses Sense resistor losses Gate-charge losses Diode-conduction losses Transition losses Input capacitor losses Losses due to the operating supply current of the IC.
The first order equation for maximum allowed inductance is: ( V IN - V OUT )D m V tb L min = 2Co ---------------------------------------------------Ip2 where: * Co = The total output capacitance * Ip = Peak to peak load transient current * Vtb = The output voltage tolerance budget allocated to load transient * Dm = Maximum duty cycle for the DC/DC converter (usually 95%). Some margin should be maintained between Lmin and Lmax. Adding margin by increasing Lmax almost always adds expense since all the variables are predetermined by system performance except for Co, which must be increased to increase Lmax. Adding margin by decreasing Lmin can either be done by purchasing capacitors with lower ESR or by increasing the DC/DC converter switching frequency. The RC5050 is capable of running at high switching frequencies and provides significant cost savings for the newer CPU systems that typically run at high supply current.
The following sections provide details of these dominant loss components.
Selecting the Inductor
The inductor is one of the most critical components to be selected in the DC-DC converter application.. The critical parameters are inductance (L), maximum DC current (Io) and the DC coil resistance (Rl). The inductor core material is a crucial factor in determining the amount of current the inductor will be able to withstand. As with all engineering designs, tradeoffs exist between various types of core materials. In general, Ferrites are popular due to their low cost, low EMI properties and high frequency (>500KHz) characteristics. Molypermalloy powder (MPP) materials exhibit good saturation characteristics, low EMI and low hysteresis losses; however, they tend to be expensive and more effectively utilized at operating frequencies below 400KHz. Another critical parameter is the DC winding resistance of the inductor. This value should typically be reduced as much as possible, as the power loss in the DC resistance will degrade the efficiency of the converter by the relationship: PLOSS = IO2 x Rl.
Implementing Short Circuit Protection
Intel currently requires all power supply manufacturers to provide continuous protection against short circuit conditions that may damage the CPU. To address this requirement, Fairchild Semiconductor has implemented a current sense methodology to limit the power delivered to the load in the event of an overcurrent condition. The voltage drop created by the output current flowing across a sense resistor is presented to one terminal of an internal comparator with hysterisis. The other comparator terminal has a threshold voltage, nominally 120mV. Table 6 states the limits for the comparator threshold of the Switching Regulator.
12
PRODUCT SPECIFICATION
RC5050
Table 6. RC5050 Short Circuit Comparator Threshold Voltage
Short Circuit Comparator Vthreshold (mV) Typical Minimum Maximum 120 100 140
The calculation of this ripple current is as follows:
( V IN - V SW - V OUT ) ( V OUT + V D ) ( I pk - I min ) --------------------------- = ---------------------------------------------------- ---------------------------------------------- T L ( V IN - V SW + V D ) 2
where: * Vin = input voltage to converter * VSW = voltage across the MOSFET = ILOAD x RDS,ON * VD = Forward Voltage of the Schottky diode * T = the switching period of the converter = 1/fS, where fS = switching frequency. For an input voltage of 5V, an output voltage of 2.8V, an inductor value of 1.3mH and a switching frequency of 285KHz (using CEXT = 100pF), the inductor current can be calculated as follows: ( I pk - I min ) ( 5.0 - 14.5 0.037 - 2.8 ) --------------------------- = ------------------------------------------------------------- -6 2 1.3 10 1 ( 2.8 + 0.5 ) ------------------------------------------------------------- ----------------------- 3A ( 5.0 - 14.5 0.037 + 0.5 ) 285 10 3 Therefore, for a continuous load current of 14.5A, the peak current through the inductor, Ipk, is found to be:
( I PK - I min ) I SC I inductor = I Load, max + ---------------------------- = 14.5 + 3 = 17.5A 2
When designing the external current sense circuitry, the designer must pay careful attention to the output limitations during normal operation and during a fault condition. If the short circuit protection threshold current is set too low, the DC-DC converter may not be able to continuously deliver the maximum CPU load current. If the threshold level is too high, the output driver may not be disabled at a safe limit and the resulting power dissipation within the MOSFET(s) may rise to destructive levels. The design equation used to set the short circuit threshold limit is as follows: V th -, R SENSE = ------- where: I SC = Output short circuit current I SC ( I pk - I min ) I SC I inductor = I Load, max + --------------------------2 where Ipk and Imin are peak ripple current and Iload, max = maximum output load current The designer must also take into account the current (Ipk -Imin), or the ripple current flowing through the inductor under normal operation. Figure 6 illustrates the inductor current waveform for the RC5050 DC-DC converter at maximum load.
Ipk
For continuous operation at 14.5A, the short circuit detection threshold must be at least 17.5A. The next step is to determine the value of the sense resistor. Including tolerance, the sense resistor value can be approximated as follows:
V th,min V th,min R SENSE = --------------- ( 1 - TF ) = ---------------------------------- ( 1 - TF ) I SC 3.0 + I Load,max
I
(Ipk-Imin)/2 Imin TON T=1/f s TOFF I LOAD, MAX t
where TF = Tolerance Factor for the sense resistor. There are several different types of sense resistors. Table 7 describes tolerance, size, power capability, temperature coefficient and cost of various sense resistors.
Figure 6. Typical DC-DC Converter Inductor Current Waveform
13
RC5050
PRODUCT SPECIFICATION
Table 7. Comparison of Sense Resistors
Discrete Iron Alloy resistor (IRC) 5% (1% available) 0.45" x 0.065" x 0.200" 1 watt (3W and 5W available) +30 ppm $0.31 Discrete Metal Strip surface mount resistor (Dale) 1% 0.25" x 0.125" x 0.025" 1 watt 75 ppm $0.47 Discrete MnCu Alloy wire resistor 10% 0.200" x 0.04" x 0.160" 1 watt 30 ppm $0.09 Discrete CuNi Alloy wire resistor (Copel) 10% 0.200" x 0.04" x 0.100" 1 watt 20 ppm $0.09
Description Tolerance Factor (TF) Size (L x W x H) Power capability Temperature Coefficient Cost @10,000 piece
Motherboard Trace Resistor 29% 2" x 0.2" x 0.001" (1 oz Cu trace) >50A/in +4,000 ppm Low included in motherboard
Based on the Tolerance in the above table: * For an embedded PC trace resistor and Iload,max = 14.5A: V th,min R SENSE = ---------------------------------------- ( 1 - TF ) = 3.0A + I Load, max 100mV --------------------------------- ( 1 - 29% ) = 4.1mW 3.0A + 14.5A * For a discrete resistor and Iload, max = 14.5A: V th,min R SENSE = ---------------------------------------- ( 1 - TF ) = 3.0A + I Load, max 100mV --------------------------------- ( 1 - 5% ) = 5.4mW 3.0A + 14.5A For user convenience, Table 8 lists the recommended values for sense resistor values at various load currents using an embedded PC trace resistor or discrete resistor.
RC5050 Short Circuit Current Characteristics
The RC5050 has a short circuit current characteristic that includes a foldback function with hysteresis that prevents the DC-DC converter from oscillating in the event of a short circuit. A typical V-I characteristic of the DC-DC converter output using a sense resistor value of 6mW is presented in the Typical Operating Characteristics section, page 5. The converter performs with a typical voltage regulation characteristic until the voltage across the resistor exceeds the internal short circuit comparator threshold of 120mV. At this point, the internal comparator trips and sends a signal to the controller to turn off the gate drive to the power MOSFET. This causes a drastic reduction in the output voltage as the load regulation collapses into the short circuit control mode. The output voltage will not return to the normal load characteristic until the output short circuit current is reduced to within the safe range for the DC-DC converter.
Schottky Diode Selection
The application circuit of Figure 1 shows a Schottky diode, DS1. DS1 is used as a flyback diode to provide a constant current path for the inductor when M1 is turned off. A vital selection criteria for DS1 is that it exhibits a very low forward voltage drop, as this parameter will directly impact the regulator efficiency as the output voltage is reduced. Table 9 presents several suitable Schottky diodes for this application. Note that the diode MBR2015CTL has a very low forward voltage drop. This diode is most ideal for applications where output voltages below 2.8V are required.
Table 8. Rsense for Various Load Currents
ILoad,max (A) 10.0 11.2 12.4 13.9 14.0 14.5 RSENSE PC Trace Resistor (mW) 5.5 5.0 4.6 4.2 4.2 4.1 RSENSE Discrete Resistor (mW) 7.3 6.7 6.2 5.6 5.6 5.4
14
PRODUCT SPECIFICATION
RC5050
Table 9. Schottky Diode Selection Table
Manufacturer Model # Philips PBYR1035 Motorola MBR2035CT Motorola MBR1545CT Conditions IF = 20A; Tj=25C IF = 20A; Tj=125C IF = 20A; Tj=25C IF = 20A; Tj=125C IF = 15A; Tj=25C IF = 15A; Tj=125C Forward Voltage VF < 0.84V < 0.72V < 0.84V < 0.72V < 0.84V < 0.72V < 0.58V < 0.48V
where: * DV is the maximum voltage deviation due to load transients * DT is the reaction time of the power source (Loop response time of the RC5050), approximately 2ms * IO is the output load current. For IO = 12.2A (0.8 to 13A) and DV = 100mV, the bulk capacitance required can be approximated as follows:
I O DT 12.2 2ms C ( mF ) = ------------------------------------- = -------------------------------------------------------------- = 3200mF DV - I O ESR 100mV - 12.2A 7.5mW
Motorola IF = 20A; Tj=25C MBR2015CTL IF = 20A; Tj=150C
Input Filter
It is recommended that the design include an input inductor between the system +5V supply and the DC-DC converter input described below. This inductor will serve to isolate the +5V supply from noise occurring in the switching portion of the DC-DC converter and also to limit the inrush current into the input capacitors during power up. An inductor value of around 2.5mH is recommended, as illustrated below.
5V 2.5H Vin
Output Filter Capacitors
Optimal ripple performance and transient response are functions of the filter capacitors used. Since the 5V supply of a PC motherboard may be located several inches away from the DC-DC converter, input capacitance can play an important role in the load transient response of the RC5050. The higher the input capacitance, the more charge storage is available for improving the current transfer through the FET(s). Low "ESR" capacitors are best suited for this type of application and incorrect selection can influence the converter's overall performance. The input capacitor should be placed as close to the drain of the FET as possible to reduce the effect of ringing caused by long trace lengths. The ESR rating of a capacitor is a difficult number to quantify. ESR or Equivalent Series Resistance, is defined as the resonant impedance of the capacitor. Since the capacitor is actually a complex impedance device having resistance, inductance and capacitance, it is quite natural for this device to have a resonant frequency. As a rule, the lower the ESR, the better suited the capacitor is for use in switching power supply applications. Many capacitor manufacturers do not supply ESR data. A useful estimate of the ESR can be obtained using the following equation: DF ESR = -----------2pfC where: * DF is the dissipation factor of the capacitor * f is the operating frequency * C is the capacitance in farads. With this in mind, correct calculation of the output capacitance is crucial to the performance of the DC-DC converter. The output capacitor determines the overall loop stability, output voltage ripple and load transient response. The calculation is as follows: I O DT C ( mF ) = ------------------------------------DV - I O ESR
0.1F
1000F, 10V Electrolytic
65-5050-09
PCB Layout Guidelines and Considerations
PCB Layout Guidelines
1. Placement of the MOSFETs relative to the RC5050 is critical. The MOSFETs (M1 & M2), should be placed such that the trace length of the HIDRV pin from the RC5050 to the FET gates is minimized. A long lead length on this pin will cause high amounts of ringing due to the inductance of the trace combined with the large gate capacitance of the FET(s). This noise will radiate all over the board and will be very difficult to suppress, especially when the oscillator frequency is increased. Figure 7 depicts an example of proper placement of the MOSFETs in relation to the RC5050 as well as an example of incorrect placement of the MOSFETs. In general, all of the noisy switching lines should be kept away from the quiet analog section of the RC5050. That is to say, traces that connect to pins 12 and 13 (HIDRV and VCCQP) should be kept far away from the traces that connect to pins 1 through 5, and pin 16.
15
RC5050
PRODUCT SPECIFICATION
Correct layout
11 12 13 14 15 16 17 18 19 20 RC5050 10 9 8 7 6 5 4 3 2 1
Poor layout
11 12 13 14 15 16 17 18 19 20 RC5050 10 9 8 7 6 5 4 3 2 1
= "Quiet" Pins
65-5050-10
Figure 7. Examples of Good and Bad MOSFET Layout
2.
Place decoupling capacitors (0.1mF) as close to the RC5050 pins as possible. Extra lead length on these capacitors will negate their ability to suppress noise. Each VCC and GND pin should have its own via down to the appropriate plane underneath. This will help to add isolation between pins. The CEXT timing capacitor should be surrounded with a ground trace if possible. The placement of a ground or power plane underneath the capacitor will also provide further noise isolation. This will help to shield the oscillator from the noise on the PCB. This capacitor should be placed as close to pin 1 as possible. Group the MOSFETs, inductor and Schottky as close together as possible for the same reasons as #1 above. Also place the input bulk capacitors as close to the drains of MOSFETs as possible. In addition, placement of a 0.1mF decoupling cap right on the drain of each MOSFET will help to suppress some of the high frequency switching noise on the input of the DC-DC converter. The traces that run from the RC5050 IFB (pin 4) and VFB (pin 5) pins should be run together next to each other and be Kelvin connected to the sense resistor. Running these lines together will help in rejecting some of the common noise that is presented to the RC5050 feedback input. Try as much as possible to run the noisy switching signals (HIDRV & VCCQP) on one layer and use the inner layers for power and ground only. If the top layer is being used to route all of the noisy switching signals, use the bottom layer to route the analog sensing signals VFB and IFB.
PC Board Layout Checklist
* Bypass Capacitor near Vref pin. This pin should be adequately bypassed with a 0.1mF capacitor. * Bypass Capacitors for VCC (5V). A 0.1mF should be placed right next to the VCC pin of the controller. * Bypass Capacitors for Power MOSFET. A 0.1mF cap should be placed at the drain connection of each power MOSFET. * 5V Connection to the controller IC. Each VCC pin on the IC should be connected to the 5V power plane through its own via. * Power MOSFET Gate Drive Trace. - The gate drive trace should be routed on one layer only. - The controller IC and the power FET should be oriented in such a way as to minimize the trace length of the gate drive trace (< 1 inch). - The gate drive trace routing should stay away from the quiet analog section of the RC50XX controller IC. (i.e. keep away from Vref, IFB, VFB, and CEXT.) * Bulk Capacitance. - The input bulk capacitance needs to be located less than 1" from the drain of the power MOSFET. We recommend the following guidelines for the amount of bulk input capacitance: * For an output load of <10A use 2 X 1500mF caps. * For an output load of >10A use 3 X 1500mF caps. - The output bulk capacitors should be located as close to the CPU socket as possible. We recommend the following guidelines for the amount of bulk output capacitance: * For Pentium Pro use 4 X 1500mF. * For P55C MMX Pentium/ AMD K6 use 2X 1500mF. * For Pentium II use 7 X 1500mF.
3.
4.
5.
6.
16
PRODUCT SPECIFICATION
RC5050
* Inductor Location. The inductor should be located near to the Source of the Power MOSFET. The ideal condition would be to use an internal power plane to connect the Source of the power MOSFET, the inductor, and the flyback schottky diode together. * Sense Resistor. - The sense resistor should be located next to the inductor. - The two traces that run from the sense resistor to the RC50XX controller IC should be minimum width traces and be run parallel to each other. We recommend these sense resistor values: * For Pentium Pro use 0.006W. * For P55C MMX Pentium/ AMD K6 use 0.007W. * For Pentium II use 0.006W. * Ground Plane. The RC50XX controller IC have a continuous ground plane running underneath the entire chip area. Each of the IC ground pins should have a separate via connection down into the ground plane. * Input Filter. In many high current DC-DC converter designs, it is advisable to add an input inductor in order to create an input filter. An inductor on the order of 1-3uH is usually all that is required to perform the filter. When this component is added to the circuit, it is important that the RC50XX controller IC receive its VCC power from the system side of the input inductor and not the "dirty" side of the inductor. (ie the side that is connected to the power MOSFET drains)
* To Minimize Electromagnetic Interference (EMI). - Avoid long ground connections. Connect directly to the ground plane. - Use a star ground, where all grounds are connected to one point. - Use good quality inductors such as torrids or pot cores. Avoid rod inductors. - Route the high current carrying traces as power planes where possible. - Keep sensitive low-level signals away from the active switching components. Try to route them using the ground plane as a shield.
Example of a PC Motherboard Layout and Gerber File
A reference design for motherboard implementation of the RC5050 along with the Layout Gerber File and Silk Screen are presented below. The actual PCAD Gerber File can be obtained from a Fairchild Semiconductor local Sales Office or from Marketing at 650-966-7734.
RC5050 Evaluation Board
Fairchild Semiconductor provides an evaluation board for the purpose of verifying the system level performance of the RC5050. The evaluation board serves as a guide as to what can be expected in performance with the supplied external components and PCB layout. Please call your local Sales Office or Fairchild Semiconductor Marketing department at 650-966-7734 for an evaluation board.
17
RC5050
PRODUCT SPECIFICATION
18
PRODUCT SPECIFICATION
RC5050
Mechanical Dimensions - 20 Lead SOIC
Symbol A A1 B C D E e H h L N a ccc Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
.093 .104 .004 .012 .013 .020 .009 .013 .496 .512 .291 .299 .050 BSC .394 .010 .016 20 0 -- 8 .004 .419 .029 .050
2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 12.60 13.00 7.40 7.60 1.27 BSC 10.00 0.25 0.40 20 0 -- 8 0.10 10.65 0.75 1.27
3 6
20
11
E
H
1
10
D A e B A1 SEATING PLANE -C- LEAD COPLANARITY ccc C a
h x 45 C
L
19
RC5050
PRODUCT SPECIFICATION
Ordering Information
Product Number RC5050M Package 20 pin SOIC
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS30005050 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC5051
Programmable Synchronous DC-DC Controller for Low Voltage Microprocessors
Features
* Programmable output from 1.3V to 3.5V using an integrated 5-bit DAC * 85% efficiency typical * Adjustable operation from 80KHz to 1MHz * Integrated Power Good and Enable functions * Overvoltage protection * Overcurrent protection * Drives N-channel MOSFETs * 20 pin SOIC package * Meets Intel Pentium II specifications using minimum number of external components
Description
The RC5051 is a synchronous mode DC-DC controller IC which provides an accurate, programmable output voltage for all Pentium II CPU applications. The RC5051 uses a 5-bit D/A converter to program the output voltage from 1.3V to 3.5V. The RC5051 uses a high level of integration to deliver load currents in excess of 19A from a 5V source with minimal external circuitry. Synchronous-mode operation offers optimum efficiency over the entire specified output voltage range, and the internal oscillator can be programmed from 80KHz to 1MHz for additional flexibility in choosing external components. An on-board precision low TC reference achieves tight tolerance voltage regulation without expensive external components. The RC5051 also offers integrated functions including Power Good, Output Enable, over-voltage protection and current limiting.
Applications
* Power supply for Pentium(R) II * VRM for Pentium II processor * Programmable step-down power supply
Block Diagram
+12V RC5051
1
- +
+5V
5 4
OSC
- +
13 12
- +
- +
DIGITAL CONTROL
+5V
7 9
VO
VREF
16
5-BIT DAC
20 19 18 17 8
1.24V REFERENCE
POWER GOOD
2
3
PWRGD
65-5051-01
VID0 VID2 VID4 VID1 VID3
ENABLE
Pentium is a registered trademark of Intel Corporation.
Rev. 1.0.3
PRELIMINARY INFORMATION describes products that are not in full production at the time of printing. Specifications are based on design goals and limited characterization. They may change without notice. Contact Fairchild Semiconductor for current information.
RC5051
PRODUCT SPECIFICATION
Pin Assignments
CEXT ENABLE PWRGD IFB VFB VCCA VCCP VID4 LODRV GNDP
1 2 3 4 5 6 7 8 9 10 20 19 18 17
VID0 VID1 VID2 VID3 VREF GNDA GNDD VCCQP HIDRV GNDP
RC5051
16 15 14 13 12 11
65-5051-02
Pin Definitions
Pin Number Pin Name 1 CEXT Pin Function Description Oscillator Capacitor Connection. Connecting an external capacitor to this pin sets the internal oscillator frequency. Layout of this pin is critical to system performance. See Application Information for details. Output Enable. A logic LOW on this pin will disable the output. An internal pull-up resistor allows for either open collector or TTL compatibility. Power Good Flag. An open collector output that will be at logic LOW if the output voltage is not within 12% of the nominal output voltage setpoint. High Side Current Feedback. Pins 4 and 5 are used as the inputs for the current feedback control loop. Layout of these traces is critical to system performance. See Application Information for details. Voltage Feedback. Pin 5 is used as the input for the voltage feedback control loop and as the low side current feedback input. See Application Information for details regarding correct layout. Analog VCC. Connect to system 5V supply and decouple with a 0.1mF ceramic capacitor. Power VCC for low side FET driver. Connect to system 5V supply and place a 1mF ceramic capacitor for decoupling and local charge storage. VID4 Input. A logic 1 on this open collector/TTL input will enable the VID3-VID0 inputs to set the output from 2.1V to 3.5V, and a logic 0 will set the output from 1.3V to 2.05V, as shown in Table 1. Pullup resistors are internal to the controller. Low Side FET Driver. Connect this pin to the gate of an N-channel MOSFET for synchronous operation. The trace from this pin to the MOSFET gate should be < 0.5". Power Ground. Return pin for high currents flowing in pins 7 and 13 (VCCP and VCCQP). Connect to a low impedance ground. High Side FET Driver. Connect this pin to the gate of an N-channel MOSFET. The trace from this pin to the MOSFET gate should be < 0.5". Power VCC. For high side FET driver. VCCQP must be connected to a voltage of at least VCCA + VGS,ON (MOSFET), and place a 1mF ceramic capacitor for decoupling and local charge storage. See Application Information for details Digital Ground. Return path for digital logic. Connect to a low impedance system ground plane to minimize ground loops. Analog Ground. Return path for low power analog circuitry. This pin should be connected to a low impedance system ground plane to minimize ground loops. Reference Voltage Test point. This pin provides access to the DAC output and should be decoupled to ground using 0.1mF capacitor. No load should be connected.
2 3 4
ENABLE PWRGD IFB
5
VFB
6 7 8
VCCA VCCP VID4
9 10, 11 12 13
LODRV GNDP HIDRV VCCQP
14 15 16 17-20
GNDD GNDA VREF
VID0-VID3 Voltage Identification Code Inputs. These open collector/TTL compatible inputs will program the output voltage over the ranges specified in Table 1. Pull-up resistors are internal to the controller.
2
PRODUCT SPECIFICATION
RC5051
Absolute Maximum Ratings
Supply Voltages, VCCA, VCCP, VCCQP to GND Supply Voltage VCCQP, Charge Pump (VIN+VCCA) Voltage Identification Code Inputs, VID4-VID0 Junction Temperature, TJ Storage Temperature Lead Soldering Temperature, 10 seconds 13V 18V 13V 150C -65 to 150C 300C
Operating Conditions
Parameter Supply Voltage, VCCA, VCCP Input Logic HIGH Input Logic LOW Ambient Operating Temp Output Driver Supply, VCCQP PWRGD threshold Conditions Min. 4.75 2.0 0 8.5 93 88 Typ. 5 Max. 5.25 0.8 70 12 107 112 Units V V V C V %VOUT %VOUT
Logic High Logic Low
Electrical Specifications
(VCCA = 5V, VOUT = 2.8V, fosc = 300 KHz, and TA = +25C using circuit in Figure 1, unless otherwise noted) The * denotes specifications which apply over the full operating temperature range. Parameter Output Voltage Output Current Initial Voltage Setpoint Output Temperature Drift Load Regulation Line Regulation Output Ripple Total Output Variation Steady State1 Total Output Variation Transient2 Short Circuit Detect Threshold Efficiency Output Driver Rise and Fall Time Output Driver Deadtime 1 Output Driver Deadtime 2 Turn-on Response Time Oscillator Range Oscillator Frequency Max Duty Cycle Conditions See Table 1 ILOAD = 0.8A, VOUT = 2.8V VOUT = 2.0V TA = 0 to 70C VOUT = 2.8V VOUT = 2.0V ILOAD = 0.8A to 14.2A VIN = 4.75V to 5.25V 20MHz BW, ILOAD = 14.2A VOUT = 2.8V VOUT = 2.0V ILOAD = 0.8 to 14.2A, VOUT = 2.8V VOUT = 2.0V ILOAD = 14.2A, VOUT = 2.8V See Figure 2 See Figure 2 See Figure 2 ILOAD = 0A to 14.2A CEXT = 100 pF * * * * * * * * * * 2.740 1.940 2.670 1.900 100 120 82 80 5 80 * Min. 1.3 2.797 2.000 15 2.825 2.020 +16 +11 -20 2 13 2.900 2.060 2.930 2.100 140 Typ. Max. 3.5 2.853 2.040 Units V A V V mV mV mV mV mVpk V V V V mV % nsec %/fOSC nsec msec KHz KHz %
80 270 90
300 95
10 1000 330
Notes: 1. Steady Date Voltage Regulation includes Initial Voltage Setpoint, Load Regulation, Output Ripple and Output Temperature Drift and is measured at the converter's output capacitors. 2. As measured at the converter's output capacitors. For motherboard applications, the PCB layout should exhibit no more than 0.5mW trace resistance between the converter's output capacitors and the CPU.
3
RC5051
PRODUCT SPECIFICATION
Table 1. Output Voltage Programming Codes
VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 VOUT to CPU 1.30V 1.35V 1.40V 1.45V 1.50V 1.55V 1.60V 1.65V 1.70V 1.75V 1.80V 1.85V 1.90V 1.95V 2.00V 2.05V No CPU 2.1V 2.2V 2.3V 2.4V 2.5V 2.6V 2.7V 2.8V 2.9V 3.0V 3.1V 3.2V 3.3V 3.4V 3.5V
Note: 1. 0 = processor pin is tied to GND. 1 = processor pin is open.
4
PRODUCT SPECIFICATION
RC5051
Typical Operating Characteristics
(VCCA, VCCD = 5V, fOSC = 280 KHz, and TA = +25C using circuit in Figure 1, unless otherwise noted)
Efficiency vs. Output Current
88.0 86.0 2.83 2.82 2.81 2.80 2.79 2.78 2.77 2.76 2.75 2.74 2.73
Load Regulation, VOUT = 2.8 V
Efficiency (%)
84.0 80.0 78.0 76.0 74.0 72.0 70.0 1 3 5 7 9 11 13 14.5 VOUT = 2.0V VOUT = 2.8V
VOUT (V)
82.0
1
3
5
7
9
11
13
14.5
Output Current (A) Output Voltage vs. Output Current, RSENSE = 6m1/2
3.5 1250 3.0 2.5 1050 850 650 450 250 50 0 5 10 15 20 25 18 39
Output Current (A)
Oscillator Frequency vs. CEXT
2.0 1.5 1.0 0.5 0
Frequency (KHz)
VOUT (V)
75
150
300
560
Output Current (A)
CEXT (pf)
Output Programming, VID4 = 0
3.5 3.0 3.5 3.0
Output Programming, VID4 = 1
VOUT (V)
2.5 2.0 1.5 1.0 1.30
VOUT (V)
1.40 1.50 1.60 1.70 1.80 1.90 2.00
2.5 2.0 1.5 1.0
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5
DAC Set Point
DAC Set Point
65-5050-03
5
RC5051
PRODUCT SPECIFICATION
Typical Operating Characteristics (continued)
Output Ripple, 2.8V @ 14.2A Transient Response, 14.2A to 0.8A
2.10V
VOUT (20mV/div)
VOUT (50mV/div)
2.00V
1.90V
Time (1s/division)
Time (1s/division)
Transient Response, 0.8A to 14.2A
2.10V
VOUT (50mV/div)
2.00V
1.90V
Time (1s/division)
Switching Waveforms, 9A Load
Output Startup, System Power-up
HIDRV pin
LODRV pin
Time (1s/division)
VIN (1V/div )
2V/div
VOUT (1V/div)
5V/div
Time (2ms/division)
65-5051-12
6
PRODUCT SPECIFICATION
RC5051
Typical Operating Characteristics (continued)
Output Startup from Enable 3.18
VOUT (1V/div)
VREF Tempco
3.17 3.16 VREF (V) 3.15 3.14 3.13 3.12 3.11 0
Time (2ms/division)
ENABLE (1V/div)
25
70
100
Temperature (C)
Application Circuit
+12V L1 +5V C1 0.1mF 2.5mH CIN* C2 0.1mF R1 471/2 D1 1N4735A C6 0.1mF C5 1mF
R2 Q1 4.71/2 R3 Q2 4.71/2 L2 2.3H D2 1N5820 R SENSE* VO COUT*
VREF C3 0.1mF
11 10 9 12 8 13 14 7 15 6 RC5051 16 5 17 4 18 3 19 2 20 1 CEXT 100pF
C4 1mF
VID4 VID3 VID2 VID1 VID0 C8 0.1mF ENABLE C7 0.1mF R4 10K1/2 PWRGD VCC
*Refer to Table 3 for values of RSENSE, COUT, and CIN.
65-5051-03
Figure 1. 15A Application Circuit for Pentium II Processors
7
RC5051
PRODUCT SPECIFICATION
Table 2. RC5051 Application Bill of Materials for Intel Pentium II Processors
Reference C1-3, C6-C8 C4-5 Cext CIN COUT D1 D2 L1 L2 Q1-2 R1 R2-3 R4 RSENSE U1 Manufacturer Part # Panasonic ECU-V1H104ZFX Panasonic ECU-V1C105ZFX Panasonic ECU-V1H101JCG Sanyo 10MV1200GX Sanyo 6MV1500GX Motorola 1N4735A Motorola 1N5820 Skynet 320-6110 Any Fairchild FDP6030L or FDB6030L Any Any Any Fairchild RC10-XX* Fairchild RC5051M Quantity 6 2 1 * * 1 1 1 1 2 1 2 1 1 1 Description 100nF, 50V Capacitor 1mF, 16V Capacitor 100pF Capacitor 1200mF, 10V Electrolytic 1500mF, 6.3V Electrolytic 6.2V Zener Diode 3A Schottky Diode 2.5mH, 11A Inductor 2.3mH, 15A inductor N-Channel MOSFET (TO-220 or TO-263) 47W 4.7W 10KW CuNi Alloy Wire Resistor DC/DC Controller DCR ~ 6mW See Note 1. DCR ~ 3mW RDS(ON) = 20mW @ VGS = 4.5V See Note 2 5%, C0G IRMS = 2A ESR < 44mW Requirements/Comments
* See Table 3. Notes: 1. Inductor L1 is recommended to isolate the 5V input supply from noise generated by the MOSFET switching, and to comply with Intel dl/dt requirements. L1 may be omitted if desired. 2. For 14.2A designs using the FDP6030L MOSFETs, heatsinks with thermal resistance QSA < 20C/W should be used. For details and a spreadsheet on MOSFET selections, refer to Applications Bulletin AB-8.
8
PRODUCT SPECIFICATION
RC5051
Table 3. Recommended Values for CPU-based Applications
Output Current 13A COUT Maximum ESR* 6.1mW
Application 300MHz AMD K6 Motherboard 300 MHz Intel Pentium Motherboard 400MHz Intel Pentium II Motherboard
CIN 3 x 1200mF, 10V Sanyo 10MV1200GX 3 x 1200mF, 10V Sanyo 10MV1200GX 3 x 1200mF, 10V Sanyo 10MV1200GX
COUT* 2 x 1500mF, 6.3V Sanyo 6MV1500GX 7 x 1500mF, 6.3V Sanyo 6MV1500GX 7 x 1500mF, 6.3V Sanyo 6MV1500GX
RSENSE 5.8mW
14.2A
6.8mW
5.2mW
12.6A
6.3mW
5.8mW
* Output capacitance and ESR requirements depend critically on layout and processor type. Consult Application Bulletin AB-14 for details
Test Circuit
+12V 471/2 VCCQP +5V 0.1F VCCA HIDRV 4.71/2 3000pF 10% tDT1 3000pF 10% tDT2 1F tR 90% 50% 90% HIDRV 50% tF
VCCP LODRV 1F
4.71/2
50%
50%
LODRV
GNDA GNDD GNDP
65-5051-05
Figure 2. Output Drive Test Circuit and Timing Diagram
9
RC5051
PRODUCT SPECIFICATION
Application Information
The RC5051 Controller
The RC5051 is a programmable synchronous DC-DC controller IC. When designed around the appropriate external components, the RC5051 can be configured to deliver more than 19A of output current, as appropriate for the Klamath and Deschutes and other processors. The RC5051 functions as a fixed frequency PWM step down regulator.
VCCQP, which is supplied from an external 12V source through a series resistor or from a charge-pump circuit powered from 5V if 12V is not available. The LODRV driver has a power supply pin, VCCP, which can be supplied from either the 12V or 5V source. The resulting voltages are sufficient to provide the gate to source drive to the external MOSFETs required in order to achieve a low RDS,ON.
Internal Voltage Reference
The reference included in the RC5051 is a precision bandgap voltage reference. Its internal resistors are precisely trimmed to provide a near zero temperature coefficient (TC). Based on the reference is the output from an integrated 5-bit DAC. The DAC monitors the 5 voltage identification pins, VID0-VID4. When the VID4 pin is at logic HIGH, the DAC scales the reference voltage from 2.0V to 3.5V in 100mV increments. When VID4 is pulled LOW, the DAC scales the reference from 1.30V to 2.05V in 50mV increments. All VID codes are available, including those below 1.80V. For guaranteed stable operation under all loading conditions, 0.1mF of decoupling capacitance should be connected to the VREF pin. No load should be connected to VREF.
Main Control Loop
Refer to the RC5051 Block Diagram on page 1. The RC5051 implements "summing mode control", which is different from both classical voltage-mode and current-mode control. It provides superior performance to either by allowing a large converter bandwidth over a wide range of output loads. The control loop of the regulator contains two main sections: the analog control block and the digital control block. The analog section consists of signal conditioning amplifiers feeding into a set of comparators which provide the inputs to the digital control block. The signal conditioning section accepts inputs from the IFB (current feedback) and VFB (voltage feedback) pins and sets up two controlling signal paths. The first, the voltage control path, amplifies the difference between the VFB signal the reference voltage from the DAC and presents the output to one of the summing amplifier inputs. The second, current control path, takes the difference between the IFB and VFB pins and presents the resulting signal to another input of the summing amplifier. These two signals are then summed together with the slope compensation input from the oscillator. This output is then presented to a comparator, which provides the main PWM control signal to the digital control block. The digital control block takes the analog comparator inputs and the main clock signal from the oscillator to provide the appropriate pulses to the HIDRV and LODRV output pins. These two outputs control the external power MOSFETs. The digital block utilizes high speed Schottky transistor logic, allowing the RC5051 to operate at clock speeds as high as 1MHz. There are additional comparators in the analog control section whose function is to set the point at which the RC5051 enters its pulse skipping mode during light loads, as well as the point at which the current limit comparator disables the output drive signals to the external power MOSFETs.
Power Good (PWRGD)
The RC5051 Power Good function is designed in accordance with the Pentium II DC-DC converter specifications and provides a continuous voltage monitor on the VFB pin. The circuit compares the VFB signal to the VREF voltage and outputs an active-low interrupt signal to the CPU should the power supply voltage deviate more than 12% of its nominal setpoint. The Power Good flag provides no other control function to the RC5051.
Output Enable (ENABLE)
The RC5051 will accept an open collector/TTL signal for controlling the output voltage. The low state disables the output voltage. When disabled, the PWRGD output is in the low state. If an enable is not required in the circuit, this pin may be left open.
Over-Voltage Protection
The RC5051 constantly monitors the output voltage for protection against over voltage conditions. If the voltage at the VFB pin exceeds 20% of the selected program voltage, an over-voltage condition is assumed and the RC5051 disables the output drive signal to the external MOSFETs. The DCDC converter returns to normal operation after the fault has been removed.
High Current Output Drivers
The RC5051 contains two identical high current output drivers that utilize high speed bipolar transistors in a pushpull configuration. The drivers' power and ground are separated from the chip's power and ground for switching noise immunity. The HIDRV driver has a power supply pin,
Over-Current Protection
Current sense is implemented in the RC5051 to reduce the duty cycle of the output drive signal to the MOSFETs when an over-current condition is detected. The voltage drop created by the output current flowing across a sense resistor is presented to an internal comparator. When the voltage
10
PRODUCT SPECIFICATION
RC5051
developed across the sense resistor exceeds the 120mV comparator threshold voltage, the RC5051 reduces the output duty cycle to help protect the power devices. The DC-DC converter returns to normal operation after the fault has been removed.
MOSFET Gate Bias
The high side MOSFET gate driver can be biased by one of two methods-Charge Pump or 12V Gate Bias. The charge pump method has the advantage of requiring only +5V as an input voltage to the converter, but the 12V method will realize increased efficiency by providing an increased VGS to the high side MOSFETs.
Method 1. Charge Pump (Bootstrap)
Oscillator
The RC5051 oscillator section uses a fixed current capacitor charging configuration. An external capacitor (CEXT) is used to set the oscillator frequency between 80KHz and 1MHz. This scheme allows maximum flexibility in choosing external components. In general, a higher operating frequency decreases the peak ripple current flowing in the output inductor, thus allowing the use of a smaller inductor value. In addition, operation at higher frequencies decreases the amount of energy storage that must be provided by the bulk output capacitors during load transients due to faster loop response of the controller. Unfortunately, the efficiency losses due to switching of the MOSFETs increase as the operating frequency is increased. Thus, efficiency is optimized at lower frequencies. An operating frequency of 300KHz is a typical choice which optimizes efficiency and minimizes component size while maintaining excellent regulation and transient performance under all operating conditions.
Figure 3 shows the use of a charge pump to provide gate bias to the high side MOSFET when +12V is unavailable. Capacitor CP is the charge pump used to boost the voltage of the RC5051 output driver. When the MOSFET Q1 switches off, the source of the MOSFET is at approximately 0V because of the MOSFET Q2. (The Schottky D2 conducts for only a very short time, and is not relevent to this discussion.) CP is charged through the Schottky diode D1 to approximately 4.5V. When the MOSFET Q1 turns on, the voltage at the source of the MOSFET is equal to 5V. The capacitor voltage follows, and hence provides a voltage at VCCQP equal to almost 10V. The Schottky diode D1 is required to provide the charge path when the MOSFET is off, and reverses biases when VCCQP goes to 10V. The charge pump capacitor (CP) needs to be a high Q, high frequency capacitor. A 1mF ceramic capacitor is recommended here.
+5V D1 Q1 HIDRV CP L2 PWM/PFM Control LODRV GNDP Q2 D2
65-5051-06
Design Considerations and Component Selection
Additional information on design and component selection may be found in Fairchild Semiconductor's Application Note 53.
VCCQP
RS VO COUT
MOSFET Selection
This application requires N-channel Logic Level Enhancement Mode Field Effect Transistors. Desired characteristics are as follows: * Low Static Drain-Source On-Resistance, RDS,ON < 20mW (lower is better) * Low gate drive voltage, VGS = 4.5V rated * Power package with low Thermal Resistance * Drain-Source voltage rating > 15V. The on-resistance (RDS,ON) is the primary parameter for MOSFET selection. The on-resistance determines the power dissipation within the MOSFET and therefore significantly affects the efficiency of the DC-DC Converter. For details and a spreadsheet on MOSFET selection, refer to Applications Bulletin AB-8
Figure 3. Charge Pump Configuration Method 2. 12V Gate Bias
Figure 4 illustrates how a 12V source can be used to bias VCCQP. A 47W resistor is used to limit the transient current into the VCCQP pin and a 1mF capacitor is used to filter the VCCQP supply. This method provides a higher gate bias voltage (VGS) to the high side MOSFET than the charge pump method, and therefore reduces the RDS,ON and the resulting power loss within the MOSFET. In designs where efficiency is a primary concern, the 12V gate bias method is recommended. A 6.2V Zener diode, D1, is used to clamp the voltage at VCCQP to a maximum of 12V and ensure that the absolute maximum voltage of the IC will not be exceeded.
11
RC5051
PRODUCT SPECIFICATION
+5V +12V 471/2 D1
is capable of running at high switching frequencies and provides significant cost savings for the newer CPU systems that typically run at high supply current.
RC5051 Short Circuit Current Characteristics
VCCQP Q1 HIDRV 1F L2 PWM/PFM Control LODRV GNDP
65-5051-07
RS VO COUT
Q2
D2
Figure 4. Gate Bias Configuration
Inductor Selection
Choosing the value of the inductor is a tradeoff between allowable ripple voltage and required transient response. The system designer can choose any value within the allowed minimum to maximum range in order to either minimize ripple or maximize transient performance. The first order equation (close approximation) for minimum inductance is: L min ( V in - V out ) V out ESR = ------------------------------ ---------- ---------------V in V ripple f
The RC5051 short circuit current characteristic includes a hysteresis function that prevents the DC-DC converter from oscillating in the event of a short circuit. Figure 5 shows the typical characteristic of the DC-DC converter circuit with a 6.8 mW sense resistor. The converter exhibits a normal load regulation characteristic until the voltage across the resistor exceeds the internal short circuit threshold of 120mV (= 17.5A * 6.8mW). At this point, the internal comparator trips and signals the controller to reduce the converter's duty cycle to approximately 20%. This causes a drastic reduction in the output voltage as the load regulation collapses into the short circuit control mode. With a 40mW output short, the voltage is reduced to 15A * 40mW = 600mV. The output voltage does not return to its nominal value until the output current is reduced to a value within the safe operating range for the DC-DC converter.
Output Voltage vs. Output Current RSENSE = 6m1/2
3.5 3.0 2.5
OUT (V)
2.0 1.5
65-5051-08
where: Vin = Input Power Supply Vout = Output Voltage f = DC/DC converter switching frequency ESR = Equivalent series resistance of all output capacitors in parallel Vripple = Maximum peak to peak output ripple voltage budget. The first order equation for maximum allowed inductance is: ( V in - V out )D m V tb L max = 2C O ----------------------------------------------2 I PP where: Co = The total output capacitance Ipp = Maximum to minimum load transient current Vtb = The output voltage tolerance budget allocated to load transient Dm = Maximum duty cycle for the DC/DC converter (usually 95%). Some margin should be maintained away from both Lmin and Lmax. Adding margin by increasing L almost always adds expense since all the variables are predetermined by system performance except for Co, which must be increased to increase L. Adding margin by decreasing L can either be done by purchasing capacitors with lower ESR or by increasing the DC/DC converter switching frequency. The RC5051 12
1.0 0.5 0 0 5 10 15 20
25
Output Current (A) Figure 5. RC5051 Short Circuit Characteristic
Schottky Diode Selection
The application circuit of Figure 1 shows a Schottky diode, D2, which is used as a free-wheeling diode to assure that the body-diode in Q2 does not conduct when the upper MOSFET is turning off and the lower MOSFET is turning on. It is undesirable for this diode to conduct because its high forward voltage drop and long reverse recovery time degrades efficiency, and so the Schottky provides a shunt path for the current. Since this time duration is very short, the selection criterion for the diode is that the forward voltage of the Schottky at the output current should be less than the forward voltage of the MOSFET's body diode.
Output Filter Capacitors
The output bulk capacitors of a converter help determine its output ripple voltage and its transient response. It has already been seen in the section on selecting an inductor that the ESR helps set the minimum inductance, and the capacitance value helps set the maximum inductance. For most converters, however, the number of capacitors required is
PRODUCT SPECIFICATION
RC5051
determined by the transient response and the output ripple voltage, and these are determined by the ESR and not the capacitance value. That is, in order to achieve the necessary ESR to meet the transient and ripple requirements, the capacitance value required is already very large. The most commonly used choice for output bulk capacitors is aluminum electrolytics, because of their low cost and low ESR. The only type of aluminum capacitor used should be those that have an ESR rated at 100kHz. Consult Application Bulletin AB-14 for detailed information on output capacitor selection. The output capacitance should also include a number of small value ceramic capacitors placed as close as possible to the processor; 0.1mF and 0.01mF are recommended values.
.
Q1 L2 RSENSE RDROOP
VO
Q2 IFB VFB COUT
65-5051-14
Figure 7. Use of a Droop Resistor
PCB Layout Guidelines
* Placement of the MOSFETs relative to the RC5051 is critical. Place the MOSFETs such that the trace length of the HIDRV and LODRV pins of the RC5051 to the FET gates is minimized. A long lead length on these pins will cause high amounts of ringing due to the inductance of the trace and the gate capacitance of the FET. This noise radiates throughout the board, and, because it is switching at such a high voltage and frequency, it is very difficult to suppress. * In general, all of the noisy switching lines should be kept away from the quiet analog section of the RC5051. That is, traces that connect to pins 9, 12, and 13 (LODRV, HIDRV and VCCQP) should be kept far away from the traces that connect to pins 1 through 5, and pin 16. * Place the 0.1mF decoupling capacitors as close to the RC5051 pins as possible. Extra lead length on these reduces their ability to suppress noise. * Each VCC and GND pin should have its own via to the appropriate plane. This helps provide isolation between pins. * Surround the CEXT timing capacitor with a ground trace. Be sure to place a ground or power plane underneath the capacitor for further noise isolation, in order to provide additional shielding to the oscillator (pin 1) from the noise on the PCB. In addition, place this capacitor as close to pin 1 as possible. * Place the MOSFETs, inductor, and Schottky as close together as possible for the same reasons as in the first bullet above. Place the input bulk capacitors as close to the drains of the high side MOSFETs as possible. In addition, placement of a 0.1mF decoupling cap right on the drain of each high side MOSFET helps to suppress some of the high frequency switching noise on the input of the DC-DC converter. * Place the output bulk capacitors as close to the CPU as possible to optimize their ability to supply instantaneous current to the load in the event of a current transient. Additional space between the output capacitors and the CPU will allow the parasitic resistance of the board traces to degrade the DC-DC converter's performance under severe load transient conditions, causing higher voltage deviation. For more detailed information regarding capacitor placement, refer to Application Bulletin AB-5.
Input Filter
The DC-DC converter design may include an input inductor between the system +5V supply and the converter input as shown in Figure 6. This inductor serves to isolate the +5V supply from the noise in the switching portion of the DC-DC converter, and to limit the inrush current into the input capacitors during power up. A value of 2.5mH is recommended. It is necessary to have some low ESR aluminum electrolytic capacitors at the input to the converter. These capacitors deliver current when the high side MOSFET switches on. Figure 6 shows 3 x 1000mF, but the exact number required will vary with the speed and type of the processor. For the top speed Klamath and Deschutes, the capacitors should be rated to take 7A of ripple current. Capacitor ripple current rating is a function of temperature, and so the manufacturer should be contacted to find out the ripple current rating at the expected operational temperature. For details on the design of an input filter, refer to Applications Bulletin AB-15.
2.5H 5V 0.1F Vin 1000F, 10V Electrolytic
65-5051-09
Figure 6. Input Filter
Droop Resistor
Figure 7 shows a converter using a "droop resistor", RD. The function of the droop resistor is to improve the transient response of the converter, potentially reducing the number of output capacitors required. In operation, the droop resistor causes the output voltage to be slightly lower at heavy load current than it otherwise would be. When the load transitions from heavy to light current, the output can swing up farther without exceeding limits, because it started from a lower voltage, thus reducing the capacitor requirements.
13
RC5051
PRODUCT SPECIFICATION
* The traces that run from the RC5051 IFB (pin 4) and VFB (pin 5) pins should be run together next to each other and Kelvin connected to the sense resistor. Running these lines together rejects some of the common mode noise that is presented to the RC5051 feedback input. Try, as much as possible, to run the noisy switching signals (HIDRV, LODRV & VCCQP) on one layer, but use the inner layers for power and ground only. If the top layer is being used to route all of the noisy switching signals, use the bottom layer to route the analog sensing sign VFB and IFB. * A PC Board Layout Checklist is available from Fairchild Applications. Ask for Application Bulletin AB-11.
RC5051 Evaluation Board
Fairchild Semiconductor provides an evaluation board to verify the system level performance of the RC5051. It serves as a guide to performance expectations when using the supplied external components and PCB layout. Please call the marketing department at 650-968-9211 x 7833 for an evaluation board.
Additional Information
For additional information contact the Fairchild Semiconductor's Analog & Mixed Signal Products Group Marketing Department at 650-968-9211 x 7833.
PC Motherboard Sample Layout and Gerber File
A reference design for motherboard implementation of the RC5051 along with the PCAD layout Gerber file and silk screen can be obtained from our marketing department at 650-968-9211 x 7833.
14
PRODUCT SPECIFICATION
RC5051
Mechanical Dimensions - 20 Lead SOIC
Symbol A A1 B C D E e H h L N a ccc Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
.093 .104 .004 .012 .013 .020 .009 .013 .496 .512 .291 .299 .050 BSC .394 .010 .016 20 0 -- 8 .004 .419 .029 .050
2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 12.60 13.00 7.40 7.60 1.27 BSC 10.00 0.25 0.40 20 0 -- 8 0.10 10.65 0.75 1.27
3 6
20
11
E
H
1
10
D A e B A1 SEATING PLANE -C- LEAD COPLANARITY ccc C a
h x 45 C
L
15
RC5051
PRODUCT SPECIFICATION
Ordering Information
Product Number RC5051M Package 20 pin SOIC
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 6/4/98 0.0m 003 Stock#DS30005051 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC5052
High Performance Programmable Synchronous DC-DC Controller for Low Voltage Microprocessors
Features
* Programmable output from 1.3V to 3.5V using an integrated 5-bit DAC * Remote sense * Active Droop * 85% efficiency typical at full load * Integrated Power Good and Enable/Soft Start functions * Drives N-channel MOSFETs * Overcurrent protection using MOSFET sensing * 20 pin SOIC package * Meets Intel Pentium II specifications using minimum number of external components * Adjustable deadtime, frequency * Crowbar protection for overvoltage
Description
The RC5052 is a synchronous mode DC-DC controller IC which provides a highly accurate, programmable output voltage for all Pentium II & III CPU applications and other high-performance processors. The RC5052 features remote voltage sensing, adjustable current limit, and active droop for optimal converter transient response. The RC5052 uses a 5-bit D/A converter to program the output voltage from 1.3V to 3.5V. The RC5052 uses a high level of integration to deliver load currents in excess of 16A from a 5V source with minimal external circuitry. Synchronous-mode operation offers optimum efficiency over the entire specified output voltage range. An on-board precision low TC reference achieves tight tolerance voltage regulation without expensive external components, while active droop permits exact tailoring of voltage for the most demanding load transients. The RC5052 also offers integrated functions including Power Good, Output Enable/ Soft Start, current limiting, adjustable frequency, adjustable deadtime and overvoltage crowbar protection, and is available in a 20 pin SOIC package.
Preliminary Specification
Applications
* * * * * Power supply for Pentium(R) II & III VRM for Pentium II & III processor Telecom line cards Routers, switches & hubs Programmable step-down power supply
Block Diagram
+5V DTA 15 Rosc 1 VCCA 6 + 4 RS 13 5 11VCCQP 12 HIDRV +12V +5V
OSC +
Digital Control + + 10 9 LODRV 8 5-Bit DAC
20 19181716
VO
1.24V Reference 14 GNDA 2 ENABLE/SS
GNDP Power Good 7 OVP 3 PWRGD
VID0 VID2 VID4 VID1 VID3
Pentium is a registered trademark of Intel Corporation
Rev. 1.1.6
Preliminary Specification describes products that are not in full production at the time of printing. Specifications are based on design goals and limited characterization. They may change without notice. Contact Fairchild Semiconductor for current information.
RC5052
Pin Assignments
ROSC ENABLE/SS PWRGD IFB VFB VCCA OVP GNDP LODRV VCCP 1 2 3 4 5 6 7 8 9 10 20 19 18 VID0 VID1 VID2 VID3 VID4 DTA GNDA SW HIDRV VCCQP
RC5052
17 16 15 14 13 12 11
Pin Definitions
Preliminary Specification
Pin Number 1
Pin Name ROSC
Pin Function Description Oscillator Resistor Connection. Connect an external resistor to this pin to set the internal oscillator frequency. Layout of this pin is critical to system performance. See Application Information for details. Output Enable/Soft Start. A logic LOW on this pin will disable the output. An internal current source allows for open collector control. This pin also doubles as soft start. Power Good Flag. An open collector output that will be logic LOW if the output voltage is not within 12% of the nominal output voltage setpoint. Current Feedback. Pin 4 is used in conjunction with pin 13, as the input for the current feedback control loop. Layout of these traces is critical to system performance. See Application Information for details. Voltage Feedback. Pin 5 is used as the input for the voltage feedback control loop. See Application Information for details regarding correct layout. Analog VCC. Connect to system 5V supply and decouple with a 0.1F ceramic capacitor. Over Voltage Protection. This pin triggers the gate of an external SCR. Power Ground. Return pin for high currents flowing in pins 10 and 11. Connect to a low impedance ground. Low Side FET Driver. Connect this pin to the gate of an N-channel MOSFET for synchronous operation. The trace from this pin to the MOSFET gate should be <0.5". Power VCC. For low side FET driver. Connect to either system 12V supply or 5V supply, and decouple with a 4.7F tantalum and a 0.1F ceramic capacitor. High Side Power VCC. For high side FET driver. Connect to system 12V supply, and decouple with a 4.7F tantalum and a 0.1F ceramic capacitor. High Side FET Driver. Connect this pin to the gate of an N-channel MOSFET. The trace from this pin to the MOSFET gate should be <0.5". High side driver source and low side driver drain switching node. Together with IFB pin allows FET sensing for current. Analog Ground. Return path for low power analog circuitry. This pin should be connected to a low impedance system ground plane to minimize ground loops. Dead Time Adjust. Connect an external resistor to this pin to set the dead time. Voltage Identification Code Inputs. These open collector/TTL compatible inputs will program the output voltage over the ranges specified in Table 2. Pull-up resistors are internal to the controller.
2
ENABLE/SS
3 4
PWRGD IFB
5 6 7 8 9
VFB VCCA OVP GNDP LODRV
10 11 12 13 14 15 16-20
VCCP VCCQP HIDRV SW GNDA DTA VID0-4
2
RC5052
Absolute Maximum Ratings
Supply Voltages VCCA, VCCP, VCCQP to GND Supply Voltages (VCCQP, Charge Pump) Voltage Identification Code Inputs, VID0-VID4 Junction Temperature, TJ Storage Temperature Lead Soldering Temperature, 10 seconds Power Dissipation, PD Thermal Resistance Junction-to-case, JC 13.5V 18V VCCA 150C -65 to 150C 300C 750mW 105C/W
Recommended Operating Conditions
Parameter Supply Voltage VCCA Input Logic HIGH Input Logic LOW Ambient Operating Temperature Output Driver Supply, VCCP & VCCQP 0 11.4 12 Conditions Min. 4.75 2.0 0.8 70 13.2 Typ. 5 Max. 5.25 Units V V V C V
Preliminary Specification
3
RC5052
Electrical Specifications (VCCA = 5V, VCCP = VCCQP = 12V, VOUT = 2.0V, and TA = +25C using circuit in
Figure 1, unless otherwise noted.) The * denotes specifications which apply over the full operating temperature range. Parameter Output Voltage Output Current Initial Voltage Setpoint ILOAD = 0.8A, VOUT = 2.400V VOUT = 2.000V VOUT = 1.550V TA = 0 to 70C, VOUT = 2.000V VOUT = 1.550V VCCA = 4.75V to 5.25V, VOUT = 2.000V VOUT at ILOAD = 0.8A to Imax 20MHz BW, ILOAD = Imax VOUT = 2.000V VOUT = 1.550V3 ILOAD = 0.8A to Imax,VOUT = 2.000V VOUT = 1.550V3 ILOAD = Imax, VOUT = 2.0V See Figure 5 for tR and tF ROTA = OPEN. See Figure 5 for tDT ROSC = OPEN * 255 80 0 50 Logic HIGH Logic LOW * * * * Current4 * I = 1mA V = 1.5V 30 115 120 125 5 93 88 3.74 7.65 4 8.5 19 40 10 17 200 * * * * * 1.940 1.480 1.900 1.480 45 85 50 50 300 345 1000 100 120 107 112 4.26 9.35 * * * -44 2.397 2.000 1.550 See Table 1 Conditions * Min. 1.3 18 2.424 2.020 1.565 +8 +6 2 -40 11 2.070 1.590 2.100 1.590 60 -36 2.454 2.040 1.580 Typ. Max. 3.5 Units V A V V V mV mV mV mV mVpk V V A % nsec nsec kHz kHz % nsec %Vout V V mA mA A mV mA %Vout
Output Temperature Drift
Preliminary Specification
4
Line Regulation Internal Droop3 Output Ripple Total Output Variation, Steady State1 Total Output Variation, Transient2 Short Circuit Detect Current Efficiency Output Driver Rise & Fall Time Output Driver Deadtime Oscillator Frequency Oscillator Range Duty Cycle Dead Time Range PWRGD Threshold VCCA UVLO VCCP UVLO VCCA Supply Current VCCP Supply Soft Start Current OVP Output Low Voltage OVP Ouput High Current OVP Trigger Threshold
Notes: 1. Steady State Voltage Regulation includes Initial Voltage Setpoint, Droop, Output Ripple and Output Temperature Drift and is measured at the converter's VFB sense point. 2. As measured at the converter's VFB sense point. For motherboard applications, the PCB layout should exhibit no more than 0.5m trace resistance between the converter's output capacitors and the CPU. Remote sensing should be used for optimal performance. 3. Using the VFB pin for remote sensing of the converter's output at the load, the converter will be in compliance with Intel's VRM 8.4 specification of +50, -80mV. If Intel specifications on maximum plane resistance from the converter's output capacitors to the CPU are met, the specification of +40, -70mV at the capacitors will also be met. 4. Includes gate current.
RC5052
Table 1. Output Voltage Programming Codes VID4 VID3 VID2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
Nominal VOUT 1.30V 1.35V 1.40V 1.45V 1.50V 1.55V 1.60V 1.65V 1.70V
Preliminary Specification
1.75V 1.80V 1.85V 1.90V 1.95V 2.00V 2.05V 2.0V 2.1V 2.2V 2.3V 2.4V 2.5V 2.6V 2.7V 2.8V 2.9V 3.0V 3.1V 3.2V 3.3V 3.4V 3.5V
Note: 1. 0 = processor pin is tied to GND. 1 = processor pin is open.
5
RC5052
Typical Operating Characteristics (VCCA = 5V, VCCP = VCCQP = 12V, and TA = +25C using circuit
in Figure 1, unless otherwise noted.)
Efficiency vs. Output Current 88 86 84 82 80 78 76 74 72 70 68 66 64 0 3 VOUT = 2.000V 2.04 2.03 2.02 2.01 2.00 1.99 1.98 1.97 1.96 1.95 1.94 0 3
Droop, VOUT = 2.0V
Efficiency (%)
VOUT = 1.550V
Preliminary Specification
VOUT (V)
6
9
12
15
18
Output Current (A) 6 9 12 15 18 Output Current (A)
Output Voltage vs. Output Current 3.5 3.0 2.5 VOUT (V) 2.0 1.5 1.0 0.5 0 0 5 10 15 20 25 Output Current (A)
Output Programming, VID4 = 0 2.1 1.9 VOUT (V) VOUT (V) 1.7 1.5 1.3 1.1 1.30 3.5 3.0 2.5 2.0 1.5 1.0 1.40 1.50 1.60 1.70 1.80 1.90 2.00
Output Programming, VID4 = 1
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 DAC Setpoint
DAC Setpoint
6
RC5052
Typical Operating Characteristics (continued)
Output Ripple, 2.0V @ 18A Transient Res ponse, 12.5A to 0.5A
VOUT (20mV/div)
VOUT (50mV/div)
1.590V 1.550V 1.480V
Preliminary Specification
Time (1s/division)
Time (20s/division)
Transient Response, 0.5A to 12.5A
VOUT (50mV/div)
1.590V 1.550V 1.480V
Time (20s/division)
Switching Waveforms, 18A Load
Output Startup, System Power-up
5V/div
HIDRV pin
5V/ div
LODRV pin
Time (1s/division)
VOUT (1V/div)
VIN (2V/div)
Time (10ms/division)
7
RC5052
Typical Operating Characteristics (continued)
Output Startup from Enable 2.042 VOUT (1V/div) ENABLE (2V/div) 2.040 2.038 VOUT (V) 2.036 2.034 2.030 2.028 2.026 0 Time (10ms/division) 25 Temperature (C) 70 100 VOUT Temperature Variation
Preliminary Specification
Application Circuit
+12V F1* +5V CIN* R1 10 C5 1F C2 1F R2 4.7 Q1 C1 4.7F 11 12 13 14 15 16 17 18 19 20 10 9 8 7 6 5 4 3 2 1 R3 4.7 Q2 L2 1.3H VO D1 MBRD835L COUT* L1 (Optional) 2.5H
R6 10 Q3 2N6394
R8 (Optional) VID4 VID3 VID2 VID1 VID0
C3 0.1F
U1 RC5052
R5*
VCC R4 10K PWRGD C6 0.1F R7 (Optional)
*Refer to Table 3 for values of COUT, R5, F1 and CIN.
ENABLE/SS C4 0.1F
Figure 1. Application Circuit for Katmai, Mendocino, and Some Coppermine Processors (Worst Case Analyzed! See Appendix for Details)
8
RC5052
Table 2. RC5052 Application Bill of Materials for Intel Pentium II Processors (Components based on Worst Case Analysis--See Appendix for Details)
Reference C1 C2, C5 C3-4,6 CIN COUT D1 L1 L2 Q1
Manufacturer Part # AVX TAJB475M010R5 Panasonic ECU-V1C105ZFX Panasonic ECU-V1H104ZFX Sanyo 10MV1200GX Sanyo 6MV1500GX Motorola MBRD835L Any Any Fairchild FDP6030L or FDB6030L Fairchild FDP7030BL or FDB7030BL Motorola 2N6394 Any Any Any Any Any Any Littelfuse Fairchild RC5052M
Quantity 1 2 3 * * 1 Optional 1 1
Description 4.7F, 10V Capacitor 1F, 16V Capacitor 100nF, 50V Capacitor 1200F, 10V Electrolytic 1500F, 6.3V Electrolytic 8A Schottky Diode 2.5H, 10A Inductor 1.3H, 20A Inductor N-Channel MOSFET (TO-220 or TO-263) N-Channel MOSFET (TO-220 or TO-263) SCR 10 4.7 10K *
Requirements/Comments
IRMS = 2A ESR 44m
Preliminary Specification
DCR ~ 6m See Note 1. DCR ~ 2m RDS(ON) = 20m @ VGS = 4.5V See Note 2. RDS(ON) = 10m @ VGS = 4.5V See Note 2.
Q2
1
Q3 R1, R6 R2-3 R4 R5 R7 R8 F1 U1 *See Table 3.
1 2 2 1 1 Optional Optional 1 1
Sets frequency. Sets deadtime. * DC/DC Controller
Notes: 1. Inductor L1 is recommended to isolate the 5V input supply from noise generated by the MOSFET switching, and to comply with Intel dI/dt requirements. L1 may be omitted if desired. 2. For designs using the TO-220 MOSFETs, heatsinks with thermal resistance SA < 20C/W should be used. For designs using the TO-263 MOSFETs, adequate copper area should be used. For details and a spreadsheet on MOSFET selections, refer to Applications Bulletin AB-8.
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RC5052
Table 3. Recommended Values for CPU-based Applications
Processor Coppermine Katmai Mendocino Katmai
Chipset Whitney Camino Whitney BX
CIN 3 4 4 5
COUT* 4 6 5 6
R5 (K) 8.45 13.0 11.3 11.8
F1 (A) 5 10 10 10
* Output capacitance requirements depend critically on layout and processor type. Consult Application Bulletin AB-14 for details. See the Appendix to this datasheet for the method of calculation of these components. Pin 4 must be used to remote sense the voltage at the processor to achieve the specified performance.
+12V
Preliminary Specification
F1 5A +5V
L1 (Optional) 2.5H R1 10 C5 1F R5 2.80K R3 4.7 11 12 13 14 15 16 17 18 19 20 10 9 8 7 6 5 4 3 2 1 Q2 D2 1N4148 R2 4.7 R6 10 Q1 R10 10m C2 1F L2 1.3H R9 2.2m VO D1 MBRD835L COUT*
CIN*
Q3 2N6394
C1 4.7F
R8 (Optional) VID4 VID3 VID2 VID1 VID0
U1 RC5052
C3 0.1F
R11 2.1 R12 1K VCC
ENABLE/SS C4 0.1F R7 (Optional)
R4 10K PWRGD C6 0.1F
*Refer to Table 3 for values of COUT, and CIN.
Figure 2. Application Circuit for Coppermine/Camino Processors
(Worst Case Analyzed! See Appendix for Details)
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RC5052
Table 4. RC5052 Application Bill of Materials for Coppermine/Camino Processors
(Components based on Worst Case Analysis--See Appendix for Details) Reference C1 C2, C5 C3-4,6 CIN COUT D1 D2 L1 L2 Q1 Q2 Manufacturer Part # AVX TAJB475M010R5 Panasonic ECU-V1C105ZFX Panasonic ECU-V1H104ZFX Sanyo 10MV1200GX Sanyo 6MV1500GX Motorola MBRD835L Fairchild 1N4148 Any Any Fairchild FDP6030L or FDB6030L Fairchild FDP7030BL or FDB7030BL Motorola 2N6394 Any Any Any Any Any Any Any Dale WSL-2512-.01 Any Any Littelfuse R251 005 Fairchild RC5052M Quantity 1 2 3 3 10 1 1 Optional 1 1 1 Description 4.7F, 10V Capacitor 1F, 16V Capacitor 100nF, 50V Capacitor 1200F, 10V Electrolytic 1500F, 6.3V Electrolytic 8A Schottky Diode Signal Diode 2.5H, 10A Inductor 1.3H, 20A Inductor N-Channel MOSFET (TO-220 or TO-263) N-Channel MOSFET (TO-220 or TO-263) SCR 10 4.7 10K 2.80K Sets frequency. Sets deadtime. 2.2m 10m, 1W Resistor 2.1 1K 5A Fast Fuse DC/DC Controller PCB Trace Resistor DCR ~ 6m See Note 1. DCR ~ 2m RDS(ON) = 20m @ VGS = 4.5V See Note 2. RDS(ON) = 10m @ VGS = 4.5V See Note 2. IRMS = 2A ESR 44m Requirements/Comments
Preliminary Specification
Q3 R1, R6 R2-3 R4 R5 R7 R8 R9 R10 R11 R12 F1 U1
1 2 2 1 1 Optional Optional 1 1 1 1 1 1
Notes: 1. Inductor L1 is recommended to isolate the 5V input supply from noise generated by the MOSFET switching, and to comply with Intel dI/dt requirements. L1 may be omitted if desired. 2. For designs using the TO-220 MOSFETs, heatsinks with thermal resistance SA < 20C/W should be used. For designs using the TO-263 MOSFETs, adequate copper area should be used. For details and a spreadsheet on MOSFET selections, refer to Applications Bulletin AB-8.
11
RC5052
+12V F1* +5V CIN* R1 10 C5 1F C2 1F R2 4.7 Q1 C1 4.7F 11 12 13 14 15 16 17 18 19 20 10 9 8 7 6 5 4 3 2 1 R3 4.7 Q2 L2 1.3H D1 MBRD835L R9 3m VO COUT* L1 (Optional) 2.5H
R6 10 Q3 2N6394
Preliminary Specification
R8 (Optional) VID4 VID3 VID2 VID1 VID0
U1 RC5052
C3 0.1F
R5 6.24K VCC R4 10K PWRGD C6 0.1F R7 (Optional) *Refer to Table 3 for values of COUT, F1, and CIN.
ENABLE/SS C4 0.1F
Figure 3. Application Circuit for Coppermine/Camino Processors
(Typical Design)
12
RC5052
Table 5. RC5052 Application Bill of Materials for Coppermine/Camino Processors
(Typical Design) Reference C1 C2, C5 C3-4,6 CIN COUT D1 L1 L2 Q1-2 Manufacturer Part # AVX TAJB475M010R5 Panasonic ECU-V1C105ZFX Panasonic ECU-V1H104ZFX Sanyo 10MV1200GX Sanyo 6MV1500GX Motorola MBRD835L Any Any Fairchild FDP6030L or FDB6030L Motorola 2N6394 Any Any Any Any Any Any N/A Littelfuse R251 005 Fairchild RC5052M Quantity 1 2 3 3 8 1 Optional 1 2 Description 4.7F, 10V Capacitor 1F, 16V Capacitor 100nF, 50V Capacitor 1200F, 10V Electrolytic IRMS = 2A 1500F, 6.3V Electrolytic 8A Schottky Diode 2.5H, 10A Inductor 1.3H, 20A Inductor N-Channel MOSFET (TO-220 or TO-263) SCR 10 4.7 10K 6.24K Sets frequency. Sets deadtime. 3.0m 5A Fast Fuse DC/DC Controller PCB Trace Resistor DCR ~ 6m See Note 1. DCR ~ 2m RDS(ON) = 20m @ VGS = 4.5V See Note 2. ESR 44m Requirements/Comments
Preliminary Specification
Q3 R1, R6 R2-3 R4 R5 R7 R8 R9 F1 U1
1 2 2 1 1 Optional Optional 1 1 1
Notes: 1. Inductor L1 is recommended to isolate the 5V input supply from noise generated by the MOSFET switching, and to comply with Intel dI/dt requirements. L1 may be omitted if desired. 2. For designs using the TO-220 MOSFETs, heatsinks with thermal resistance SA < 20C/W should be used. For designs using the TO-263 MOSFETs, adequate copper area should be used. For details and a spreadsheet on MOSFET selections, refer to Applications Bulletin AB-8.
13
RC5052
+5V F1* +12V CIN* R1 10 C2 1F C5 1F R2 4.7 Q1 R3 4.7 11 12 13 14 15 16 17 18 19 20 10 9 8 7 6 5 4 3 2 1 Q2 L1 (Optional) 2.5H D2 6.2V C3 0.1F R10 10 L2 1.3H D1 MBRD835L
R6 10 Q3 2N6394 C1 1F
R9 3m VO COUT*
Preliminary Specification
R8 (Optional) VID4 VID3 VID2 VID1 VID0
U1 RC5052
R5 6.24K VCC R4 10K PWRGD C6 0.1F R7 (Optional) *Refer to Table 3 for values of COUT, F1, and CIN.
ENABLE/SS C4 0.1F
Figure 4. Application Circuit for Coppermine/Camino Processors
(Typical Design)
14
RC5052
Table 6. RC5052 Application Bill of Materials for Coppermine/Camino Processors
(Typical Design) Reference C1-2, C5 C3-4,6 CIN COUT D1 D2 L1 L2 Q1-2 Manufacturer Part # AVX TAJB475M010R5 Panasonic ECU-V1H104ZFX Sanyo 10MV1200GX Sanyo 6MV1500GX Motorola MDRDS835L Fairchild MMSZ5233B Any Any Fairchild FDP6030L or FDB6030L Motorola 2N6394 Any Any Any Any Any N/A Littelfuse R251 005 Fairchild RC5052M Quantity 3 3 3 8 1 1 Optional 1 2 Description 1F, 16V Capacitor 100nF, 50V Capacitor 1200F, 10V Electrolytic IRMS = 2A 1500F, 6.3V Electrolytic 8A Schottky Diode 6.2V Zener 2.5H, 10A Inductor 1.3H, 20A Inductor N-Channel MOSFET (TO-220 or TO-263) SCR 10 4.7 10K 6.24K Sets frequency. Sets deadtime. 3.0m 5A Fast Fuse DC/DC Controller PCB Trace Resistor DCR ~ 6m See Note 1. DCR ~ 2m RDS(ON) = 20m @ VGS = 4.5V See Note 2. ESR 44m Requirements/Comments
Preliminary Specification
Q3
1 3 2 1 1 Optional Optional 1 1 1
R1, R6, R10 Any R2-3 R4 R5 R7 R8 R9 F1 U1
Notes: 1. Inductor L1 is recommended to isolate the 5V input supply from noise generated by the MOSFET switching, and to comply with Intel dI/dt requirements. L1 may be omitted if desired. 2. For designs using the TO-220 MOSFETs, heatsinks with thermal resistance SA < 20C/W should be used. For designs using the TO-263 MOSFETs, adequate copper area should be used. For details and a spreadsheet on MOSFET selections, refer to Applications Bulletin AB-8.
15
RC5052
Test Parameters
tR 90% 10% tDT 2V 2V 90% 2V tDT 2V LODRV 10% tF HIDRV
Figure 5. Output Drive Timing Diagram
Preliminary Specification
Application Information
The RC5052 Controller
The RC5052 is a programmable synchronous DC-DC controller IC. When designed around the appropriate external components, the RC5052 can be configured to deliver more than 16A of output current, as appropriate for the Katmai and Coppermine and other processors. The RC5052 functions as a fixed frequency PWM step down regulator.
High Current Output Drivers
The RC5052 contains two identical high current output drivers that utilize high speed bipolar transistors in a push-pull configuration. The drivers' power and ground are separated from the chip's power and ground for switching noise immunity. The high-side driver's power supply pin, VCCQP, is supplied from an external 12V source through a series resistor. The resulting voltage is sufficient to provide the gate to source drive to the external MOSFETs required in order to achieve a low RDS,ON. The low-side driver's power supply pin, VCCP, is supplied from either 5V or from the same source as VCCQP. Choosing 12V will ensure lowest possible RDS,ON; choosing 5V will result in lower gate current, which may be important when operating the RC5052 at high frequency and lower output power. The VCCQP pin may also be run as charge pump for +12V Main Power, as shown in Figure 4.
Main Control Loop
Refer to the RC5052 Block Diagram on page 1. The RC5052 implements "summing mode control", which is different from both classical voltage-mode and current-mode control. It provides superior performance to either by allowing a large converter bandwidth over a wide range of output loads. The control loop of the regulator contains two main sections: the analog control block and the digital control block. The analog section consists of signal conditioning amplifiers feeding into a comparator which provides the input to the digital control block. The signal conditioning section accepts input from the IFB (current feedback) and VFB (voltage feedback) pins and sets up two controlling signal paths. The first, the voltage control path, amplifies the difference between the VFB signal and the reference voltage from the DAC and presents the output to one of the summing amplifier inputs. The second, current control path, takes the difference between the IFB and SW pins when the high-side MOSFET is on, reproducing the voltage across the MOSFET and thus the input current; it presents the resulting signal to another input of the summing amplifier. These two signals are then summed together. This output is then presented to a comparator looking at the oscillator ramp, which provides the main PWM control signal to the digital control block. The digital control block takes the analog comparator input and the main clock signal from the oscillator to provide the appropriate pulses to the HIDRV and LODRV output pins. These two outputs control the external power MOSFETs. There is an additional comparator in the analog control section whose function is to set the point at which the RC5052 current limit comparator disables the output drive signals to the external power MOSFETs.
16
Internal Voltage Reference
The reference included in the RC5052 is a precision band-gap voltage reference. Its internal resistors are precisely trimmed to provide a near zero temperature coefficient (TC). Based on the reference is the output from an integrated 5-bit DAC. The DAC monitors the 5 voltage identification pins, VID0-4. When the VID4 pin is at logic HIGH, the DAC scales the reference voltage from 2.0V to 3.5V in 100mV increments. When VID4 is pulled LOW, the DAC scales the reference from 1.30V to 2.05V in 50mV increments. All VID codes are available, including those below 1.80V. The output voltage may be changed while the converter is on by changing the VID codes; however, it is necessary to do so in 1-bit steps, to avoid triggering the overvoltage protection.
Power Good (PWRGD)
The RC5052 Power Good function is designed in accordance with the Pentium II DC-DC converter specifications and provides a continuous voltage monitor on the VFB pin. The circuit compares the VFB signal to the VREF voltage and outputs an active-low interrupt signal to the CPU should the power supply voltage deviate more than 12% of its nominal setpoint. The output is guaranteed open-collector high when the power supply voltage is within 7% of its nominal setpoint. The Power Good flag provides no other control function to the RC5052.
RC5052
Output Enable/Soft Start (ENABLE/SS)
The RC5052 will accept an open collector/TTL signal for controlling the output voltage. The low state disables the output voltage. When disabled, the PWRGD output is in the low state. Even if an enable is not required in the circuit, this pin should have attached a capacitor (typically 100nF) to softstart the switching.
MOSFET Selection
This application requires N-channel Logic Level Enhancement Mode Field Effect Transistors. Desired characteristics are as follows: Low Static Drain-Source On-Resistance, RDS,ON < 20m (lower is better) Low gate drive voltage, VGS = 4.5V rated Power package with low Thermal Resistance Drain-Source voltage rating > 15V.
Over-Voltage Protection
The RC5052 constantly monitors the output voltage for protection against over-voltage conditions. If the voltage at the VFB pin exceeds the selected program voltage, an over-voltage condition is assumed and the RC5052 disables the output drive signal to the external high-side MOSFET, and drives the OVP pin high. This is designed to drive the gate of an external SCR, which blows a fuse, disconnecting the short from the power bus.
The on-resistance (RDS,ON) is the primary parameter for MOSFET selection. The on-resistance determines the power dissipation within the MOSFET and therefore significantly affects the efficiency of the DC-DC Converter. For details and a spreadsheet on MOSFET selection, refer to Applications Bulletin AB-8.
Preliminary Specification
Oscillator
The RC5052 oscillator free runs at 300 kHz, and may be adjusted from 80KHz to 1MHz as desired. Higher frequensies will permit smaller components, while decreasing efficiency. A typical operating frequency is 300KHz. The frequency may be adjusted upwith a resistor to ground on pin 1, according to the formula:
f = 300kHz* 40K ROSC
Inductor Selection
Choosing the value of the inductor is a tradeoff between allowable ripple voltage and required transient response. The system designer can choose any value within the allowed minimum to maximum range in order to either minimize ripple or maximize transient performance. The first order equation (close approximation) for minimum inductance is:
Lmin = (Vin - Vout) f x Vout Vin ESR x Vripple
where: and may be adjusted down with aresistor to 5V on pin 1, according to the formula:
160K f = 300kHz* 1ROSC
Vin = Input Power Supply Vout = Output Voltage f = DC/DC converter switching frequency ESR = Equivalent series resistance of all output capacitors in parallel Vripple = Maximum peak to peak output ripple voltage budget. The first order equation for maximum allowed inductance is:
Lmax = 2C0 (Vin - Vout) Dm Vtb Ipp2
Dead Time
The RC5052 can control the deadtime, that is, the time between when the high-side MOSFET is turned off and the low-side MOSFET is turned on, and vice versa. Longer dead times are appropriate when using multiple MOSFETs in parallel, or when MOSFETs with larger gate capacitance are used. The dead time may be adjusted with a resistor to ground on pin 15, according to the formula:
RDTA 80K
TDT = 100nsec*
where: Co = The total output capacitance
Design Considerations and Component Selection
Additional information on design and component selection may be found in Fairchild's Application Note 57.
Ipp = Maximum to minimum load transient current Vtb = The output voltage tolerance budget allocated to load transient
17
RC5052
Dm = Maximum duty cycle for the DC/DC converter (usually 95%). Some margin should be maintained away from both Lmin and Lmax. Adding margin by increasing L almost always adds expense since all the variables are predetermined by system performance except for Co, which must be increased to increase L. Adding margin by decreasing L can be done by purchasing capacitors with lower ESR. The RC5052 provides significant cost savings for the newer CPU systems that typically run at high supply current.
the internal comparator trips and signals the controller to reduce the converter's duty cycle to approximately 20%. This causes a drastic reduction in the output voltage as the load regulation collapses into the short circuit control mode. With a 40m output short, the voltage is reduced to 16.4A * 40m = 650mV. The output voltage does not return to its nominal value until the output current is reduced to a value within the safe operating range for the DC-DC converter.
RC5052 Short Circuit Current Characteristics
RS IFB RSENSE VFB VOUT
Preliminary Specification
The RC5052 short circuit current characteristic includes a hysteresis function that prevents the DC-DC converter from oscillating in the event of a short circuit. The short circuit limit is set with the RS resistor, as given by the formula
RS = ISC x *RDS, on IDetect
with IDetect 50A, ISC the desired current limit, and RDS,on the high-side MOSFET's on resistance. Remember to make the RS large enough to include the effects of initial tolerance and temperature variation on the MOSFET's RDS,on. Alternately, use of a sense resistor in series with the source of the MOSFET, as shown in Figure 6, eliminates this source of inaccuracy in the current limit. Note one addition of one diode, which is necessary for proper operation of this circuit. As an example, Figure 6 shows the typical characteristic of the DC-DC converter circuit with an FDB6030L high-side MOSFET (RDS = 20m maximum at 25C * 1.25 at 75C = 25m) and a 8.2K RS.
3.5 3.0 2.5 VOUT (V) 2.0 1.5 1.0 0.5 0 0 5 10 15 20 25 Output Current (A)
Figure 7. Precision Current Sensing
Schottky Diode Selection
The application circuit of Figure 1 shows a Schottky diode, D1, which is used as a free-wheeling diode to assure that the body-diode in Q2 does not conduct when the upper MOSFET is turning off and the lower MOSFET is turning on. It is undesirable for this diode to conduct because its high forward voltage drop and long reverse recovery time degrades efficiency, and so the Schottky provides a shunt path for the current. Since this time duration is very short, the selection criterion for the diode is that the forward voltage of the Schottky at the output current should be less than the forward voltage of the MOSFET's body diode.
Output Filter Capacitors
The output bulk capacitors of a converter help determine its output ripple voltage and its transient response. It has already been seen in the section on selecting an inductor that the ESR helps set the minimum inductance, and the capacitance value helps set the maximum inductance. For most converters, however, the number of capacitors required is determined by the transient response and the output ripple voltage, and these are determined by the ESR and not the capacitance value. That is, in order to achieve the necessary ESR to meet the transient and ripple requirements, the capacitance value required is already very large. The most commonly used choice for output bulk capacitors is aluminum electrolytics, because of their low cost and low ESR. The only type of aluminum capacitor used should be those that have an ESR rated at 100kHz. Consult Application Bulletin AB-14 for detailed information on output capacitor selection.
Figure 6. RC5052 Short Circuit Characteristic
The converter exhibits a normal load regulation characteristic until the voltage across the MOSFET exceeds the internal short circuit threshold of 50A * 8.2K = 410mV, which occurs at 410mV/25m = 16.4A. (Note that this current limit level can be as high as 410mV/15m = 27A, if the MOSFET has typical RDS,on rather than maximum, and is at 25C. This is the reason for using the external sense resistor.) At this point,
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RC5052
The output capacitance should also include a number of small value ceramic capacitors placed as close as possible to the processor; 0.1F and 0.01F are recommended values.
PCB Layout Guidelines
Placement of the MOSFETs relative to the RC5052 is critical. Place the MOSFETs such that the trace length of the HIDRV and LODRV pins of the RC5052 to the FET gates is minimized. A long lead length on these pins will cause high amounts of ringing due to the inductance of the trace and the gate capacitance of the FET. This noise radiates throughout the board, and, because it is switching at such a high voltage and frequency, it is very difcult to suppress. In general, all of the noisy switching lines should be kept away from the quiet analog section of the RC5052. That is, traces that connect to pins 9, 10, 11, 12 and 13 (LODRV, VCCP, VCCQP, HIDRV and SW) should be kept far away from the traces that connect to pins 4 through 6, and pin 14. Place the 0.1F decoupling capacitors as close to the RC5052 pins as possible. Extra lead length on these reduces their ability to suppress noise. Each VCC and GND pin should have its own via to the appropriate plane. This helps provide isolation between pins. Place the MOSFETs, inductor, and Schottky as close together as possible for the same reasons as in the rst bullet above. Place the input bulk capacitors as close to the drains of the high side MOSFETs as possible. In addition, placement of a 0.1F decoupling cap right on the drain of each high side MOSFET helps to suppress some of the high frequency switching noise on the input of the DC-DC converter. Place the output bulk capacitors as close to the CPU as possible to optimize their ability to supply instantaneous current to the load in the event of a current transient. Additional space between the output capacitors and the CPU will allow the parasitic resistance of the board traces to degrade the DC-DC converterOs performance under severe load transient conditions, causing higher voltage deviation. For more detailed information regarding capacitor placement, refer to Application Bulletin AB-5. A PC Board Layout Checklist is available from Fairchild Applications. Ask for Application Bulletin AB-11.
Input Filter
The DC-DC converter design may include an input inductor between the system +5V supply and the converter input as shown in Figure 8. This inductor serves to isolate the +5V supply from the noise in the switching portion of the DC-DC converter, and to limit the inrush current into the input capacitors during power up. A value of 2.5H is recommended. It is necessary to have some low ESR aluminum electrolytic capacitors at the input to the converter. These capacitors deliver current when the high side MOSFET switches on. Figure 8 shows 3 x 1000F, but the exact number required will vary with the speed and type of the processor. For the top speed Katmai and Coppermine, the capacitors should be rated to take 9A and 6A RMS of ripple current respectively. Capacitor ripple current rating is a function of temperature, and so the manufacturer should be contacted to find out the ripple current rating at the expected operational temperature. For details on the design of an input filter, refer to Applications Bulletin AB-15.
2.5H 5V 0.1F Vin 1000F, 10V Electrolytic
Preliminary Specification
Figure 8. Input Filter
Active Droop
The RC5052 includes active droop: as the output current increases, the output voltage drops. This is done in order to allow maximum headroom for transient response of the converter. The current is sensed by measuring the voltage across the high-side MOSFET during its on time. Note that this makes the droop dependent on the temperature of the MOSFET. However, when the formula given for selecting RS (current limit) is used, there is a maximum droop possible (-40mV), and when this value is reached, additional drop across the MOSFET will not cause any increase in droop--until current limit is reached. Additional droop can be added to the active droop using a discrete resistor (typically a PCB trace) outside the control loop, as shown in Figure 1. This is typically only required for the most demanding applications, such as for the next generation Intel processor (tolerance = +40/-70mV), as shown in Figure 1.
PC Motherboard Sample Layout and Gerber File
A reference design for motherboard implementation of the RC5052 along with the PCAD layout Gerber file and silk screen can be obtained from our marketing department at 650-968-9211 x7624.
RC5052 Evaluation Board
Fairchild provides an evaluation board to verify the system level performance of the RC5052. It serves as a guide to performance expectations when using the supplied external components and PCB layout. Please call the marketing department at 650-968-9211 x7624 for an evaluation board.
Additional Information
For additional information contact Fairchild Semiconductor's Analog & Mixed Signal Products Group Marketing Department at 650-968-9211 x7624.
19
RC5052
Appendix
Worst-Case Formulae for the Calculation of Cout, R5, and Cin (Circuit of Figure 1 Only)
The following formulae design the RC5052 for worst-case operation, including initial tolerance and temperature dependence of all of the IC parameters (initial setpoint, reference tolerance and tempco, active droop tolerance, current sensor gain), the initial tolerance and temperature dependence of the MOSFET, and the ESR of the capacitors. The following information must be provided: VT+, the value of the positive transient voltage limit;
Number of capacitors needed for Cout = the greater of:
X= ESR * IO VT-
or
ESR * IO VT+ -0.004 * Vnom + 14400 * IO * RD 18 * R5 * 1.1
Y=
Preliminary Specification
|VT-|, the absolute value of the negative transient voltage limit; IO, the maximum output current; Vnom, the nominal output voltage; Vin, the input voltage (typically 5V); ESR, the ESR of the output caps, per cap (44m for the Sanyo parts shown in this datasheet); RD, the on-resistance of the MOSFET (20m for the FDB6030); RD, the tolerance of the current sensor (usually about 67% for MOSFET sensing, including temperature). Irms, the rms current rating of the input caps (2A for the Sanyo parts shown in this datasheet).
2 IO * Cin = Irms IO* RD * (1 + RD) * 1.10 50 * 10
-6
Example: Suppose that the transient limits are 134mV, current I is 14.2A, and the nominal voltage is 2.000V, using MOSFET current sensing and the usual caps. We have VT+ = |VT-| = 0.134, IO = 14.2, Vnom = 2.000, and RD = 0.67. We calculate:
2
2.000 14.2 * 5 Cin = 2
-
2.000 5
= 3.47 4 caps
R5 =
14.2 * 0.020 * (1 + 0.67) * 1.10 50 * 10
-6
= 10.4K
X=
0.044 * 14.2 0.134 0.044 * 14.2
= 4.66
Vnom Vin
-
Vnom Vin
Y= 0.134 - 0.004 * 2.000 + 14400 * 14.2 * 0.020 18 * 10400 * 1.1
= 4.28
Since X > Y, we choose X, and round up to find we need 5 capacitors for COUT. A detailed explanation of this calculation, and the calculations used for Figure 2, may be found Applications Bulletin AB-XX.
R5 =
20
RC5052
Mechanical Dimensions
20 Lead SOIC
Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
Symbol A A1 B C D E e H h L N ccc
Inches Min. .093 .004 .013 .009 .496 Max. .104 .012 .020 .013 .512
Millimeters Min. 2.35 0.10 0.33 0.23 12.60 Max. 2.65 0.30 0.51 0.32 13.00
.291 .299 .050 BSC .394 .010 .016 20 0 -- 8 .004 .419 .029 .050
7.40 7.60 1.27 BSC 10.00 0.25 0.40 20 0 -- 8 0.10 10.65 0.75 1.27
Preliminary Specification
3 6
20
11
E
H
1
10
D A e B A1 SEATING PLANE -C- LEAD COPLANARITY ccc C
h x 45 C
L
21
RC5052
Ordering Information
Product Number RC5052M Package 20 pin SOIC
Preliminary Specification
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
6/22/99 0.0m 008 Stock#DS30005052 (c) 1998 Fairchild Semiconductor Corporation
www.fairchildsemi.com
RC5053
5-Bit Programmable Synchronous Switching Regulator Controller for Pentium(R) II Processor
Features
* 5-Bit Digitally Programmable 1.8V to 3.5V Fixed Output Voltage * Provides All Features Required by the Intel Pentium II Processor VRM 8.2 DC/DC Converter Specification * Flags for Power Good, Over-Temperature and OverVoltage Fault * Output Current Exceeds 14A from a 5V Supply * Dual N-Channel MOSFET Synchronous Driver * Initial Output Accuracy: 1.5% * Excellent Output Accuracy: 2% Typ Over Line, Load and Temperature Variations * High Efficiency: Over 95% Possible * Adjustable Current Limit Without External Sense Resistors * Fast Transient Response * Available in SO-20 and SSOP-20 Packages
Descriptions
The RC5053 is a high power, high efficiency switching regulator controller optimized for 5V input to 1.8V-3.5V output applications. It features a digitally programmable output voltage, a precision internal reference and an internal feedback system that provides output accuracy of 1.5% at room temperature and typically 2% over-temperature, load current and line voltage shifts. The RC5053 uses a synchronous switching architecture with two external N-channel output devices, providing high efficiency and eliminating the need for a high power, high cost P-channel device. Additionally, it senses the output current across the on-resistance of the upper N-channel MOSFET, providing an adjustable current limit without an external low value sense resistor. The RC5053 free-runs at 300kHz and can be synchronized to a faster external clock if desired. It includes all the inputs and outputs required to implement a power supply conforming to the Intel Pentium(R) II Processor VRM 8.2 DC/DC Converter Specification.
Preliminary Information
Applications
* Power Supply for Pentium II, SPARC, ALPHA and PA-RISC Microprocessors * High Power 5V to 1.8V-3.5V Regulators
Block Diagram
115% VREF + FC - OUTEN 19 LOGIC DISDR SYSTEM POWER DOWN - 12 FAULT 11 OT DELAY 13 PWRGD
2 PVCC 20 G1
PWM COMP 10 I SS SS 9 Q SS +
R S
1 G2
ERR + - -
BG MIN + - MAX + FB 6 SENSE 18 VID0 17 VID1 16 VID2 - gm CC + 7 I MAX I MAX + 0.7VREF VREF DAC 14 VID4 8 I FB 15 VID3
VREF
VREF - 5%
VREF + 5%
MHCL
HCL MONO
LVC -
Pentium is a registered trademark of Intel Corporation.
Rev. 1.0.1
RC5053
PRODUCT SPECIFICATION
Pin Assignment
TOP VIEW G2 PV CC GND SGND VCC SENSE IMAX IFB SS COMP 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 G1 OUTEN VID0 VID1 VID2 VID3 VID4 PWRGD FAULT OT
Preliminary Information
G PACKAGE 20-LEAD PLASTIC SSOP
M PACKAGE 20-LEAD PLASTIC SO
TJMAX = 125C, JA = 130C/ W (F) TJMAX = 125C, JA = 85.2C/ W (M)
Pin Definitions
Pin Number 1 Pin Name G2 Pin Description Gate Drive for the Lower N-Channel MOSFET, Q2. This output will swing from PVCC to GND. It will always be low when G1 is high or when the output is disabled. To prevent undershoot during a soft start cycle, G2 is held low until G1 first goes high. Power Supply for G1 and G2. PVCC must be connected to a potential of at least VIN + VGS(ON)Q1. If VIN = 5V, PVCC can be generated using a simple charge pump connected to the switching node between Q1 and Q2 (see Figure 7), or it can be connected to an auxiliary 12V supply if one exists. Power Ground. GND should be connected to a low impedance ground plane in close proximity to the source of Q2. Signal Ground. SGND is connected to the low power internal circuitry and should be connected to the negative terminal of the output capacitor where it returns to the ground plane. GND and SGND should be shorted right at the RC5053. Power Supply. Power for the internal low power circuitry. VCC should be wired separately from the drain of Q1 if they share the same supply. A 10F bypass capacitor is recommended from this pin to SGND. Output Voltage Pin. Connect to the positive terminal of the output capacitor. There is an internal 120k resistor connected from this pin to SGND. SENSE is a very sensitive pin; for optimum performance, connect an external 0.1F capacitor from this pin to SGND. By connecting a small external resistor between the output capacitor and the SENSE pin, the initial output voltage can be raised slightly. Since the internal divider has a nominal impedance of 120k, a 1200 series resistor will raise the nominal output voltage by 1%. If an external resistor is used, the value of the 0.1F capacitor on the SENSE pin must be greatly reduced or loop phase margin will suffer. Set a time constant for the RC combination of approximately 0.1s. So, for example, with a 1200 resistor, set C = 83pF. Use a standard 100pF capacitor. Current Limit Threshold. Current limit is set by the voltage drop across an external resistor connected between the drain of Q1 and IMAX. There is a 180A internal pull-down at IMAX.
2
PVCC
3 4
GND SGND
5
VCC
6
SENSE
7
IMAX
2
PRODUCT SPECIFICATION
RC5053
Pin Definitions (continued)
Pin Number 8 Pin Name IFB Pin Description Current Limit Sense Pin. Connect to the switching node between the source of Q1 and the drain of Q2. If IFB drops below IMAX when G1 is on, the RC5053 will go into current limit. The current limit circuit can be disabled by floating IMAX and shorting IFB to VCC through an external 10k resistor. Soft Start. Connect to an external capacitor to implement a soft start function. During moderate overload conditions, the soft start capacitor will be discharged slowly in order to reduce the duty cycle. In hard current limit, the soft start capacitor will be forced low immediately and the RC5053 will rerun a complete soft start cycle. CSS must be selected such that during power-up the current through Q1 will not exceed the current limit value. External Compensation. The COMP pin is connected directly to the output of the error amplifier and the input of the PWM comparator. An RC+ C network is used at this node to compensate the feedback loop to provide optimum transient response. Over-Temperature Fault. OT is an open-drain output and will be pulled low if OUTEN is less than 2V. Overvoltage Fault. FAULT is an open-drain output. If VOUT reaches 15% above the nominal output voltage, FAULT will go low and G1 and G2 will be disabled. Once triggered, the RC5053 will remain in this state until the power supply is recycled or the OUTEN pin is toggled. If OUTEN = 0, FAULT floats or is pulled high by an external resistor. Power Good. This is an open-drain signal to indicate validity of output voltage. A high indicates that the output has settled to within 5% of the rated output for more than 1ms. PWRGD will go low if the output is out of regulation for more than 500s. If OUTEN = 0, PWRGD pulls low. Digital Voltage Select.TTL inputs used to set the regulated output voltage required by the processor (Table 3). There is an internal 20k pull-up at each pin. When all five VIDn pins are high or floating, the chip will shut down. Output Enable. TTL input which enables the output voltage.The external MOSFET temperature can be monitored with an external thermistor as shown in Figure 6. When the OUTEN input voltage drops below 2V, OT trips. As OUTEN drops below 1.7V, the drivers are internally disabled to prevent the MOSFETs from heating further. If OUTEN is less than 1.2V for longer than 30s, the RC5053 will enter shutdown mode. The internal oscillator can be synchronized to a faster external clock by applying the external clocking signal to the OUTEN pin. Gate Drive for the Upper N-Channel MOSFET, Q1.This output will swing from PVCC to GND. It will always be low when G2 is high or the output is disabled.
9
SS
10
COMP
Preliminary Information
11 12
OT FAULT
13
PWRGD
18, 17, 16, 15, 14 19
VID0, VID1, VID2, VID3, VID4 OUTEN
20
G1
Absolute Maximum Ratings1
Parameter Supply Voltage VCC PVCC Input Voltage IFB (Note 2) IMAX All Other Inputs -0.3V -0.3V PVCC + 0.3V 13V VCC + 0.3V 3 7V 13.5V Min. Typ. Max.
RC5053
PRODUCT SPECIFICATION
Absolute Maximum Ratings1 (continued)
Parameter Digital Output Voltage IFB Input Current (Notes 2, 3) Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering, 10 sec.) Min. -0.3V -100mA 0C -65C 70C 150C 300C Typ. Max. 7V
Electrical Characteristics (VCC = 5V, PVCC = 12V, TA = 25C, unless otherwise noted.)3
Symbol Parameter Supply Voltage Supply Voltage for G1, G2 1.8V Initial Output Voltage 2.8V Initial Output Voltage 3.5V Initial Output Voltage 1.8V Initial Output Voltage 2.8V Initial Output Voltage 3.5V Initial Output Voltage VOUT Output Load Regulation Output Line Regulation Negative Power Good Trip Point VFAULT ICC FAULT Trip Point Operating Supply Current Shutdown Supply Current IPVCC Supply Current IOUT = 0 to 14A (Fig. 2) VCC = 4.75V to 5.25V (Fig. 2) * * * * * -10 10 % Below Output Voltage (Fig. 2) % Above Output Voltage (Fig. 2) OUTEN = VCC = 5V4 (Fig. 3) OUTEN = 0, VID0 to VID4 Floating (Fig. 3) PVCC = 12V, OUTEN = VCC5 (Fig. 3) PVCC = 12V, OUTEN = 0, VID0 to VID4 Floating fOSC VSAWL VSAWH GERR gmERR Internal Oscillator Frequency VCOMP at Minimum Duty Cycle VCOMP at Maximum Duty Cycle Error Amplifier Open-Loop DC Gain Error Amplifier Transconductance * * 40 0.7 (Fig. 4) * 250 * * * With Respect to Rated Output Voltage (Fig. 2) Conditions * * 1.5% 1.5% 1.5% 2% 2% 2% -5 1 5 -5 15 2.0 760 26 430 300 1.8 2.8 53 1.3 1.9 350 20 3.0 1500 10 Min. 4.5 Typ. Max. Units 5.5 13.2 V V mV mV mV mV mV mV mV mV % % % mA A mA A kHz V V dB mmho
Preliminary Information
VCC PVCC VOUT
VPWRGD Positive Power Good Trip Point % Above Output Voltage (Fig. 2)
4
PRODUCT SPECIFICATION
RC5053
Electrical Characteristics (VCC = 5V, PVCC = 12V, TA = 25C, unless otherwise noted.)3 (continued)
Symbol BWERR IIMAX ISS ISSIL ISSHIL tSSHIL Parameter IMAX Sink Current Soft Start Source Current Maximum Soft Start Sink Current Under Current Limit Soft Start Sink Current Under Hard Current Limit Hard Current Limit Hold Time VIMAX = VCC VSENSE = VOUT, VIMAX = VCC, VIFB = 0V6, 7, VSS = VCC VSENSE = 0V, VIMAX = VCC, VIFB = 0V, VSS = VCC VSENSE = 0V, VIMAX = 4V, VIFB from 5V * * * * * * * * * * * * * * 10 10 20 30 77 2 0.8 0.5 200 200 15 1.9 1.6 0.8 Conditions * * * Min. 150 -13 30 20 Typ. 400 180 -10 60 45 500 1 500 500 40 2 1.7 1.2 90 100 82 88 2 1000 1000 60 2.12 1.8 1.5 150 220 -7 150 Max. Units kHz A A A mA s ms s s s V V V ns ns % V V k mA Error Amplifier -3dB Bandwidth COMP = Open VSS = 0.4V, VIMAX = 0V, VIFB = VCC *
tPWRGD Power Good Response Time VSENSE from 0V to Rated VOUT tPWRBAD Power Good Response Time VSENSE from Rated VOUT to 0V tFAULT tOT VOT VOTDD VSHDN tr, tf tNOL DCMAX VIH VIL RIN ISINK FAULT Response Time OT Response Time Over-Temperature Trip Point Over-Temperature Driver Disable Shutdown Driver Rise and Fall Time Driver Nonoverlap Time Maximum G1 Duty Cycle VID0 to VID4 = 1 Input High Voltage VID0 to VID4 = 0 Input Low Voltage VID0 to VID4 = 0 Internal Pull-Up Resistance Digital Output Sink Current VSENSE from Rated VOUT to VCC OUTEN, VID0 to VID4 = 0 (Fig. 3)8 OUTEN, VID0 to VID4 = 0 (Fig. OUTEN, VID0 to VID4 = 0 (Fig. 3)8 3)8
Preliminary Information
OUTEN, VID0 to VID4 = 0 (Fig. 3)8 (Figure 4) (Figure 4) (Figure 4)
The * denotes specifications which apply over the full operating temperature range. Notes: 1. Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. 2. When IFB is taken below GND, it will be clamped by an internal diode. This pin can handle input currents greater than 100mA below GND without latchup. In the positive direction, it is not clamped to VCC nor PVCC. 3. All currents into device pins are positive; all currents out of the device pins are negative. All voltages are referenced to ground unless otherwise specified. 4. The RC5053 goes into the shutdown mode if VID0 to VID4 are floating. Due to the internal pull-up resistors, there will be an additional 0.25mA/pin if any of the VID0 to VID4 pins are pulled low. 5. Supply current in normal operation is dominated by the current needed to charge and discharge the external FET gates. This will vary with the RC5053 operating frequency, supply voltage and the external FETs used. 6. The current limiting amplifier can sink but cannot source current. Under normal (not current limited) operation, the output current will be zero. 7. Under typical soft current limit, the net soft start discharge current will be 60A (ISSIL ) + [-10A(ISS )] = 50A. The soft start sink-to-source current ratio is designed to be 6:1. 8. When VID0 to VID4 are all HIGH, the RC5053 will be forced to shut down internally. The OUTEN trip voltages are guaranteed by design for all other input codes.
5
RC5053
PRODUCT SPECIFICATION
Typical Application
PV CC 12V 10 VIN 5V
+
0.1F 5.6k 5.6k 5.6k VCC IMAX PV CC 10F 1.8k 0.1F
+
1F
+
CIN ** 1200 F x4
PWRGD FAULT PENTIUM II SYSTEM 5 OT VID0 TO VID4 OUTEN COMP SS
4.7 G1 RC5053 56 IFB 4.7 G2 SGND GND SENSE Q2* Q1*
LO 2 H 15A COUT + 330 F x7
VOUT 1.8V TO 3.5V 14A
Preliminary Information
C1 100pF
RC 15k CC 2200pF
CSS 0.1F
0.1F
* FAIRCHILD NDB6030L ** SANYO 10MV1200GX COILTRONICS CTX02-13198 OR PANASONIC 12TS-2R5SP AVX TPSE337M006R0100
Figure 1. 5V to 1.8V-3.5V Supply Application
Test Circuits
PVCC 12V VCC 5V 10 VIN 5V
+
3k 3k 3k 10F 0.1F 1F
+
0.1F 10k
+
CIN ** 1200F x4
100pF
100pF
VCC OUTEN PWRGD FAULT OT RC5053
PV CC IFB 4.7 G1 IMAX G2 SGND GND SENSE NC 4.7 Q2* C OUT + 330F x7 LO Q1* 2H 15A VOUT
100pF
VID0 TO VID4
VID0 TO VID4 COMP SS
C1 100pF
RC 15k CC 2200pF
0.1F
0.1F
* FAIRCHILD NDB6030L ** SANYO 10MV1200GX COILTRONICS CTX02-13198 OR PANASONIC 12TS-2R5SP AVX TPSE337M006R0100
Figure 2
VCC VID0 VID1 VID2 VID3 VID4 10k VID0 VID1 VID2 VID3 VID4 OUTEN NC NC NC NC PWRGD FAULT OT COMP SS NC SGND GND SENSE RC5053 IMAX G2 NC NC VCC IFB PVCC G1 NC 0.1F 0.1F PVCC 10
VCC
+
10F
+
1F
Figure 3
6
PRODUCT SPECIFICATION
RC5053
Test Circuits (continued)
VCC 5V PV CC 12V 10 tr tf 90% 50% 4.7 G1 RC5053 4.7 SENSE SGND GND G2 G2 RISE/FALL 5000pF 50% 50% t NOL t NOL G1 RISE/FALL 5000pF 10% 90% 50% 10%
+
10F 0.1F 10k VCC IFB PVCC 0.1F
+
1F
Preliminary Information
Figure 4
Function Tables
Table 1. OT Logic
OUTEN (V) <2 >2
Note: 1. With external pull-up resistor
OT1 0 1
Table 2. PWRGD and FAULT Logic
Input OUTEN 0 1 1 1 1 VSENSE2 X < 95% > 95% < 105% >105% > 115% 1 1 1 0 0 0 OT 0 1 1 Output1 FAULT 1 1 1 PWRGD 0 0 1
Notes: 1. With external pull-up resistor 2. With respect to the output voltage selected in Table 3 as required by Intel Specification VRM 8.2 3. X = Don't care
Table 3. Rated Output Voltage
Input Pin VID4 0 0 0 0 0 0 0 VID3 1 1 1 1 1 1 1 VID2 1 1 1 1 0 0 0 VID1 1 1 0 0 1 1 0 VID0 1 0 1 0 1 0 1 Rated Output Voltage (V) Disabled1 (1.30) Disabled1 (1.35) Disabled1 (1.40) Disabled1 (1.45) Disabled1 (1.50) Disabled1 (1.55) Disabled1 (1.60)
7
RC5053
PRODUCT SPECIFICATION
Table 3. Rated Output Voltage (continued)
Input Pin VID4 0 0 0 0 0 0 0 0 VID3 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Rated Output Voltage (V) Disabled1 (1.65) Disabled1 (1.70) Disabled1 (1.75) 1.80 1.85 1.90 1.95 2.00 2.05 SHDN 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5
Preliminary Information
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Notes: 1. These code selections are disabled in RC5053
Applications Information
Overview
The RC5053 is a voltage feedback, synchronous switching regulator controller (see Block Diagram) designed for use in high power, low voltage step-down (buck) converters. It is designed to satisfy the requirements of the Intel Pentium II power supply specification. It includes an on-chip DAC to control the output voltage, a PWM generator, a precision reference trimmed to 1%, two high power MOSFET gate drivers and all the necessary feedback and control circuitry to form a complete switching regulator circuit. The RC5053 includes a current limit sensing circuit that uses the upper external power MOSFET as a current sensing element, eliminating the need for an external sense resistor. Once the current comparator, CC, detects an overcurrent condition, the duty cycle is reduced by discharging the soft start capacitor through a voltage-controlled current source. Under 8
severe overloads or output short circuit conditions, the chip will be repeatedly forced into soft start until the short is removed, preventing the external components from being damaged. Under output over-voltage conditions, the MOSFET drivers will be disabled permanently until the chip power supply is recycled or the OUTEN pin is toggled. OUTEN can optionally be connected to an external negative temperature coefficient (NTC) thermistor placed near the external MOSFETs or the microprocessor. Three threshold levels are provided internally. When OUTEN drops to 2V, OT will trip, issuing a warning to the external CPU. If the temperature continues to rise and the OUTEN input drops to 1.7V, the G1 and G2 pins will be forced low. If OUTEN is pulled below 1.2V, the RC5053 will go into shutdown mode, cutting the supply current to a minimum. If thermal shutdown is not required, OUTEN can be connected to a conventional TTL enable signal. The free-running 300kHz PWM frequency can be synchronized to a faster external clock
PRODUCT SPECIFICATION
RC5053
connected to OUTEN. Adjusting the oscillator frequency can add flexibility in the external component selection. See the Clock Synchronization section. Output regulation can be monitored with the PWRGD pin which in turn monitors the internal MIN and MAX comparators. If the output is 5% beyond the selected value for more than 500s, the PWRGD output will be pulled low. Once the output has settled within 5% of the selected value for more than 1ms, PWRGD will return high.
to regulate the output.The MIN comparator is disabled when soft start is active to prevent it from overriding the soft start function. The RC5053 includes yet another feedback loop to control operation in current limit. Just before every falling edge of G1, the current comparator, CC, samples and holds the voltage drop measured across the external MOSFET, Q1, at the IFB pin. CC compares the voltage at IFB to the voltage at the IMAX pin. As the peak current rises, the measured voltage across Q1 increases due to the drop across the RDS(ON) of Q1.When the voltage at IFB drops below IMAX, indicating that Q1's drain current has exceeded the maximum level, CC starts to pull current out of the external soft start capacitor, cutting the duty cycle and controlling the output current level. The CC comparator pulls current out of the SS pin in proportion to the voltage difference between IFB and IMAX. Under minor overload conditions, the SS pin will fall gradually, creating a time delay before current limit takes effect. Very short, mild overloads may not affect the output voltage at all. More significant overload conditions will allow the SS pin to reach a steady state, and the output will remain at a reduced voltage until the overload is removed. Serious overloads will generate a large overdrive at CC, allowing it to pull SS down quickly and preventing damage to the output components. By using the RDS(ON) of Q1 to measure the output current, the current limiting circuit eliminates an expensive discrete sense resistor that would otherwise be required. This helps minimize the number of components in the high current path. Due to switching noise and variation of RDS(ON), the actual current limit trip point is not highly accurate. The current limiting circuitry is primarily meant to prevent damage to the power supply circuitry during fault conditions. The exact current level where the limiting circuit begins to take effect will vary from unit to unit as the RDS(ON) of Q1 varies. For a given current limit level, the external resistor from IMAX to VIN can be determined by:
( I LMAX ) ( R DS(ON)Q1 ) R IMAX = ---------------------------------------------------I IMAX
Theory of Operation
Primary Feedback Loop
The regulator output voltage at the SENSE pin is divided down internally by a resistor divider with a total resistance of approximately 120k. This divided down voltage is subtracted from a reference voltage supplied by the DAC output. The resulting error voltage is amplified by the error amplifier and the output is compared to the oscillator ramp waveform by the PWM comparator. This PWM signal controls the external MOSFETs through G1 and G2. The resulting chopped waveform is filtered by LO and COUT closing the loop. Loop frequency compensation is achieved with an external RC + C network at the COMP pin, which is connected to the output node of the transconductance amplifier.
Preliminary Information
MIN, MAX Feedback Loops
Two additional comparators in the feedback loop provide high speed fault correction in situations where the ERR amplifier may not respond quickly enough. MIN compares the feedback signal FB to a voltage 60mV (5%) below the internal reference. If FB is lower than the threshold of this comparator, the MIN comparator overrides the ERR amplifier and forces the loop to full duty cycle which is set by the internal oscillator typically to 82%. Similarly, the MAX comparator forces the output to 0% duty cycle if FB is more than 5% above the internal reference. To prevent these two comparators from triggering due to noise, the MIN and MAX comparators' response times are deliberately controlled so that they take two or three microseconds to respond. These two comparators help prevent extreme output perturbations with fast output transients, while allowing the main feedback loop to be optimally compensated for stability.
where,
Soft Start and Current Limit
The RC5053 includes a soft start circuit which is used for initial start-up and during current limit operation. The SS pin requires an external capacitor to SGND with the value determined by the required soft start time. An internal 10A current source is included to charge the external SS capacitor. During start-up, the COMP pin is clamped to a diode drop above the voltage at the SS pin. This prevents the error amplifier, ERR, from forcing the loop to maximum duty cycle. The RC5053 will begin to operate at low duty cycle as the SS pin rises above about 1.2V (VCOMP 1.8V). As SS continues to rise, QSS turns off and the error amplifier begins
I RIPPLE I LMAX = I LOAD + -----------------2
ILOAD = Maximum load current; IRIPPLE = Inductor ripple current
( V IN - V OUT ) ( V OUT ) = ------------------------------------------------------( f OSC ) ( L O ) ( V IN )
fOSC = RC5053 oscillator frequency = 300kHz LO = Inductor value RDS(ON)Q1 = Hot on-resistance of Q1 at ILMAX IIMAX = Internal 180A sink current at IMAX
9
RC5053
PRODUCT SPECIFICATION
VIN RC5053 IMAX R IMAX
Clock Synchronization
+
CIN
+
CC 180A
7 G1 IFB 56 8 Q1 LO VOUT
-
+
G2 Q2 COUT
Figure 5. Current Limit Setting
The internal oscillator can be synchronized to an external clock by applying the external clocking signal to the OUTEN pin. The synchronizing range extends from the initial operating frequency up to 500kHz. If the external frequency is much higher than the natural free-running frequency, the peak-to-peak sawtooth amplitude within the RC5053 will decrease. Since the loop gain is inversely proportional to the amplitude of the sawtooth, the compensation network may need to be adjusted slightly. Note that the temperature sensing circuitry does not operate when external synchronization is used.
OUTEN and Thermistor Input
Preliminary Information
The RC5053 includes a low power shutdown mode, controlled by the logic at the OUTEN pin. A high at OUTEN allows the part to operate normally. A low level at OUTEN stops all internal switching, pulls COMP and SS to ground internally and turns Q1 and Q2 off. OT and PWRGD are pulled low, and FAULT is left floating. In shutdown, the RC5053 quiescent current will drop to about 760A. The remaining current is used to keep the thermistor sensing circuit at OUTEN alive. Note that the leakage current of the external MOSFETs may add to the total shutdown current consumed by the circuit, especially at elevated temperature. OUTEN is designed with multiple thresholds to allow it to also be utilized for over-temperature protection. The power MOSFET operating temperature can be monitored with an external negative temperature coefficient (NTC) thermistor mounted next to the external MOSFET which is expected to run the hottest --often the high-side device, Q1. Electrically, the thermistor should form a voltage divider with another resistor, R1, connected to VCC. Their midpoint should be connected to OUTEN (see Figure 6). As the temperature increases, the OUTEN pin voltage is reduced. Under normal operating conditions, the OUTEN pin should stay above 2V. All circuits will function normally, and the OT pin will remain in a high state. If the temperature gets abnormally high, the OUTEN pin voltage will eventually drop below 2V. OT will switch to a logic low, providing an over-temperature warning to the system. As OUTEN drops below 1.7V, the RC5053 disables both FET drivers. If OUTEN is less than 1.2V, the RC5053 will enter shutdown mode. To activate any of these three modes, the OUTEN voltage must drop below the respective threshold for longer than 30s.
VCC 5.6k PENTIUM II SYSTEM VCC RC5053 R1 R2 NTC THERMISTOR MOUNT IN CLOSE THERMAL PROXIMITY TO Q1 OUTEN G2 OT G1 VIN
MOSFET Gate Drive
Power for the internal MOSFET drivers is supplied by PVCC. This supply must be above the input supply voltage by at least one power MOSFET VGS(ON) for efficient operation. This higher voltage can be supplied with a separate supply, or it can be generated using a simple charge pump as shown in Figure 7. The 82% typical maximum duty cycle ensures sufficient off-time to refresh the charge pump during each cycle.
1N5817 VIN = 5V
2 PVCC 0.1F RC5053 G1 20
+
CIN
4.7
Q1 LO VOUT
G2 1
4.7
Q2
+
COUT
Figure 7. Doubling Charge Pump
Upon power-down, G1 and G2 will both be held low to prevent output voltage under shoot. On power-up or wake-up from thermal shutdown, the driver is designed such G2 will be held low until after G1 first goes high.
Power MOSFETs
Two N-channel power MOSFETs are required for most RC5053 circuits. They should be selected based primarily on gate threshold and on-resistance considerations. The required MOSFET threshold should be determined based on the available power supply voltages and/or the complexity of the gate driver charge pump scheme. In 5V input designs where a 12V supply is used to power PVCC, standard MOSFETs with RDS(ON) specified at VGS = 5V or 6V can be used with good results. However, logic level devices will improve efficiency. The current drawn from the 12V supply varies with the MOSFETs used and the RC5053 operating frequency, but is generally less than 50mA.
4.7
Q1 LO VOUT
4.7
Q2
+
COUT
Figure 6. OUTEN Pin as a Thermistor Input
10
PRODUCT SPECIFICATION
RC5053
RC5053 designs that use a 5V VIN voltage and a doubler charge pump to generate PVCC will not provide enough drive voltage to fully enhance standard power MOSFETs. Under this condition, the effective MOSFET RDS(ON) may be quite high, raising the dissipation in the MOSFETs and reducing efficiency. Logic level MOSFETs are a better choice for 5V-only systems. They can be fully enhanced with the generated charge pump voltage and will operate at maximum efficiency. See the MOSFET Gate Drive section for more charge pump information. Once the threshold voltage has been selected, RDS(ON) should be chosen based on input and output voltage, allowable power dissipation and maximum required output current. In a typical RC5053 buck converter circuit the average inductor current is equal to the output load current. This current is always flowing through either Q1 or Q2 with the power dissipation split up according to the duty cycle:
V OUT DC ( Q1 ) = -------------V IN V OUT ( V IN - V OUT ) DC ( Q2 ) = 1 - -------------- = ---------------------------------V IN V IN
MOSFETs for Q2 and using a single device for Q1. Note that using a higher PMAX value in the RDS(ON) calculations will generally decrease MOSFET cost and circuit efficiency while increasing MOSFET heat sink requirements.
Inductor Selection
The inductor is often the largest component in the RC5053 design and should be chosen carefully. Inductor value and type should be chosen based on output slew rate requirements, output ripple requirements and expected peak current. Inductor value is primarily controlled by the required current slew rate. The maximum rate of rise of current in the inductor is set by its value, the input-to-output voltage differential and the maximum duty cycle of the RC5053. In a typical 5V input, 2.0V output application, the maximum current slew rate will be:
( V IN - V OUT ) 2.46 DC MAX ---------------------------------- = --------L L A ----s
Preliminary Information
The RDS(ON) required for a given conduction loss can now be calculated by rearranging the relation P = I2 R.
P MAX(Q1) ( V IN ) [ P MAX(Q1) ] R DS(ON)Q1 = ----------------------------------------------- = ------------------------------------------2 2 [ DC ( Q1 ) ] ( I MAX ) ( V OUT ) ( I MAX ) P MAX(Q2) ( V IN ) [ P MAX(Q2) ] R DS(ON)Q2 = ----------------------------------------------- = -------------------------------------------------------2 2 [ DC ( Q2 ) ] ( I MAX ) ( V IN - V OUT ) ( I MAX )
PMAX should be calculated based primarily on required efficiency or allowable thermal dissipation. A typical high efficiency circuit designed for Pentium II with a 5V input and a 2.0V, 14.2A output might allow no more than 4% loss at full load for each MOSFET. Assuming roughly 90% efficiency at this current level, this gives a PMAX value of: [(2.0)(14.2A/0.9)(0.04)] = 1.26W per MOSFET and a required RDS(ON) of:
( 5V ) ( 1.26W ) R DS(ON)Q1 = --------------------------------------- = 0.016 2 ( 2.0V ) ( 14.2A ) ( 5V ) ( 1.26W ) R DS(ON)Q2 = ----------------------------------------------------- = 0.010 2 ( 5V - 2.0V ) ( 14.2A )
where L is the inductor value in H. With proper frequency compensation, the combination of the inductor and output capacitor will determine the transient recovery time. In general, a smaller value inductor will improve transient response at the expense of increased output ripple voltage and inductor core saturation rating. A 2H inductor would have a 1.23A/s rise time in this application, resulting in a 4.1s delay in responding to a 5A load current step. During this 4.1s, the difference between the inductor current and the output current must be made up by the output capacitor, causing a temporary voltage droop at the output. To minimize this effect, the inductor value should usually be in the 1H to 5H range for most typical 5V input RC5053 circuits. To optimize performance, different combinations of input and output voltages and expected loads may require different inductor values. Once the required value is known, the inductor core type can be chosen based on peak current and efficiency requirements. Peak current in the inductor will be equal to the maximum output load current plus half of the peak-to- peak inductor ripple current. Ripple current is set by the inductor value, the input and output voltage and the operating frequency. The ripple current is approximately equal to:
( V IN - V OUT ) ( V OUT ) I RIPPLE = ------------------------------------------------------( f OSC ) ( L O ) ( V IN )
Note also that while the required RDS(ON) values suggest large MOSFETs, the dissipation numbers are only 1.26W per device or less--large TO-220 packages and heat sinks are not necessarily required in high efficiency applications. Fairchild NDB6030L are small footprint surface mount devices with RDS(ON) values below 0.03 at 5V of gate drive that work well in RC5053 circuits. With lower output voltages, the RDS(ON) of Q2 may need to be significantly lower than that for Q1. These conditions can often be met by paralleling two
fOSC = RC5053 oscillator frequency = 300kHz LO = Inductor value Solving this equation with our typical 5V to 2.0V application with a 2H inductor, we get:
( 3.0 ) ( 0.40 ) ---------------------------------------- = 2Ap-p ( 300kHz ) ( 2H )
11
RC5053
PRODUCT SPECIFICATION
Peak inductor current at 14.2A load:
2A 14.2A + ------ = 15.2A 2
The ripple current should generally be between 10% and 40% of the output current. The inductor must be able to withstand this peak current without saturating, and the copper resistance in the winding should be kept as low as possible to minimize resistive power loss. Note that in noncurrent limited circuits, the current in the inductor may rise above this maximum under short circuit or fault conditions; the inductor should be sized accordingly to withstand this additional current. Inductors with gradual saturation characteristics are often the best choice.
Electrolytic capacitors rated for use in switching power supplies with specified ripple current ratings and ESR can be used effectively in RC5053 applications. OS-CON electrolytic capacitors from SANYO and other manufacturers give excellent performance and have a very high performance/size ratio for electrolytic capacitors. Surface mount applications can use either electrolytic or dry tantalum capacitors. Tantalum capacitors must be surge tested and specified for use in switching power supplies. Low cost, generic tantalums are known to have very short lives followed by explosive deaths in switching power supply applications. AVX TPS series surface mount devices are popular surge tested tantalum capacitors that work well in RC5053 applications. A common way to lower ESR and raise ripple current is to parallel several capacitors. A typical RC5053 application might exhibit 5A input ripple current. SANYO OS-CON part number 10SA220M (220F/10V) capacitors feature 2.3A allowable ripple current at 85C; three in parallel at the input (to withstand the input ripple current) will meet the above requirements. Similarly, AVX TPSE337M006R0100 (330F/6V) have a rated maximum ESR of 0.1; seven in parallel will lower the net output capacitor ESR to 0.014. For low cost application, SANYO MV-GX series of capacitors can be used with acceptable performance.
Preliminary Information
Input and Output Capacitors
A typical RC5053 design puts significant demands on both the input and the output capacitors. During constant load operation, a buck converter like the RC5053 draws square waves of current from the input supply at the switching frequency. The peak current value is equal to the output load current plus 1/2 peak-to-peak ripple current, and the minimum value is zero. Most of this current is supplied by the input bypass capacitor. The resulting RMS current flow in the input capacitor will heat it up, causing premature capacitor failure in extreme cases. Maximum RMS current occurs with 50% PWM duty cycle, giving an RMS current value equal to IOUT/2. A low ESR input capacitor with an adequate ripple current rating must be used to ensure reliable operation. Note that capacitor manufacturers' ripple current ratings are often based on only 2000 hours (three months) lifetime at rated temperature. Further derating of the input capacitor ripple current beyond the manufacturer's specification is recommended to extend the useful life of the circuit. Lower operating temperature will have the largest effect on capacitor longevity. The output capacitor in a buck converter sees much less ripple current under steady-state conditions than the input capacitor. Peak-to-peak current is equal to that in the inductor, usually 10% to 40% of the total load current. Output capacitor duty places a premium not on power dissipation but on ESR. During an output load transient, the output capacitor must supply all of the additional load current demanded by the load until the RC5053 can adjust the inductor current to the new value. Output capacitor ESR results in a step in the output voltage equal to the ESR value multiplied by the change in load current. An 11A load step with a 0.05 ESR output capacitor will result in a 550mV output voltage shift; this is 27.5% of the output voltage for a 2.0V supply! Because of the strong relationship between output capacitor ESR and output load transient response, the output capacitor is usually chosen for ESR, not for capacitance value; a capacitor with suitable ESR will usually have a larger capacitance value than is needed for energy storage.
Feedback Loop Compensation
The RC5053 voltage feedback loop is compensated at the COMP pin, attached to the output node of the internal gm error amplifier. The feedback loop can generally be compensated properly with an RC + C network from COMP to GND as shown in Figure 8a.
6 SENSE
COMP 10 ERR
RC CC
C1 DAC RC5053
Figure 8a. Compensation Pin Hook-Up
Loop stability is affected by the values of the inductor, output capacitor, output capacitor ESR, error amplifier transconductance and error amplifier compensation network. The inductor and the output capacitor creates a double pole at the frequency:
1 f LC = -----------------------------------------2 ( L O ) ( C OUT )
12
- +
PRODUCT SPECIFICATION
RC5053
The ESR of the output capacitor forms a zero at the frequency:
1 f ESR = -----------------------------------------2 ( ESR ) ( C OUT )
Table 4. Suggested Compensation Network for 5V Input Application Using Multiple Paralleled 330F AVX TPS Output Capacitors
LO (H) 1 1 1 2.7 2.7 2.7 5.6 5.6 5.6 CO (F) 990 1980 4950 990 1980 4950 990 1980 4950 RC (k) 3.6 6.8 22 10 20 51 20 39 100 CC (pF) 10000 4700 2200 3300 2200 1000 2200 1000 470 C1 (pF) 470 220 100 150 68 47 68 47 33
The compensation network at the error amplifier output is to provide enough phase margin at the 0dB crossover frequency for the overall closed-loop transfer function. The zero and pole from the compensation network are:
1 1 f Z = ------------------------------- and f P = ------------------------------- respectively. 2 ( R C ) ( C1 ) 2 ( R C ) ( C C )
fZ LOOP GAIN
fSW = RC5053 SWITCHING FREQUENCY fCO = CLOSED-LOOP CROSSOVER FREQUENCY
Preliminary Information
-20dB /DECADE
fP fLC fESR fCO FREQUENCY
Table 4 shows the suggested compensation components for 5V input applications based on the inductor and output capacitor values. The values were calculated using multiple paralleled 330F AVX TPS series surface mount tantalum capacitors as the output capacitor. The optimum component values might deviate from the suggested values slightly because of board layout and operating condition differences. An alternate output capacitor is the Sanyo MV-GX series. Using multiple parallel 1500F Sanyo MV-GX capacitors for the output capacitor, Table 5 shows the suggested compensation component value for a 5V input application based on the inductor and output capacitor values.
Figure 8b. Bode Plot of the RC5053 Overall Transfer Function
Figure 8b shows the Bode plot of the overall transfer function. The compensation value used in this design is based on the following criteria: fSW = 12fCO, fZ = fLC and fP = 5fCO. At the closed-loop frequency fCO, the attenuation due the LC filter and the input resistor divider is compensated by the gain of the PWM modulator and the gain of the error amplifier (gmERR)(RC). Although a mathematical approach to frequency compensation can be used, the added complication of input and/or output filters, unknown capacitor ESR, and gross operating point changes with input voltage, load current variations, all suggest a more practical empirical method. This can be done by injecting a transient current at the load and using an RC network box to iterate toward the final compensation values, or by obtaining the optimum loop response using a network analyzer to find the actual loop poles and zeros.
Table 5. Suggested Compensation Network for 5V Input Application Using Multiple Paralleled 1500F SANYO MV-GX Output Capacitors
LO (H) 1 1 1 2.7 2.7 2.7 5.6 5.6 5.6 CO (F) 4500 6000 9000 4500 6000 9000 4500 6000 9000 RC (k) 9.1 10 18 22 30 47 47 62 91 CC (pF) 3300 3300 2200 1500 1000 680 680 470 330 C1 (pF) 150 100 68 47 47 33 33 33 22
VID0 to VID4, PWRGD and FAULT
The digital inputs (VID0 to VID4) program the internal DAC which in turn controls the output voltage. These digital input controls are intended to be static and are not designed for high speed switching. Forcing VOUT to step from a high to a low voltage by changing the VIDn pins quickly can cause FAULT to trip.
13
RC5053
PRODUCT SPECIFICATION
Figure 9 shows the relationship between the VOUT voltage, PWRGD and FAULT. To prevent PWRGD from interrupting the CPU unnecessarily, the RC5053 has a built-in tPWRBAD delay to prevent noise at the SENSE pin from toggling PWRGD. The internal time delay is designed to take about 500s for PWRGD to go low and 1ms for it to recover. Once PWRGD goes low, the internal circuitry watches for the output voltage to exceed 115% of the rated voltage. If this happens, FAULT will be triggered. Once FAULT is triggered, G1 and G2 will be forced low immediately and the RC5053 will remain in this state until VCC power supply is recycled or OUTEN is toggled.
15%
Layout Considerations
When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the RC5053. These items are also illustrated graphically in the layout diagram of Figure 10. The thicker lines show the high current paths. Note that at 10A current levels or above, current density in the PC board itself is a serious concern. Traces carrying high current should be as wide as possible. For example, a PCB fabricated with 2oz copper requires a minimum trace width of 0.15" to carry 10A. 1. In general, layout should begin with the location of the power devices. Be sure to orient the power circuitry so that a clean power flow path is achieved. Conductor widths should be maximized and lengths minimized. After you are satisfied with the power path, the control circuitry should be laid out. It is much easier to find routes for the relatively small traces in the control circuits than it is to find circuitous routes for high current paths. The GND and SGND pins should be shorted right at the RC5053. This helps to minimize internal ground disturbances in the RC5053 and prevents differences in ground potential from disrupting internal circuit operation. This connection should then tie into the ground plane at a single point, preferably at a fairly quiet point
Preliminary Information
VOUT 5% RATED VOUT -5% t PWRBAD PWRGD t FAULT FAULT t PWRGD t PWRBAD
2.
Figure 9. PWRGD and FAULT
V IN
+
CIN LO V OUT Q1
4.7 4.7 PVCC 10 56 1 2 0.1F 3 RC5053 20 19 18 17 16 15 14 13 12 11 VID0 VID1 5.6k VID2 5.6k VID3 VID4 5.6k
G2
G1
+
COUT Q2
1F
+
PV CC GND
OUTEN VID0 VID1 VID2
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 10. RC5053 Layout Diagram
14
+
10F 0.1F 5 6 R IMAX R IFB 7 8 9 10 CSS C1 RC CC
4 SGND
VCC SENSE IMAX IFB SS COMP
VID3 VID4 PWRGD FAULT OT
0.1F
PRODUCT SPECIFICATION
RC5053
in the circuit such as close to the output capacitors. This is not always practical, however, due to physical constraints. Another reasonably good point to make this connection is between the output capacitors and the source connection of the lowside FET Q2. Do not tie this single point ground in the trace run between the low side FET source and the input capacitor ground, as this area of the ground plane will be very noisy. 3. The small signal resistors and capacitors for frequency compensation and soft start should be located very close to their respective pins and the ground ends connected to the signal ground pin through a separate trace. Do not connect these parts to the ground plane! The VCC and PVCC decoupling capacitors should be as close to the RC5053 as possible. The 10F bypass capacitors for VCC and a 1F bypass capacitor for PVCC will help provide optimum regulation performance.
5.
The (+) plate of CIN should be connected as close as possible to the drain of the upper MOSFET. An additional 1F ceramic capacitor between VIN and power ground is recommended. The SENSE pin is very sensitive to pickup from the switching node. Care should be taken to isolate SENSE from possible capacitive coupling to the inductor switching signal. A 0.1F is required between the SENSE pin and the SGND pin next to the RC5053. OUTEN is a high impedance input and should be externally pulled up to a logic HIGH for normal operation. Kelvin sense IMAX and IFB at Q1 drain and source pins.
6.
7. 8.
Preliminary Information
4.
VIN 5V 56 0.1F 5.6k 5.6k 5.6k VCC 0.1F
+
10F 1.8k 1N5817
+
C IN** 1200F x4
PWRGD FAULT PENTIUM II SYSTEM 5V 1.8k DALE NTHS-1206N02 MOUNT THERMISTER IN CLOSE THERMAL PROXIMITY TO Q1 C1 100pF RC 15k CC 2200pF 5 OT
IMAX
PV CC G1
0.1F 4.7 56
Q1*
LO 2H 18A VOUT COUT + 330 F x7
RC5053
VID0 TO VID4 OUTEN COMP SS SGND
IFB G2 GND SENSE Q2* 4.7
CSS 0.01F 0.1F * FAIRCHILD NDB6030L ** SANYO 10MV1200GX COILTRONICS CTX02-13198 OR PANASONIC 12TS-2R5SP AVX TPSE337M006R0100
Figure 11. Single Supply RC5053 5V to 1.8V-3.5V Application with Thermal Monitor
15
RC5053
PRODUCT SPECIFICATION
Notes:
Preliminary Information
16
PRODUCT SPECIFICATION
RC5053
Notes:
Preliminary Information
17
PRODUCT SPECIFICATION
RC5053
Mechanical Dimensions (20 Lead SSOP)
Symbol A A1 A2 b c D E E1 e L N ccc Inches Min. -- .002 .065 .009 .004 .272 .291 Max. .079 -- .073 .015 .010 .295 .323 Millimeters Min. -- 0.05 1.65 0.22 0.09 6.90 7.40 Max. 2.00 -- 1.85 0.38 0.25 7.50 8.20 2 3 6 5 5 2, 4 Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E1" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5. "b" and "c" dimensions include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
.197 .220 .026 BSC .022 .037 20 0 -- 8 .004
5.00 5.60 0.65 BSC 0.55 0.95 20 0 -- 8 0.10
Preliminary Information
D
E
H
A
A2 B e
A1 SEATING PLANE -C- LEAD COPLANARITY ccc C L
C
18
RC5053
PRODUCT SPECIFICATION
Mechanical Dimensions (20 Lead SOIC)
Symbol A A1 B C D E e H h L N ccc Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
.093 .104 .004 .012 .013 .020 .009 .013 .496 .512 .291 .299 .050 BSC .394 .010 .016 20 0 -- 8 .004 .419 .029 .050
2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 12.60 13.00 7.40 7.60 1.27 BSC 10.00 0.25 0.40 20 0 -- 8 0.10 10.65 0.75 1.27
Preliminary Information
3 6
20
11
E
H
1
10
D A e B A1 SEATING PLANE -C- LEAD COPLANARITY ccc C
h x 45 C
L
19
RC5053
PRODUCT SPECIFICATION
Ordering Information
Product Number RC5053M RC5053G Package SOIC SSOP
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com 1/14/99 0.0m 007 Stock#DS30005053 (c) 1998 Fairchild Semiconductor Corporation
www.fairchildsemi.com
RC5054A
Programmable Synchronous DC-DC Converter Controller for Low Voltage Microprocessors
Features
* * * * * Drives Two N-Channel MOSFETs Operates from +5V or +12V VCC Bias Operates from +5V Power Input Simple Single-Loop Control Design - Voltage-Mode PWM Control Fast Transient Response - High-Bandwidth Error Amplifier - Full 0% to 100% Duty Ratio Excellent Output Voltage Regulation - 1% Over Line Voltage and Temperature TTL Compatible 5 Bit Digital-to-Analog Output Voltage Selection - Wide Range - 1.3VDC to 3.5VDC - 0.1V Binary Steps from 2.1VDC to 3.5VDC - 0.05V Binary Steps from 1.3VDC to 2.1VDC Power-Good Output Voltage Monitor Over-Voltage and Over-Current Fault Monitors - Does Not Require Extra Current Sensing Element, - Uses MOSFET's RDS(ON) Small Converter Size - Constant Frequency Operation - 200kHz Free-Running Oscillator Programmable from 50kHz to 1MHz
Applications
* Power Supply for Pentium(R), Pentium Pro, PowerPCTM and AlphaTM Microprocessors * High-Power 5V to 3.xV DC-DC Regulators * Low-Voltage Distributed Power Supplies
Preliminary Information
Description
The RC5054A provides complete control and protection for a DC-DC converter optimized for high-performance microprocessor applications. It is designed to drive two N-Channel MOSFETs in a synchronous-rectified buck topology. The RC5054A integrates all of the control, output adjustment, monitoring and protection functions into a single package. The output voltage of the converter is easily adjusted and precisely regulated. The RC5054A includes a 5-input digitalto-analog converter (DAC) that adjusts the output voltage from 2.1VDC to 3.5VDC in 0.1V increments and from 1.3VDC to 2.1VDC in 0.05V steps. The precision reference and voltage-mode regulator hold the selected output voltage to within 1% over temperature and line voltage variations.
* *
* *
*
Block Diagram
VSEN 110% + POWER-ON RESET (POR)
-
PGOOD
90% + 115% + OVERVOLTAGE 10A OVP SOFTSTART OVERCURRENT 4V SS BOOT UGATE PHASE VID0 VID1 VID2 VID3 VID4 FB COMP GND RT OSCILLATOR D/A CONVERTER (DAC) DACOUT + PWM COMPARATOR GATE CONTROL LOGIC LGATE PGND
-
+ OCSET REFERENCE 200A
-
+
INHIBIT PWM
-
ERROR AMP
Alpha is a trademark of Digital Equipment Corporation. Pentium is a registered trademark of Intel Corporation. PowerPCTM is a trademark of IBM Corporation.
Rev. 0.9.3
PRELIMINARY INFORMATION describes products that are not in full production at the time of printing. Specifications are based on design goals and limited characterization. They may change without notice. Contact Fairchild Semiconductor for current information.
RC5054A
PRODUCT SPECIFICATION
The RC5054A provides simple, single feedback loop, voltage-mode control with fast transient response. It includes a 200KHz free-running triangle-wave oscillator that is adjustable from 50KHz to 1MHz. The error amplifier features a 15MHz gain-bandwidth product and 6V/ms slew rate which enables high converter bandwidth for fast transient performance. The resulting PWM duty ratio ranges from 0% to 100%. The RC5054A monitors the output voltage with a window comparator that tracks the DAC output and issues a Power Good signal when the output is within 10%. The RC5054A protects against over-current conditions by inhibiting PWM operation. Built-in over-voltage protection triggers an external SCR to crowbar the input supply. The RC5054A monitors the current by using the RDS(ON) of the upper MOSFET which eliminates the need for a current sensing resistor.
Pin Assignments
RC5054 (SOIC) TOP VIEW
VSEN OCSET SS VID0 VID1 VID2 VID3 VID4 COMP FB 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 RT OVP VCC LGATE PGND BOOT UGATE PHASE PGOOD GND
Preliminary Information
Pin Definitions
Pin Number Pin Names 1 VSEN Pin Function Description This pin is connected to the converters output voltage. The PGOOD and OVP comparator circuits use this signal to report output voltage status and for overvoltage protection. Connect a resistor (ROCSET) from this pin to the drain of the upper MOSFET. ROCSET, an internal 200mA current source (IOCS), and the upper MOSFET onresistance (RDS(ON)) set the converter over-current (OC) trip point according to the following equation:
I OCS * R OCSET I PEAK = --------------------------------------R DS ( ON )
2
OCSET
An over-current trip cycles the soft-start function. 3 4-8 SS VID0-VID4 Connect a capacitor from this pin to ground. This capacitor, along with an internal 10mA current source, sets the soft-start interval of the converter. VID0-4 are the input pins to the 5-bit DAC. The states of these five pins program the internal voltage reference (DACOUT). The level of DACOUT sets the converter output voltage. It also sets the PGOOD and OVP thresholds. Table 1 specifies DACOUT for the 32 combinations of DAC inputs. COMP and FB are the available external pins of the error amplifier. The FB pin is the inverting input of the error amplifier and the COMP pin is the error amplifier output. These pins are used to compensate the voltage-control feedback loop of the converter. Signal ground for the IC. All voltage levels are measured with respect to this pin. PGOOD is an open collector output used to indicate the status of the converter output voltage. This pin is pulled low when the converter output is not within 10% of the DACOUT reference voltage. Connect the PHASE pin to the upper MOSFET source. This pin is used to monitor the voltage drop across the MOSFET for over-current protection. This pin also provides the return path for the upper gate drive. Connect UGATE to the upper MOSFET gate. This pin provides the gate drive for the upper MOSFET. This pin provides bias voltage to the upper MOSFET driver. A bootstrap circuit may be used to create a BOOT voltage suitable to drive a standard N-Channel MOSFET. This is the power ground connection. Tie the lower MOSFET source to this pin.
9 10
COMP FB
11 12
GND PGOOD
13
PHASE
14 15 16
UGATE BOOT PGND
2
PRODUCT SPECIFICATION
RC5054A
Pin Definitions (continued)
Pin Number Pin Names 17 18 19 20 LGATE VCC OVP RT Pin Function Description Connect LGATE to the lower MOSFET gate. This pin provides the gate drive for the lower MOSFET. Provide a 12V bias supply for the chip to this pin. The OVP pin can be used to drive an external SCR in the event of an overvoltage condition. This pin provides oscillator switching frequency adjustment. By placing a resistor (RT) from this pin to GND, the nominal 200KHz switching frequency is increased according to the following equation:
5.6E3 [ KHz Kohm ] F S = 200kHz + ------------------------------------------------------R T [ Kohm ] ( R T to GND )
Preliminary Information
Conversely, connecting a pull-up resistor (RT) from this pin to VCC reduces the switching frequency according to the following equation:
30.0E3 [ KHz Kohm ] F S = 200kHz - ----------------------------------------------------------R T [ Kohm ] ( R T to 12V )
Absolute Maximum Ratings
Min. Power Input Voltage, VIN Supply Voltage, VCC Boot Voltage, VBOOT - VPHASE VCC or I/O Voltage ESD Classification GND -0.3V Max. 6V +13.5V +13.5V VCC + 0.3V Class 2
Operating Conditions
Min. Supply Voltage, VCC Ambient Temperature Range Junction Temperature Range +12V -10% 0C 0C Max. +12V +10% 70C 125C
Thermal Characteristics
Parameter Thermal Resistance1 qJA SOIC Package SOIC Package Maximum Junction Temperature Maximum Storage Temperature Range Maximum Lead Temperature Soldering 10s Conditions Min. Typ. 110 86 150 -65 150 300 Max. Units C/W C/W C C C
With 3in2 of Copper Plastic Package
NOTE: 1. qJA is measured with the component mounted on an evaluation PC board in free air.
3
RC5054A
PRODUCT SPECIFICATION
Electrical Specifications
Symbol ICC Parameter Nominal Supply Power-On Reset Rising VCC Threshold Falling VCC Threshold Rising VOCSET Threshold Oscillator Free Running Frequency Total Variation RT = OPEN 6KW < RT to GND < 200KW RT = Open 185 -15 - -1.0 - - COMP = 10pF VBOOT - VPHASE = 12V VUGATE - VPHASE = 1V VCC = 12V, VLGATE = 6V VUGATE - VPHASE = 1V - 350 - 300 - - VOCSET = 4.5VDC VSEN = 5.5V, VOVP = 0V 170 60 - VSEN Rising VSEN Falling Upper and Lower Threshold IPGOOD = -5mA 106 89 - - 200 - 1.9 - 88 15 6 500 100 450 100 115 200 - 10 - - 2 0.5 215 +15 - +1.0 - - - - - - - 120 230 - - 111 94 - - KHz % VP-P % dB MHz V/ms mA mA mA mA % mA mA mA % % % V VOCSET = 4.5V VOCSET = 4.5V - 8.8 - - - 1.26 10.4 - - V V V Test Conditions UGATE and LGATE Open Min. - Typ. 22 Max. - Units mA VCC Supply Current
Preliminary Information
DVOSC
Ramp Amplitude DACOUT Voltage Accuracy
Reference and DAC Error Amplifier DC Gain GBW SR IUGATE IUGATE ILGATE ILGATE Protection Over-Voltage Trip (VSEN/DACOUT) IOCSET IOVP ISS OCSET Current Source OVP Sourcing Current Soft Start Current Upper Threshold (VSEN/DACOUT) Lower Threshold (VSEN/DACOUT) Hysteresis (VSEN/DACOUT) VPGOOD PGOOD Voltage Low Gain-Bandwidth Product Slew Rate Upper Gate Source Upper Gate Sink Lower Gate Source Lower Gate Sink
Gate Drivers
Power Good
Functional Description
Initialization
The RC5054A automatically initializes upon receipt of power. Special sequencing of the input supplies is not necessary. The Power-On Reset (POR) function continually monitors the input supply voltages. The POR monitors the bias volt-age at the VCC pin and the input voltage (VIN) on the OCSET pin. The level on OCSET is equal to VIN less a fixed voltage drop (see over-current protection). The POR function initiates soft start operation after both input supply voltages exceed their POR thresholds. For operation with a single +12V power source, VIN and VCC are equivalent and the 4
+12V power source must exceed the rising VCC threshold before POR initiates operation.
Soft Start
The POR function initiates the soft start sequence. An internal 10mA current source charges an external capacitor (CSS) on the SS pin to 4V. Soft start clamps the error amplifier output (COMP pin) and reference input (+ terminal of error amp) to the SS pin voltage. Figure 1 shows the soft start interval with CSS = 0.1mF. Initially the clamp on the error amplifier (COMP pin) controls the converter's output voltage. At t1 in Figure 1, the SS voltage reaches the valley of the oscillator's triangle wave. The oscillator's triangular
PRODUCT SPECIFICATION
RC5054A
Output Inductor
waveform is compared to the ramping error amplifier voltage. This generates PHASE pulses of increasing width that charge the output capacitor(s). This interval of increasing pulse width continues to t2. With sufficient output voltage, the clamp on the reference input controls the output voltage. This is the interval between t2 and t3 in Figure 1. At t3 the SS voltage exceeds the DACOUT voltage and the output voltage is in regulation. This method provides a rapid and controlled output voltage rise. The PGOOD signal toggles `high' when the output voltage (VSEN pin) is within 5% of DACOUT. The 2% hysteresis built into the power good comparators prevents PGOOD oscillation due to nominal output voltage ripple.
The over-current function will trip at a peak inductor current (IPEAK) determined by:
I OCSET * R OCSET I PEAK = ------------------------------------------R DS ( ON )
4V 2V 0V 15A 10A 5A 0A
Soft -Start
Preliminary Information
PGOOD (2V/DIV)
0V Time (20ms/DIV)
SOFT-START (1V/DIV) OUTPUT VOLTAGE (1V/DIV)
Figure 2. Over-Current Operation
0V 0V
t1 t2 t3
where IOCSET is the internal OCSET current source (200mA typical). The OC trip point varies mainly due to the MOSFET's RDS(ON) variations. To avoid over-current tripping in the normal operating load range, find the ROCSET resistor from the equation above with: * The maximum RDS(ON) at the highest junction temperature. * The minimum IOCSET from the specification table. * Determine IPEAK for IPEAK > IOUT(MAX) + (DI)/2, where DI is the output inductor ripple current. For an equation for the ripple current see the section under component guidelines titled `Output Inductor Selection.' A small ceramic capacitor should be placed in parallel with ROCSET to smooth the voltage across ROCSET in the presence of switching noise on the input voltage.
Time (5ms/DIV)
Figure 1. Soft Start Interval
Over-Current Protection
The over-current function protects the converter from a shorted output by using the upper MOSFET's on-resistance, RDS(ON) to monitor the current. This method enhances the converter's efficiency and reduces cost by eliminating a current sensing resistor. The over-current function cycles the soft-start function in a hiccup mode to provide fault protection. A resistor (ROCSET) programs the over-current trip level. An internal 200mA current sink develops a voltage across ROCSET that is referenced to VIN. When the voltage across the upper MOSFET (also referenced to VIN) exceeds the voltage across ROCSET , the over-current function initiates a soft-start sequence. The soft-start function discharges CSS with a 10mA current sink and inhibits PWM operation. The soft-start function recharges CSS, and PWM operation resumes with the error amplifier clamped to the SS voltage. Should an overload occur while recharging CSS, the soft start function inhibits PWM operation while fully charging CSS to 4V to complete its cycle. Figure 2 shows this operation with an overload condition. Note that the inductor current increases to over 15A during the CSS charging interval and causes an over-current trip. The converter dissipates very little power with this method. The measured input power for the conditions of Figure 2 is 2.5W.
Output Voltage Program
The output voltage of a RC5054A converter is programmed to discrete levels between 1.3VDC and 3.5VDC . The voltage identification (VID) pins program an internal voltage reference (DACOUT) with a 5-bit digital-to-analog converter (DAC). The level of DACOUT also sets the PGOOD and OVP thresholds. Table 1 specifies the DACOUT voltage for the 32 combinations of open or short connections on the VID pins. The output voltage should not be adjusted while the converter is delivering power. Remove input power before changing the output voltage. Adjusting the output voltage during operation could toggle the PGOOD signal and exercise the overvoltage protection. Grounding any combination of the VID pins increases the DACOUT voltage. 5
RC5054A
PRODUCT SPECIFICATION
Table 1. Output Voltage Table
PIN NAME VID4 0 0 0 0 0 0 0 0 VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 NOMINAL OUTPUT VOLTAGE 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05 PIN NAME VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 NOMINAL OUTPUT VOLTAGE SHDN 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5
Preliminary Information
0 0 0 0 0 0 0 0
Note: 1. 0 = connected to GND or VSS, 1 = OPEN
Typical Application
+12V VCC PGOOD SS OVP RT VID0 VID1 VID2 VID3 VID4 FB MONITOR AND PROTECTION OCSET EN BOOT VIN = +5V or +12V
OSC
UGATE PHASE +VOUT
RC5054
D/A + +
-
LGATE PGND VSEN GND
-
COMP
Applications Discussion
Layout Considerations
As in any high frequency switching converter, layout is very important. Switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. These interconnecting impedances should be minimized by 6
using wide, short printed circuit traces. The critical components should be located as close together as possible, using ground plane construction or single point grounding. Figure 3 shows the critical power components of the converter. To minimize the voltage overshoot the interconnecting wires indicated by heavy lines should be part of ground or power plane in a printed circuit board. The components
PRODUCT SPECIFICATION
RC5054A
shown in Figure 3 should be located as close together as possible. Please note that the capacitors CIN and CO each represent numerous physical capacitors. Locate the RC5054A within 3 inches of the MOSFETs, Q1 and Q2. The circuit traces for the MOSFETs' gate and source connections from the RC5054A must be sized to handle up to 1A peak current.
VIN
VIN OSC PWM COMPARATOR DRIVER LO DRIVER PHASE CO ESR (PARASITIC) ZFB VE/A + VOUT
DVOSC
-
+
RC5054A
UGATE PHASE Q2 LGATE PGND D2 Q1 LO
-
ZIN REFERENCE
VOUT LOAD
ERROR AMP
DETAILED COMPENSATION COMPONENTS
Preliminary Information
CIN
CO
C2 C1 R2
ZFB ZIN C3 R1 FB R3
VOUT
RETURN
COMP
-
Figure 3. Printed Circuit Board Power and Ground Planes or Islands
+
RC5054
DACOUT
Figure 4 shows the circuit traces that require additional layout consideration. Use single point and ground plane construction for the circuits shown. Minimize any leakage current paths on the SS PIN and locate the capacitor, CSS close to the SS pin because the internal current source is only 10mA. Provide local VCC decoupling between VCC and GND pins. Locate the capacitor, CBOOT as close as practical to the BOOT and PHASE pins.
BOOT CBOOT +VIN D1 Q1 L O VOUT VCC LOAD
Figure 5. Voltage-Mode Buck Converter Compensation Design
The modulator transfer function is the small-signal transfer function of VOUT/VE/A. This function is dominated by a DC Gain and the output filter (LO and CO), with a double pole break freaquency at FLC and a zero at FESR. The DC Gain of the modulator is simply the input voltage (VIN) divided by the peak-to-peak oscillator voltage DVOSC.
RC5054A
SS
PHASE +12V Q2 CO
Modulator Break Frequency Equations
1 F LC = -----------------------------------2p * L O * C O 1 F ESR = -----------------------------------2p * ESR * C O
CSS GND
CVCC
Figure 4. Printed Circuit Board Small Signal Layout Guidelines
Feedback Compensation
Figure 5 highlights the voltage-mode control loop for a synchronous-rectified buck converter. The output voltage (VOUT) is regulated to the Reference voltage level. The error amplifier (Error Amp) output (VE/A) is compared with the oscillator (OSC) triangular wave to provide a pulse-width modulated (PWM) wave with an amplitude of VIN at the PHASE node. The PWM wave is smoothed by the output filter (LO and CO).
The compensation network consists of the error amplifier (internal to the RC5054A) and the impedance networks ZIN and ZFB. The goal of the compensation network is to provide a closed loop transfer function with the highest 0dB crossing frequency (f0dB) and adequate phase margin. Phase margin is the difference between the closed loop phase at f0dB and 180 degrees. The equations below relate the compensation network's poles, zeros and gain to the components (R1, R2, R3, C1, C2, and C3) in Figure 5. Use these guidelines for locating the poles and zeros of the compensation network: 1. 2. 3. Pick Gain (R2/R1) for desired converter bandwidth Place 1ST Zero Below Filter's Double Pole (~75% FLC) Place 2ND Zero at Filter's Double Pole
7
RC5054A
PRODUCT SPECIFICATION
4. 5. 6. 7.
Place 1ST Pole at the ESR Zero Place 2ND Pole at Half the Switching Frequency Check Gain against Error Amplifier's Open-Loop Gain Estimate Phase Margin - Repeat if Necessary
function of the switching frequency and the ripple current. The load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. These requirements are generally met with a mix of capacitors and careful layout. Modern microprocessors produce transient load rates above 1A/ns. High frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (effective series resistance) and voltage rating requirements rather than actual capacitance requirements. High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. Consult with the manufacturer of the load on specific decoupling requirements. For example, Intel recommends that the high frequency decoupling for the Pentium Pro be composed of at least forty (40) 1mF ceramic capacitors in the 1206 surface-mount package. Use only specialized low-ESR capacitors intended for switching-regulator applications for the bulk capacitors. The bulk capacitor's ESR will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. An aluminum electrolytic capacitor's ESR value is related to the case size with lower ESR available in larger case sizes. However, the equivalent series inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. Unfortunately, ESL is not a specified parameter. Work with your capacitor supplier and measure the capacitor's impedance with frequency to select a suitable component. In most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor.
Compensation Break Frequency Equations
1 F Z1 = -------------------------------2p * R2 * C1 1 F P1 = --------------------------------------------------C1 * C2 2p * R2 * ae --------------------o e C1 + C2o 1 F P2 = -------------------------------2p * R3 * C3
1 F Z2 = -------------------------------------------------2p * ( R1 + R3 ) * C3
Preliminary Information
Figure 6 shows an asymptotic plot of the DC-DC converter's gain vs. frequency. The actual Modulator Gain has a high gain peak due to the high Q factor of the output filter and is not shown in Figure 6. Using the above guidelines should give a Compensation Gain similar to the curve plotted. The open loop error amplifier gain bounds the compensation gain. Check the compensation gain at FP2 with the capabilities of the error amplifier. The Closed Loop Gain is constructed on the log-log graph of Figure 6 by adding the Modulator Gain (in dB) to the Compensation Gain (in dB). This is equivalent to multiplying the modulator transfer function to the compensation transfer function and plotting the gain. The compensation gain uses external impedance networks ZFB and ZIN to provide a stable, high bandwidth (BW) overall loop. A stable control loop has a gain crossing with -20dB/decade slope and a phase margin greater than 45 degrees. Include worst case component variations when determining phase margin.
100 80 60 GAIN (dB) 40 20 0 -20 -40
FLC MODULATOR GAIN FESR 20LOG (R2/R1) 20LOG (VIN /DVOSC) COMPENSATION GAIN CLOSED LOOP GAIN OPEN LOOP ERROR AMP GAIN
FZ1 FZ2
FP1
FP2
Output Inductor Selection
The output inductor is selected to meet the output voltage ripple requirements and minimize the converter's response time to the load transient. The inductor value determines the converter's ripple current and the ripple voltage is a function of the ripple current. The ripple voltage and current are approximated by the following equations:
V IN - V OUT V OUT DI = ----------------------------- * -------------FS L V IN DV OUT = DI ESR
-60
10
100
1K
10K 100K 1M FREQUENCY (Hz)
10M
Figure 6. Asymptotic Bode Plot of Converter Gain
Increasing the value of inductance reduces the ripple current and voltage. However, the large inductance values reduce the converter's response time to a load transient. One of the parameters limiting the converter's response to a load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, the RC5054A will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply the load transient current. The filtering requirements are a 8
PRODUCT SPECIFICATION
RC5054A
required to slew the inductor current from an initial current value to the transient current level. During this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor. Minimizing the response time can minimize the output capacitance required. The response time to a transient is different for the application of load and the removal of load. The following equations give the approximate response time interval for application and removal of a transient load:
L I TRAN t RISE = ----------------------------V IN - V OUT L I TRAN t FALL = ------------------------V OUT
where: ITRAN is the transient load current step, tRISE is the response time to the application of load, and tFALL is the response time to the removal of load. With a +5V input source, the worst case response time can be either at the application or removal of load and dependent upon the DACOUT setting. Be sure to check both of these equations at the minimum and maximum output levels for the worst case response time.
In high-current applications, the MOSFET power dissipation, package selection and heatsink are the dominant design factors. The power dissipation includes two loss components; conduction loss and switching loss. The conduction losses are the largest component of power dissipation for both the upper and the lower MOSFETs. These losses are distributed between the two MOSFETs according to duty factor (see the equations below). Only the upper MOSFET has switching losses, since the Schottky rectifier clamps the switching node before the synchronous rectifier turns on. These equations assume linear voltage-current transitions and do not adequately model power loss due the reverserecovery of the lower MOSFET's body diode. The gatecharge losses are dissipated by the RC5054A and don't heat the MOSFETs. However, large gate-charge increases the switching interval, tSW which increases the upper MOSFET switching losses. Ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. A separate heatsink may be necessary depending upon MOSFET power, package type, ambient temperature and air flow.
Preliminary Information
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage overshoot across the MOSFETs. Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time Q1 turns on. Place the small ceramic capacitors physically close to the MOSFETs and between the drain of Q1 and the source of Q2. The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. The RMS current rating requirement for the input capacitor of a buck regulator is approximately 1/2 the DC load current. For a through hole design, several electrolytic capacitors (Panasonic HFQ series or Nichicon PL series or Sanyo MVGX or equivalent) may be needed. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. These capacitors must be capable of handling the surge-current at power-up. The TPS series available from AVX, and the 593D series from Sprague are both surge current tested.
P LOWER = I O R DS ( ON ) ( 1 - D ) 1 2 P UPPER = I O R DS ( ON ) D + -- Io V IN t SW F S 2
2
Where: D is the duty cycle = VOUT/VIN, tSW is the switching interval, and FS is the switching frequency Standard-gate MOSFETs are normally recommended for use with the RC5054A. However, logic-level gate MOSFETs can be used under special circumstances. The input voltage, upper gate drive level, and the MOSFET's absolute gateto-source voltage rating determine whether logic-level MOSFETs are appropriate. Figure 7 shows the upper gate drive (BOOT pin) supplied by a bootstrap circuit from VCC. The boot capacitor, CBOOT develops a floating supply voltage referenced to the PHASE pin. This supply is refreshed each cycle to a voltage of VCC less the boot diode drop (VD) when the lower MOSFET, Q2 turns on. Logic-level MOSFETs can only be used if the MOSFET's absolute gate-to-source voltage rating exceeds the maximum voltage applied to VCC.
MOSFET Selection/Considerations
The RC5054A requires 2 N-Channel power MOSFETs. These should be selected based upon RDS(ON), gate supply requirements, and thermal management requirements.
9
RC5054A
PRODUCT SPECIFICATION
+12V DBOOT +5V VCC + VD BOOT CBOOT UGATE PHASE Q1 NOTE: VG-S Y VCC -VD Q2 D2
RC5054A
Figure 9 shows the upper gate drive supplied by a direct connection to VCC. This option should only be used in converter systems where the main input voltage is +5VDC or less. The peak upper gate-to-source voltage is approximately VCC less the input supply. For +5V main power and +12VDC for the bias, the gate-to-source voltage of Q1 is 7V. A logic-level MOSFET is a good choice for Q1 and a logic-level MOSFET can be used for Q2 if its absolute gate-to-source voltage rating exceeds the maximum voltage applied to VCC.
+12V +5V OR LESS
+
-
LGATE PGND GND
VCC NOTE: VG-S YVCC
Preliminary Information
RC5054A
BOOT Q1 NOTE: VG-S Y VCC -5V Q2 D2 NOTE: VG-S Y VCC
Figure 7. Upper Gate Drive - Bootstrap Option
UGATE PHASE
Figure 8 shows a similar circuit for 12 Volt power input applications with two major differences. DBoot has been replaced with a 5.1 Volt Zener diode and a small resistor (5W-10W) is inserted in series with CBoot. This circuit will deliver the necessary drive voltage for Q1 while maintaining a safe operating voltage on pin 15 (Boot).
+12V DBOOT +12V VCC + VD BOOT CBOOT UGATE PHASE R Q1 NOTE: VG-S Y VCC -VD Q2 D2 NOTE: VG-S YVCC
-
+
LGATE PGND GND
Figure 9. Upper Gate Drive - Direct VCC Drive Option
Schottky Selection
Rectifier D2 is a clamp that catches the negative inductor swing during the dead time between turning off the lower MOSFET and turning on the upper MOSFET. The diode must be a Schottky type to prevent the lossy parasitic MOSFET body diode from conducting. It is acceptable to omit the diode and let the body diode of the lower MOSFET clamp the negative inductor swing, but efficiency will drop one or two percent as a result. The diode's rated reverse breakdown voltage must be greater than the maximum input voltage.
RC5054A
+
-
LGATE PGND GND
Figure 8. Upper Gate Drive Bootstrap Option-Server Application
10
PRODUCT SPECIFICATION
RC5054A
RC5054A DC-DC Converter Application Circuit
Figure 10 shows an application circuit of a DC-DC Converter for an Intel Pentium Pro microprocessor.
F1 VIN = +5V
L1 - 1mH
C1 5x 1000mF
2N6394 +12V 2K D1
2x 1mF
0.1mF 1000pF VCC 18 SS 3 0.1mF VSEN 1 RT VID0 VID1 VID2 VID3 VID4 FB 20 4 5 6 7 8 10 OSC OVP 19 2 OCSET 12 PGOOD 15 BOOT 0.1mF Q1 L2 3mH 1K
Preliminary Information
MONITOR AND PROTECTION
14 UGATE 13 PHASE
RC5054A
D/A
+VO
+
+ 9 11 COMP
17 LGATE 16 PGND GND
Q2
D2
-
CO 9x 1000mF
2.2nF 8.2nF 0.1mF 1.33K 15 20K
Component Selection Notes; C0 - 9 Each 1000mF 6.3W VDC, Sanyo MV-GX or Equivalent C1 - 5 Each 1000mF 25W VDC, Sanyo MV-GX or Equivalent L2 - Core: Micrometals T50-52B; Each Winding: 10 Turns of 16AWG L1 - Core: Micrometals T50-52; Winding: 5 Turns of 18AWG D1 - 1N4148 or Equivalent D2 - 3A, 40V Schottky, Motorola MBR340 or Equivalent Q1, Q2 - Fairchild FDB6030L
Figure 10. Pentium Pro DC-DC Converter
11
RC5054A
PRODUCT SPECIFICATION
Notes:
Preliminary Information
12
PRODUCT SPECIFICATION
RC5054A
Mechanical Dimensions (20 Lead SOIC)
Symbol A A1 B C D E e H h L N a ccc Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
.093 .104 .004 .012 .013 .020 .009 .013 .496 .512 .291 .299 .050 BSC .394 .010 .016 20 0 -- 8 .004 .419 .029 .050
2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 12.60 13.00 7.40 7.60 1.27 BSC 10.00 0.25 0.40 20 0 -- 8 0.10 10.65 0.75 1.27
3 6
Preliminary Information
20
11
E
H
1
10
D A e B A1 SEATING PLANE -C- LEAD COPLANARITY ccc C a
h x 45 C
L
13
RC5054A
PRODUCT SPECIFICATION
Ordering Information
Part Number RC5054ACB Temperature Range (C) 0 to 70 Package 20 Ld SOIC
Preliminary Information
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/28/98 0.0m 002 Stock#DS30005054 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC5054A
Programmable Synchronous DC-DC Converter Controller for Low Voltage Microprocessors
Features
* Drives Two N-Channel MOSFETs * Operates from +5V Power Input * Simple Single-Loop Control Design - Voltage-Mode PWM Control * Fast Transient Response - High-Bandwidth Error Amplifier - Full 0% to 100% Duty Ratio * Excellent Output Voltage Regulation * TTL Compatible 5 Bit Digital-to-Analog Output Voltage Selection - Wide Range - 1.3VDC to 3.5VDC - 0.1V Binary Steps from 2.1VDC to 3.5VDC - 0.05V Binary Steps from 1.3VDC to 2.1VDC * Power-Good Output Voltage Monitor * Over-Voltage and Over-Current Fault Monitors - Does Not Require Extra Current Sensing Element, Uses MOSFET's RDS(ON) * Small Converter Size - Constant Frequency Operation - 200kHz Free-Running Oscillator Programmable from 50kHz to 1MHz
Applications
* Power Supply for Pentium(R), Pentium Pro, PowerPCTM and AlphaTM Microprocessors * High-Power 5V to 3.xV DC-DC Regulators * Low-Voltage Distributed Power Supplies
Description
The RC5054A provides complete control and protection for a DC-DC converter optimized for high-performance microprocessor applications. It is designed to drive two N-Channel MOSFETs in a synchronous-rectified buck topology. The RC5054A integrates all of the control, output adjustment, monitoring and protection functions into a single package. The output voltage of the converter is easily adjusted and precisely regulated. The RC5054A includes a 5-input digitalto-analog converter (DAC) that adjusts the output voltage from 2.1VDC to 3.5VDC in 0.1V increments and from 1.3VDC to 2.1VDC in 0.05V steps. The RC5054A provides simple, single feedback loop, volt-
Block Diagram
VCC
VSEN 110% + POWER-ON RESET (POR)
-
PGOOD
90% + 115% + OVERVOLTAGE 10A OVP SOFTSTART OVERCURRENT 4V SS BOOT UGATE PHASE VID0 VID1 VID2 VID3 VID4 FB COMP GND RT OSCILLATOR D/A CONVERTER (DAC) DACOUT + PWM COMPARATOR GATE CONTROL LOGIC LGATE PGND
-
+ OCSET REFERENCE 200A
-
+
INHIBIT PWM
-
ERROR AMP
Rev. 1.0.2 Alpha is a trademark of Digital Equipment Corporation. Pentium is a registered trademark of Intel Corporation. PowerPC is a trademark of IBM Corporation.
RC5054A
PRODUCT SPECIFICATION
age-mode control with fast transient response. It includes a 200KHz free-running triangle-wave oscillator that is adjustable from 50KHz to 1MHz. The error amplifier features a 15MHz gain-bandwidth product and 6V/s slew rate which enables high converter bandwidth for fast transient performance. The resulting PWM duty ratio ranges from 0% to 100%. The RC5054A monitors the output voltage with a window comparator that tracks the DAC output and issues a Power Good signal when the output is within 10%. The RC5054A protects against over-current conditions by inhibiting PWM operation. Built-in over-voltage protection triggers an external SCR to crowbar the input supply. The RC5054A monitors the current by using the RDS(ON) of the upper MOSFET which eliminates the need for a current sensing resistor.
Pin Assignments
RC5054 (SOIC) TOP VIEW
VSEN OCSET SS VID0 VID1 VID2 VID3 VID4 COMP FB 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 RT OVP VCC LGATE PGND BOOT UGATE PHASE PGOOD GND
Pin Definitions
Pin Number Pin Names 1 VSEN Pin Function Description This pin is connected to the converter's output voltage. The PGOOD and OVP comparator circuits use this signal to report output voltage status and for overvoltage protection. Connect a resistor (ROCSET) from this pin to the drain of the upper MOSFET. ROCSET, an internal 200A current source (IOCS), and the upper MOSFET onresistance (RDS(ON)) set the converter over-current (OC) trip point according to the following equation:
I OCS * R OCSET I PEAK = --------------------------------------R DS ( ON )
2
OCSET
An over-current trip cycles the soft-start function. 3 4-8 SS VID0-VID4 Connect a capacitor from this pin to ground. This capacitor, along with an internal 10A current source, sets the soft-start interval of the converter. VID0-4 are the input pins to the 5-bit DAC. The states of these five pins program the internal voltage reference (DACOUT). The level of DACOUT sets the converter output voltage. It also sets the PGOOD and OVP thresholds. Table 1 specifies DACOUT for the 32 combinations of DAC inputs. COMP and FB are the available external pins of the error amplifier. The FB pin is the inverting input of the error amplifier and the COMP pin is the error amplifier output. These pins are used to compensate the voltage-control feedback loop of the converter. Signal ground for the IC. All voltage levels are measured with respect to this pin. PGOOD is an open collector output used to indicate the status of the converter output voltage. This pin is pulled low when the converter output is not within 10% of the DACOUT reference voltage. Connect the PHASE pin to the upper MOSFET source. This pin is used to monitor the voltage drop across the MOSFET for over-current protection. This pin also provides the return path for the upper gate drive. Connect UGATE to the upper MOSFET gate. This pin provides the gate drive for the upper MOSFET. This pin provides bias voltage to the upper MOSFET driver. A bootstrap circuit may be used to create a BOOT voltage suitable to drive a standard N-Channel MOSFET. This is the power ground connection. Tie the lower MOSFET source to this pin.
9 10
COMP FB
11 12
GND PGOOD
13
PHASE
14 15 16
UGATE BOOT PGND
2
PRODUCT SPECIFICATION
RC5054A
Pin Definitions (continued)
Pin Number Pin Names 17 18 19 20 LGATE VCC OVP RT Pin Function Description Connect LGATE to the lower MOSFET gate. This pin provides the gate drive for the lower MOSFET. Provide a 12V bias supply for the chip to this pin. The OVP pin can be used to drive an external SCR in the event of an overvoltage condition. This pin provides oscillator switching frequency adjustment. By placing a resistor (RT) from this pin to GND, the nominal 200KHz switching frequency is increased according to the following equation:
3.5 x 10 [ KHz x Kohm ] F S = 200kHz + -----------------------------------------------------------R T [ Kohm ]
6
( R T to GND )
Conversely, connecting a pull-up resistor (RT) from this pin to VCC reduces the switching frequency according to the following equation:
3 x 10 [ KHz x Kohm ] F S = 200kHz - ------------------------------------------------------R T [ Kohm ]
5
( R T to 12V )
Absolute Maximum Ratings
Min. Power Input Voltage, VIN Supply Voltage, VCC Boot Voltage, VBOOT - VPHASE VCC or I/O Voltage ESD Classification GND -0.3V Max. 6V +13.5V +13.5V VCC + 0.3V Class 2
Recommended Operating Conditions
Min. Supply Voltage, VCC Ambient Temperature Range Junction Temperature Range +12V -10% 0C 0C Max. +12V +10% 70C 125C
Thermal Characteristics
Parameter Thermal Resistance JA SOIC Package SOIC Package
1
Conditions
Min.
Typ. 110 86
Max.
Units C/W C/W
With 3in2 of Copper Plastic Package -65 Soldering 10s
Maximum Junction Temperature Maximum Storage Temperature Range Maximum Lead Temperature
150 150 300
C C C
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
3
RC5054A
PRODUCT SPECIFICATION
Electrical Specifications (Recommended Operating Conditions unless otherwise specified)
Symbol ICC Parameter Nominal Supply Power-On Reset Rising VCC Threshold Falling VCC Threshold Rising VOCSET Threshold Oscillator Free Running Frequency VOSC Ramp Amplitude Initial Voltage Setpoint Error Amplifier DC Gain GBW SR IUGATE IUGATE ILGATE ILGATE Protection Over-Voltage Trip (VSEN/DACOUT) IOCSET IOVP ISS OCSET Current Source OVP Sourcing Current Soft Start Current Upper Threshold (VSEN/DACOUT) Lower Threshold (VSEN/DACOUT) Hysteresis (VSEN/DACOUT) VPGOOD PGOOD Voltage Low VSEN Rising VSEN Falling Upper and Lower Threshold IPGOOD = -5mA VOCSET = 4.5VDC VSEN = 5.5V, VOVP = 0V - 170 60 - 106 89 - - 115 200 - 10 - - 2 0.5 120 230 - - 111 94 - - % A mA A % % % V Gain-Bandwidth Product Slew Rate Upper Gate Source Upper Gate Sink Lower Gate Source Lower Gate Sink COMP = 10pF VBOOT - VPHASE = 12V VUGATE - VPHASE = 1V VCC = 12V, VLGATE = 6V VUGATE - VPHASE = 1V - - - 350 - 300 - 88 15 6 500 100 450 100 - - - - - - - dB MHz V/s mA mA mA mA Reference and DAC ILOAD = 0.8A, VOUT = 2.000V 1.980 2.000 2.020 VOUT = 1.550V 1.534 1.550 1.566 V V RT = OPEN RT = Open 185 - 200 1.9 215 - KHz VP-P VOCSET = 4.5V VOCSET = 4.5V - 8.8 - - - 1.26 10.4 - - V V V Test Conditions UGATE and LGATE Open Min. - Typ. 22 Max. - Units mA VCC Supply Current
Gate Drivers
Power Good
4
PRODUCT SPECIFICATION
RC5054A
Functional Description
Initialization
The RC5054A automatically initializes upon receipt of power. Special sequencing of the input supplies is not necessary. The Power-On Reset (POR) function continually monitors the input supply voltages. The POR monitors the bias volt-age at the VCC pin and the input voltage (VIN) on the OCSET pin. The level on OCSET is equal to VIN less a fixed voltage drop (see over-current protection). The POR function initiates soft start operation after both input supply voltages exceed their POR thresholds. For operation with a single +12V power source, VIN and VCC are equivalent and the +12V power source must exceed the rising VCC threshold before POR initiates operation.
Over-Current Protection
The over-current function protects the converter from a shorted output by using the upper MOSFET's on-resistance, RDS(ON) to monitor the current. This method enhances the converter's efficiency and reduces cost by eliminating a current sensing resistor. The over-current function cycles the softstart function in a hiccup mode to provide fault protection. A resistor (ROCSET) programs the over-current trip level. An internal 200A current sink develops a voltage across ROCSET that is referenced to VIN. When the voltage across the upper MOSFET (also referenced to VIN) exceeds the voltage across ROCSET , the over-current function initiates a soft-start sequence. The soft-start function discharges CSS with a 10A current sink and inhibits PWM operation. The soft-start function recharges CSS, and PWM operation resumes with the error amplifier clamped to the SS voltage. Should an overload occur while recharging CSS, the soft start function inhibits PWM operation while fully charging CSS to 4V to complete its cycle. Figure 2 shows this operation with an overload condition. Note that the inductor current increases to over 15A during the CSS charging interval and causes an over-current trip. The converter dissipates very little power with this method. The measured input power for the conditions of Figure 2 is 2.5W. The over-current function will trip at a peak inductor current (IPEAK) determined by:
I OCSET * R OCSET I PEAK = ------------------------------------------R DS ( ON )
4V 2V 0V 15A 10A 5A 0A
Soft Start
The POR function initiates the soft start sequence. An internal 10A current source charges an external capacitor (CSS) on the SS pin to 4V. Soft start clamps the error amplifier output (COMP pin) and reference input (+ terminal of error amp) to the SS pin voltage. Figure 1 shows the soft start interval with CSS = 0.1F. Initially the clamp on the error amplifier (COMP pin) controls the converter's output voltage. At t1 in Figure 1, the SS voltage reaches the valley of the oscillator's triangle wave. The oscillator's triangular waveform is compared to the ramping error amplifier voltage. This generates PHASE pulses of increasing width that charge the output capacitor(s). This interval of increasing pulse width continues to t2. With sufficient output voltage, the clamp on the reference input controls the output voltage. This is the interval between t2 and t3 in Figure 1. At t3 the SS voltage exceeds the DACOUT voltage and the output voltage is in regulation. This method provides a rapid and controlled output voltage rise. The PGOOD signal toggles `high' when the output voltage (VSEN pin) is within 5% of DACOUT. The 2% hysteresis built into the power good comparators prevents PGOOD oscillation due to nominal output voltage ripple.
PGOOD (2V/DIV)
Output Inductor
Soft -Start
0V
Time (20ms/DIV)
SOFT-START (1V/DIV) OUTPUT VOLTAGE (1V/DIV)
Figure 2. Over-Current Operation
0V 0V
t1 t2 t3
where IOCSET is the internal OCSET current source (200A typical). The OC trip point varies mainly due to the MOSFET's RDS(ON) variations. To avoid over-current tripping in the normal operating load range, find the ROCSET resistor from the equation above with: * The maximum RDS(ON) at the highest junction temperature. * The minimum IOCSET from the specification table. * Determine IPEAK for IPEAK > IOUT(MAX) + (I)/2, where I is the output inductor ripple current. 5
Time (5ms/DIV)
Figure 1. Soft Start Interval
RC5054A
PRODUCT SPECIFICATION
For an equation for the ripple current see the section under component guidelines titled `Output Inductor Selection.' A small ceramic capacitor should be placed in parallel with ROCSET to smooth the voltage across ROCSET in the presence of switching noise on the input voltage.
Output Voltage Program
The output voltage of a RC5054A converter is programmed to discrete levels between 1.3VDC and 3.5VDC . The voltage identification (VID) pins program an internal voltage reference (DACOUT) with a 5-bit digital-to-analog converter
(DAC). The level of DACOUT also sets the PGOOD and OVP thresholds. Table 1 specifies the DACOUT voltage for the 32 combinations of open or short connections on the VID pins. The output voltage should not be adjusted while the converter is delivering power. Remove input power before changing the output voltage. Adjusting the output voltage during operation could toggle the PGOOD signal and exercise the overvoltage protection. Grounding any combination of the VID pins increases the DACOUT voltage.
Table 1. Output Voltage Table
PIN NAME VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 NOMINAL OUTPUT VOLTAGE 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05 PIN NAME VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 NOMINAL OUTPUT VOLTAGE SHDN 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5
Note: 1. 0 = connected to GND or VSS, 1 = OPEN
6
PRODUCT SPECIFICATION
RC5054A
Typical Application
+12V
VIN = +5V VCC PGOOD SS OVP RT VID0 VID1 VID2 VID3 VID4 FB MONITOR AND PROTECTION OCSET EN BOOT
OSC
UGATE PHASE +VOUT
RC5054
D/A + +
-
LGATE PGND VSEN GND
-
COMP
Applications Discussion
Layout Considerations
As in any high frequency switching converter, layout is very important. Switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. These interconnecting impedances should be minimized by using wide, short printed circuit traces. The critical components should be located as close together as possible, using ground plane construction or single point grounding. Figure 3 shows the critical power components of the converter. To minimize the voltage overshoot the interconnecting wires indicated by heavy lines should be part of ground or power plane in a printed circuit board The components shown in Figure 3 should be located as close together as possible. Please note that the capacitors CIN and CO each represent numerous physical capacitors. Locate the RC5054A within 3 inches of the MOSFETs, Q1 and Q2. The circuit traces for the MOSFETs' gate and source connections from the RC5054A must be sized to handle up to 1A peak current.
VIN
Figure 4 shows the circuit traces that require additional layout consideration. Use single point and ground plane construction for the circuits shown. Minimize any leakage current paths on the SS PIN and locate the capacitor, CSS close to the SS pin because the internal current source is only 10A. Provide local VCC decoupling between VCC and GND pins. Locate the capacitor, CBOOT as close as practical to the BOOT and PHASE pins.
BOOT CBOOT +VIN D1 Q1 L O VOUT VCC LOAD
RC5054A
SS
PHASE +12V Q2 CO
CSS GND
CVCC
Figure 4. Printed Circuit Board Small Signal Layout Guidelines
Feedback Compensation
Figure 5 highlights the voltage-mode control loop for a synchronous-rectified buck converter. The output voltage (VOUT) is regulated to the Reference voltage level. The error amplifier (Error Amp) output (VE/A) is compared with the oscillator (OSC) triangular wave to provide a pulse-width modulated (PWM) wave with an amplitude of VIN at the PHASE node. The PWM wave is smoothed by the output filter (LO and CO).
RC5054A
UGATE PHASE Q2 LGATE PGND D2 Q1 LO
VOUT LOAD
CIN
CO
RETURN
Figure 3. Printed Circuit Board Power and Ground Planes or Islands
7
RC5054A
PRODUCT SPECIFICATION
3.
VIN OSC PWM COMPARATOR DRIVER LO DRIVER PHASE CO ESR (PARASITIC) ZFB VE/A + ERROR AMP VOUT
Place 2ND Zero at Filter's Double Pole Place 1ST Pole at the ESR Zero Place 2ND Pole at Half the Switching Frequency Check Gain against Error Amplifier's Open-Loop Gain Estimate Phase Margin - Repeat if Necessary
4. 5. 6. 7.
DVOSC
-
+
Compensation Break Frequency Equations
ZIN REFERENCE
-
1 F Z1 = -------------------------------2 * R2 * C1
1 F P1 = --------------------------------------------------C1 * C2 2 * R2 * -------------------- C1 + C2 1 F P2 = -------------------------------2 * R3 * C3
DETAILED COMPENSATION COMPONENTS C2 C1 R2 ZFB ZIN C3 R1 FB R3 VOUT
1 F Z2 = -------------------------------------------------2 * ( R1 + R3 ) * C3
COMP
+
RC5054
DACOUT
Figure 5. Voltage-Mode Buck Converter Compensation Design
The modulator transfer function is the small-signal transfer function of VOUT/VE/A. This function is dominated by a DC Gain and the output filter (LO and CO), with a double pole break freaquency at FLC and a zero at FESR. The DC Gain of the modulator is simply the input voltage (VIN) divided by the peak-to-peak oscillator voltage VOSC.
Figure 6 shows an asymptotic plot of the DC-DC converter's gain vs. frequency. The actual Modulator Gain has a high gain peak due to the high Q factor of the output filter and is not shown in Figure 6. Using the above guidelines should give a Compensation Gain similar to the curve plotted. The open loop error amplifier gain bounds the compensation gain. Check the compensation gain at FP2 with the capabilities of the error amplifier. The Closed Loop Gain is constructed on the log-log graph of Figure 6 by adding the Modulator Gain (in dB) to the Compensation Gain (in dB). This is equivalent to multiplying the modulator transfer function to the compensation transfer function and plotting the gain. The compensation gain uses external impedance networks ZFB and ZIN to provide a stable, high bandwidth (BW) overall loop. A stable control loop has a gain crossing with -20dB/decade slope and a phase margin greater than 45 degrees. Include worst case component variations when determining phase margin.
100 80 60 GAIN (dB) 40 20 0 -20 -40
FLC MODULATOR GAIN FESR 20LOG (R2/R1) 20LOG (VIN /VOSC) COMPENSATION GAIN CLOSED LOOP GAIN OPEN LOOP ERROR AMP GAIN
Modulator Break Frequency Equations
1 F LC = -----------------------------------2 * L O * C O 1 F ESR = -----------------------------------2 * ESR * C O
FZ1 FZ2
FP1
FP2
The compensation network consists of the error amplifier (internal to the RC5054A) and the impedance networks ZIN and ZFB. The goal of the compensation network is to provide a closed loop transfer function with the highest 0dB crossing frequency (f0dB) and adequate phase margin. Phase margin is the difference between the closed loop phase at f0dB and 180 degrees. The equations below relate the compensation network's poles, zeros and gain to the components (R1, R2, R3, C1, C2, and C3) in Figure 5. Use these guidelines for locating the poles and zeros of the compensation network: 1. 2. Pick Gain (R2/R1) for desired converter bandwidth Place 1ST Zero Below Filter's Double Pole (~75% FLC)
-60
10
100
1K
10K 100K 1M FREQUENCY (Hz)
10M
Figure 6. Asymptotic Bode Plot of Converter Gain
8
PRODUCT SPECIFICATION
RC5054A
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply the load transient current. The filtering requirements are a function of the switching frequency and the ripple current. The load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. These requirements are generally met with a mix of capacitors and careful layout. Modern microprocessors produce transient load rates above 1A/ns. High frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (effective series resistance) and voltage rating requirements rather than actual capacitance requirements. High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. Consult with the manufacturer of the load on specific decoupling requirements. For example, Intel recommends that the high frequency decoupling for the Pentium Pro be composed of at least forty (40) 1F ceramic capacitors in the 1206 surface-mount package. Use only specialized low-ESR capacitors intended for switching-regulator applications for the bulk capacitors. The bulk capacitor's ESR will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. An aluminum electrolytic capacitor's ESR value is related to the case size with lower ESR available in larger case sizes. However, the equivalent series inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. Unfortunately, ESL is not a specified parameter. Work with your capacitor supplier and measure the capacitor's impedance with frequency to select a suitable component. In most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor.
Increasing the value of inductance reduces the ripple current and voltage. However, the large inductance values reduce the converter's response time to a load transient. One of the parameters limiting the converter's response to a load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, the RC5054A will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time required to slew the inductor current from an initial current value to the transient current level. During this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor. Minimizing the response time can minimize the output capacitance required. The response time to a transient is different for the application of load and the removal of load. The following equations give the approximate response time interval for application and removal of a transient load:
L x I TRAN t RISE = ----------------------------V IN - V OUT L x I TRAN tFALL = ------------------------V OUT
where: ITRAN is the transient load current step, tRISE is the response time to the application of load, and tFALL is the response time to the removal of load. With a +5V input source, the worst case response time can be either at the application or removal of load and dependent upon the DACOUT setting. Be sure to check both of these equations at the minimum and maximum output levels for the worst case response time.
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage overshoot across the MOSFETs. Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time Q1 turns on. Place the small ceramic capacitors physically close to the MOSFETs and between the drain of Q1 and the source of Q2. The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. The RMS current rating requirement for the input capacitor of a buck regulator is approximately 1/2 the DC load current. For a through hole design, several electrolytic capacitors (Panasonic HFQ series or Nichicon PL series or Sanyo MVGX or equivalent) may be needed. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. These capacitors must be capable of handling the surge-current at power-up. The TPS series available from AVX, and the 593D series from Sprague are both surge current tested. 9
Output Inductor Selection
The output inductor is selected to meet the output voltage ripple requirements and minimize the converter's response time to the load transient. The inductor value determines the converter's ripple current and the ripple voltage is a function of the ripple current. The ripple voltage and current are approximated by the following equations:
V IN - V OUT V OUT I = ----------------------------- * -------------FS x L V IN V OUT = I x ESR
RC5054A
PRODUCT SPECIFICATION
MOSFET Selection/Considerations
The RC5054A requires 2 N-Channel power MOSFETs. These should be selected based upon RDS(ON), gate supply requirements, and thermal management requirements. In high-current applications, the MOSFET power dissipation, package selection and heatsink are the dominant design factors. The power dissipation includes two loss components; conduction loss and switching loss. The conduction losses are the largest component of power dissipation for both the upper and the lower MOSFETs. These losses are distributed between the two MOSFETs according to duty factor (see the equations below). Only the upper MOSFET has switching losses, since the Schottky rectifier clamps the switching node before the synchronous rectifier turns on. These equations assume linear voltage-current transitions and do not adequately model power loss due the reverse-recovery of the lower MOSFET's body diode. The gate-charge losses are dissipated by the RC5054A and don't heat the MOSFETs. However, large gate-charge increases the switching interval, tSW, which increases the upper MOSFET switching losses. Ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. A separate heatsink may be necessary depending upon MOSFET power, package type, ambient temperature and air flow.
+12V DBOOT +5V VCC
RC5054A
BOOT CBOOT UGATE PHASE Q1 NOTE: VG-S VCC -VD Q2 D2 NOTE: VG-S VCC
+
-
LGATE PGND GND
Figure 7. Upper Gate Drive - Bootstrap Option
Figure 8 shows the upper gate drive supplied by a direct connection to VCC. This option should only be used in converter systems where the main input voltage is +5VDC or less. The peak upper gate-to-source voltage is approximately VCC less the input supply. For +5V main power and +12VDC for the bias, the gate-to-source voltage of Q1 is 7V. A logic-level MOSFET is a good choice for Q1 and a logic-level MOSFET can be used for Q2 if its absolute gate-to-source voltage rating exceeds the maximum voltage applied to VCC.
+12V
P LOWER =
2 IO
x R DS ( ON ) x ( 1 - D )
VCC
+5V OR LESS
1 2 P UPPER = I O x R DS ( ON ) x D + -- Io x V IN x t SW x F S 3 RC5054A
BOOT Q1 NOTE: VG-S VCC -5V Q2 D2 NOTE: VG-S VCC
Where: D is the duty cycle = VOUT/VIN, tSW is the switching interval, and FS is the switching frequency Standard-gate MOSFETs are normally recommended for use with the RC5054A. However, logic-level gate MOSFETs can be used under special circumstances. The input voltage, upper gate drive level, and the MOSFET's absolute gateto-source voltage rating determine whether logic-level MOSFETs are appropriate. Figure 7 shows the upper gate drive (BOOT pin) supplied by a bootstrap circuit from VCC. The boot capacitor, CBOOT develops a floating supply voltage referenced to the PHASE pin. This supply is refreshed each cycle to a voltage of VCC less the boot diode drop (VD) when the lower MOSFET, Q2 turns on. Logic-level MOSFETs can only be used if the MOSFET's absolute gate-to-source voltage rating exceeds the maximum voltage applied to VCC.
+
UGATE PHASE
LGATE PGND GND
Figure 8. Upper Gate Drive - Direct VCC Drive Option
Schottky Selection
Rectifier D2 is a clamp that catches the negative inductor swing during the dead time between turning off the lower MOSFET and turning on the upper MOSFET. The diode must be a Schottky type to prevent the lossy parasitic MOSFET body diode from conducting. It is acceptable to omit the diode and let the body diode of the lower MOSFET clamp the negative inductor swing, but efficiency will drop one or two percent as a result. The diode's rated reverse breakdown voltage must be greater than the maximum input voltage.
10
PRODUCT SPECIFICATION
RC5054A
RC5054A DC-DC Converter Application Circuit
Figure 10 shows an application circuit of a DC-DC Converter for an Intel Pentium Pro microprocessor.
F1 VIN = +5V
L1 - 1H
C1 5x 1000F
+12V 2N6394 47 2K
2x 1F
1 F 1000pF VCC 18 SS 3 0.1F VSEN 1 RT VID0 VID1 VID2 VID3 VID4 FB 20 4 5 6 7 8 10 OSC OVP 19 2 OCSET 12 PGOOD 15 BOOT 1K
MONITOR AND PROTECTION
14 UGATE 4.7 13 PHASE
Q1
RC5054A
D/A
L2 3H
+VO
+
+ 9 11 COMP
17 LGATE 4.7 16 PGND GND
Q2
D1
-
CO 9x 1000F
2.2nF 8.2nF 0.1F 1.33K 15 20K
Component Selection Notes; C0 - 9 Each 1000F 6.3W VDC, Sanyo MV-GX or Equivalent C1 - 5 Each 1000F 25W VDC, Sanyo MV-GX or Equivalent L2 - Core: Micrometals T50-52B; Each Winding: 10 Turns of 16AWG L1 - Core: Micrometals T50-52; Winding: 5 Turns of 18AWG D1 - 3A, 40V Schottky, Motorola MBR340 or Equivalent Q1, Q2 - Fairchild FDB6030L
Figure 9. Pentium Pro DC-DC Converter
11
RC5054A
PRODUCT SPECIFICATION
Mechanical Dimensions (20 Lead SOIC)
Symbol A A1 B C D E e H h L N ccc Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
.093 .104 .004 .012 .013 .020 .009 .013 .496 .512 .291 .299 .050 BSC .394 .010 .016 20 0 -- 8 .004 .419 .029 .050
2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 12.60 13.00 7.40 7.60 1.27 BSC 10.00 0.25 0.40 20 0 -- 8 0.10 10.65 0.75 1.27
3 6
20
11
E
H
1
10
D A e B A1 SEATING PLANE -C- LEAD COPLANARITY ccc C
h x 45 C
L
12
RC5054A
PRODUCT SPECIFICATION
Ordering Information
Part Number RC5054AM Temperature Range (C) 0 to 70 Package 20 Ld SOIC
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com 8/11/99 0.0m 004 Stock#DS30005054 (c) 1998 Fairchild Semiconductor Corporation
www.fairchildsemi.com
RC5055
Programmable Synchronous DC-DC Converter Controller for Low Voltage Microprocessors, Vtt and Clock Linear Regulator
Features
* Current Sensing is achieved using MOSFET RDS(ON) * Programmable output from 1.3V to 3.5V using an integrated 5-bit DAC * 85% efficiency typical at full load * Adjustable operation from 100KHz to 1MHz * Integrated Power Good and Enable/Soft Start functions * Overvoltage protection pin controls external SCR * Short circuit protection with current limiting * Drives N-channel MOSFETs * 24 pin SSOP and SOIC package * Meets Intel Pentium II specifications using minimum number of external components * On board Linear regulator for GTL termination * On board fixed linear regulator for Clock power supply * TTL Compatible inputs
Description
The RC5055 is a triple combo combining a synchronous DC-DC controller with a fixed 2.5V output linear regulator and an adjustable linear regulator. The synchronous mode DC-DC controller provides an accurate, programmable output voltage for all Pentium II CPU applications. It uses a 5-bit D/A converter to program the output voltage from 1.3V to 3.5V and uses a high level of integration to deliver load currents in excess of 17A from a 5V source with minimal external circuitry. Synchronous-mode operation offers optimum efficiency over the entire specified output voltage range, and the internal oscillator can be programmed from 100KHz to 1MHz for additional flexibility in choosing external components. An on-board precision low TC reference achieves tight tolerance voltage regulation without expensive external components. The RC5055 also offers integrated functions including Power Good, Output Enable/Soft Start, over-voltage protection and current limiting.
Applications
* Power supply for Pentium(R) II * VRM for Pentium II processor * Programmable step-down power supply
Block Diagram
VCC 20 VSEN 1 110% + 90% + 115% OVERVOLTAGE + + - OVERCURRENT REFERENCE 6 7 8 9 10 200A 4V SOFTSTART 10A 23 3 19 18 17 GATE CONTROL LOGIC 21 22 LGATE PGND GNDA OVP SS BOOT UGATE PHASE VID0 VID1 VID2 VID3 VID4 FB 14 COMP RT 13 15 24 OPAMP1 GATE1 FB1 OSCILLA TOR D/A CONVERTER (DAC) DACOUT + ERROR AMP PWM COMPARATOR + INHIBIT PWM 16 POWER-ON RESET (POR)
PGOOD
OCSET
2
+
4 5
VREF FIXED 2.5V LINEAR REGULATOR 11 12 LVIN LVOUT
-
Pentium is a registered trademark of Intel Corporation.
Rev. 1.01
RC5055
PRODUCT SPECIFICATION
Pin Assignments
VSEN OCSET SS GATE1 FB1 VID0 VID1 VID2 VID3 VID4 LVIN LVOUT
1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13
65-5055-02
RT OVP PGND LGATE VCC BOOT UGATE PHASE PGOOD GND FB COMP
Pin Definitions
Pin Number Pin Name 1 VSEN Pin Function Description This pin is connected to the converter's output voltage. The PGOOD and OVP comparator circuits use this signal to report output voltage status and for overvoltage protection. Connect a resistor (ROCSET) from this pin to the drain of the upper MOSFET. An internal 200A current source (Iocs) and the upper MOSFET RDS(ON) set the converter peak over-current trip point: I OCS * R OCSET I PEAK = -------------------------------------R DS ( ON ) Soft Start. A capacitor from this point to ground together with an internal 10A will cause the output duty cycle to increase slowly Linear Regulator Error Amplifier Output. Linear Regulator Error Amplifier Inverting Input. When FB1 and GATE1 are tied together the Output Voltage = Vref DAC inputs. Used to adjust the output voltage to the voltage required by the processor. Input for fixed linear regulator 2.5V fixed output from fixed linear regulator PWM Loop Error Amplifier output. PWM Loop Voltage Feedback. Inverting input of Error Amplifier. Analog Ground. Power good. This pin is pulled low when any of the regulator's output is not within the spec. Connect the PHASE pin to the upper MOSFET source. This pin is used to monitor the voltage drop across the MOSFET for over-current protection. This pin also provides the return path for the upper gate drive. Upper MOSFET gate driver Upper MOSFET bootstrap. 12V bias supply. Low MOSFET gate driver. Power ground. Over-voltage Protection. This pin drives an external SCR. Oscillator switching frequency adjust according to the following equations: 3.5 x 10 [ KHz x Kohm ] F S = 200kHz + -----------------------------------------------------------R T [ Kohm ] 3 x 10 [ KHz x Kohm ] F S = 200kHz - ------------------------------------------------------R T [ Kohm ]
5 6
2
OCSET
3 4 5 6-10 11 12 13 14 15 16 17
SS GATE1 FB1 VID0-4 LVIN LVOUT COMP FB GND PGOOD PHASE
18 19 20 21 22 23 24
UGATE BOOT VCC LGATE PGND OVP RT
( R T to GND ) ( R T to 12V )
2
PRODUCT SPECIFICATION
RC5055
Absolute Maximum Ratings
Parameter Power Input Voltage, Vin Supply Voltage Vcc Boot Voltage, VBOOT-VPHASE I/O Voltages ESD Classification GND-0.3V Min. Max. 6V 13.5V 13.5V Vin+0.3V Class 2
Operating Conditions
Parameter Supply Voltage Ambient Temperature Junction Temperature Min. +12V -10% 0C 0C Max. +12+10% 70C 125C
Thermal Information
Parameter Thermal Resistance, JA Maximum Junction Temperature Storage Temperature Maximum Lead Temperature Soldering 10 Seconds -65C SOIC SSOP Conditions Min. Typ. 80 89 Max. C/W 150C 150C 300C
Electrical Specifications
(VCC=12V, FOSC=200KHz and TA=25C using circuit in figure 1, unless otherwise noted) Parameter PWM Section VCC Supply Current Nominal Supply Power-On Reset Rising VCC Threshold Falling VCC Threshold Rising VOCSET Threshold Oscillator Free Running Frequency Ramp Amplitude Reference and DAC Input Voltage Setpoint Error Amplifier DC Gain Gain-Bandwidth Product Slew Rate ADC GBW SR COMP = 10pF - - - 88 15 6 - - - dB MHz V/s ILOAD = 0.8A, VOUT=2.000V VOUT=1.550V 1.980 1.534 2.000 1.550 2.020 1.566 V V FS VOSC RT = OPEN RT = OPEN 185 - 200 1.9 215 - kHz VP-P VOCSET = 4.5V VOCSET = 4.5V - 8.8 - - - 1.26 10.4 - - V V V ICC UGATE and LGATE Open - 24 35 mA Symbol Test Conditions Min. Typ. Max. Units
3
RC5055
PRODUCT SPECIFICATION
Electrical Specifications (continued) (VCC=12V, FOSC=200KHz and TA=25C using circuit in figure 1, unless otherwise noted)
Parameter Gate Driver Upper Gate Source Current Lower Gate Source Current Protection Over-Voltage Trip (VSEN/DACOUT) OCSET Current Source OVP Sourcing Current Soft Start Current Power Good Upper Threshold (VSEN /DACOUT) Lower Threshold (VSEN /DACOUT) Hysteresis (VSEN /DACOUT) PGOOD Voltage Low Adjustable Linear Regulator Output Voltage Output Voltage Precision Set by external resistors ILOAD = 50 mAto 5.4A VCC = 12V 10% TA = 0 to 70C Power good trigger point GATE 1 50mA to 4.4 Amp Set by ESR of output caps FB 1 FB 1 20 -135 1 1.265 135 1.3 -2 +2 V % VSEN Rising VSEN Falling Upper and Lower Threshold VPGOOD IPGOOD = -5mA 106 89 - - - - 2 0.5 111 94 - - % % % V IOCSET IOVP ISS VOCSET = 4.5VDC VSEN = 5.5V; VOVP = 0V - 170 60 - 115 200 - 10 120 230 - - % A mA A IUGATE ILGATE VBOOT - VPHASE = 12V VCC = 12V, VLGATE = 6V 1 1 - - A A Symbol Test Conditions Min. Typ. Max. Units
Under Voltage Level Controller Output Current Output Transient Tolerance Bias Current Feedback Voltage Fixed Linear Regulator Output Voltage Under Voltage Level Output Current Over Current Trip Point ISC Foldback Input Voltage VIN IOUT VOUT
60
% mA mV A V
ILOAD 100mA VCC = 12V 10% VIN = 5V Power good trigger point VCC = 12V 10% VIN = 5V VCC = 12V 10% VIN = 5V VOUT = 0 VCC = 12V 10%
2.375
2.5 60
2.625
V % mA
100 150 25 4.75 5 5.25
mA mA V
4
PRODUCT SPECIFICATION
RC5055
+12V
F1
R1 10
L1 0.9uH (optional)
Vin = +5 (optional)
VCC 20 23 SS 3 2 16 R11 R2 51.1K RT 24 19 BOOT R12 4.7 VID0 VID1 VID2 VID3 VID4 COMP R3 30K C4 6.8nF 14 FB R6 1 VSEN 22 6 7 8 9 10 13 R13 21 LGATE PGND 4.7 18 UGATE PHASE 3K OVP C12 1000pF OCSET PGOOD R4 3.3V
C9-11 3 x 15000uF Q2 2N6394
(optional)
C1 1uF
R9 10K
C2 .1uF
R10 1K C13 1uF C14 1uF
C15 1uF
Q3 FDB6030L
R14 L2 1.3uH 20K C16 .1uF R15 7.5K +Vo
U1 RC5055
17
Q4 FDB6030L
C3 390pF
D1 MBRS320
C17-22 6 x 1500uF
R4 12 R5 1K
C5 .1uF
Q1 3.3V GATE1 1.5V C8 22F NDB4050 R7 187 4 5 C6-7 2 x 1500uF FB1 15 GNDA 12 VOUT 2.5V C23 270uF R8 1K 11 VIN 5V
Figure 1. Deschutes 400MHz DC-DC Converter
5
RC5055
PRODUCT SPECIFICATION
Table 1. Deschutes 400MHz DC-DC Converter Bill of Materials
Item C1, C13-15 C2, C5, C16 C3 C4 C6-7, C17-22 C8 C9-11 C12 C23 D1 L1 L2 Q1 Q2 Q3-4 R1 R2 R3 R4 R5, R8, R10 R6 R7 R9 R11 R12-13 R14 R15 F1 U1 Sanyo 10MV1200GX Any Sanyo 6MV270GX Fairchild MBRS320L Any Any Fairchild NDB4050 Motoraola 2N6394 Fairchild FDB6030L Any Any Any Any Any Any Any Any Any Any Any Any Littelfuse Fairchild RC5055M Manufacturer Part # Any Any Any Any Sanyo 6MV1500GX Quantity 4 3 1 1 8 1 3 1 1 1 Optional 1 1 1 2 1 1 1 1 3 1 1 1 1 2 1 1 1 1 187 10K 3.01K 4.7 20K 7.5K 12A, 32V fast-acting fuse DC/DC Controller Description 1F, 16V Capacitor 100nF, 50V Capacitor 390pF, 50V Capacitor 6.8nF, 50V Capacitor 1500F, 6.3V Electrolytic 22F, 16V Capacitor 1200F, 10V Electrolytic 1nF, 50V Capacitor 270F, 6.3V Electrolytic 3A, 20V Schottky Diode 0.9H inductor 1.3H inductor1.3H N-Channel MOSFET SCR N-Channel MOSFET 10 51.1K 30.1K 12 1K Used to adjust output voltage offset. RDS(ON) =20m @ VGS = 4.5V See Note 1. See Note 2. IRMS = 2A ESR 44M Requirements/Comments
Notes: 1. 12 turns of 16AWG wire on mocrometals T60-2 core. 2. 9 turns of 16AWG wire on Micrometals T50-8/90 core.
6
PRODUCT SPECIFICATION
RC5055
Applications
Increasing the Clock Current
The RC5055 can produce as much as 100mA of current at 2.5V for powering the motherboard's clock chips. If additional current capability is required, an external PNP transistor may be used to enhance the current to 600mA or more, as shown in Figure 2. This circuit also provides a measure of current limit by letting the first 100mA of current be sourced through the 6.8 resistor, so that if too much collector, and thus base, current is demanded, the RC5055 cuts off the drive to the base.
6.8
5V
20 11 TIP32B
RC5055
12 1F 270F 2.5V
65-5055-05
Figure 2. Boosting the Clock Current
Table 2. Output Voltage Table
PIN NAME VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 NOMINAL OUTPUT VOLTAGE 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05 PIN NAME VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 NOMINAL OUTPUT VOLTAGE 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5
Note: 1. 0 = connected to GND or VSS, 1 = OPEN
7
RC5055
PRODUCT SPECIFICATION
Package Dimensions
24-pin SSOP package
Symbol A A1 A2 b c D E E1 e L N ccc Inches Min. -- .002 .065 .010 .0035 .311 .291 Max. .078 -- .073 .015 .010 .335 .323 Millimeters Min. -- 0.05 1.65 0.22 0.09 7.90 7.40 Max. 2.00 -- 1.85 0.38 0.25 8.50 8.20 2 3 6 5 5 2, 4 Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .006 inch (0.15mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5. "b" and "c" dimensions include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
.197 .220 .026 BSC .022 .037 24 0 -- 8 .004
5.00 5.60 0.65 BSC 0.55 0.95 24 0 -- 8 0.10
D
E1
E
A
A2 B e
A1 SEATING PLANE -C- LEAD COPLANARITY ccc C L
C
8
PRODUCT SPECIFICATION
RC5055
24-pin .300 mil SOIC package
Symbol A A1 B C D E e H h L N ccc Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
.093 .104 .004 .012 .013 .020 .009 .013 .599 .614 .290 .299 .050 BSC .394 .419 .010 .016 24 0 -- 8 .004 .020 .050
2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 15.20 15.60 7.36 7.60 1.27 BSC 10.00 10.65 0.25 0.40 24 0 -- 8 0.10 0.51 1.27
3 6
24
13
E
H
1
12
D A e B A1 SEATING PLANE -C- LEAD COPLANARITY ccc C L
h x 45 C
9
RC5055
PRODUCT SPECIFICATION
Notes
10
RC5055
PRODUCT SPECIFICATION
Ordering Information
Product Number RC5055G RC5055M Package 24 pin SSOP 24 pin SOIC
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com 8/11/99 0.0m 008 Stock#DS30005055 (c) 1998 Fairchild Semiconductor Corporation
www.fairchildsemi.com
RC5056
Programmable Synchronous DC-DC Converter Controller for Low Voltage Microprocessors and Vtt Linear Regulator
Features
* Current Sensing is achieved using MOSFET RDS(ON) * Programmable output from 1.3V to 3.5V using an integrated 5-bit DAC * 85% efficiency typical at full load * Adjustable operation from 50KHz to 1MHz * Integrated Power Good and Enable/Soft Start functions * Overvoltage protection pin controls external SCR * Short circuit protection with current limiting * Drives N-channel MOSFETs * 20 pin SSOP and SOIC package * Meets Intel Pentium II specifications using minimum number of external components * On board LDO for GTL termination * On board LDO for Clock power supply * TTL Compatible inputs
Description
The RC5056 is a synchronous mode DC-DC controller IC which provides an accurate, programmable output voltage for all Pentium II CPU applications. The RC5056 uses a 5-bit D/A converter to program the output voltage from 1.3V to 3.5V. The RC5056 uses a high level of integration to deliver load currents in excess of 17A from a 5V source with minimal external circuitry. Synchronous-mode operation offers optimum efficiency over the entire specified output voltage range, and the internal oscillator can be programmed from 50KHz to 1MHz for additional flexibility in choosing external components. An on-board precision low TC reference achieves tight tolerance voltage regulation without expensive external components. The RC5056 also offers integrated functions including Power Good, Output Enable/ Soft Start, over-voltage protection and current limiting. The linear regulator is also specified at 1% precision.
Preliminary Information
Applications
* Power supply for Pentium(R) II * VRM for Pentium II processor * Programmable step-down power supply
Block Diagram
VCC 16 VSEN 20 110% + 90% + 115% OVERVOLTAGE + + - OVERCURRENT REFERENCE 5 6 7 8 9 200A 4V SOFTSTART 10A 23 2 OVP SS 13 POWER-ON RESET (POR)
PGOOD
OCSET
1
15 14 GATE CONTROL LOGIC 17 18
UGATE PHASE
VID0 VID1 VID2 VID3 VID4 FB
D/A CONVERTER (DAC)
DACOUT + ERROR AMP
PWM COMPARATOR + INHIBIT PWM
LGATE PGND GNDA
11 COMP OVP/RT 10
12 19 OPAMP1 GATE1 FB1 OSCILLATOR
+
3 4
VREF
-
65-5056-01
Pentium is a registered trademark of Intel Corporation.
Rev. 0.9.0
PRELIMINARY INFORMATION describes products that are not in full production at the time of printing. Specifications are based on design goals and limited characterization. They may change without notice. Contact Fairchild Semiconductor for current information.
RC5056
PRODUCT SPECIFICATION
Pin Assignments
OCSET SS GATE1 FB1 VID0 VID1 VID2 VID3 VID4 COMP
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
65-5056-02
VSEN OVP/RT PGND LGATE VCC UGATE PHASE PGOOD GNDA FB
Preliminary Information
Pin Definitions
Pin Number Pin Name 20 VSEN Pin Function Description This pin is connected to the converter's output voltage. The PGOOD and OVP comparator circuits use this signal to report output voltage status and for overvoltage protection. Connect a resistor (ROCSET) from this pin to the drain of the upper MOSFET. An internal 200A current source (Iocs) and the upper MOSFET RDS(ON) set the converter peak over-current trip point: I OCS * R OCSET I PEAK = -------------------------------------R DS ( ON ) Soft Start. A capacitor from this point to ground together with an internal 10A will cause the output duty cycle to increase slowly First LDO Error Amplifier Output. First LDO Error Amplifier Inverting Input. When FB1 and GATE1 are tied together the Output Voltage = Vref DAC inputs. Used to adjust the output voltage to the voltage required by the processor. PWM Loop Error Amplifier output. PWM Loop Voltage Feedback. Inverting input of Error Amplifier. Signal Ground. Power good. This pin is pulled low when the converter output is not within 10% of the Dacout reference voltage. Connect the PHASE to the upper MOSFET source. Upper MOSFET gate driver 12V bias supply. Low MOSFET gate driver. Power ground. Over-voltage Protection. This pin drives an external SCR. 5 x 10 [ KHz x Kohm ] FS = 200kHz + ------------------------------------------------------R T [ Kohm ] 4 x 10 [ KHz x Kohm ] F S = 200kHz - ------------------------------------------------------R T [ Kohm ]
7 6
1
OCSET
2 3 4 5-9 10 11 12 13 14 15 16 17 18 19
SS GATE1 FB1 VID0-4 COMP FB GND PGOOD PHASE UGATE VCC LGATE PGND OVP/RT
( RT to GND ) ( RT to 12V )
2
PRODUCT SPECIFICATION
RC5056
Absolute Maximum Ratings
Parameter Power Input Voltage, Vin Supply Voltage Vcc Boot Voltage, VBOOT-VPHASE I/O Voltages ESD Classification GND-0.3V Min. Max. 6V 13.5V 13.5V Vcc+0.3V Class 2
Operating Conditions
Parameter Supply Voltage Ambient Temperature Junction Temperature Min. +12V -10% 0C 0C Max. +12+10% 70C 125C
Preliminary Information
Thermal Information
Parameter Thermal Resistance SOIC 24 pin package Maximum Junction Temperature Storage Temperature Maximum Lead Temperature Soldering 10 Seconds Conditions With TBD in of Copper Plastic Package -65C 150C 150C 300C
2
Min.
Typ.
Max.
Electrical Specifications
(VCC=12V, FOSC=200KHz and TA=25C using circuit in figure 1, unless otherwise noted) Parameter PWM Section VCC Supply Current Nominal Supply Power-On Reset Rising VCC Threshold Falling VCC Threshold Rising VOCSET Threshold Oscillator Free Running Frequency Total Variation Ramp Amplitude Reference and DAC DACOUT Voltage Accuracy Error Amplifier DC Gain Gain-Bandwidth Product Slew Rate ADC GBW SR COMP = 10pF - - - 88 15 6 - - - dB MHz V/s -1.0 - +1.0 % VOSC FS RT = OPEN 6k < RT to GND < 200k RT = OPEN 185 -15 - 200 - 1.9 215 +15 - kHz % VP-P VOCSET = 4.5V VOCSET = 4.5V - 8.8 - - - 1.26 10.4 - - V V V ICC UGATE and LGATE Open - 22 - mA Symbol Test Conditions Min. Typ. Max. Units
3
RC5056
PRODUCT SPECIFICATION
Electrical Specifications
Parameter Gate Driver Upper Gate Source Current Upper Gate Sink Current Lower Gate Source Current Lower Gate Sink Current Protection
(continued) (VCC=12V, FOSC=200KHz and TA=25C using circuit in figure 1, unless otherwise noted) Symbol IUGATE IUGATE ILGATE ILGATE Test Conditions VBOOT - VPHASE = 12V VUGATE - VPHASE = 1V VCC = 12V, VLGATE = 6V VUGATE - VPHASE = 1V Min. 350 - 350 - - IOCSET IOVP ISS VSEN Rising VSEN Falling Upper and Lower Threshold VPGOOD IPGOOD = -5mA Set by external resistors ILOAD = 50 mAto 5.4A VCC = 12V 10% TA = 0 to 70C R1 = TBD R2 = TBD GATE 1 50mA to 4.4 Amp Set by ESR of output caps FB 1 FB 1 VOCSET = 4.5VDC VSEN = 5.5V; VOVP = 0V 170 60 - 106 89 - - 1.3 -2 +2 Typ. 500 100 450 100 115 200 - 10 - - 2 0.5 Max. - - - - 120 230 - - 111 94 - - Units mA mA mA mA % A mA A % % % V V %
Over-Voltage Trip (VSEN/DACOUT) OCSET Current Source
Preliminary Information
OVP Sourcing Current Soft Start Current Power Good Upper Threshold (VSEN /DACOUT) Lower Threshold (VSEN /DACOUT) Hysteresis (VSEN /DACOUT) PGOOD Voltage Low Adjustable Linear Regulator Output Voltage Output Voltage Precision
Controller Output Current Output Transient Tolerance Bias Current Feedback Voltage
20 -135 1 1265 135
mA mV A mV
4
PRODUCT SPECIFICATION
RC5056
F1 VIN = +5V
L1 - 1H
C1 5x 330 F
2N6394 +12V 2K
2x 1F
0.1F 1000pF VCC 16 SS 2 0.1F VSEN 20 OSC VID0 VID1 VID2 VID3 VID4 FB 0.2F 20K 0.1F 15 1.33K COMP 3.3V Q3 +1.5V C3 Gate 1 R1 182 R2 1K 3 + VREF 12 GNDA 5 6 7 8 9 11 2.2F OVP/RT 19 1 OCSET 13 PGOOD 1K
MONITOR AND PROTECTION
15 UGATE 14 PHASE
Q1
RC5055
D/A
L2 3H
Preliminary Information
+VO
+
+
17 LGATE 18 PGND
Q2
D2
-
CO 6x 1000F
10
-
4 FB1
65-5056-03
Figure 1. Pentium II DC-DC Converter
Table 1. Bill of Materials for Figure 1
Item C0 C1 C3 R1 R2 L1 L2 D1 D2 Q1, Q2 Q3 Quantity 6 5 2 1 2 1 1 1 1 2 1 Manufacturer Sanyo Sanyo Sanyo Generic Generic Micrometals Micrometals Generic Motorola Fairchild Semiconductor Fairchild Semiconductor Core: T50-52 Core: T50-52B 1N4148 MBR340 NDB7030L NDB4050 Part Number MV-GX MV-GX 10MV1200GX Description 1000F 6.3 WVDC 330F 25 WVDC 1200F 10 WVDC 182 1% 1K 1% 5 Turns of 18 AWG Copper Wire 5 Turns of 16 AWG Copper Wire Diode Schottky Diode Power MOSFET MOSFET RDS(ON) = 1
5
RC5056
PRODUCT SPECIFICATION
The output voltage of a RC5056 converter is programmed to discrete levels between 1.3VDC and 3.5VDC . The voltage identification (VID) pins program an internal voltage reference (DACOUT) with a 5-bit digital-to-analog converter (DAC). The level of DACOUT also sets the PGOOD and OVP thresholds. Table 2 specifies the DACOUT voltage for the 32 combinations of open or short connections on the VID pins. The output voltage should not be adjusted while the converter is delivering power. Remove input power before
changing the output voltage. Adjusting the output voltage during operation could toggle the PGOOD signal and exercise the overvoltage protection. The DAC function is a precision non-inverting summation amplifier shown in Figure 2. The resistor values shown are only approximations of the actual precision values used. Grounding any combination of the VID pins increases the DACOUT voltage. The `open' circuit voltage on the VID pins is the band gap reference voltage, 1.26V.
Table 2. Output Voltage Table
Preliminary Information
PIN NAME VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
NOMINAL OUTPUT VOLTAGE 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05
PIN NAME VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
NOMINAL OUTPUT VOLTAGE 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5
Note: 1. 0 = connected to GND or VSS, 1 = OPEN
6
PRODUCT SPECIFICATION
RC5056
Absolute Maximum Ratings
Power Input Voltage, Vin Supply Voltage Vcc
Vcc or I/O Voltage
ESD Classification
6V 13.5V Vcc+0.3V Class 2
Package Dimensions
20-pin SOIC package
Symbol A A1 B C D E e H h L N ccc Inches Min. .093 .004 .013 .009 .496 Max. .104 .012 .020 .013 .512 Millimeters Min. 2.35 0.10 0.33 0.23 12.60 Max. 2.65 0.30 0.51 0.32 13.00 5 2 2 Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm).
Preliminary Information
3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
.291 .299 .050 BSC .394 .010 .016 20 0 -- 8 .004 .419 .029 .050
7.40 7.60 1.27 BSC 10.00 0.25 0.40 20 0 -- 8 0.10 10.65 0.75 1.27
3 6
20
11
E
H
1
10
D A e B A1 SEATING PLANE -C- LEAD COPLANARITY ccc C
h x 45 C
L
7
RC5056
PRODUCT SPECIFICATION
Ordering Information
Product Number RC5056M Package 20 pin SOIC
Preliminary Information
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 1/14/99 0.0m 001 Stock#DS30005056 (c) 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC5057
High Performance Programmable Synchronous DC-DC Controller for Low Voltage Microprocessors
Features
Programmable output from 1.3V to 3.5V using an integrated 5-bit DAC Remote sense Active Droop 85% efciency typical at full load Integrated Power Good and Enable/Soft Start functions Drives N-channel MOSFETs Overcurrent protection using MOSFET sensing 16 pin SOIC package Meets Intel Pentium II specications using minimum number of external components
Description
The RC5057 is a synchronous mode DC-DC controller IC which provides a highly accurate, programmable output voltage for all Pentium II & III CPU applications and other high-performance processors. The RC5057 features remote voltage sensing, adjustable current limit, and active droop for optimal converter transient response. The RC5057 uses a 5-bit D/A converter to program the output voltage from 1.3V to 3.5V. The RC5057 uses a high level of integration to deliver load currents in excess of 16A from a 5V source with minimal external circuitry. Synchronous-mode operation offers optimum efficiency over the entire specified output voltage range. An onboard precision low TC reference achieves tight tolerance voltage regulation without expensive external components, while active droop permits exact tailoring of voltage for the most demanding load transients. The RC5057 also offers integrated functions including Power Good, Output Enable/ Soft Start and current limiting, and is available in a 16 pin SOIC package.
Applications
Power supply for Pentium II & III VRM for Pentium II & III processor Telecom line cards Routers, switches & hubs Programmable step-down power supply
Block Diagram
+5V VCCA 5 + 3 RS 10 4 8 VCCP 9 HIDRV +12V +5V
OSC +
Digital Control + + 7 6 5-Bit DAC
16 15141312
VO LODRV GNDP Power Good 2 PWRGD
1.24V Reference 11 GNDA 1 ENABLE/SS
VID0 VID2 VID4 VID1 VID3
Pentium is a registered trademark of Intel Corporation
Rev. 1.1.8
RC5057
PRODUCT SPECIFICATION
Pin Assignments
ENABLE/SS PWRGD IFB VFB VCCA GNDP LODRV VCCP 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VID0 VID1 VID2 VID3 VID4 GNDA SW HIDRV
RC5057
Pin Definitions
Pin Number 1 Pin Name ENABLE/SS Pin Function Description Output Enable/Softstart. A logic LOW on this pin will disable the output. An internal current source allows for open collector control. This pin also doubles as soft start. Power Good Flag. An open collector output that will be logic LOW if the output voltage is not within 12% of the nominal output voltage setpoint. Current Feedback. Pin 3 is used in conjunction with pin 10, as the input for the current feedback control loop. Layout of these traces is critical to system performance. See Application Information for details. Voltage Feedback. Pin 4 is used as the input for the voltage feedback control loop. See Application Information for details regarding correct layout. Analog VCC. Connect to system 5V supply and decouple with a 0.1F ceramic capacitor. Power Ground. Return pin for high currents flowing in pin 8 (VCCP). Connect to a low impedance ground. Low Side FET Driver. Connect this pin to the gate of an N-channel MOSFET for synchronous operation. The trace from this pin to the MOSFET gate should be <0.5". Power VCC. For both high side and low side FET drivers. Connect to system 12V supply, and decouple with a 4.7F tantalum and a 0.1F ceramic capacitor. High Side FET Driver. Connect this pin to the gate of an N-channel MOSFET. The trace from this pin to the MOSFET gate should be <0.5". High side driver source and low side driver drain switching node. Together with IFB pin allows FET sensing for current. Analog Ground. Return path for low power analog circuitry. This pin should be connected to a low impedance system ground plane to minimize ground loops. Voltage Identification Code Inputs. These open collector/TTL compatible inputs will program the output voltage over the ranges specified in Table 2. Pull-up resistors are internal to the controller.
2 3
PWRGD IFB
4 5 6 7
VFB VCCA GNDP LODRV
8 9 10 11 12-16
VCCP HIDRV SW GNDA VID0-4
2
PRODUCT SPECIFICATION
RC5057
Absolute Maximum Ratings
Supply Voltages VCCA, VCCP to GND Supply Voltages (VCCP, Charge Pump) Voltage Identification Code Inputs, VID0-VID4 Junction Temperature, TJ Storage Temperature Lead Soldering Temperature, 10 seconds Power Dissipation, PD Thermal Resistance Junction-to-case, JC 13.5V 18V VCCA 150C -65 to 150C 300C 750mW 105C/W
Recommended Operating Conditions
Parameter Supply Voltage VCCA Input Logic HIGH Input Logic LOW Ambient Operating Temperature Output Driver Supply, VCCP 0 11.4 12 Conditions Min. 4.75 2.0 0.8 70 13.2 Typ. 5 Max. 5.25 Units V V V C V
3
RC5057
PRODUCT SPECIFICATION
Electrical Specifications (VCCA = 5V, VCCP = 12V, VOUT = 2.0V, and TA = +25C using circuit in Figure
1, unless otherwise noted.) The * denotes specifications which apply over the full operating temperature range. Parameter Output Voltage Output Current Initial Voltage Setpoint ILOAD = 0.8A, VOUT = 2.400V VOUT = 2.000V VOUT = 1.550V TA = 0 to 70C, VOUT = 2.000V VOUT = 1.550V VCCA = 4.75V to 5.25V, VOUT = 2.000V VOUT at ILOAD = 0.8A to Imax 20MHz BW, ILOAD = Imax VOUT = 2.000V VOUT = 1.550V3 ILOAD = 0.8A to Imax,VOUT = 2.000V VOUT = 1.550V3 ILOAD = Imax, VOUT = 2.0V See Figure 4 for tR and tF See Figure 7 for tDT * Logic HIGH Logic LOW * * * * 255 0 93 88 3.74 7.65 4 8.5 19 40 * 5 10 17 * * * * * 1.940 1.480 1.900 1.480 45 85 50 50 300 345 100 107 112 4.26 9.35 * * * -44 2.394 2.000 1.550 See Table 1 Conditions * Min. 1.3 18 2.424 2.020 1.565 +8 +6 2 -40 11 2.070 1.590 2.100 1.590 60 -36 2.454 2.040 1.580 Typ. Max. 3.5 Units V A V V V mV mV mV mV mVpk V V A % nsec nsec kHz % %Vout V V mA mA A
Output Temperature Drift Line Regulation Internal Droop3 Output Ripple Total Output Variation, Steady State1 Total Output Variation, Transient2 Short Circuit Detect Current Efficiency Output Driver Rise & Fall Time Output Driver Deadtime Oscillator Frequency Duty Cycle PWRGD Threshold VCCA UVLO VCCP UVLO VCCA Supply Current VCCP Supply Current4 Soft Start Current
Notes: 1. Steady State Voltage Regulation includes Initial Voltage Setpoint, Droop, Output Ripple and Output Temperature Drift and is measured at the converter's VFB sense point. 2. As measured at the converter's VFB sense point. For motherboard applications, the PCB layout should exhibit no more than 0.5m trace resistance between the converter's output capacitors and the CPU. Remote sensing should be used for optimal performance. 3. Using the VFB pin for remote sensing of the converter's output at the load, the converter will be in compliance with Intel's VRM 8.4 specification of +50, -80mV. If Intel specifications on maximum plane resistance from the converter's output capacitors to the CPU are met, the specification of +40, -70mV at the capacitors will also be met. 4. Includes gate current.
4
PRODUCT SPECIFICATION
RC5057
Table 1. Output Voltage Programming Codes VID4 VID3 VID2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
Nominal VOUT 1.30V 1.35V 1.40V 1.45V 1.50V 1.55V 1.60V 1.65V 1.70V 1.75V 1.80V 1.85V 1.90V 1.95V 2.00V 2.05V 2.0V 2.1V 2.2V 2.3V 2.4V 2.5V 2.6V 2.7V 2.8V 2.9V 3.0V 3.1V 3.2V 3.3V 3.4V 3.5V
Note: 1. 0 = processor pin is tied to GND. 1 = processor pin is open.
5
RC5057
PRODUCT SPECIFICATION
Typical Operating Characteristics (VCCA = 5V, VCCP = 12V, and TA = +25C using circuit in Figure 1,
unless otherwise noted.)
Efficiency vs. Output Current 2.04 88 86 84 82 80 78 76 74 72 70 68 66 64 VOUT = 2.000V 2.03 2.02 2.01 VOUT (V) VOUT = 1.550V 2.00 1.99 1.98 1.97 1.96 1.95 1.94 0 3 6 9 12 15 18 Output Current (A) 0 3 6 9 12 15 18 Output Current (A) Droop, VOUT = 2.0V
Efficiency (%)
Output Voltage vs. Output Current 3.5 3.0 2.5 VOUT (V) 2.0 1.5 1.0 0.5 0 0 5 10 15 20 25 Output Current (A)
Output Programming, VID4 = 0 2.1 1.9 VOUT (V) VOUT (V) 1.7 1.5 1.3 1.1 1.30 3.5 3.0 2.5 2.0 1.5 1.0 1.40 1.50 1.60 1.70 1.80 1.90 2.00
Output Programming, VID4 = 1
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 DAC Setpoint
DAC Setpoint
6
PRODUCT SPECIFICATION
RC5057
Typical Operating Characteristics (continued)
Output Ripple, 2.0V @ 18A
Transient Response, 12.5A to 0.5A
VOUT (20mV/div)
VCPU (50mV/div)
1.590V 1.550V 1.480V
Time (1s/division)
Time (100s/div)
Transient Response, 0.5A to 12.5A
VCPU (50mV/div)
1.590V 1.550V 1.480V
Time (100s/div)
Switching Waveforms, 18A Load
Output Startup, System Power-up
5V/div
HIDRV pin
5V/ div
LODRV pin
Time (1s/division)
VOUT (1V/div)
VIN (2V/div)
Time (10ms/division)
7
RC5057
PRODUCT SPECIFICATION
Typical Operating Characteristics (continued)
Output Startup from Enable 2.042 VOUT (1V/div) ENABLE (2V/div) 2.040 2.038 VOUT (V) 2.036 2.034 2.030 2.028 2.026 0 Time (10ms/division) 25 Temperature (C) 70 100 VOUT Temperature Variation
Application Circuit
+12V L1 (Optional) 2.5H +5V CIN* R1 33 C5 1F C2 1F R2 4.7 Q1 C1 4.7F 9 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1 R3 4.7 Q2 L2 1.3H VO D1 MBRD835L COUT*
R6 10
VID4 VID3 VID2 VID1 VID0
U1 RC5057
C3 0.1F R5*
ENABLE/SS C4 0.1F
VCC R4 10K PWRGD C6 0.1F
*Refer to Table 3 for values of COUT, R5, and CIN.
Figure 1. Application Circuit for Katmai, Mendocino, and Some Coppermine Processors (Worst Case Analyzed! See Appendix for Details)
8
PRODUCT SPECIFICATION
RC5057
Table 2. RC5057 Application Bill of Materials for Intel Pentium II & III Processors (Components based on Worst Case Analysis--See Appendix for Details)
Reference C1 C2, C5 C3-4,6 CIN COUT D1 L1 L2 Q1
Manufacturer Part # AVX TAJB475M010R5 Panasonic ECU-V1C105ZFX Panasonic ECU-V1H104ZFX Sanyo 10MV1200GX Sanyo 6MV1500GX Motorola MBRD835L Any Any Fairchild FDP6030L or FDB6030L Fairchild FDP7030BL or FDB7030BL Any Any Any Any Any Fairchild RC5057M
Quantity 1 2 3 * * 1 Optional 1 1
Description 4.7F, 10V Capacitor 1F, 16V Capacitor 100nF, 50V Capacitor 1200F, 10V Electrolytic 1500F, 6.3V Electrolytic 8A Schottky Diode 2.5H, 10A Inductor 1.3H, 20A Inductor N-Channel MOSFET (TO-220 or TO-263) N-Channel MOSFET (TO-220 or TO-263) 33 4.7 10K * 10 DC/DC Controller
Requirements/Comments
IRMS = 2A ESR 44m
DCR ~ 6m See Note 1. DCR ~ 2m RDS(ON) = 20m @ VGS = 4.5V See Note 2. RDS(ON) = 10m @ VGS = 4.5V See Note 2.
Q2
1
R1 R2-3 R4 R5 R6 U1 *See Table 3.
1 2 1 1 1 1
Notes: 1. Inductor L1 is recommended to isolate the 5V input supply from noise generated by the MOSFET switching, and to comply with Intel dI/dt requirements. L1 may be omitted if desired. 2. For designs using the TO-220 MOSFETs, heatsinks with thermal resistance SA < 20C/W should be used. For designs using the TO-263 MOSFETs, adequate copper area should be used. For details and a spreadsheet on MOSFET selections, refer to Applications Bulletin AB-8. Table 3. Recommended Values for CPU-based Applications
Processor Coppermine Katmai Mendocino Katmai
Chipset Whitney Camino Whitney BX
CIN 3 4 4 5
COUT* 4 6 5 6
R5 (K) 8.45 13.0 11.3 11.8
*Output capacitance requirements depend critically on layout and processor type. Consult Application Bulletin AB-14 for details. See the Appendix to this datasheet for the method of calculation of these components. Pin 4 must be used to remote sense the voltage at the processor to achieve the specified performance.
9
RC5057
PRODUCT SPECIFICATION
+12V L1 (Optional) 2.5H +5V CIN* C5 1F D2 1N4148 R2 4.7 Q1 C1 4.7F R3 4.7 9 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1 Q2 L2 R10 10m 1.3H D1 MBRD835L R7 2.2m VO COUT* R1 33
R6 10
C2 1F
VID4 VID3 VID2 VID1 VID0
U1 RC5057
C3 0.1F R5 2.80K
R8 2.1 R9 1K VCC
ENABLE/SS C4 0.1F
R4 10K PWRGD C6 0.1F
*Refer to Table 4 for values of COUT, and CIN.
Figure 2. Application Circuit for Coppermine/Camino Processors
(Worst Case Analyzed! See Appendix for Details)
10
PRODUCT SPECIFICATION
RC5057
Table 4. RC5057 Application Bill of Materials for Coppermine/Camino Processors
(Components based on Worst Case Analysis--See Appendix for Details) Reference C1 C2, C5 C3-4,6 CIN COUT D1 D2 L1 L2 Q1 Q2 Manufacturer Part # AVX TAJB475M010R5 Panasonic ECU-V1C105ZFX Panasonic ECU-V1H104ZFX Sanyo 10MV1200GX Sanyo 6MV1500GX Motorola MBRD835L Fairchild 1N4148 Any Any Fairchild FDP6030L or FDB6030L Fairchild FDP7030BL or FDB7030BL Any Any Any Any Any N/A Any Any Dale WSL-2512-.01 Fairchild RC5057M Quantity 1 2 3 3 10 1 1 Optional 1 1 1 Description 4.7F, 10V Capacitor 1F, 16V Capacitor 100nF, 50V Capacitor 1200F, 10V Electrolytic 1500F, 6.3V Electrolytic 8A Schottky Diode Signal Diode 2.5H, 10A Inductor 1.3H, 20A Inductor N-Channel MOSFET (TO-220 or TO-263) N-Channel MOSFET (TO-220 or TO-263) 33 4.7 10K 2.80K 10 1.8m 2.1 1K 10m, 1W Resistor DC/DC Controller PCB Trace Resistor DCR ~ 6m See Note 1. DCR ~ 2m RDS(ON) = 20m @ VGS = 4.5V See Note 2. RDS(ON) = 10m @ VGS = 4.5V See Note 2. IRMS = 2A ESR 44m Requirements/Comments
R1 R2-3 R4 R5 R6 R7 R8 R9 R10 U1
1 2 1 1 1 1 1 1 1 1
Notes: 1. Inductor L1 is recommended to isolate the 5V input supply from noise generated by the MOSFET switching, and to comply with Intel dI/dt requirements. L1 may be omitted if desired. 2. For designs using the TO-220 MOSFETs, heatsinks with thermal resistance SA < 20C/W should be used. For designs using the TO-263 MOSFETs, adequate copper area should be used. For details and a spreadsheet on MOSFET selections, refer to Applications Bulletin AB-8.
11
RC5057
PRODUCT SPECIFICATION
+12V L1 (Optional) 2.5H +5V CIN* C5 1F C2 1F R2 4.7 Q1 C1 4.7F 9 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1 R3 4.7 Q2 L2 1.3H D1 MBRD835L R1 33
R6 10
R7 3m VO COUT*
VID4 VID3 VID2 VID1 VID0
U1 RC5057
C3 0.1F R5 6.24K
ENABLE/SS C4 0.1F
VCC R4 10K PWRGD C6 0.1F
*Refer to Table 4 for values of COUT, and CIN.
Figure 3. Application Circuit for Coppermine/Camino Processors
(Typical Design)
12
PRODUCT SPECIFICATION
RC5057
Table 5. RC5057 Application Bill of Materials for Coppermine/Camino Processors
(Typical Design) Reference C1 C2, C5 C3-4,6 CIN COUT D1 L1 L2 Q1-2 Manufacturer Part # AVX TAJB475M010R5 Panasonic ECU-V1C105ZFX Panasonic ECU-V1H104ZFX Sanyo 10MV1200GX Sanyo 6MV1500GX Motorola MBRD835L Any Any Fairchild FDP6030L or FDB6030L Any Any Any Any Any N/A Fairchild RC5057M Quantity 1 2 3 3 8 1 Optional 1 2 Description 4.7F, 10V Capacitor 1F, 16V Capacitor 100nF, 50V Capacitor 1200F, 10V Electrolytic IRMS = 2A 1500F, 6.3V Electrolytic 3A Schottky Diode 2.5H, 10A Inductor 1.3H, 20A Inductor N-Channel MOSFET (TO-220 or TO-263) 33 4.7 10K 6.24K 10 3.0m DC/DC Controller PCB Trace Resistor DCR ~ 6m See Note 1. DCR ~ 2m RDS(ON) = 20m @ VGS = 4.5V See Note 2. ESR 44m Requirements/Comments
R1 R2-3 R4 R5 R6 R7 U1
1 2 1 1 1 1 1
Notes: 1. Inductor L1 is recommended to isolate the 5V input supply from noise generated by the MOSFET switching, and to comply with Intel dI/dt requirements. L1 may be omitted if desired. 2. For designs using the TO-220 MOSFETs, heatsinks with thermal resistance SA < 20C/W should be used. For designs using the TO-263 MOSFETs, adequate copper area should be used. For details and a spreadsheet on MOSFET selections, refer to Applications Bulletin AB-8.
Test Parameters
tR 90% 10% tDT 2V 2V 90% 2V tDT 2V LODRV 10% tF HIDRV
Figure 4. Output Drive Timing Diagram
13
RC5057
PRODUCT SPECIFICATION
Application Information
The RC5057 Controller
The RC5057 is a programmable synchronous DC-DC controller IC. When designed around the appropriate external components, the RC5057 can be configured to deliver more than 16A of output current, as appropriate for the Katmai and Coppermine and other processors. The RC5057 functions as a fixed frequency PWM step down regulator.
Internal Voltage Reference
The reference included in the RC5057 is a precision band-gap voltage reference. Its internal resistors are precisely trimmed to provide a near zero temperature coefficient (TC). Based on the reference is the output from an integrated 5-bit DAC. The DAC monitors the 5 voltage identification pins, VID0-4. When the VID4 pin is at logic HIGH, the DAC scales the reference voltage from 2.0V to 3.5V in 100mV increments. When VID4 is pulled LOW, the DAC scales the reference from 1.30V to 2.05V in 50mV increments. All VID codes are available, including those below 1.80V.
Main Control Loop
Refer to the RC5057 Block Diagram on page 1. The RC5057 implements "summing mode control", which is different from both classical voltage-mode and current-mode control. It provides superior performance to either by allowing a large converter bandwidth over a wide range of output loads. The control loop of the regulator contains two main sections: the analog control block and the digital control block. The analog section consists of signal conditioning amplifiers feeding into a comparator which provides the input to the digital control block. The signal conditioning section accepts input from the IFB (current feedback) and VFB (voltage feedback) pins and sets up two controlling signal paths. The first, the voltage control path, amplifies the difference between the VFB signal and the reference voltage from the DAC and presents the output to one of the summing amplifier inputs. The second, current control path, takes the difference between the IFB and SW pins when the high-side MOSFET is on, reproducing the voltage across the MOSFET and thus the input current; it presents the resulting signal to another input of the summing amplifier. These two signals are then summed together. This output is then presented to a comparator looking at the oscillator ramp, which provides the main PWM control signal to the digital control block. The digital control block takes the analog comparator input and the main clock signal from the oscillator to provide the appropriate pulses to the HIDRV and LODRV output pins. These two outputs control the external power MOSFETs. There is an additional comparator in the analog control section whose function is to set the point at which the RC5057 current limit comparator disables the output drive signals to the external power MOSFETs.
Power Good (PWRGD)
The RC5057 Power Good function is designed in accordance with the Pentium II & III DC-DC converter specifications and provides a continuous voltage monitor on the VFB pin. The circuit compares the VFB signal to the VREF voltage and outputs an active-low interrupt signal to the CPU should the power supply voltage deviate more than 12% of its nominal setpoint. The output is guaranteed open-collector high when the power supply voltage is within 7% of its nominal setpoint. The Power Good flag provides no other control function to the RC5057.
Output Enable/Soft Start (ENABLE/SS)
The RC5057 will accept an open collector/TTL signal for controlling the output voltage. The low state disables the output voltage. When disabled, the PWRGD output is in the low state. Even if an enable is not required in the circuit, this pin should have attached a capacitor (typically 100nF) to softstart the switching.
Over-Voltage Protection
The RC5057 constantly monitors the output voltage for protection against over-voltage conditions. If the voltage at the VFB pin exceeds the selected program voltage, an over-voltage condition is assumed and the RC5057 disables the output drive signal to the external high-side MOSFET. The DC-DC converter returns to normal operation after the fault has been removed. If it is desired to have an active over-voltage protection circuit, the RC5052, which includes all the features of the RC5057, may be chosen instead of the RC5057.
Oscillator
The RC5057 oscillator section uses a fixed frequency of operation of 300KHz. If it is desired to adjust this frequency for reasons of efficiency or component size, the RC5052, which includes all of the features of the RC5057, may be chosen instead of the RC5057.
High Current Output Drivers
The RC5057 contains two identical high current output drivers that utilize high speed bipolar transistors in a push-pull configuration. The drivers' power and ground are separated from the chip's power and ground for switching noise immunity. The power supply pin, VCCP, is supplied from an external 12V source through a series resistor. The resulting voltage is sufficient to provide the gate to source drive to the external MOSFETs required in order to achieve a low RDS,ON.
Design Considerations and Component Selection
Additional information on design and component selection may be found in Fairchild's Application Note 57.
14
PRODUCT SPECIFICATION
RC5057
MOSFET Selection
This application requires N-channel Logic Level Enhancement Mode Field Effect Transistors. Desired characteristics are as follows: Low Static Drain-Source On-Resistance, RDS,ON < 20m (lower is better) Low gate drive voltage, VGS = 4.5V rated Power package with low Thermal Resistance Drain-Source voltage rating > 15V.
Dm = Maximum duty cycle for the DC/DC converter (usually 95%). Some margin should be maintained away from both Lmin and Lmax. Adding margin by increasing L almost always adds expense since all the variables are predetermined by system performance except for Co, which must be increased to increase L. Adding margin by decreasing L can be done by purchasing capacitors with lower ESR. The RC5057 provides significant cost savings for the newer CPU systems that typically run at high supply current.
The on-resistance (RDS,ON) is the primary parameter for MOSFET selection. The on-resistance determines the power dissipation within the MOSFET and therefore significantly affects the efficiency of the DC-DC Converter. For details and a spreadsheet on MOSFET selection, refer to Applications Bulletin AB-8.
RC5057 Short Circuit Current Characteristics
The RC5057 protects against output short circuit by turning off both the high-side and low-side MOSFETs and resetting softstart. The short circuit limit is set with the RS resistor, as given by the formula
RS = ISC x RDS, on IDetect
Inductor Selection
Choosing the value of the inductor is a tradeoff between allowable ripple voltage and required transient response. The system designer can choose any value within the allowed minimum to maximum range in order to either minimize ripple or maximize transient performance. The first order equation (close approximation) for minimum inductance is:
Lmin = (Vin - Vout) f x Vout Vin ESR x Vripple
where: Vin = Input Power Supply Vout = Output Voltage f = DC/DC converter switching frequency ESR = Equivalent series resistance of all output capacitors in parallel
with IDetect 50A, ISC the desired current limit, and RDS,on the high-side MOSFET's on resistance. Remember to make the RS large enough to include the effects of initial tolerance and temperature variation on the MOSFET's RDS,on. However, the value of RS should be less than 10K. If a greater value is necessary, a lower RDS,on MOSFET should be used instead. Alternately, use of a sense resistor in series with the source of the MOSFET, as shown in Figure 6, eliminates this source of inaccuracy in the current limit. Note the addition of the diode, which is necessary for proper operation of this circuit. As an example, Figure 5 shows the typical characteristic of the DC-DC converter circuit with an FDB6030L high-side MOSFET (RDS = 20m maximum at 25C * 1.25 at 75C = 25m) and a 8.2K RS.
3.5 3.0 2.5 VOUT (V)
Vripple = Maximum peak to peak output ripple voltage budget. The first order equation for maximum allowed inductance is:
Lmax = 2C0 (Vin - Vout) Dm Vtb Ipp2
2.0 1.5 1.0 0.5 0 0 5 10 15 20 25 Output Current (A)
where: Co = The total output capacitance Ipp = Maximum to minimum load transient current Vtb = The output voltage tolerance budget allocated to load transient
Figure 5. RC5057 Short Circuit Characteristic
The converter exhibits a normal load regulation characteristic until the voltage across the MOSFET exceeds the internal short circuit threshold of 50A * 8.2K = 410mV, which occurs at 410mV/25m = 16.4A. (Note that this current limit level can be as high as 410mV/15m = 27A, if the MOSFET
15
RC5057
PRODUCT SPECIFICATION
has typical RDS,on rather than maximum, and is at 25C. This is the reason for using the external sense resistor.) At this point, the internal comparator trips and signals the controller to discharge the softstart capacitor. This causes a drastic reduction in the output voltage as the load regulation collapses into the short circuit control mode. With a 40m output short, the voltage is reduced to 16.4A * 40m = 650mV. The output voltage does not return to its nominal value until the output current is reduced to a value within the safe operating range for the DC-DC converter.
1N4148
The output capacitance should also include a number of small value ceramic capacitors placed as close as possible to the processor; 0.1F and 0.01F are recommended values.
Input Filter
The DC-DC converter design may include an input inductor between the system +5V supply and the converter input as shown in Figure 7. This inductor serves to isolate the +5V supply from the noise in the switching portion of the DC-DC converter, and to limit the inrush current into the input capacitors during power up. A value of 2.5H is recommended. It is necessary to have some low ESR aluminum electrolytic capacitors at the input to the converter. These capacitors deliver current when the high side MOSFET switches on. Figure 7 shows 3 x 1000F, but the exact number required will vary with the speed and type of the processor. For the top speed Katmai and Coppermine, the capacitors should be rated to take 9A and 6A RMS of ripple current respectively. Capacitor ripple current rating is a function of temperature, and so the manufacturer should be contacted to find out the ripple current rating at the expected operational temperature. For details on the design of an input filter, refer to Applications Bulletin AB-15.
2.5H 5V 0.1F Vin 1000F, 10V Electrolytic
RS IFB RSENSE SW VOUT
Figure 6. Precision Current Sensing
Schottky Diode Selection
The application circuit of Figure 1 shows a Schottky diode, D1, which is used as a free-wheeling diode to assure that the body-diode in Q2 does not conduct when the upper MOSFET is turning off and the lower MOSFET is turning on. It is undesirable for this diode to conduct because its high forward voltage drop and long reverse recovery time degrades efficiency, and so the Schottky provides a shunt path for the current. Since this time duration is very short, the selection criterion for the diode is that the forward voltage of the Schottky at the output current should be less than the forward voltage of the MOSFET's body diode.
Figure 7. Input Filter
Active Droop
The RC5057 includes active droop: as the output current increases, the output voltage drops. This is done in order to allow maximum headroom for transient response of the converter. The current is sensed by measuring the voltage across the high-side MOSFET during its on time. Note that this makes the droop dependent on the temperature of the MOSFET. However, when the formula given for selecting RS (current limit) is used, there is a maximum droop possible (-40mV), and when this value is reached, additional drop across the MOSFET will not cause any increase in droop--until current limit is reached. Additional droop can be added to the active droop using a discrete resistor (typically a PCB trace) outside the control loop, as shown in Figure 2. This is typically only required for the most demanding applications, such as for the next generation Intel processor (tolerance = +40/-70mV), as shown in Figure 2.
Output Filter Capacitors
The output bulk capacitors of a converter help determine its output ripple voltage and its transient response. It has already been seen in the section on selecting an inductor that the ESR helps set the minimum inductance, and the capacitance value helps set the maximum inductance. For most converters, however, the number of capacitors required is determined by the transient response and the output ripple voltage, and these are determined by the ESR and not the capacitance value. That is, in order to achieve the necessary ESR to meet the transient and ripple requirements, the capacitance value required is already very large. The most commonly used choice for output bulk capacitors is aluminum electrolytics, because of their low cost and low ESR. The only type of aluminum capacitor used should be those that have an ESR rated at 100kHz. Consult Application Bulletin AB-14 for detailed information on output capacitor selection.
16
PRODUCT SPECIFICATION
RC5057
PCB Layout Guidelines
Placement of the MOSFETs relative to the RC5057 is critical. Place the MOSFETs such that the trace length of the HIDRV and LODRV pins of the RC5057 to the FET gates is minimized. A long lead length on these pins will cause high amounts of ringing due to the inductance of the trace and the gate capacitance of the FET. This noise radiates throughout the board, and, because it is switching at such a high voltage and frequency, it is very difcult to suppress. In general, all of the noisy switching lines should be kept away from the quiet analog section of the RC5057. That is, traces that connect to pins 7, 9, 10, and 8 (LODRV, HIDRV, SW and VCCP) should be kept far away from the traces that connect to pins 3 through 5, and pin 11. Place the 0.1F decoupling capacitors as close to the RC5057 pins as possible. Extra lead length on these reduces their ability to suppress noise. Each VCC and GND pin should have its own via to the appropriate plane. This helps provide isolation between pins. Place the MOSFETs, inductor, and Schottky as close together as possible for the same reasons as in the rst bullet above. Place the input bulk capacitors as close to the drains of the high side MOSFETs as possible. In addition, placement of a 0.1F decoupling cap right on the drain of each high side MOSFET helps to suppress some of the high frequency switching noise on the input of the DC-DC converter. Place the output bulk capacitors as close to the CPU as possible to optimize their ability to supply instantaneous current to the load in the event of a current transient. Additional space between the output capacitors and the CPU will allow the parasitic resistance of the board traces to degrade the DC-DC converterOs performance under severe load transient conditions, causing higher voltage deviation. For more detailed information regarding capacitor placement, refer to Application Bulletin AB-5. A PC Board Layout Checklist is available from Fairchild Applications. Ask for Application Bulletin AB-11.
Appendix
Worst-Case Formulae for the Calculation of Cout, R5, and Cin (Circuit of Figure 1 Only)
The following formulae design the RC5057 for worst-case operation, including initial tolerance and temperature dependence of all of the IC parameters (initial setpoint, reference tolerance and tempco, active droop tolerance, current sensor gain), the initial tolerance and temperature dependence of the MOSFET, and the ESR of the capacitors. The following information must be provided: VT+, the value of the positive transient voltage limit; |VT-|, the absolute value of the negative transient voltage limit; IO, the maximum output current; Vnom, the nominal output voltage; Vin, the input voltage (typically 5V); ESR, the ESR of the output caps, per cap (44m for the Sanyo parts shown in this datasheet); RD, the on-resistance of the MOSFET (20m for the FDB6030); RD, the tolerance of the current sensor (usually about 67% for MOSFET sensing, including temperature). Irms, the rms current rating of the input caps (2A for the Sanyo parts shown in this datasheet).
2 IO * Cin = Irms IO* RD * (1 + RD) * 1.10 50 * 10
-6
Vnom Vin
-
Vnom Vin
PC Motherboard Sample Layout and Gerber File
A reference design for motherboard implementation of the RC5057 along with the PCAD layout Gerber file and silk screen can be obtained from our marketing department at 650-966-7624.
R5 =
Number of capacitors needed for Cout = the greater of:
X= ESR * IO VT-
RC5057 Evaluation Board
Fairchild provides an evaluation board to verify the system level performance of the RC5057. It serves as a guide to performance expectations when using the supplied external components and PCB layout. Please call the marketing department at 650-966-7624 for an evaluation board.
or
ESR * IO VT+ -0.004 * Vnom + 14400 * IO * RD 18 * R5 * 1.1
Additional Information
For additional information contact Fairchild Semiconductor's Analog & Mixed Signal Products Group Marketing Department at 650-966-7624.
Y=
17
RC5057
PRODUCT SPECIFICATION
Example: Suppose that the transient limits are 134mV, current I is 14.2A, and the nominal voltage is 2.000V, using MOSFET current sensing and the usual caps. We have VT+ = |VT-| = 0.134, IO = 14.2, Vnom = 2.000, and RD = 0.67. We calculate:
2
R5 =
14.2 * 0.020 * (1 + 0.67) * 1.10 50 * 10-6
= 10.4K
X=
0.044 * 14.2 0.134
= 4.66
2.000 14.2 * 5 Cin = 2
-
2.000 5
0.044 * 14.2 Y= = 3.47 4 caps 0.134 - 0.004 * 2.000 + 14400 * 14.2 * 0.020 18 * 10400 * 1.1
= 4.28
Since X > Y, we choose X, and round up to find we need 5 capacitors for COUT.
18
PRODUCT SPECIFICATION
RC5057
Mechanical Dimensions
16 Lead SOIC
Inches Min. A A1 B C D E e H h L N ccc Max. Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
Symbol
.053 .069 .004 .010 .013 .020 .008 .010 .386 .394 .150 .158 .050 BSC .228 .010 .016 16 0 -- 8 .004 .244 .020 .050
1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 9.80 10.00 3.81 4.00 1.27 BSC 5.80 0.25 0.40 16 0 -- 8 0.10 6.20 0.50 1.27
3 6
16
9
E
H
1
8
D A1 A SEATING PLANE -C- LEAD COPLANARITY ccc C e B
h x 45 C
L
19
RC5057
PRODUCT SPECIFICATION
Ordering Information
Product Number RC5057M Package 16 pin SOIC
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
10/14/99 0.0m 009 Stock#DS30005057 (c) 1999 Fairchild Semiconductor Corporation
www.fairchildsemi.com
RC5058
High Performance Programmable Synchronous DC-DC Controller for Multi-Voltage Platforms
Features
Programmable output for Vcore from 1.3V to 3.5V using an integrated 5-bit DAC * Controls adjustable linears for Vagp (selectable 1.5V/3.3V), Vclock (2.5V), and Vtt (1.5V) or Vnorthbridge (1.8V) * Meets VRM specification with as few as 5 capacitors * Meets 1.550V +40/-70mV over initial tolerance, temperature and transients * * * * * * * Remote sense Programmable Active DroopTM (Voltage Positioning) Drives N-Channel MOSFETs Overcurrent protection using MOSFET sensing 85% efficiency typical at full load Integrated Power Good and Enable/Soft Start functions 24 pin SOIC package
Applications
* * * * Power supply for Pentium(R) III Camino Platform Power supply for Pentium III Whitney Platform VRM for Pentium III processor Programmable multi-output power supply
Preliminary Specification
Description
The RC5058 is a synchronous mode DC-DC controller IC which provides a highly accurate, programmable set of output voltages for multi-voltage platforms such as the Intel Camino, and provides a complete solution for the Intel Whitney and other high-performance processors. The RC5058 features remote voltage sensing, independently adjustable current limit, and a proprietary Programmable Active DroopTM for optimal converter transient response. The RC5058 uses a 5-bit D/A converter to program the output voltage from 1.3V to 3.5V. The RC5058 uses a high level of integration to deliver load currents in excess
Block Diagram
+3.3V 9 10 VCCP 1 + + +5V VCCA 21 REF PWRGD, OCL OCL REF +12V PWRGD, OCL OSC + 15 14 13 3.3/1.5V 5-Bit DAC 8765 4 VID0 VID2 VID4 VID1 VID3 1.24V Reference 3 GNDA 16 ENABLE/SS Power Good + + 18 RS 20 24 VCCP 1 HIDRV +5V + 19 RD
+1.5V
12 +2.5V
Digital Control
2
VCC
+ -
V PWRGD, OCL
+
23 LODRV 22 GNDP 17 PWRGD
Pentium is a registered trademark of Intel Corporation. Programmable Active Droop is a trademark of Fairchild Semiconductor.
Rev. 0.8.2
Preliminary Specification describes products that are not in full production at the time of printing. Specifications are based on design goals and limited characterization. In the process of final product release, specification. Contact Fairchild Semiconductor for current information.
RC5058
of 16A from a 5V source with minimal external circuitry. Synchronous-mode operation offers optimum efficiency over the entire specified output voltage range. An on-board precision low TC reference achieves tight tolerance voltage regulation without expensive external components, while Programmable Active DroopTM permits exact tailoring of voltage for the most demanding load transients. The RC5058 includes linear regulator controllers for Vtt termination (1.5V), Vclock (2.5V), and Vnorthbridge (1.8V) or Vagp (selectable 1.5V/3.3V), each adjustable with an external divider. The RC5058 also offers integrated functions including Power Good, Output Enable/Soft Start and current limiting, and is available in a 24 pin SOIC package.
Pin Assignments
HIDRV SW GNDA VID4 VID3 VID2 VID1 VID0 VTTGATE VTTFB VCKGATE VCKFB 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCCP LODRV GNDP VCCA VFB DROOP ILIM PWRGD SS/ENABLE TYPEDET VAGPGATE VAGPFB
RC5058
Preliminary Specification
Pin Definitions
Pin Number Pin Name 1 2 3 4-8 HIDRV SW GNDA VID0-4 Pin Function Description High Side FET Driver. Connect this pin through a resistor to the gate of an N-channel MOSFET. The trace from this pin to the MOSFET gate should be <0.5". High side Driver Source and Low side Driver Drain Switching Node. Together with DROOP and ILIM pins allows FET sensing for Vcc current. Analog Ground. Return path for low power analog circuitry. This pin should be connected to a low impedance system ground plane to minimize ground loops. Voltage Identification Code Inputs. These open collector/TTL compatible inputs will program the output voltage over the ranges specified in Table 2. Pull-up resistors are internal to the controller. Gate Driver for VTT Transistor. For 1.5V output. Voltage Feedback for VTT. Gate Driver for VCK Transistor. For 2.5V output. Voltage Feedback for VCK. Voltage Feedback for VAGP. Gate Driver for VAGP Transistor. For 3.3/1.5V output. Type Detect. Sets 3.3V or 1.5V for AGP. Output Enable. A logic LOW on this pin will disable all outputs. An internal current source allows for open collector control. This pin also doubles as soft start for all outputs. Power Good Flag. An open collector output that will be logic LOW if any output voltage is not within 12% of the nominal output voltage setpoint. Vcc Current Feedback. Pin 18 is used in conjunction with pin 2 as the input for the Vcc current feedback control loop. Layout of these traces is critical to system performance. See Application Information for details. Droop set. Use this pin to set magnitude of active droop. Vcc Voltage Feedback. Pin 20 is used as the input for the Vcc voltage feedback control loop. See Application Information for details regarding correct layout. Analog VCC. Connect to system 5V supply and decouple with a 0.1F ceramic capacitor. Power Ground. Return pin for high currents flowing in pin 24 (VCCP). Vcc Low Side FET Driver. Connect this pin through a resistor to the gate of an N-channel MOSFET for synchronous operation. The trace from this pin to the MOSFET gate should be <0.5". Power VCC. For all FET drivers. Connect to system 12V supply through a 33, and decouple with a 1F ceramic capacitor.
9 10 11 12 13 14 15 16 17 18
VTTGATE VTTFB VCKGATE VCKFB VAGPFB VAGPGATE TYPEDET ENABLE/SS PWRGD ILIM
19 20 21 22 23
DROOP VFB VCCA GNDP LODRV
24
VCCP
2
RC5058
Absolute Maximum Ratings
Supply Voltages VCCA, VCCP to GND Voltage Identification Code Inputs, VID0-VID4 All Other Pins Junction Temperature, TJ Storage Temperature Lead Soldering Temperature, 10 seconds Thermal Resistance Junction-to-ambient, JA
Note: 1. Component mounted on demo board in free air.
1
13.5V VCCA 13.5V 150C -65 to 150C 300C 75C/W
Preliminary Specification
Recommended Operating Conditions
Parameter Supply Voltage VCCA Input Logic HIGH Input Logic LOW Ambient Operating Temperature Output Driver Supply, VCCP 0 10.8 12 Conditions Min. 4.75 2.0 0.8 70 13.2 Typ. 5 Max. 5.25 Units V V V C V
Electrical Specifications
(VCCA = 5V, VCCP = 12V, VOUT = 2.0V, and TA = +25C using circuit in Figure 1 unless otherwise noted.) The * denotes specifications which apply over the full operating temperature range. Parameter VCC Regulator Output Voltage Output Current Initial Voltage Setpoint ILOAD = 0.8A,VOUT = 2.400V VOUT = 2.000V VOUT = 1.550V TA = 0 to 70C,VOUT = 2.000V VOUT = 1.550V VIN = 4.75V to 5.25V ILOAD = 0.8A to 12.5A 20MHz BW, ILOAD = 18A VOUT = 2.000V VOUT = 1.550V3 ILOAD = 0.8A to 18A, VOUT = 2.000V VOUT = 1.550V3 ILOAD = 18A, VOUT = 2.0V See Figure 3 See Figure 3 0 * * * * * 1.940 1.480 1.900 1.480 45 50 85 50 50 100 * * * 13.0 2.397 2.000 1.550 See Table 1 * 1.3 18 2.424 2.020 1.565 +8 +6 -4 14.4 60 11 2.070 1.590 2.100 1.590 60 15.8 2.454 2.040 1.580 3.5 V A V V V mV mV mV/V K mV mVpk V V A % nsec nsec % Conditions Min. Typ. Max. Units
Output Temperature Drift Line Regulation Internal Droop Impedance Maximum Droop Output Ripple Total Output Variation, Steady State1 Total Output Variation, Transient2 Short Circuit Detect Current Efficiency Output Driver Rise & Fall Time Output Driver Deadtime Duty Cycle
3
RC5058
Electrical Specifications (Continued)
(VCCA = 5V, VCCP = 12V, VOUT = 2.0V, and TA = +25C using circuit in Figure 1 unless otherwise noted.) The * denotes specifications which apply over the full operating temperature range. Parameter 5V UVLO 12V UVLO Soft Start Current VTT Linear Regulator Output Voltage Under Voltage Trip Level VCLK Linear Regulator ILOAD 2A Over Current ILOAD 2A Over Current ILOAD 2A, TYPEDET=0V ILOAD 2A, TYPEDET=OPEN Over Current * Logic HIGH, All Outputs Logic LOW, Any Output * * 255 93 88 30 * * 1.425 3.135 * 2.375 * 1.425 1.5 80 2.5 80 1.5 3.3 80 310 345 107 112 1.575 3.465 2.625 1.575 V %VO V %VO V V %VO kHz %VOUT sec Conditions * * * Min. 3.74 7.65 5 Typ. 4 8.5 10 Max. 4.26 9.35 17 Units V V A
Preliminary Specification
Output Voltage Under Voltage Trip Level VAGP Linear Regulator Output Voltage Output Voltage Under Voltage Trip Level Common Functions Oscillator Frequency PWRGD Threshold
Linear Regulator Under Voltage Over Current Delay Time
Notes: 1. Steady State Voltage Regulation includes Initial Voltage Setpoint, Droop, Output Ripple and Output Temperature Drift and is measured at the converter's VFB sense point. 2. As measured at the converter's VFB sense point. For motherboard applications, the PCB layout should exhibit no more than 0.5m trace resistance between the converter's output capacitors and the CPU. Remote sensing should be used for optimal performance. 3. Using the VFB pin for remote sensing of the converter's output at the load, the converter will be in compliance with Intel's VRM 8.4 specification of +50, -80mV. If Intel specifications on maximum plane resistance from the converter's output capacitors to the CPU are met, the specification of +40, -70mV at the capacitors will also be met.
4
RC5058
Table 1. Output Voltage Programming Codes
VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Nominal VOUT 1.30V 1.35V 1.40V 1.45V 1.50V 1.55V 1.60V 1.65V
Preliminary Specification
1.70V 1.75V 1.80V 1.85V 1.90V 1.95V 2.00V 2.05V 2.0V 2.1V 2.2V 2.3V 2.4V 2.5V 2.6V 2.7V 2.8V 2.9V 3.0V 3.1V 3.2V 3.3V 3.4V 3.5V
Note: 1. 0 = processor pin is tied to GND. 1 = processor pin is open.
5
RC5058
Typical Operating Characteristics
(VCCA = 5V, VCCP = 12V, and TA = +25C using circuits in Figure 1, unless otherwise noted.)
VCPU Efficiency vs. Output Current 2.04 88 86 84 82 80 78 76 74 72 70 68 66 64 0 3 VOUT = 2.000V 2.03 2.02 2.01 2.00 VOUT (V) VOUT = 1.550V 1.99 1.98 1.97 1.96 1.95 1.94 0 3 6 9 12 15 18 Output Current (A) 6 9 12 Output Current (A) 15 18 Droop, VCPU = 2.0V, RD = 8K
Preliminary Specification
Efficiency (%)
CPU Output Voltage vs. Output Current 3.5 3.0 2.5 VOUT (V) 2.0 1.5 1.0 0.5 0 0 5 10 15 20 25 Output Current (A)
Output Programming, VID4 = 0 2.1 1.9 1.7 1.5 1.3 1.1 1.30 1.40 1.50 1.60 1.70 1.80 1.90 2.00 DAC Setpoint 3.5 3.0 2.5 2.0 1.5 1.0
Output Programming, VID4 = 1
VCPU(V)
VCPU(V)
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2. 3.3 3.4 3.5 DAC Setpoint
6
RC5058
Typical Operating Characteristics (continued)
Output Ripple, 2.0V @ 18A Transient Response, 12.5A to 0.5A
VCPU (20mV/div)
VCPU (50mV/div)
1.590V 1.550V 1.480V
Preliminary Specification
Time (1s/div)
Time (100s/div)
Transient Response, 0.5A to 12.5A
Switching Waveforms, 18A Load
5V/div
VCPU (50mV/div)
1.590V 1.550V 1.480V 5V/div
HIDRV pin
LODRV pin
Time (1s/div) Time (100s/div)
Output Startup, System Power-up VCPU (1V/div) ENABLE (2V/div)
Output Startup from Enable
VCPU (1V/div)
VIN (2V/div)
Time (10ms/div)
Time (10ms/div)
7
RC5058
Typical Operating Characteristics (continued)
Linear Regulator Noise
2.042 2.040 2.038 VCPU (V) 2.036 2.034 2.030 2.028
AC COUPLED VOUT (10mV/div)
Preliminary Specification
2.026 0 25 70 100
Time (100s/div)
Temperature (C)
Application Circuit
L1 (Optional) +5V CIN*
R6 R7 R5 C2
C1
Q1 L2 VO COUT* D1 3.3V IN Q3 C10 C11 1.5V C8 Q4 2.5V C9 Q2
R2
1 2 3 VID4 VID3 VID2 VID1 VID0 4 5 6 7 8 9 10 11 12 U1 RC5058
24 23 22 21 20 19 18 17 16 15 14 13 C7 C12
R1 +12V C5
R3
C3
VCC R4 PWRGD ENABLE/SS
TYPEDET
C6
Q5
C4 3.3/1.5V (AGP)
* Refer to Table 4 for values of CIN and COUT. Adjustable with an external divider.
Figure 1. Application Circuit for Katmai/Camino/BX/ZX Motherboards (Worst Case Analyzed! See Appendix for Details)
8
RC5058
Table 2. RC5058 Application Bill of Materials for Intel Katmai/Camino/BX/ZX Motherboards
(Components based on Worst Case Analysis--See Appendix for Details) Reference C1 C2, C5 C3-4,C6 C7-9 C10-12 CIN COUT D1 L1 L2 Q1 Q2 Q3-5 R1 R2-3 R4 R5 R6 R7 U1 Manufacturer Part # AVX TAJB475M010R5 Panasonic ECU-V1C105ZFX Panasonic ECU-V1H104ZFX Sanyo 6MV1000FA Any Sanyo 10MV1200GX Sanyo 6MV1500GX Motorola MBRD835L Any Any Fairchild FDB6030L Fairchild FDB7030BL Fairchild FDB4030L Any Any Any Any Any Any Fairchild RC5058M Quantity 1 2 3 3 3 * * 1 Optional 1 1 1 3 1 2 1 1 1 1 1 Description 4.7F, 10V Capacitor 1F, 16V Capacitor 100nF, 50V Capacitor 1000F, 6.3V Electrolytic 22F, 6.3V Capacitor 1200F, 10V Electrolytic 1500F, 6.3V Electrolytic 8A Schottky Diode 2.5H, 8A Inductor 1.3H, 20A Inductor N-Channel MOSFET N-Channel MOSFET N-Channel MOSFET 33 4.7 10K * 10 * DC/DC Controller DCR ~ 10m See Note 1. DCR ~ 2m RDS(ON) = 20m @ VGS = 4.5V See Note 2. RDS(ON) = 10m @ VGS = 4.5V See Note 2. Low ESR IRMS = 2A ESR 44m Requirements/Comments
Preliminary Specification
Notes: 1. Inductor L1 is recommended to isolate the 5V input supply from noise generated by the MOSFET switching, and to comply with Intel dI/dt requirements. L1 may be omitted if desired. 2. For 17.4A designs using the TO-220 MOSFETs, heatsinks with thermal resistance SA < 20C/ should be used. For designs using the TO-263 MOSFETs, adequate copper area should be used. For details and a spreadsheet on MOSFET selections, refer to Applications Bulletins AB-8 and AB-15. *Refer to table 4 for values.
9
RC5058
L1 (Optional) +5V CIN*
R6 R7 R5 C2
C1
Preliminary Specification
R8 VO COUT*
L2
Q1
R2
1 2 3 VID4 VID3 VID2 VID1 VID0 4 5 6 7 8 9 10 11 12 U1 RC5058
24 23 22 21 20 19 18 17 16 15 14 13 C7
R1 +12V C5
Q2 D1 3.3V IN Q3
R3
C3
VCC R4 PWRGD ENABLE/SS
C10
C11 1.5V C8 Q4 2.5V
TYPEDET
C6
Q5
C4 3.3/1.5V (AGP)
C12 C9 *Refer to Table 4 for values of COUT and CIN. Adjustable with an external divider.
Figure 2. Application Circuit for Coppermine/Camino Motherboards (Typical Design)
10
RC5058
Table 3. RC5058 Application Bill of Materials for Intel Coppermine/Camino Motherboards
(Typical Design) Reference C1 C2, C5 C3-4,C6 C7-9 C10-12 CIN COUT D1 L1 L2 Q1 Q2 Q3-5 R1 R2-3 R4 R5, R7 R6 R8 U1 Manufacturer Part # AVX TAJB475M010R5 Panasonic ECU-V1C105ZFX Panasonic ECU-V1H104ZFX Sanyo 6MV1000FA Any Sanyo 10MV1200GX Sanyo 6MV1500GX Motorola MBRD835L Any Any Fairchild FDB6030L Fairchild FDB7030BL Fairchild FDB4030L Any Any Any Any Any N/A Fairchild RC5058M Quantity 1 2 3 3 3 3 12 1 Optional 1 1 1 3 1 2 1 2 1 1 1 Description 4.7F, 10V Capacitor 1F, 16V Capacitor 100nF, 50V Capacitor 1000F, 6.3V Electrolytic 22F, 6.3V Capacitor 1200F, 10V Electrolytic 1500F, 6.3V Electrolytic 8A Schottky Diode 2.5H, 5A Inductor 1.3H, 15A Inductor N-Channel MOSFET N-Channel MOSFET N-Channel MOSFET 33 4.7 10K 6.24K 10 3.0m DC/DC Controller PCB Trace Resistor DCR ~ 10m See Note 1. DCR ~ 3m RDS(ON) = 20m @ VGS = 4.5V See Note 2. RDS(ON) = 10m @ VGS = 4.5V See Note 2. Low ESR Requirements/Comments
Preliminary Specification
IRMS = 2A ESR 44m
Notes: 1. Inductor L1 is recommended to isolate the 5V input supply from noise generated by the MOSFET switching, and to comply with Intel dI/dt requirements. L1 may be omitted if desired. 2. For 12.5A designs using the TO-220 MOSFETs, heatsinks with thermal resistance SA < 20C/ should be used. For designs using the TO-263 MOSFETs, adequate copper area should be used. For details and a spreadsheet on MOSFET selections, refer to Applications Bulletins AB-8 and AB-15.
11
RC5058
Application Circuit Summary
Table 4 summarizes the worst-case design schematics presented in this section. The basic choices are: A) The processor, B) the chipset used, and C) the use or not of a sense resistor. Depending on board layout and component selection, it may be possible to use fewer output capacitors than shown here. For configurations not shown in this datasheet, consult the Appendix for selection of component values.
Table 4. Recommended Values for CPU-based Applications
Processor Coppermine Katmai Mendocino Katmai Chipset Whitney Camino Whitney BX CIN 3 4 4 5 COUT* 4 6 5 6 R5, R7 (K) 8.45 13.0 11.3 11.8
Preliminary Specification
*Output capacitance requirements depend critically on layout and processor type. Consult Application Bulletin AB-14 for details. See the Appendix to this datasheet for the method of calculation of these components. Pin 4 must be used to remote sense the voltage at the processor to achieve the specified performance.
Test Parameters
tR 5V 2V t DT 2V 5V 2V tDT LODRV tF HIDRV to SW
output to one of the summing amplifier inputs. The second, current control path, takes the difference between the DROOP and SW pins when the high-side MOSFET is on, reproducing the voltage across the MOSFET and thus the input current; it presents the resulting signal to another input of the summing amplifier. These two signals are then summed together. This output is then presented to a comparator looking at the oscillator ramp, which provides the main PWM control signal to the digital control block. The digital control block takes the analog comparator input and the main clock signal from the oscillator to provide the appropriate pulses to the HIDRV and LODRV output pins. These two outputs control the external power MOSFETs. There is an additional comparator in the analog control section whose function is to set the point at which the RC5058 current limit comparator disables the output drive signals to the external power MOSFETs.
2V
Figure 3. Ouput Drive Timing Diagram
Application Information
The RC5058 Controller
The RC5058 is a programmable synchronous DC-DC controller IC. When designed around the appropriate external components, the RC5058 can be configured to deliver more than 16A of output current, as appropriate for the Katmai and Coppermine and other processors. The RC5058 functions as a fixed frequency PWM step down regulator.
High Current Output Drivers
The RC5058 contains two identical high current output drivers that utilize high speed bipolar transistors in a push-pull configuration. The drivers' power and ground are separated from the chip's power and ground for switching noise immunity. The power supply pin, VCCP, is supplied from an external 12V source through a series 33 resistor. The resulting voltage is sufficient to provide the gate to source drive to the external MOSFETs required in order to achieve a low RDS,ON.
Main Control Loop
Refer to the RC5058 Block Diagram on page 1. The RC5058 implements "summing mode control", which is different from both classical voltage-mode and current-mode control. It provides superior performance to either by allowing a large converter bandwidth over a wide range of output loads. The control loop of the regulator contains two main sections: the analog control block and the digital control block. The analog section consists of signal conditioning amplifiers feeding into a comparator which provides the input to the digital control block. The signal conditioning section accepts input from the DROOP (current feedback) and VFB (voltage feedback) pins and sets up two controlling signal paths. The first, the voltage control path, amplifies the difference between the VFB signal and the reference voltage from the DAC and presents the
12
Internal Voltage Reference
The reference included in the RC5058 is a precision band-gap voltage reference. Its internal resistors are precisely trimmed to provide a near zero temperature coefficient (TC). Based on the reference is the output from an integrated 5-bit DAC. The DAC monitors the 5 voltage identification pins, VID0-4. When the VID4 pin is at logic HIGH, the DAC scales the reference voltage from 2.0V to 3.5V in 100mV increments. When VID4
RC5058
is pulled LOW, the DAC scales the reference from 1.30V to 2.05V in 50mV increments. All VID codes are available, including those below 1.80V.
affects the efficiency of the DC-DC Converter. For details and a spreadsheet on MOSFET selection, refer to Applications Bulletin AB-8.
Power Good (PWRGD)
The RC5058 Power Good function is designed in accordance with the Pentium II DC-DC converter specifications and provides a continuous voltage monitor on the VFB pin. The circuit compares the VFB signal to the VREF voltage and outputs an active-low interrupt signal to the CPU should the power supply voltage deviate more than 12% of its nominal setpoint. The Power Good flag provides no other control function to the RC5058.
Inductor Selection
Choosing the value of the inductor is a tradeoff between allowable ripple voltage and required transient response. The system designer can choose any value within the allowed minimum to maximum range in order to either minimize ripple or maximize transient performance. The first order equation (close approximation) for minimum inductance is:
Lmin = (Vin - Vout) f x Vout Vin ESR x Vripple
Preliminary Specification
Output Enable/Soft Start (ENABLE/SS)
The RC5058 will accept an open collector/TTL signal for controlling the output voltage. The low state disables the output voltage. When disabled, the PWRGD output is in the low state. Even if an enable is not required in the circuit, this pin should have attached a capacitor (typically 100nF) to softstart the switching.
where: Vin = Input Power Supply Vout = Output Voltage f = DC/DC converter switching frequency ESR = Equivalent series resistance of all output capacitors in parallel Vripple = Maximum peak to peak output ripple voltage budget. The first order equation for maximum allowed inductance is:
Lmax = 2CO (Vin - Vout) Dm Vtb Ipp2
Over-Voltage Protection
The RC5058 constantly monitors the output voltage for protection against over-voltage conditions. If the voltage at the VFB pin exceeds the selected program voltage, an over-voltage condition is assumed and the RC5058 disables the output drive signal to the external high-side MOSFET. The DC-DC converter returns to normal operation after the output voltage returns to normal levels.
Oscillator
The RC5058 oscillator section uses a fixed frequency of operation of 300KHz.
where: Co = The total output capacitance Ipp = Maximum to minimum load transient current Vtb = The output voltage tolerance budget allocated to load transient Dm = Maximum duty cycle for the DC/DC converter (usually 95%). Some margin should be maintained away from both Lmin and Lmax. Adding margin by increasing L almost always adds expense since all the variables are predetermined by system performance except for CO, which must be increased to increase L. Adding margin by decreasing L can be done by purchasing capacitors with lower ESR. The RC5058 provides significant cost savings for the newer CPU systems that typically run at high supply current.
Design Considerations and Component Selection
Additional information on design and component selection may be found in Fairchild's Application Note 57.
MOSFET Selection
This application requires N-channel Logic Level Enhancement Mode Field Effect Transistors. Desired characteristics are as follows: Low Static Drain-Source On-Resistance, RDS,ON < 20m (lower is better) Low gate drive voltage, VGS = 4.5V rated Power package with low Thermal Resistance Drain-Source voltage rating > 15V. The on-resistance (RDS,ON) is the primary parameter for MOSFET selection. The on-resistance determines the power dissipation within the MOSFET and therefore significantly
RC5058 Short Circuit Current Characteristics
The RC5058 protects against output short circuit on the core supply by turning off both the high-side and low-side MOSFETs and resetting softstart. The short circuit limit is set with the RS resistor, as given by the formula
RS =
ISC *RDS, on IDetect
13
RC5058
with IDetect 50A, ISC is the desired current limit, and RDS,on the high-side MOSFET's on resistance. Remember to make the RS large enough to include the effects of initial tolerance and temperature variation on the MOSFET's RDS,on. Alternately, use of a sense resistor in series with the source of the MOSFET eliminates this source of inaccuracy in the current limit. The value of RS should be less than 10K. If a greater value is necessary, a lower RDS,on MOSFET should be used instead. As an example, Figure 4 shows the typical characteristic of the DC-DC converter circuit with an FDB6030L high-side MOSFET (RDS = 20m maximum at 25C * 1.25 at 75C = 25m) and a 8.2K RS.
Since this time duration is very short, the selection criterion for the diode is that the forward voltage of the Schottky at the output current should be less than the forward voltage of the MOSFET's body diode.
Output Filter Capacitors
The output bulk capacitors of a converter help determine its output ripple voltage and its transient response. It has already been seen in the section on selecting an inductor that the ESR helps set the minimum inductance, and the capacitance value helps set the maximum inductance. For most converters, however, the number of capacitors required is determined by the transient response and the output ripple voltage, and these are determined by the ESR and not the capacitance value. That is, in order to achieve the necessary ESR to meet the transient and ripple requirements, the capacitance value required is already very large. The most commonly used choice for output bulk capacitors is aluminum electrolytics, because of their low cost and low ESR. The only type of aluminum capacitor used should be those that have an ESR rated at 100kHz. Consult Application Bulletin AB-14 for detailed information on output capacitor selection. The output capacitance should also include a number of small value ceramic capacitors placed as close as possible to the processor; 0.1F and 0.01F are recommended values.
Preliminary Specification
CPU Output Voltage vs. Output Current 3.5 3.0 2.5 VOUT (V) 2.0 1.5 1.0 0.5 0 0 5 10 15 20 25
Figure 4. RC5058 Short Circuit Characteristic
The converter exhibits a normal load regulation characteristic until the voltage across the MOSFET exceeds the internal short circuit threshold of 50A * 8.2K = 410mV, which occurs at 410mV/25m = 16.4A. (Note that this current limit level can be as high as 410mV/15m = 27A, if the MOSFET has typical RDS,on rather than maximum, and is at 25C). At this point, the internal comparator trips and signals the controller to discharge softstart. This causes a drastic reduction in the output voltage as the load regulation collapses into the short circuit control mode. With a 40m output short, the voltage is reduced to 16.4A * 40m = 650mV. The output voltage does not return to its nominal value until the output current is reduced to a value within the safe operating ranges for the DC-DC converter. If any of the linear regulator outputs are loaded heavily enough that their output voltage drops below 80% of nominal for >30sec, all RC5058 outputs, including the switcher, are shut off and remain off until power is recycled.
Input Filter
The DC-DC converter design may include an input inductor between the system +5V supply and the converter input as shown in Figure 5. This inductor serves to isolate the +5V supply from the noise in the switching portion of the DC-DC converter, and to limit the inrush current into the input capacitors during power up. A value of 2.5H is recommended. It is necessary to have some low ESR aluminum electrolytic capacitors at the input to the converter. These capacitors deliver current when the high side MOSFET switches on. Figure 5 shows 3 x 1000F, but the exact number required will vary with the speed and type of the processor. For the top speed Katmai and Coppermine, the capacitors should be rated to take 9A and 6A of ripple current respectively. Capacitor ripple current rating is a function of temperature, and so the manufacturer should be contacted to find out the ripple current rating at the expected operational temperature. For details on the design of an input filter, refer to Applications Bulletin AB-15.
2.5H 5V 0.1F Vin 1000F, 10V Electrolytic
Schottky Diode Selection
The application circuit of Figure 1 shows a Schottky diode, D1, which is used as a free-wheeling diode to assure that the body-diode in Q2 does not conduct when the upper MOSFET is turning off and the lower MOSFET is turning on. It is undesirable for this diode to conduct because its high forward voltage drop and long reverse recovery time degrades efficiency, and so the Schottky provides a shunt path for the current.
Figure 5. Input Filter
14
RC5058
Programmable Active DroopTM
The RC5058 includes Programmable Active DroopTM: as the output current increases, the output voltage drops, and the amount of this drop is user adjustable. This is done in order to allow maximum headroom for transient response of the converter. The current is typically sensed by measuring the voltage across the RDS,on of the high-side MOSFET during its on time, as shown in Figure 1. To program the amount of droop, use the formula
RD 14.4K *Imax *Rsense VDroop *18
For example, to get the VTT voltage to be 1.55V instead of 1.50V, use R = 10K * [(1.55/1.50) - 1] = 333.
Using the RC5058 for Vnorthbridge = 1.8V
In some motherboards, Intel requires that the AGP power can not be greater than 2.2V while the chipset voltage (Vnorthbridge = 1.8V) is less than 1.0V. The RC5058 can accomplish this by using the VTT regulator to generate Vnorthbridge. Use the circuit in Figure 6 with R = 2K. Since the linear regulators on the RC5058 all rise proportionally to one another, when Vnorthbridge = 1.0V, Vagp = 1.8V, meeting the Intel requirement.
PCB Layout Guidelines
Preliminary Specification
where Imax is the current at which the droop occurs, and Rsense is the resistance of the current sensor, either the source resistor or the high-side MOSFET's on-resistance. For example, to get 30mV of droop with a maximum output current of 12.5A and a 10m sense resistor, use RD = 14.4K * 12.5A * 10m/ (30mV * 18) = 3.33K. Further details on use of the Programmable Active DroopTM may be found in Applications Bulletin AB-24.
Placement of the MOSFETs relative to the RC5058 is critical. Place the MOSFETs such that the trace length of the HIDRV and LODRV pins of the RC5058 to the FET gates is minimized. A long lead length on these pins will cause high amounts of ringing due to the inductance of the trace and the gate capacitance of the FET. This noise radiates throughout the board, and, because it is switching at such a high voltage and frequency, it is very difcult to suppress. In general, all of the noisy switching lines should be kept away from the quiet analog section of the RC5058. That is, traces that connect to pins 1, 2, 23, and 24 (HIDRV, SW, LODRV and VCCP) should be kept far away from the traces that connect to pins 3, 20 and 21. Place the 0.1F decoupling capacitors as close to the RC5058 pins as possible. Extra lead length on these reduces their ability to suppress noise. Each VCC and GND pin should have its own via to the appropriate plane. This helps provide isolation between pins. Place the MOSFETs, inductor, and Schottky as close together as possible for the same reasons as in the rst bullet above. Place the input bulk capacitors as close to the drains of the high side MOSFETs as possible. In addition, placement of a 0.1F decoupling cap right on the drain of each high side MOSFET helps to suppress some of the high frequency switching noise on the input of the DC-DC converter. Place the output bulk capacitors as close to the CPU as possible to optimize their ability to supply instantaneous current to the load in the event of a current transient. Additional space between the output capacitors and the CPU will allow the parasitic resistance of the board traces to degrade the DC-DC converterOs performance under severe load transient conditions, causing higher voltage deviation. For more detailed information regarding capacitor placement, refer to Application Bulletin AB-5. A PC Board Layout Checklist is available from Fairchild Applications. Ask for Application Bulletin AB-11.
Remote Sense
The RC5058 offers remote sense of the output voltage to minimize the output capacitor requirements of the converter. It is highly recommended that the remote sense pin, Pin 20, be tied directly to the processor power pins, so that the effects of power plane impedance are eliminated. Further details on use of the remote sense feature of the RC5058 may be found in Applications Bulletin AB-24.
Adjusting the Linear Regulators' Output Voltages
Any or all of the linear regulators' outputs may be adjusted high to compensate for voltage drop along traces, as shown in Figure 6.
VGATE VOUT R VFB 10K
Figure 6. Adjusting the Output Voltage of the Linear Regulator
The resistor value should be chosen as
R = 10K*
Vout Vnom
-1
15
RC5058
PC Motherboard Sample Layout and Gerber File
A reference design for motherboard implementation of the RC5058 along with the PCAD layout Gerber file and silk screen can be obtained from our marketing department at 650-966-7624.
RD, the resistance of the current sensor (usually the MOSFET); RD, the tolerance of the current sensor (usually about 67% for MOSFET sensing, including temperature); and ESR, the ESR of the output capacitors, per cap (44m for the Sanyo parts shown in this datasheet).
2 IO * Cin = Irms Vnom Vin - Vnom Vin
RC5058 Evaluation Board
Fairchild provides an evaluation board to verify the system level performance of the RC5058. It serves as a guide to performance expectations when using the supplied external components and PCB layout. Please call the marketing department at 650-966-7624 for an evaluation board.
Preliminary Specification
Additional Information
For additional information contact Fairchild Semiconductor's Analog & Mixed Signal Products Group Marketing Department at 650-966-7624.
Roffset = VS+ - .024 * Vnom 1.01 * Vnom IO* RD * (1 + RD) 45 * 10-6 * 1K
Appendix
Worst-Case Formulae for the Calculation of Cin, Cout , R5, R7 and Roffset (Circuits similar to
Figure 1 only) The following formulae design the RC5058 for worst-case operation, including initial tolerance and temperature dependence of all of the IC parameters (initial setpoint, reference tolerance and tempco, internal droop impedance, current sensor gain), the initial tolerance and temperature dependence of the MOSFET, and the ESR of the capacitors. The following information must be provided: VS+, the value of the positive static voltage limit; |VS-|, the absolute value of the negative static voltage limit; VT+, the value of the positive transient voltage limit; |VT-|, the absolute value of the negative transient voltage limit; IO, the maximum output current; Vnom, the nominal output voltage; Vin, the input voltage (typically 5V); Irms, the ripple current rating of the input capacitors, per cap (2A for the Sanyo parts shown in this datasheet);
Y=
R7 =
14400 * IO* RD * (1 + RD) *1.1 R5 = 18 * (VS+ + VS- - .024 * Vnom)
Number of capacitors needed for Cout = the greater of:
X= VTESR * IO + VS+ - .024 * Vnom
or
ESR * IO VT+ - VS+ + 14400 * IO * RD 18 * R5 * 1.1
16
RC5058
Example: Suppose that the static limits are +89mV/-79mV, transient limits are 134mV, current I is 14.2A, and the nominal voltage is 2.000V, using MOSFET current sensing. We have VS+ = 0.089, |VS-| = 0.079, VT+ = |VT-| = 0.134, IO = 14.2, Vnom = 2.000, and RD = 1.67. We calculate:
2
Since Y > X, we choose Y, and round up to find we need 7 capacitors for COUT. A detailed explanation of this calculation may be found in Applications Bulletin AB-24.
2.000 14.2 * 5 Cin = 2
-
2.000 5
= 3.47 4 caps
Roffset =
0.089 - .024 * 2.000 1.01 * 2.000
*1000 = 20.3
Preliminary Specification
R7 =
14.2 * 0.020 * (1 + 0.67) 45 * 10-6
= 10.5K
R5 =
14400 * 14.2 * 0.020 * (1 + 0.67) * 1.1 18 * (0.089 + 0.079 - .024 * 2.000)
= 3.48K
X=
0.044 * 14.2 0.134 + 0.089 - .024 * 2.00 0.044 * 14.2
= 3.57
Y= 0.134 - 0.089 + 14400 * 14.2 * 0.020 18 * 3640 * 1.1
= 6.14
17
RC5058
Mechanical Dimensions
24 Lead SOIC
Symbol A A1 B C D E e H h L N ccc Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
.093 .104 .004 .012 .013 .020 .009 .013 .599 .614 .290 .299 .050 BSC .394 .419 .010 .016 24 0 -- 8 .004 .020 .050
2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 15.20 15.60 7.36 7.60 1.27 BSC 10.00 10.65 0.25 0.40 24 0 -- 8 0.10 0.51 1.27
Preliminary Specification
3 6
24
13
E
H
1
12
D A e B A1 SEATING PLANE -C- LEAD COPLANARITY ccc C L
h x 45 C
18
RC5058
Ordering Information
Product Number RC5058M Package 24 pin SOIC
Preliminary Specification
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
10/14/99 0.0m 010 Stock#DS30005057 (c) 1998 Fairchild Semiconductor Corporation
www.fairchildsemi.com
RC5060
ACPI Switch Controller
Features
Implements ACPI control with PWROK, SLP_S3# and SLP_S5# Switch and linear regulator controller for 3.3V Dual (PCI) Linear regulator controller and linear regulator for 2.5V Dual (RAMBUS) Two switch controller for 5V Dual (USB) Switch controller and linear regulator for 3.3V SDRAM Provides SDRAM and RAMBUS power simutaneously Adaptive Break-before-Make Integrated Power Good Drives all N-Channel MOSFETs plus NPN Latched overcurrent protection for outputs, functional during startup too Power-up softstarts for the linear regulators UVLO guarantees correct operation for all conditions 20 pin SOIC package
Applications
Camino Platform ACPI Controller Whitney Platform ACPI Controller
Description
The RC5060 is an ACPI Switch Controller for the Camino and Whitney Platforms. It is controlled by PWROK, SLP_S3# and SLP_S5#, and provides 3.3V Dual for PCI, 3.3V for SDRAM, 2.5V Dual for RAMBUS, and 5V Dual voltages. An on-board precision low TC reference achieves tight tolerance voltage regulation without expensive external components. The RC5060 also offers integrated Power Good and Current Limiting that protects each output, and softstart for the linear regulators. The RC5060 is available in a 20 pin SOIC.
Preliminary Specification
Block Diagram
+5V Standby PWROK 3.3V Main 3 +5V Main 4 3.3V SDRAM 13 9 PWRGD Over Current +3.3V Main 3.3V MAIN 16 Over Current + REF + 14 + + REF 7 8 +3.3V Dual (PCI) 6 +5V Standby Softstart + + Over Current Ref + 19 Osc 18 17 REF +5V Dual (USB) +5V Standby 12 SLP S3# 10 SLP S5# 11 5 1 2 20 +12V
15 2.5V Dual (RAMBUS)
REF
Rev. 0.8.0 Preliminary Specification describes products that are not in full production at the time of printing. Specifications are based on design goals and limited characterization. They may change without notice. Contact Fairchild Semiconductor for current information.
RC5060
Pin Assignments
QCAP PUMP SDRAMOUT SDRAMFB 5VSTBY 3VOUT1 3VOUT2 3VFB PWRGD SLP_S3# 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCCP 5VOUT1 5VOUT2 5VFB RAMBUSOUT RAMBUSFB GND SS PWROK SLP_S5#
RC5060
Pin Definitions
Preliminary Specification
Pin Number 1 2 3 4
Pin Name QCAP PUMP SDRAMOUT SDRAMFB
Pin Function Description Charge pump cap. Attach flying capacitor between this pin and PUMP to generate high voltage from standby power. Charge pump switcher. 3.3V SDRAM gate control. Attach this pin to a transistor powering 3.3V SDRAM from the 3.3V main supply. 3.3V SDRAM voltage feedback. Pin 4 is used as the input for the voltage feedback control loop for 3.3V SDRAM, and also sources 3.3V SDRAM in standby. 5V Standby. Apply +5V standby on this pin to run the circuit in standby mode. 3.3V main gate control. Attach this pin to a transistor powering 3.3V dual from the 3.3V main supply. 3.3V standby gate control. Attach this pin to a transistor powering 3.3V dual from the 5V standby supply. 3.3V voltage Feedback. Pin 8 is used as the input for the voltage feedback control loop for 3.3V dual. Power Good. Open collector output is high when all outputs are valid. SLP_S3#. Control signal governing the Soft Off state S3. Internal current source pulls this line high if left open. SLP_S5#. Control signal governing the Soft Off state S5. Internal current source pulls this line high if left open. PWROK. Control signal for switches. Internal current source pulls this line high if left open. Softstart. Attach a capacitor to this pin to determine the softstart rate. Ground. Connect this pin to ground. 2.5V feedback. Pin 15 is used as the input for the voltage feedback control loop for 2.5V dual (RAMBUS), and also sources 2.5V dual in standby. 2.5V base drive control. Attach this pin to an NPN transistor powering 2.5V dual (RAMBUS) from the 3.3V main supply. 5V Voltage Feedback. Pin 17 is used to sense undervoltage to protect the 5V dual from overcurrent. 5V standby gate control. Attach this pin to a transistor powering 5V dual from the 5V standby supply. 5V main gate control. Attach this pin to a transistor powering 5V dual from the 5V main supply. Main Power. Apply +12V through a diode on this pin to run the circuit in normal mode. Bypass with a 0.1F capacitor. When 12V is not present, this pin produces voltage doubled 5V standby.
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
5VSTBY 3VOUT1 3VOUT2 3VFB PWRGD SLP_S3# SLP_S5# PWROK SS GND RAMBUSFB RAMBUSOUT 5VFB 5VOUT2 5VOUT1 VCCP
2
RC5060
Absolute Maximum Ratings
All Pins Junction Temperature, TJ Storage Temperature Lead Soldering Temperature, 10 seconds Thermal Resistance Junction to Ambient JA Thermal Resistance Junction-to-case, JC 13.5V 150C -65 to 150C 300C 85C/W 24C/W
Recommended Operating Conditions
Parameter +3.3VMAIN +5VMAIN +5VSTBY +12V Ambient Operating Temperature Conditions Min. 3.135 4.75 4.75 11.4 0 Typ. 3.3 5 5 12 Max. 3.465 5.25 5.25 12.6 70 Units
Preliminary Specification
3
V V V V C
RC5060
Electrical Specifications
(V+5VSTBY = V+5VMAIN =5V, V+3.3V = 3.3V, V+12V = 12V and TA = +25C using circuit in Figure 3, unless otherwise noted.) The * denotes specifications which apply over the full operating temperature range. Parameter +5V DUAL VOut1, On VOut1, Off VGS, Out2 VOut2, Off Maximum Drive Current, Each Standby * * * * * 10 80 30 See Figure 2 * * * 3VOUT2 On 3VOUT2 On * * * 80 30 See Figure 2: Main Standby : Standby Main +2.5V DUAL IB, On IOut Total Output Voltage Variation1 Overcurrent Limit Overcurrent Delay Time Output Driver Overlap Time +3.3V SDRAM Vout, On Vout, Off IOut Overcurrent Limit Total Output Voltage Variation Overcurrent Delay Time Output Driver Dead Time Common Functions PWRGD Threshold PWRGD Delay Time PWRGD Sink Current Charge Pump Frequency +5VSTBY UVLO +5VSTBY UVLO Hysteresis * 1 200 4.5 0.5 80 30 %Vout sec mA KHz V V * 200
1
Conditions
Min. 10
Typ.
Max.
Units V
200 2.7 200
mV V mV mA %Vout sec
Preliminary Specification
Overcurrent Limit: Undervoltage Overcurrent Delay Time Output Driver Overlap Time +3.3V DUAL VOut1, On VOut1, Off Total Output Voltage Variation1 Maximum Drive Current Minimum Load Current Overcurrent Limit: Undervoltage Overcurrent Delay Time Output Driver Deadtime * * * * * 2 200 200 144 2.375 10 1
5
sec V
200 3.135 100 50 3.3 3.465
mV V mA mA %Vout sec
6 1000
sec nsec mA mA
RAMBUSOUT On RAMBUSOUT Off
2.5 80 30
2.625
V %Vout sec
See Figure 2
* * *
1 10
5
sec V
200 100 80 3.135 3.3 30 1500 3.465
mV mA %Vout V sec nsec
SDRAMOUT Off SDRAMFB On
* *
4
RC5060
Electrical Specifications (continued)
(V+5VSTBY = V+5VMAIN =5V, V+3.3V = 3.3V, V+12V = 12V and TA = +25C using circuit in Figure 3, unless otherwise noted.) The * denotes specifications which apply over the full operating temperature range. Parameter +12V UVLO +12V UVLO Hysteresis +5VSTBY Current +12V Current Input Logic HIGH Input Logic LOW Softstart Current Control Line Input Current Over Temperature Shutdown
Note: 1. Voltage Regulation includes Initial Voltage Setpoint and Output Temperature Drift.
Conditions
Min.
Typ. 7.5 1
Max.
Units V V
MAIN Power Present * * 2.0
10 2.5
25 10 0.8
mA mA V V A
10 SLP_S5#, SLP_S3#, PWROK * 150 10
Preliminary Specification
A C
Table 1. Static Power Descriptors
PWROK 0 0 1 1 1 SLP_S3# 0 0 0 0 1 SLP_S5# 0 1 0 1 1
STBY SLP_S3# PWROK MAIN MAIN
Main OFF OFF OFF OFF ON
5 & 3.3V Duals ON ON ON ON ON
2.5V Dual/3.3V SDRAM OFF ON OFF ON, Powered from STBY ON, Powered from MAIN
State S5 S3 S0 S5 S0 S3 S0
STBY
SLP_S3# PWROK
SLP_S5# DUAL MEMORY
Figure 1. Control Logic for Dual Voltages and Memory Voltages
OUTPUT 1 2V 2V tDT 2V OUTPUT2 2V tOT 2V 2V 2V tOT
OUTPUT1
tDT 2V
OUTPUT2
Figure 2. Deadtime and Overlap Time Measurements 5
RC5060
Application Circuits
+5V Standby 5V Main +12V 3.3V Main
D1
PWRGD
R1
C1 C3 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
C2 C9 Q5 Q6
+5V Dual
Q1
Q3
U1 RC5060
Q2
Preliminary Specification
Q4
C10
C7
C8
2.5V Dual (RAMBUS) 3.3V SDRAM 3.3V Dual (PCI)
SLPS5# PWROK SLPS3#
C5
C6
C4
Figure 3. Camino ACPI Selector
Table 2. RC5060 Application Bill of Materials for Camino
Reference C1-3, C8 C4-6, C9 C7 C10 R1 D1 Q1, Q3 Q2 Q4 Q5-6 U1 Manufacturer, Part # Various Various Various Various Various Fairchild MBR0520L Fairchild FDS4410DY Fairchild TIP41A Fairchild NDS9956A Fairchild NDH833N Fairchild RC5060 Quantity 4 4 1 1 1 1 2 1 1 2 1 Description 100nF, 25V 220F, 6V 10nF, 50V 47F, 10V 10K Resistor 20V, 1/2A Schottky N-channel MOSFET NPN N-channel MOSFET N-channel MOSFET ACPI Switch Controller Rds,on = 20m @ Vgs = 4.5V VCE ~0.4V @ IC = 2A, IB = 100mA Rds,on = 110m @ Vgs = 4.5V Rds,on = 25m @ Vgs = 2.7V Ceramic Tantalum, ESR ~ 0.1 Ceramic Tantalum Comments
6
RC5060
+5V Standby 5V Main +12V 3.3V Main
D1
PWRGD
R1
C1 C3 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
C2
C9
Q5 Q6
+5V Dual
Q1
Q3 Q4
U1 RC5060
C7
C8
Preliminary Specification
C10
3.3V SDRAM 3.3V Dual (PCI) SLPS5# PWROK SLPS3#
C5
C4
Figure 4. Whitney ACPI Selector
Table 3. RC5060 Application Bill of Materials for Whitney
Reference C1-3, C8 C4-5, C9 C7 C10 R1 D1 Q1, Q3 Q4 Q5-6 U1 Manufacturer, Part # Various Various Various Various Various Fairchild MBR0520L Fairchild FDS4410DY Fairchild NDS9956A Fairchild NDH833N Fairchild RC5060 Quantity 4 3 1 1 1 1 2 1 2 1 Description 100nF, 25V 220F, 6V 10nF, 50V 47F, 10V 10K Resistor 20V, 1/2A Schottky N-channel MOSFET N-channel MOSFET N-channel MOSFET ACPI Switch Controller Rds,on = 20m @ Vgs = 4.5V Rds,on = 110m @ Vgs = 4.5V Rds,on = 25m @ Vgs = 2.7V Ceramic Tantalum, ESR ~ 0.1 Ceramic Tantalum Comments
7
RC5060
Vcore 2V/17.4A ATX 5Vmain, 18A RC5058 SO24 5Vstdby 720mA Typedet Synchronous Conversion Vnb 1.8V/2A Linear Linear/Switch Vck 2.5V/600mA Linear Switch Switch RC1587 Vtt 1.5V/2A Vagp 3.3V/1.5V/2A
12V, 6A
5Vdual 1A/1A/200mA USB
Preliminary Specification
3.3Vmain, 14A RC5060 SO20 Linear Switch Linear PWROK SLP_S3# SLP_S5# Linear 2.5V RDRAM @ 2A/144mA 3.3Vdual 2.4A/500mA/500mA PCI
Linear Switch
3.3V SDRAM @ 4.8A/100mA
Figure 5. Camino System Architectural Block Diagram (Power Paths Only)
Application Information
The RC5060 Controller
The RC5060 is a fully compliant ACPI controller IC. Used with an ATX power supply, it generates a 5V Dual voltage, a 3.3V Dual for PCI, and power for both SDRAM and RAMBUS, and has a large array of additional protection functions integrated in. Used in conjunction with Fairchild's RC5058, it provides the complete set of control and power functions necessary to implement a Camino or Whitney motherboard.
As shown in Figure 5, the available power inputs to the computer system from the ATX power supply are +5V main, +12V main, +3.3V main, and +5V standby. "Main" means that these power outputs are available under full-power operation of the system, but can be turned off in some of the powersaving modes. "Standby" means that this power output is always present. The most general ACPI system requires four dual outputs: 5V dual, 3.3V dual, 3.3V SDRAM, and 2.5V RAMBUS (or 2.5V dual). "Dual" means that the power can be (but is not necessarily) present whether the main power supplies are present or not. To ensure the presence of these outputs, while not overloading the standby power, they have dual inputs, from both main power and standby. The presence or absence of the dual outputs is determined by the control signals to the RC5060.
Overview of ACPI
The Advanced Configuration and Power Interface, or ACPI, is a system for controlling the use of power in a computer. It enables the computer manufacturer and the computer user to determine the computer's power usage dynamically. For example, when the computer has been unused for a certain time, the monitor and peripherals could be turned off, and their states saved to memory. After a longer period, the processor could be turned off, and the memory saved to disk. A peripheral could then re-awaken the entire system on the occurrence of an event, such as the arrival of a FAX on a modem.
ACPI States
As shown in Table 1, there are three ACPI states that are of primary concern to the system designer, designated S0, S3 and S5. S0 is the full-power state, the state of the computer when it is being actively used. The other two states are sleep states, reflecting differing levels of power-down.
8
RC5060
S3 is a state in which the processor is powered down, but its last state is being preserved in IC memory, which is kept on. Since memory is fast, the computer can quickly come back up to full operation. However, this state continues to draw moderate power, due to the memory being kept S5 is a state in which memory is off, and the last state of the processor has been written to the hard disk. Since the disk is slow, the computer takes longer to come back to full operation. However, since memory is off, this state draws minimal power. It is anticipated that only the following state transitions will occur: S0 S3, S0 S5, S3 S5, S5 S0, and S3 S0; the transition S5 S3 will not occur, as going from save-todisk to save-to-memory will not be activated by any mechanism.
3.3V Dual Output
The 3.3V dual output is intended to power subsystems such as the computer's PCI slots. A typical application that would require the use of 3.3V dual rather than +3.3V main for a PCI slot would be the use of a modem: if the system needs to be able to awaken from sleep when the modem receives incoming data, then that slot must be powered from dual, because main power is off. Other slots not requiring dual power can be configured using the control signals. 3.3V dual is generated by two MOSFETs, one from +3.3V main, the other from +5V standby, as shown in Figures 3 or 4. When main power is present, the MOSFET Q3 is turned on as a switch, so that input and output are connected together. When main power is absent, the MOSFET Q4 is controlled by the RC5060 as a linear regulator, generating a regulated 3.3V from +5V standby. As with the 5V dual, the MOSFET Q3 must be connected as shown in the figures, to avoid back-feed. The state of the MOSFETs is controlled by the SLP_S3# and PWROK lines, as shown in Figure 1. When both SLP_S3# and PWROK are asserted, the main switch is on, and the linear regulator is off. If either line is de-asserted, the main switch is off and the linear regulator is on. Q3 and Q4 as shown in Tables 2 or 3 have different RDS,on ratings. In a typical system, it is anticipated that full-power current will be about 2.4A maximum, and standby current will be about 500mA maximum. The difference in maximum currents means that Q4 can be a less expensive device than Q3.
Preliminary Specification
5V Dual Output
The RC5060 controls four separate dual outputs, the first of which is the 5V dual. This output is intended to run subsystems such as the USB ports. A typical application that would require the use of 5V dual rather than +5V main for a USB port would be the use of a USB mouse: if the system needs to be able to awaken from sleep when the mouse is moved, then the mouse must be powered from dual, because main power is off. 5V dual is generated by two MOSFET switches, one from +5V main, the other from +5V standby, as shown in Figures 3 or 4. When main power is present, the first switch is on and the second off, and the opposite when main power is absent. Note carefully the polarity of the MOSFET Q5 that delivers power from the +5V main to the 5V dual: opposite to the connection of Q6, the source is connected to the +5V main input, and the drain is connected to the 5V dual output. This connection must be done this way because of Q5's body diode. When +5V main is not present, 5V dual is still on, and if Q5 were connected with the same polarity as Q6, the dual voltage would conduct through the body diode of Q5, attempting to power up the entire +5V main line. It is to avoid this overload that Q5 must be connected as shown. The state of the switches is controlled by the SLP_ S3# and PWROK lines, as shown in Figure 1. When both SLP_ S3# and PWROK are asserted, the main switch is on, and the standby switch is off. If either line is de-asserted, the main switch is off and the standby switch is on. Note that Q5 and Q6 should be low-gate-voltage type MOSFETs, with guaranteed operation at 2.7V Vgs, in order to ensure full enhancement in worst case. In a typical system, it is anticipated that full-power current will be about 1A maximum, and standby current will be about 200mA maximum.
3.3V SDRAM Output
3.3V SDRAM output is intended to provide power to SDRAM memory. Most systems will use this power. Those systems using RAMBUS may also use the SDRAM power, possibly piped to the same slots, to ensure backward compatibility or even mixed operation of SDRAM with RAMBUS. 3.3V SDRAM is generated by one external MOSFET switch from +3.3V main, and one linear regulator internal to the RC5060 from +5V standby, as shown in Figures 3 or 4, and in the block diagram on the front page. When main power is present, the MOSFET Ql is turned on as a switch, so that input and output are connected together. When main power is absent, the internal linear regulator is on, generating a regulated 3.3V from +5V standby. As with the other duals, the MOSFET Ql must be connected as shown in the figures, to avoid back-feed. The state of the external MOSFET and the internal linear regulator is controlled by the SLP_S3# and PWROK lines, and additionally the SLP_S5# line, as shown in Figure 1. When SLP_S5# is de-asserted, both the external MOSFET and the internal linear regulator are off, and there is no output voltage on the 3.3V SDRAM line.
9
RC5060
If the SLP_S5# line is asserted, the 3.3V SDRAM output is on. In this condition, if either the SLP_S3# or the PWROK line, or both, are de-asserted, the linear regulator is on and the MOSFET is off. Only in the case if both the SLP_S3# and the PWROK lines are asserted, the MOSFET is on and the linear regulator is off. In a typical system, it is anticipated that standby current will be about 100mA maximum. Full power current will be as high as 4.8A maximum, so that Ql must have a low RDS,on in order to prevent excessive voltage drop across it.
RC5060 Dynamic Operation
The RC5060 is designed to minimize the output capacitance required to hold up the various output lines during transitions between different states. Thus in particular, the 5V dual and 2.5V dual outputs have guaranteed minimum overlap times, the time (as shown in Figure 2) during a state transition during which both main and standby are connected to the output. This overlap time guarantees that a power source is always connected to the output, so that there will be no dip in the output voltage during state transitions. There is also a maximum overlap time, to ensure that the standby power doesn't have to source main power very long, thus minimizing thermal stress on the standby device. The 3.3V dual and 3.3V SDRAM are different than the other outputs, because they are powered by both a linear regulator and a switch. If the linear regulator were to turn on while the switch is on (or vice versa) the linear regulator would supply power to the main line through the switch. For this reason, the linear regulator must be off before the switch is on, and vice versa. Thus, these two outputs have guaranteed minimum deadtime when both linear regulator and switch are off. During this time, the output capacitors must hold up the load, and so there is also a specified maximum deadtime, allowing a maximum necessary capacitance to be selected, see below.
2.5V Dual Output
Preliminary Specification
The 2.5V dual output is intended to provide power to RAMBUS memory. Only high-end systems will use this power. Those systems using RAMBUS may also use the SDRAM power, possibly piped to the same slots, to ensure backward compatibility or even mixed operation of SDRAM with RAMBUS. 2.5V dual is generated by one external NPN bipolar acting as a linear regulator from +3.3V main, and one linear regulator internal to the RC5060 from +5V standby, as shown in Figure 3, and in the block diagram on the front page. When main power is present, the NPN Q2 linear regulates, and when main power is absent, the internal linear regulator is on. Q2 cannot be substituted with a MOSFET. If used in one direction, the MOSFET's body diode would permit backfeed; if used in the other direction, it would short-circuit the linear regulator action. 2.5V dual output is controlled in the same way and by the same lines as the 3.3V SDRAM output. In a typical system, it is anticipated that standby current will be a maximum of 144mA, and full-power current may be as high as 2A. This places some significant constraints on the selection of Q2. Since its input may be as low as (3.3V - 5%) = 3.135V, there is only 3.135V -2.5V = 635mV of VCE headroom for its operation as a linear regulator. For this reason the RC5060 can provide up to 200mA of steady-state base current. The TIP41 device shown has a sufficiently low VCE, sat to guarantee worst-case regulation even at 2A IE with this base current.
Stability
As with all linear regulators, the RC5060's linear regulators require a minimum load. With the exception of the 3.3V dual output, however, all of these minimum loads are internal to the RC5060. The 3.3V dual output requires a minimum load of 50mA; if a situation may occur in which the load is less than 50mA, additional steps may be necessary to ensure stability. Furthermore, depending on location, it may be necessary to bypass the drain (or collector) of the linear regulator with a low ESR capacitor for stability. As a rule of thumb, if the pass element is more than 1" from its power source, it should have a bypass.
Softstart
Pin 13 of the RC5060 functions as a softstart. When power is first applied to the chip, a constant current is applied from the pin into an external capacitor, linearly ramping up the voltage. This ramp in turn controls the internal reference of the RC5060. providing a softstart for the linear regulators. The actual state of the RC5060 on power up will be determined by the state of its control lines. The switches in the system must be either on or off, and so softstart has no effect on their characteristics: if the appropriate control signals are asserted, they will turn on at once. The softstart is effective only during power on. During a transition between states, such as from S5 S0, the linear regulators are not softstarted.
RC5060 ACPI Control Lines
As already discussed, the RC5060 outputs are controlled by the three ACPI control lines, SLP_S3#, SLP_S5# and PWROK, as summarized in Table 1. System designers must in particular be careful to ensure that their system is designed with SLP_S5#, not SLP_S5#; if SLP_S5 is used, it must be inverted before being used with the RC5060. The control lines have internal pull-ups of approximately 10A, and so can be controlled by open collector drivers if desired. In a noisy system, it may be desirable to filter these lines, which can be done with a 1K resistor and a small capacitor.
10
RC5060
It is important to note that the softstart pin is not an enable; pulling it low will not necessarily turn off all outputs.
Charge Pump
In main power operation, the RC5060 is run from the +12V main supply. This supply also provides voltage to the various MOSFET gates. However, during standby, this supply is off. To provide power to the chip and the appropriate gates, the RC5060 incorporates a free-running charge pump. As shown in Figures 3 and 4, and in the block diagram on the front page, a capacitor attached between pins 1 and 2 of the RC5060 acts as a charge pump with internal diodes. The charge pump output is internally diode or'red with the 12V input. The 12V input must have a series diode to prevent back-feeding the charge pump to the + 12V main when in standby. The 12V input line needs a bypass capacitor for high-frequency noise rejection.
dissipation, any overloading of outputs can cause excessive heating. If the RC5060 die temperature exceeds about 150, all outputs are shut off. Outputs remain off until the die temperature returns to its safe area.
Transistor Selection
External transistor selection depends on usage, differing for the linear regulators and the switches. The MOSFET switches, Ql, Q3, Q5 and Q6 should be sized based on regulation requirements and power dissipation. Since the ATX outputs are 5%, the outputs driven from them must be wider. As an example, if we want to hold 3.3V SDRAM to -10%, we can drop only 5% = 165mV across Q1. At 4.8A, this means Ql must have a maximum RDS,on of 165mV/4.8A = 34m, including tolerance and self-heating effects. We thus choose a Fairchild FDS4410Y, which has 20m maximum RDS, on at 4.5V VGS at 25C. We can estimate power dissipation as (4.8A)2 * 20m = 460mW, which should be acceptable for this package. Similar calculations apply to the other MOSFET switches. Q4 is a MOSFET functioning as a linear regulator. Since it delivers only 500mA, it is easy to select a MOSFET, it need only have RDS,on less than (5V-5%-3.3V)/500mA = 2.9. We select the Fairchild NDS9956A which has maximum RDS, on of 110m at 4.5V VGS at 25C. Power dissipation will be a maximum of (0.5A)2 * 110m = 27mW. Q2 is an NPN bipolar functioning as a linear regulator. As already discussed, it must have a VCE,sat lower than 635mV at IE = 2A and IB = 200mA. Its power dissipation can be as high as (3.3V + 5%-2.5V) * 2A = l.9W.
Preliminary Specification
Overcurrent
The RC5060 does not directly detect current through the eight devices that power its outputs. Instead, it monitors the four output voltages. In the event of a hard short, the voltage drops below 80% of nominal, and all outputs are latched off, and remain off until 5V standby power is recycled. The overcurrent latch off is delayed by 30sec to prevent nuisance trips. During softstart, the overcurrent voltage monitors are kept proportional to the reference, to avoid tripping overcurrent during startup. The monitors are kept active during softstart, to avoid turning on into a short. In the S5 state, when the memory outputs are off, the voltage monitors on the memory lines are disabled, to prevent tripping the overcurrent. When turning these lines back on from the S5 state, the delay prevents overcurrent from tripping. If the 2.5V dual is not used, its feedback line, pin 15, must be connected to 5V dual as shown in Figure 4, to prevent an overcurrent trip.
Output Capacitor Selection
Output capacitor selection depends on whether the line has overlap time or not. For both the 5V dual and the 2.5V dual, there is guaranteed overlap time between when one source is turned on and the other source turned off. For these outputs, the output capacitor is not needed to hold up the supply, but only for noise filtering and to respond to transient loading. The 3.3V dual and 3.3V SDRAM outputs have deadtime between when one source is turned off and the other source turned on. During the time when both are off, the output current must be supplied by the output capacitor. Mitigating this, it must be realized that the system will be designed in such a way that the current has gone to its sleep value before the transition occurs. For example, the 3.3V dual has a sleep current of 500mA maximum. Maximum deadtime is 6sec, and so charge depletion is 500mA * 6sec = 3C. Suppose that we have a total of 8% drop due to the source tolerance and the MOSFET drop, and we are trying to hold 10% regulation. The remaining 2% = 66mV implies a minimum capacitance of 3C/66mV = 45F.
UVLO
If the +5V standby is below approximately 4.5V, the RC5060 will leave off or turn off all outputs. Similar comments apply to the +12V main at 7.5V. The +5V standby UVLO has approximately 0.5V hysteresis, the +12V main UVLO 1V.
Power Good
The Power Good is an open collector that pulls low if any of the outputs are less than 80% of nominal.
Over Temperature
The RC5060 is capable of sourcing substantial current, 200mA minimum to the RAMBUS transistor's base during S0, 144mA to the RAMBUS line during S3, and 100mA to SDRAM during S3. As a result, there can be heavy power dissipation in the IC. While the RC5060 is designed to accept this power
11
RC5060
Mechanical Dimensions
20 Lead SOIC
Inches Min. A A1 B C D E e H h L N ccc Max. Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
Symbol
.093 .104 .004 .012 .013 .020 .009 .013 .496 .512 .291 .299 .050 BSC .394 .010 .016 20 0 -- 8 .004 .419 .029 .050
2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 12.60 13.00 7.40 7.60 1.27 BSC 10.00 0.25 0.40 20 0 -- 8 0.10 10.65 0.75 1.27
Preliminary Specification
3 6
20
11
E
H
1
10
D A e B A1 SEATING PLANE -C- LEAD COPLANARITY ccc C
h x 45 C
L
12
RC5060
Ordering Information
Product Number RC5060M Package 20 pin SOIC
Preliminary Specification
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
8/23/99 0.0m 008 Stock#DS30005057 (c) 1998 Fairchild Semiconductor Corporation
www.fairchildsemi.com
RC5061
High Performance Programmable Synchronous DC-DC Controller for Multi-Voltage Platforms
Features
* Programmable output for Vcore from 1.3V to 3.5V using an integrated 5-bit DAC * Controls adjustable linears for Vtt (1.5V), and Vclock (2.5V) * Meets VRM specification with as few as 5 capacitors * Meets 1.550V +40/-70mV over initial tolerance, temperature and transients * Remote sense * Active Droop (Voltage Positioning) * Drives N-Channel MOSFETs * Overcurrent protection using MOSFET sensing * 85% efficiency typical at full load * Integrated Power Good and Enable/Soft Start functions * 20 pin SOIC package
Applications
* * * * Power supply for Pentium(R) III Camino Platform Power supply for Pentium III Whitney Platform VRM for Pentium III processor Programmable multi-output power supply
Preliminary Specification
Description
The RC5061 is a synchronous mode DC-DC controller IC which provides a highly accurate, programmable set of output voltages for multi-voltage platforms such as the Intel Camino, and provides a complete solution for the Intel Whitney and other high-performance processors. The RC5061 features remote voltage sensing, independently adjustable current limit, and Active Droop for optimal converter transient response. The RC5061 uses a 5-bit D/A converter to program the output voltage from 1.3V to 3.5V. The RC5061 uses a high level of integration to deliver load currents in excess of 16A from a 5V
Block Diagram
+3.3V 9 10 VCCP 11 + + +5V VCCA 17 REF PWRGD, OCL OCL REF +12V PWRGD, OCL OSC + + 15 RS 16 20 VCCP 1 HIDRV +5V
+1.5V
12 +2.5V
+
+
Digital Control
2
VCC
19 LODRV 18 GNDP
5-Bit DAC 8765 4 VID0 VID2 VID4 VID1 VID3
1.24V Reference 3 GNDA 13 ENABLE/SS
Power Good
14
PWRGD
Pentium is a registered trademark of Intel Corporation.
Rev. 0.8.2
Preliminary Specification describes products that are not in full production at the time of printing. Specifications are based on design goals and limited characterization. In the process of final product release, specification. Contact Fairchild Semiconductor for current information.
RC5061
source with minimal external circuitry. Synchronous-mode operation offers optimum efficiency over the entire specified output voltage range. An on-board precision low TC reference achieves tight tolerance voltage regulation without expensive external components, while Active Droop permits exact tailoring of voltage for the most demanding load transients. The RC5061 includes linear regulator controllers for Vtt termination (1.5V), and Vclock (2.5V), each adjustable with an external divider. The RC5061 also offers integrated functions including Power Good, Output Enable/Soft Start and current limiting, and is available in a 20 pin SOIC package.
Pin Assignments
HIDRV SW GNDA VID4 VID3 VID2 VID1 VID0 VTTGATE VTTFB 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCCP LODRV GNDP VCCA VFB IFB PWRGD SS/ENABLE VCKFB VCKGATE
RC5061
Preliminary Specification
Pin Definitions
Pin Number Pin Name 1 2 3 4-8 HIDRV SW GNDA VID0-4 Pin Function Description High Side FET Driver. Connect this pin through a resistor to the gate of an N-channel MOSFET. The trace from this pin to the MOSFET gate should be <0.5". High side Driver Source and Low side Driver Drain Switching Node. Together with DROOP and ILIM pins allows FET sensing for Vcc current. Analog Ground. Return path for low power analog circuitry. This pin should be connected to a low impedance system ground plane to minimize ground loops. Voltage Identification Code Inputs. These open collector/TTL compatible inputs will program the output voltage over the ranges specified in Table 2. Pull-up resistors are internal to the controller. Gate Driver for VTT Transistor. For 1.5V output. Voltage Feedback for VTT. Gate Driver for VCK Transistor. For 2.5V output. Voltage Feedback for VCK. Output Enable. A logic LOW on this pin will disable all outputs. An internal current source allows for open collector control. This pin also doubles as soft start for all outputs. Power Good Flag. An open collector output that will be logic LOW if any output voltage is not within 12% of the nominal output voltage setpoint. Vcc Current Feedback. Pin 15 is used in conjunction with pin 2 as the input for the Vcc current feedback control loop. Layout of these traces is critical to system performance. See Application Information for details. Vcc Voltage Feedback. Pin 16 is used as the input for the Vcc voltage feedback control loop. See Application Information for details regarding correct layout. Analog VCC. Connect to system 5V supply and decouple with a 0.1F ceramic capacitor. Power Ground. Return pin for high currents flowing in pin 20 (VCCP). Vcc Low Side FET Driver. Connect this pin through a resistor to the gate of an N-channel MOSFET for synchronous operation. The trace from this pin to the MOSFET gate should be <0.5". Power VCC. For all FET drivers. Connect to system 12V supply through a 33, and decouple with a 1F ceramic capacitor.
9 10 11 12 13 14 15
VTTGATE VTTFB VCKGATE VCKFB ENABLE/SS PWRGD IFB
16 17 18 19
VFB VCCA GNDP LODRV
20
VCCP
2
RC5061
Absolute Maximum Ratings
Supply Voltages VCCA, VCCP to GND Voltage Identification Code Inputs, VID0-VID4 All Other Pins Junction Temperature, TJ Storage Temperature Lead Soldering Temperature, 10 seconds Thermal Resistance Junction-to-ambient, JA
Note: 1. Component mounted on demo board in free air.
1
13.5V VCCA 13.5V 150C -65 to 150C 300C 75C/W
Preliminary Specification
Recommended Operating Conditions
Parameter Supply Voltage VCCA Input Logic HIGH Input Logic LOW Ambient Operating Temperature Output Driver Supply, VCCP 0 10.8 12 Conditions Min. 4.75 2.0 0.8 70 13.2 Typ. 5 Max. 5.25 Units V V V C V
Electrical Specifications
(VCCA = 5V, VCCP = 12V, VOUT = 2.0V, and TA = +25C using circuit in Figure 1 unless otherwise noted.) The * denotes specifications which apply over the full operating temperature range. Parameter VCC Regulator Output Voltage Output Current Initial Voltage Setpoint ILOAD = 0.8A, VOUT = 2.400V VOUT = 2.000V VOUT = 1.550V TA = 0 to 70C, VOUT = 2.000V VOUT = 1.550V VIN = 4.75V to 5.25V ILOAD = 0.8A to 12.5A 20MHz BW, ILOAD = 18A VOUT = 2.000V VOUT = 1.550V3 ILOAD = 0.8A to 18A, VOUT = 2.000V VOUT = 1.550V3 ILOAD = 18A, VOUT = 2.0V See Figure 3 See Figure 3 0 * * * * * 1.940 1.480 1.900 1.480 45 50 85 50 50 100 * * * 13.0 2.397 2.000 1.550 See Table 1 * 1.3 18 2.424 2.020 1.565 +8 +6 -4 14.4 60 11 2.070 1.590 2.100 1.590 60 15.8 2.454 2.040 1.580 3.5 V A V V V mV mV mV/V K mV mVpk V V A % nsec nsec %
3
Conditions
Min.
Typ.
Max.
Units
Output Temperature Drift Line Regulation Internal Droop Impedance Maximum Droop Output Ripple Total Output Variation, Steady State1 Total Output Variation, Transient2 Short Circuit Detect Current Efficiency Output Driver Rise & Fall Time Output Driver Deadtime Duty Cycle
RC5061
Electrical Specifications (Continued)
(VCCA = 5V, VCCP = 12V, VOUT = 2.0V, and TA = +25C using circuit in Figure 1 unless otherwise noted.) The * denotes specifications which apply over the full operating temperature range. Parameter 5V UVLO 12V UVLO Soft Start Current VTT Linear Regulator Output Voltage Under Voltage Trip Level VCLK Linear Regulator ILOAD 2A Over Current ILOAD 2A Over Current * Logic HIGH, All Outputs Logic LOW, Any Output Over Current * * 255 93 88 30 * 2.375 * 1.425 1.5 80 2.5 80 310 345 107 112 2.625 1.575 V %VO V %VO kHz %VOUT sec Conditions * * * Min. 3.74 7.65 5 Typ. 4 8.5 10 Max. 4.26 9.35 17 Units V V A
Preliminary Specification
Output Voltage Under Voltage Trip Level Common Functions Oscillator Frequency PWRGD Threshold Linear Regulator Under Voltage Delay Time
Notes: 1. Steady State Voltage Regulation includes Initial Voltage Setpoint, Droop, Output Ripple and Output Temperature Drift and is measured at the converter's VFB sense point. 2. As measured at the converter's VFB sense point. For motherboard applications, the PCB layout should exhibit no more than 0.5m trace resistance between the converter's output capacitors and the CPU. Remote sensing should be used for optimal performance. 3. Using the VFB pin for remote sensing of the converter's output at the load, the converter will be in compliance with Intel's VRM 8.4 specification of +50, -80mV. If Intel specifications on maximum plane resistance from the converter's output capacitors to the CPU are met, the specification of +40, -70mV at the capacitors will also be met.
4
RC5061
Table 1. Output Voltage Programming Codes
VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Nominal VOUT 1.30V 1.35V 1.40V 1.45V 1.50V 1.55V 1.60V 1.65V
Preliminary Specification
1.70V 1.75V 1.80V 1.85V 1.90V 1.95V 2.00V 2.05V 2.0V 2.1V 2.2V 2.3V 2.4V 2.5V 2.6V 2.7V 2.8V 2.9V 3.0V 3.1V 3.2V 3.3V 3.4V 3.5V
Note: 1. 0 = processor pin is tied to GND. 1 = processor pin is open.
5
RC5061
Typical Operating Characteristics
(VCCA = 5V, VCCP = 12V, and TA = +25C using circuits in Figure 1, unless otherwise noted.)
VCPU Efficiency vs. Output Current 2.04 88 86 84 82 80 78 76 74 72 70 68 66 64 0 3 6 9 12 Output Current (A) 15 18 VOUT = 1.550V VOUT = 2.000V 2.03 2.02 2.01 2.00 VOUT (V) 1.99 1.98 1.97 1.96 1.95 1.94 0 3 6 9 12 15 18 Output Current (A) Droop, VCPU = 2.0V, RD = 8K
Preliminary Specification
Efficiency (%)
CPU Output Voltage vs. Output Current 3.5 3.0 2.5 VOUT (V) 2.0 1.5 1.0 0.5 0 0 5 10 15 20 25 Output Current (A)
Output Programming, VID4 = 0 2.1 1.9 1.7 1.5 1.3 1.1 1.30 1.40 1.50 1.60 1.70 1.80 1.90 2.00 DAC Setpoint 3.5 3.0 2.5 2.0 1.5 1.0
Output Programming, VID4 = 1
VCPU(V)
VCPU(V)
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2. 3.3 3.4 3.5 DAC Setpoint
6
RC5061
Typical Operating Characteristics (continued)
Output Ripple, 2.0V @ 18A Transient Response, 12.5A to 0.5A
VCPU (20mV/div)
VCPU (50mV/div)
1.590V 1.550V 1.480V
Preliminary Specification
Time (1s/div)
Time (100s/div)
Transient Response, 0.5A to 12.5A
Switching Waveforms, 18A Load
5V/div
VCPU (50mV/div)
1.590V 1.550V 1.480V 5V/div
HIDRV pin
LODRV pin
Time (1s/div) Time (100s/div)
Output Startup, System Power-up VCPU (1V/div) ENABLE (2V/div)
Output Startup from Enable
VCPU (1V/div)
VIN (2V/div)
Time (10ms/div)
Time (10ms/div)
7
RC5061
Typical Operating Characteristics (continued)
Linear Regulator Noise
2.042 2.040 2.038 VCPU (V) 2.036 2.034 2.030 2.028
AC COUPLED VOUT (10mV/div)
Preliminary Specification
2.026 0 25 70 100
Time (100s/div)
Temperature (C)
Application Circuit
L1 (Optional) +5V CIN*
R6
C1
R7 C2
L2 VO COUT* D1 3.3V IN Q3 C10 1.5V C8
Q1
R2
1 2 3 VID4 VID3 VID2 VID1 VID0 4 5 6 7 8 9 10 U1 RC5061
Q2
R3
20 19 18 17 16 15 14 13 12 11
R1 +12V C5 VCC R4 PWRGD ENABLE/SS Q4 C11 C4 C6
C3
2.5V C9 * Refer to Table 4 for values of COUT and CIN. Adjustable with an external divider.
Figure 1. Application Circuit for Katmai/Camino/BX/ZX Motherboards (Worst Case Analyzed! See Appendix for Details)
8
RC5061
Table 2. RC5061 Application Bill of Materials for Intel Katmai/Camino/BX/ZX Motherboards
(Components based on Worst Case Analysis--See Appendix for Details) Reference C1 C2, C5 C3-4,C6 C8-9 C10-11 CIN COUT D1 L1 L2 Q1 Q2 Q3-4 R1 R2-3 R4 R6 R7 U1 Manufacturer Part # AVX TAJB475M010R5 Panasonic ECU-V1C105ZFX Panasonic ECU-V1H104ZFX Sanyo 6MV1000FA Any Sanyo 10MV1200GX Sanyo 6MV1500GX Motorola MBRD835L Any Any Fairchild FDB6030L Fairchild FDB7030BL Fairchild FDB4030L Any Any Any Any Any Fairchild RC5061M Quantity 1 2 3 2 2 * * 1 Optional 1 1 1 2 1 2 1 1 1 1 Description 4.7F, 10V Capacitor 1F, 16V Capacitor 100nF, 50V Capacitor 1000F, 6.3V Electrolytic 22F, 6.3V Capacitor 1200F, 10V Electrolytic 1500F, 6.3V Electrolytic 8A Schottky Diode 2.5H, 8A Inductor 1.3H, 20A Inductor N-Channel MOSFET N-Channel MOSFET N-Channel MOSFET 33 4.7 10K 10 * DC/DC Controller DCR ~ 10m See Note 1. DCR ~ 2m RDS(ON) = 20m @ VGS = 4.5V See Note 2. RDS(ON) = 10m @ VGS = 4.5V See Note 2. Low ESR IRMS = 2A ESR 44m Requirements/Comments
Preliminary Specification
Notes: 1. Inductor L1 is recommended to isolate the 5V input supply from noise generated by the MOSFET switching, and to comply with Intel dI/dt requirements. L1 may be omitted if desired. 2. For 17.4A designs using the TO-220 MOSFETs, heatsinks with thermal resistance SA < 20C/ should be used. For designs using the TO-263 MOSFETs, adequate copper area should be used. For details and a spreadsheet on MOSFET selections, refer to Applications Bulletins AB-8 and AB-15. *Refer to table 4 for values.
9
RC5061
L1 (Optional) +5V CIN*
R6
C1
C2 Q1 R7 R2
Preliminary Specification
R8 VO COUT*
L2
R10
1 2 3 R3 VID4 VID3 VID2 VID1 VID0 4 5 6 7 8 9 10 U1 RC5061
Q2 D1 3.3V IN Q3
C10 1.5V C8
20 19 18 17 16 15 14 13 12 11
R1 +12V C5 VCC R4 PWRGD ENABLE/SS C4 Q5 C11 C6
C3
2.5V C9 *Refer to Table 3 for values of COUT, and CIN. Adjustable with an external divider.
Figure 2. Application Circuit for Coppermine/Camino Motherboards (Typical Design)
10
RC5061
Table 3. RC5061 Application Bill of Materials for Intel Coppermine/Camino Motherboards
(Typical Design) Reference C1 C2, C5 C3-4,C6 C8-9 C10-11 CIN COUT D1 L1 L2 Q1 Q2 Q3-4 R1 R2-3 R4 R6 R7 R8 U1 Manufacturer Part # AVX TAJB475M010R5 Panasonic ECU-V1C105ZFX Panasonic ECU-V1H104ZFX Sanyo 6MV1000FA Any Sanyo 10MV1200GX Sanyo 6MV1500GX Motorola MBRD835L Any Any Fairchild FDB6030L Fairchild FDB7030BL Fairchild FDB4030L Any Any Any Any Any N/A Fairchild RC5061M Quantity 1 2 3 2 2 3 12 1 Optional 1 1 1 2 1 2 1 1 1 1 1 Description 4.7F, 10V Capacitor 1F, 16V Capacitor 100nF, 50V Capacitor 1000F, 6.3V Electrolytic 22F, 6.3V Capacitor 1200F, 10V Electrolytic 1500F, 6.3V Electrolytic 8A Schottky Diode 2.5H, 5A Inductor 1.3H, 15A Inductor N-Channel MOSFET N-Channel MOSFET N-Channel MOSFET 33 4.7 10K 10 6.24K 30m DC/DC Controller PCB Trace Resistor DCR ~ 10m See Note 1. DCR ~ 3m RDS(ON) = 20m @ VGS = 4.5V See Note 2. RDS(ON) = 10m @ VGS = 4.5V See Note 2. Low ESR Requirements/Comments
Preliminary Specification
IRMS = 2A ESR 44m
Notes: 1. Inductor L1 is recommended to isolate the 5V input supply from noise generated by the MOSFET switching, and to comply with Intel dI/dt requirements. L1 may be omitted if desired. 2. For 12.5A designs using the TO-220 MOSFETs, heatsinks with thermal resistance SA < 20C/ should be used. For designs using the TO-263 MOSFETs, adequate copper area should be used. For details and a spreadsheet on MOSFET selections, refer to Applications Bulletins AB-8 and AB-15.
11
RC5061
Application Circuit Summary
Table 4 summarizes the worst-case design schematics presented in this section. The basic choices are: A) The processor, B) the chipset used, and C) the use or not of a sense resistor. Depending on board layout and component selection, it may be possible to use fewer output capacitors than shown here. For configurations not shown in this datasheet, consult the Appendix for selection of component values.
Table 4. Recommended Values for CPU-based Applications
Processor Coppermine Katmai Mendocino Katmai Chipset Whitney Camino Whitney BX CIN 3 4 4 5 COUT* 4 6 5 6 R5, R7 (K) 8.45 13.0 11.3 11.8
Preliminary Specification
*Output capacitance requirements depend critically on layout and processor type. Consult Application Bulletin AB-14 for details. See the Appendix to this datasheet for the method of calculation of these components. Pin 4 must be used to remote sense the voltage at the processor to achieve the specified performance.
Test Parameters
tR 5V 2V t DT 2V 5V 2V tDT LODRV tF HIDRV to SW
output to one of the summing amplifier inputs. The second, current control path, takes the difference between the DROOP and SW pins when the high-side MOSFET is on, reproducing the voltage across the MOSFET and thus the input current; it presents the resulting signal to another input of the summing amplifier. These two signals are then summed together. This output is then presented to a comparator looking at the oscillator ramp, which provides the main PWM control signal to the digital control block. The digital control block takes the analog comparator input and the main clock signal from the oscillator to provide the appropriate pulses to the HIDRV and LODRV output pins. These two outputs control the external power MOSFETs. There is an additional comparator in the analog control section whose function is to set the point at which the RC5061 current limit comparator disables the output drive signals to the external power MOSFETs.
2V
Figure 3. Ouput Drive Timing Diagram
Application Information
The RC5061 Controller
The RC5061 is a programmable synchronous DC-DC controller IC. When designed around the appropriate external components, the RC5061 can be configured to deliver more than 16A of output current, as appropriate for the Katmai and Coppermine and other processors. The RC5061 functions as a fixed frequency PWM step down regulator.
High Current Output Drivers
The RC5061 contains two identical high current output drivers that utilize high speed bipolar transistors in a push-pull configuration. The drivers' power and ground are separated from the chip's power and ground for switching noise immunity. The power supply pin, VCCP, is supplied from an external 12V source through a series 33 resistor. The resulting voltage is sufficient to provide the gate to source drive to the external MOSFETs required in order to achieve a low RDS,ON.
Main Control Loop
Refer to the RC5061 Block Diagram on page 1. The RC5061 implements "summing mode control", which is different from both classical voltage-mode and current-mode control. It provides superior performance to either by allowing a large converter bandwidth over a wide range of output loads. The control loop of the regulator contains two main sections: the analog control block and the digital control block. The analog section consists of signal conditioning amplifiers feeding into a comparator which provides the input to the digital control block. The signal conditioning section accepts input from the DROOP (current feedback) and VFB (voltage feedback) pins and sets up two controlling signal paths. The first, the voltage control path, amplifies the difference between the VFB signal and the reference voltage from the DAC and presents the
12
Internal Voltage Reference
The reference included in the RC5061 is a precision band-gap voltage reference. Its internal resistors are precisely trimmed to provide a near zero temperature coefficient (TC). Based on the reference is the output from an integrated 5-bit DAC. The DAC monitors the 5 voltage identification pins, VID0-4. When the VID4 pin is at logic HIGH, the DAC scales the reference voltage from 2.0V to 3.5V in 100mV increments. When VID4
RC5061
is pulled LOW, the DAC scales the reference from 1.30V to 2.05V in 50mV increments. All VID codes are available, including those below 1.80V.
affects the efficiency of the DC-DC Converter. For details and a spreadsheet on MOSFET selection, refer to Applications Bulletin AB-8.
Power Good (PWRGD)
The RC5061 Power Good function is designed in accordance with the Pentium III DC-DC converter specifications and provides a continuous voltage monitor on the VFB pin. The circuit compares the VFB signal to the VREF voltage and outputs an active-low interrupt signal to the CPU should the power supply voltage deviate more than 12% of its nominal setpoint. The Power Good flag provides no other control function to the RC5061.
Inductor Selection
Choosing the value of the inductor is a tradeoff between allowable ripple voltage and required transient response. The system designer can choose any value within the allowed minimum to maximum range in order to either minimize ripple or maximize transient performance. The first order equation (close approximation) for minimum inductance is:
Lmin = (Vin - Vout) f x Vout Vin ESR x Vripple
Preliminary Specification
Output Enable/Soft Start (ENABLE/SS)
The RC5061 will accept an open collector/TTL signal for controlling the output voltage. The low state disables the output voltage. When disabled, the PWRGD output is in the low state. Even if an enable is not required in the circuit, this pin should have attached a capacitor (typically 100nF) to softstart the switching.
where: Vin = Input Power Supply Vout = Output Voltage f = DC/DC converter switching frequency ESR = Equivalent series resistance of all output capacitors in parallel Vripple = Maximum peak to peak output ripple voltage budget. The first order equation for maximum allowed inductance is:
Lmax = 2CO (Vin - Vout) Dm Vtb Ipp2
Over-Voltage Protection
The RC5061 constantly monitors the output voltage for protection against over-voltage conditions. If the voltage at the VFB pin exceeds the selected program voltage, an over-voltage condition is assumed and the RC5061 disables the output drive signal to the external high-side MOSFET. The DC-DC converter returns to normal operation after the output voltage returns to normal levels.
Oscillator
The RC5061 oscillator section uses a fixed frequency of operation of 300KHz.
where: Co = The total output capacitance Ipp = Maximum to minimum load transient current Vtb = The output voltage tolerance budget allocated to load transient Dm = Maximum duty cycle for the DC/DC converter (usually 95%). Some margin should be maintained away from both Lmin and Lmax. Adding margin by increasing L almost always adds expense since all the variables are predetermined by system performance except for CO, which must be increased to increase L. Adding margin by decreasing L can be done by purchasing capacitors with lower ESR. The RC5061 provides significant cost savings for the newer CPU systems that typically run at high supply current.
Design Considerations and Component Selection
Additional information on design and component selection may be found in Fairchild's Application Note 57.
MOSFET Selection
This application requires N-channel Logic Level Enhancement Mode Field Effect Transistors. Desired characteristics are as follows: Low Static Drain-Source On-Resistance, RDS,ON < 20m (lower is better) Low gate drive voltage, VGS = 4.5V rated Power package with low Thermal Resistance Drain-Source voltage rating > 15V. The on-resistance (RDS,ON) is the primary parameter for MOSFET selection. The on-resistance determines the power dissipation within the MOSFET and therefore significantly
RC5061 Short Circuit Current Characteristics
The RC5061 protects against output short circuit on the core supply by turning off both the high-side and low-side MOSFETs and resetting softstart. The short circuit limit is set with the RS resistor, as given by the formula
RS = ISC *RDS, on IDetect
13
RC5061
with IDetect 50A, ISC is the desired current limit, and RDS,on the high-side MOSFET's on resistance. Remember to make the RS large enough to include the effects of initial tolerance and temperature variation on the MOSFET's RDS,on. Alternately, use of a sense resistor in series with the source of the MOSFET eliminates this source of inaccuracy in the current limit. The value of RS should be less than 10K. If a greater value is necessary, a lower RDS,on MOSFET should be used instead. As an example, Figure 4 shows the typical characteristic of the DC-DC converter circuit with an FDB6030L high-side MOSFET (RDS = 20m maximum at 25C * 1.25 at 75C = 25m) and a 8.2K RS.
Since this time duration is very short, the selection criterion for the diode is that the forward voltage of the Schottky at the output current should be less than the forward voltage of the MOSFET's body diode.
Output Filter Capacitors
The output bulk capacitors of a converter help determine its output ripple voltage and its transient response. It has already been seen in the section on selecting an inductor that the ESR helps set the minimum inductance, and the capacitance value helps set the maximum inductance. For most converters, however, the number of capacitors required is determined by the transient response and the output ripple voltage, and these are determined by the ESR and not the capacitance value. That is, in order to achieve the necessary ESR to meet the transient and ripple requirements, the capacitance value required is already very large. The most commonly used choice for output bulk capacitors is aluminum electrolytics, because of their low cost and low ESR. The only type of aluminum capacitor used should be those that have an ESR rated at 100kHz. Consult Application Bulletin AB-14 for detailed information on output capacitor selection. The output capacitance should also include a number of small value ceramic capacitors placed as close as possible to the processor; 0.1F and 0.01F are recommended values.
Preliminary Specification
CPU Output Voltage vs. Output Current 3.5 3.0 2.5 VOUT (V) 2.0 1.5 1.0 0.5 0 0 5 10 15 20 25
Figure 4. RC5061 Short Circuit Characteristic
The converter exhibits a normal load regulation characteristic until the voltage across the MOSFET exceeds the internal short circuit threshold of 50A * 8.2K = 410mV, which occurs at 410mV/25m = 16.4A. (Note that this current limit level can be as high as 410mV/15m = 27A, if the MOSFET has typical RDS,on rather than maximum, and is at 25C). At this point, the internal comparator trips and signals the controller to discharge softstart. This causes a drastic reduction in the output voltage as the load regulation collapses into the short circuit control mode. With a 40m output short, the voltage is reduced to 16.4A * 40m = 650mV. The output voltage does not return to its nominal value until the output current is reduced to a value within the safe operating ranges for the DC-DC converter. If any of the linear regulator outputs are loaded heavily enough that their output voltage drops below 80% of nominal for > 30sec, all RC5061 outputs, including the switcher, are shut off and remain off until power is recycled.
Input Filter
The DC-DC converter design may include an input inductor between the system +5V supply and the converter input as shown in Figure 5. This inductor serves to isolate the +5V supply from the noise in the switching portion of the DC-DC converter, and to limit the inrush current into the input capacitors during power up. A value of 2.5H is recommended. It is necessary to have some low ESR aluminum electrolytic capacitors at the input to the converter. These capacitors deliver current when the high side MOSFET switches on. Figure 5 shows 3 x 1000F, but the exact number required will vary with the speed and type of the processor. For the top speed Katmai and Coppermine, the capacitors should be rated to take 9A and 6A of ripple current respectively. Capacitor ripple current rating is a function of temperature, and so the manufacturer should be contacted to find out the ripple current rating at the expected operational temperature. For details on the design of an input filter, refer to Applications Bulletin AB-15.
2.5H 5V 0.1F Vin 1000F, 10V Electrolytic
Schottky Diode Selection
The application circuit of Figure 1 shows a Schottky diode, D1, which is used as a free-wheeling diode to assure that the body-diode in Q2 does not conduct when the upper MOSFET is turning off and the lower MOSFET is turning on. It is undesirable for this diode to conduct because its high forward voltage drop and long reverse recovery time degrades efficiency, and so the Schottky provides a shunt path for the current.
Figure 5. Input Filter
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RC5061
Active Droop
The RC5061 includes active droop; as the ouptut current increases, the output voltage drops. This is done in order to allow maximum headroom for transient response of the converter. The current is sensed by measuring the voltage across the high-side MOSFET during its on time. Note that this makes the droop dependent on the temperature of the MOSFET. However, when the formula given for selecting RS (current limit) is used, there is a maximum droop possible (-40mV), and when this value is reached, additional drop across the MOSFET will not cause any increase in droop--until current limit is reached. Additional droop can be added to the active droop using a discrete resistor (typically a PCB trace) outside the control loop, as shown in Figure 2. This is typically only required for the most demanding applications, such as for the next generation Intel processor (tolerance = +40/-70mV), as shown in Figure 2.
PCB Layout Guidelines
Placement of the MOSFETs relative to the RC5061 is critical. Place the MOSFETs such that the trace length of the HIDRV and LODRV pins of the RC5061 to the FET gates is minimized. A long lead length on these pins will cause high amounts of ringing due to the inductance of the trace and the gate capacitance of the FET. This noise radiates throughout the board, and, because it is switching at such a high voltage and frequency, it is very difcult to suppress. In general, all of the noisy switching lines should be kept away from the quiet analog section of the RC5061. That is, traces that connect to pins 1, 2, 19, and 20 (HIDRV, SW, LODRV and VCCP) should be kept far away from the traces that connect to pins 3, 16 and 17. Place the 0.1F decoupling capacitors as close to the RC5061 pins as possible. Extra lead length on these reduces their ability to suppress noise. Each VCC and GND pin should have its own via to the appropriate plane. This helps provide isolation between pins. Place the MOSFETs, inductor, and Schottky as close together as possible for the same reasons as in the rst bullet above. Place the input bulk capacitors as close to the drains of the high side MOSFETs as possible. In addition, placement of a 0.1F decoupling cap right on the drain of each high side MOSFET helps to suppress some of the high frequency switching noise on the input of the DC-DC converter. Place the output bulk capacitors as close to the CPU as possible to optimize their ability to supply instantaneous current to the load in the event of a current transient. Additional space between the output capacitors and the CPU will allow the parasitic resistance of the board traces to degrade the DC-DC converterOs performance under severe load transient conditions, causing higher voltage deviation. For more detailed information regarding capacitor placement, refer to Application Bulletin AB-5. A PC Board Layout Checklist is available from Fairchild Applications. Ask for Application Bulletin AB-11.
Preliminary Specification
Remote Sense
The RC5061 offers remote sense of the output voltage to minimize the output capacitor requirements of the converter. It is highly recommended that the remote sense pin, Pin 16, be tied directly to the processor power pins, so that the effects of power plane impedance are eliminated. Further details on use of the remote sense feature of the RC5061 may be found in Applications Bulletin AB-24.
Adjusting the Linear Regulators' Output Voltages
Any or all of the linear regulators' outputs may be adjusted high to compensate for voltage drop along traces, as shown in Figure 6.
VGATE VOUT R VFB 10K
PC Motherboard Sample Layout and Gerber File
Figure 6. Adjusting the Output Voltage of the Linear Regulator
A reference design for motherboard implementation of the RC5061 along with the PCAD layout Gerber file and silk screen can be obtained from our marketing department at 650-966-7624.
The resistor value should be chosen as
RC5061 Evaluation Board
-1
Fairchild provides an evaluation board to verify the system level performance of the RC5061. It serves as a guide to performance expectations when using the supplied external components and PCB layout. Please call the marketing department at 650-966-7624 for an evaluation board.
R = 10K*
Vout Vnom
For example, to get the VTT voltage to be 1.55V instead of 1.50V, use R = 10K * [(1.55/1.50) - 1] = 333.
15
RC5061
Additional Information
For additional information contact Fairchild Semiconductor's Analog & Mixed Signal Products Group Marketing Department at 650-966-7624.
Number of capacitors needed fo Cout = the greater of:
ESR * IO VT-
X=
Appendix
Worst-Case Formulae for the Calculation of Cout, R5, and Cin (Circuit of Figure 1 only)
The following formulae design the RC5061 for worst-case operation, including initial tolerance and temperature dependence of all of the IC parameters (initial setpoint, reference tolerance and tempco, active droop tolerance, current sensor gain), the initial tolerance and temperature dependence of the MOSFET, and the ESR of the capacitors. The following information must be provided: VT+, the value of the positive transient voltage limit; |VT-|, the absolute value of the negative transient voltage limit; IO, the maximum output current; Vnom, the nominal output voltage; Vin, the input voltage (typically 5V); ESR, the ESR of the ouput caps, per cap (44m for the Sanyo parts shown in this datsheet); RD, the on-resistance of the MOSFET (20m for the FDB6030); RD, the tolerance of the current sensor (usually about 67% for MOSFET sensing, including temperature). Irms, the rms current rating of the input caps (2A for the sanyo parts shown in this datasheet.)
2 IO * Cin = Irms IO* RD * (1 + RD) * 1.10 50 * 10
-6
or
ESR * IO VT+ -0.004 * Vnom + 14400 * IO * RD 18 * R5 * 1.1
Y=
Preliminary Specification
Example: Suppose that the transient limits are 134mV, current I is 14.2A, and the nominal voltage is 2.000V, using MOSFET current sensing and the usual caps. We have VT+ = |VT-| = 0.134, IO = 14.2, Vnom = 2.000, and RD = 0.67. We calculate:
2.000 14.2 * 5 Cin = 2
-
2.000 5
2
= 3.47 4 caps
R5 =
14.2 * 0.020 * (1 + 0.67) * 1.0 50 * 10-6 0.044 * 14.2 X= 0.134 0.044 * 14.2
= 10.4K
= 4.66
Y= 0.134 - 0.004 * 2.000 + 14400 * 14.2 * 0.020 18 * 10400 * 1.1
= 4.28
Since X > Y, we choose X, and round up to find we need 5 capacitors for COUT.
Vnom Vin
-
Vnom Vin
R5 =
16
RC5061
Mechanical Dimension
20-Lead SOIC
Symbol A A1 B C D E e H h L N ccc
Inches Min. Max.
Millimeters Min. Max.
Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
.093 .104 .004 .012 .013 .020 .009 .013 .496 .512 .291 .299 .050 BSC .394 .010 .016 20 0 -- 8 .004 .419 .029 .050
2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 12.60 13.00 7.40 7.60 1.27 BSC 10.00 0.25 0.40 20 0 -- 8 0.10 10.65 0.75 1.27
Preliminary Specification
3 6
20
11
E
H
1
10
D A e B A1 SEATING PLANE -C- LEAD COPLANARITY ccc C
h x 45 C
L
17
RC5061
Ordering Information
Product Number RC5061M Package 20 pin SOIC
Preliminary Specification
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
10/14/99 0.0m 001 Stock#DS30005051 (c) 1999 Fairchild Semiconductor Corporation
www.fairchildsemi.com
RC5102
Dual Adjustable Voltage Regulators
Features
* * * * * * * * * 0.5% Setpoint Accuracy Both outputs adjustable from 1.5V to 3.6V 100mA output drivers for high current loads Short circuit protection Fast transient response Low Icc current < 1mA Factory trimmed low TC voltage reference Drives N-Channel MOSFET, NPN or Darlington Pair 8 Lead SOIC
Description
The RC5102, in combination with low Rds,on n-channel MOSFETs, provides a precision low-dropout dual voltage regulator for Pentium, Cyrix(R) and Power PC(R) CPUs. By using the 12V supply available within the motherboard of the PC, the RC5102 achieves the high Vgs drive voltage to minimize the Rds, on of the MOSFET for low dropout applications. Earlier designs involving p-channel MOSFETs or pnp transistors are either too costly or provide inadequate drop-out voltages at the high current required. Using the RC5102, a linear conversion from 5V to 2.8V is achieved at load currents in excess of 7A, depending upon the pass element. The RC5102 incorporates a 50MHz operational amplifier in the control path, thus optimizing transient performance due to instantaneous load changes.. Wafer-level trimming is used to adjust the precision of the reference to a nominal accuracy of 0.5%. Improved line regulation is achieved through the use of a bootstrapped architecture within the bandgap reference. Overcurrent protection is available through the use of an external sense resistor.
Preliminary Information
Applications
* 3.3V, 2.8V dual power supply for Pentium(R) P55 Processor * Switchable single/dual power supply for Pentium P54C/P55C flexible motherboard implementation * 1.5V regulator for Pentium Pro GTL+ Bus * Adjustable dual output power supply for high current loads
Block Diagram
+5V +12V
VREF
- +
I
OVER CURRENT PROTECT
V1
- +
I V2
RC5102
65-5102-01
Rev. 0.9.1
PRELIMINARY INFORMATION describes products that are not in full production at the time of printing. Specifications are based on design goals and limited characterization. They may change without notice. Contact Fairchild Semiconductor for current information.
RC5102
PRODUCT SPECIFICATION
Pin Assignments
VSC VFB2 VCCP DRV2
1 2 3 4 8 7 6 5
65-5102-02
Pin Description
GND VFB1 VCC DRV1
Pin Name VSC VFB2 VCCP DRV2 DRV1 VCC VFB1 GND
Pin Number 1 2 3 4 5 6 7 8
Pin Function Description Over Current Protection Input Regulator 2 Voltage Feedback Output driver VCC; 12V nominal Regulator 2 Driver Output Regulator 1 Driver Output Analog VCC; 5V nominal Regulator 1 Voltage Feedback Ground
Preliminary Information
Absolute Maximum Ratings1
Parameter VCCP VCC TS Driver Supply Voltage Analog Supply Voltage Storage Temperature Soldering Temperature 10 Seconds -65 Conditions Min. Typ. Max. 13 13 150 300 Unit V V C C
Note: 1. Functional operation under any of these condition is not implied. Performance is guaranteed only if Operating Conditions are not exceeded.
Operating Conditions
(VCC = 5V, VCCP = +12V, TA = 25C unless otherwise noted) Parameter VCC VCCP TA Analog Supply Voltage Driver Supply Voltage Ambient Temperature Minimum VCC + 3V Conditions Min. 4.75 8 0 Typ. 5 12 Max. 10 13 70 Unit V V C
2
PRODUCT SPECIFICATION
RC5102
DC Electrical Characteristics
(VCC = 5V, VCCP = +12V, TA = 25C unless otherwise noted) Parameter Vo Io Vref Acc VTC LDR LIR1 LIR2 Vr Vsc Pd Output Voltage Output Drive Current Setpoint Accuracy Output Voltage TC Load Regulation 5V Line Regulation 12V Line Regulation Output Noise Short Circuit trip Power Dissipation Conditions TA = 0-70C Each output IL = 1mA, Vout = 1.5V 0 to 70 C 0.5A to 7A VCC = 5V 5%, IL = 3.5A VCCP = 12V 10%, IL = 3.5A 0.1 to 20KHz Rsense = 0.01W No Load Min. 1.5 100 0.5 -230 0.25 12 19 30 100 68 1.2 Typ. Max. 3.6 Unit V mA % mV/C %Vo mV/V mV/V mV
Preliminary Information
mV mW
AC Electrical Characteristics
(VCC = 5V, VCCP = +12V, TA = 25C unless otherwise noted) Parameter Tr PSRR Response Time Power Supply Rejection Ratio Conditions IL = 0.5A to 5.5A Min. Typ. 5 65 Max. Unit ms dB
Application Schematics
+5V VCC C6 0.1F +12V C7 10F C8 0.1F 5 6 7 8 4 3 2 1 C9 1200F R1 0.01 Q2 D44H11 3.3V V1 R2 1.8K R3 1.5K GND Q1 D44H11 R4 1.3K R5 1.5K 2.8V V2 C4 1200F
65-5102-03
RC5102
C2 1200F
Figure 1. RC5102 Dual Output, 4A Application Schematic
3
RC5102
PRODUCT SPECIFICATION
+5V VCC C6 0.1mF +12V C7 10mF C8 0.1mF 5 6 7 8 4 3 2 1 C9 1200mF R1 0.01 M1 2SK1388 R7 200 R2 C7 100pF 1.8K R3 1.5K GND M2 2SK1388 R6 200 C6 100pF 2.8V V2 R4 1.3K R5 1.5K C4 1200mF
65-5102-04
3.3V V1
RC5102
C2 1200mF
Preliminary Information
Figure 2. RC5102 Dual Output, 5A Application Schematic
+5V VCC C6 0.1mF +12V C7 10mF C8 0.1mF 5 4 6 3 7 RC5102 2 1 8 C9 1200mF
R1 0.01
Q2 D44H11 +1.5V V1 C2 1200mF
GND Q1 D44H11 C4 1200mF +1.5V V2
65-5102-05
Figure 3. RC5102 Application Schematic for Pentium Pro GTL+ Bus Termination
4
PRODUCT SPECIFICATION
RC5102
+5V VCC C6 0.1F +12V C7 10F C8 0.1F 5 6 7 8 4 3 2 1 C9 330F R1 0.01 R8 40 R7 7K C10 10nF Q3 2N2222 R9 200 R2 2.0K R3 2.3K GND Q1 D44H11 R4 1.3K R5 1.5K P54C = No Output P55C = 3.3V @ 3A V2 C4 1500F
65-5102-06
Q2 D44H11
P54C = 3.5V @ 10A P55C = 2.8V @ 6A V1
RC5102
OPEN: V1=2.8V CLOSED:V1=3.5V
J1
R3A 4.3K
C2 1500F
Preliminary Information
Figure 4. RC5102 Application Schematic for Pentium P54/P55C
Table 2. Components for P54C/P55C Application Circuit
Quantity 1 1 2 2 1 1 2 1 1 1 1 1 1 1 1 1 2 Reference C9 C7 C6, C8 Q1, Q2 Q3 R1 R5, R2 R3 R4 R7 R6 R8 R11 R12 R13 R14 C2, C4 Part 330 mF 1 mF 0.1 mF D44H11 2N2222 0.01 200 1.8 K 1.5 K 1.5 K 1.3 K 2.786 K 2K 300 K 100 K 20 K 1500 mF Description AVX Electrolytic Chip Cap Chip Ceramic Power NPN Transistor General Purpose NPN Transistor 1% Resistor 1% Resistor 1% Resistor 1% Resistor 0.1% Resistor 1% Resistor 1% Resistor 1% Resistor 5% Resistor 5% Resistor 5% Resistor Sanyo Electrolytic
5
RC5102
PRODUCT SPECIFICATION
Applications Information
Theory of Operation
The RC5102 is a dual output, low dropout voltage regulator controller intended for use in applications that require dual voltages at moderate to high output currents. Using external power transistors and precision trim resistors, a dual adjustable voltage regulator can be implemented. The choice of the component(s) will depend heavily upon the type of application. For load currents of up to 5A per output, the use of low-cost power NPN transistors is sufficient, as illustrated in figure 1. For applications requiring load currents greater than 5A, either an NPN darlington pair or an N-channel MOSFET is recommended due to the increased power throughput. Because the gate/base drive voltage is derived from the 12V input supply, the overall dropout voltage will depend only on the load current and either the Vce,sat of the NPN transistor or the Ron of the MOSFET. Therefore, very low dropout voltages can be achieved when the load currents are sufficiently low and a low Ron MOSFET or a low Vce,sat transistor is used. In applications using N-channel MOSFETs, the external R-C network should be implemented as illustrated in figure 2. Failure to include this circuitry can result in an unstable gate drive signal. The actual component values may vary depending upon the individual application.
Output Capacitors
For stability and output noise reduction, the use of output capacitors is required. The required amount of load capacitance will depend upon the actual load current; higher loads will require larger capacitors. Regardless, an absolute minimum of 1uF is required to maintain stability under all load conditions. It is not necessary to use expensive low ESR type capacitors here; standard aluminum electrolytics are generally sufficient and can actually provide increased stability over extremely low ESR type devices. If possible, solid tantalum capacitors should be used in applications where transient response is critical.
Current Sense resistor
Over current protection is implemented using an external current sense resistor between the 5V input and the VSC pin that feeds the collector/drain of the pass transistors. This resistor will need to carry currents in excess of the sum of the two loads in order to perform correctly. The RC5102 will begin to limit the output current to the load(s) by turning off the output driver when the voltage across the sense resistor exceeds the nominal 100mV threshold. When this happens, the output voltage will temporarily go out of regulation. As the voltage across the resistor increases, the switch will continue to turn off until the current limit value is reached. At this point, the RC5102 will continuously deliver the limit current at a reduced output voltage level. To insure that load transient conditions do not momentarily cause deregulation of the output voltage, a 20% margin in the limit voltage is recommended. Thus the current sense resistor should be determined by the relationship: R = 100mV/Ipeak , Where Ipeak = Imax * 1.2 Since the value of the sense resistor is generally in the 10mW region, care should be taken in the layout of the PCB. Trace resistance can contribute significant errors. The traces to the VCC and VSC pins of the RC5102 should be Kelvin connected to the outside pads of the sense resistor.
Preliminary Information
Minimum Load
The RC5102 regulator controller is specified over a finite load range. If the output current becomes too small, leakage currents will dominate and the output voltage(s) may drift out of regulation. Maintaining a minimum of 1mA load current on each output will assure that the load current will dominate any leakage currents over the operating temperature range.
Adjustable Output Voltage Design
The RC5102 allows each of the two outputs to be adjusted between the 1.5V reference voltage and 3.6V using two external precision resistors. In order to maintain the 1% output voltage accuracy, a minimum of 100uA should be fed back to the VFB1 and VFB2 pin to correctly bias the internal op-amp. For most applications, the sum value of the two resistors should not exceed approximately 35KW. For figures 1 and 2, the resistor values can be calculated using the following equations:
Dual Power Supply Application
Some CPU power applications such as the Intel Pentium(R) P55C will require separate voltages for the CPU core and I/O circuitry. The circuit illustrated in figure 2 addresses this requirement using a minimum of external components. In this configuration, both linear regulator outputs can be easily programmed between 1.5V and 3.6V to meet a variety of dual voltage requirements. For loads of 4A or lower, the power dissipation of the external MOSFET should not pose any thermal design problems if it is chosen wisely. For loads greater than 10W, an appropriate heatsink must be chosen to assure the pass transistor remains within its Safe Operating Area for the desired output current level.
R2 + R3 V 1 = V REF ae --------------------o e R3 o R4 + R5 V 2 = V REF ae --------------------o e R5 o
6
PRODUCT SPECIFICATION
RC5102
Auto Switching Single/Dual Power Supply for a Flexible Motherboard Design
A detailed analysis of the new Pentium-class processors reveals the requirement for an open-ended motherboard power supply design that can accomodate different CPUs in a single system. As an example, consider the Intel(R) P54C and P55C Pentium(R) processors. Although these two processors may occupy the same CPU socket, distinct differences exist in their power supply requirements. The present generation P54C uses a single supply for both the processor core and the I/O. For the higher performance devices, the supply voltage required is 3.5V 100mV (VRE s-specification). For the lower performance models, a 3.3V 5% supply is acceptable. For improved compatibility, Intel has now respecified its 3.3V standard CPUs for operation at the new 3.5V VRE level. The P55C multimedia upgrade processor, due to be released in the latter part of 1996, requires separate voltages for the core and I/O circuitry. The nominal core voltage is currently 2.8V 100mV, while the I/O supply remains at a nominal 3.3V. It is therefore desirable to implement a power supply design that will automatically detect the CPU model present and program each output voltage accordingly. The circuit in figure 4 directly addresses this requirement. The basic theory of this design is to provide an automatic switch between a single and a dual linear power supply depending upon which CPU occupies the socket. To ease the task of identifying the CPU, the P55C processor includes a single-bit identification pin VCC2DET, at location AL1, to distinguish itself from the standard Pentium(R) P54C processor. This pin is always bonded to ground on the P55C CPU, while it is an internal no connect on the P54C. Therefore, the user can easily identify which processor occupies the CPU socket by direct monitoring of this pin. The circuit in figure 4 uses the CPU identification pin to select either a single or a dual output as well as select the appropriate output voltage for the CPU core power island.
Because the I/O circuitry can always operate from a nominal 3.5V supply, output 1 is set at a fixed 3.5V output. The CPU core supply is thus switched between 2.8V and 3.5V using an external FET and the appropriate resistor values. Using this circuit configuration, both output s can source up to 5A. These current ranges will easily accomodate the standard Pentium(R) P54C and the P55C as well as other Pentium(R) compatible processors. For selected processors, the load currents required by each output will force the use of a MOSFET or Darlington pair as the pass elements. Using these higher-powered devices, the RC5102 can source up to 10A given the appropriate thermal requirements are also met. Please consult Fairchild Semiconductor Applications for additional details regarding CPU applications.
Current Sharing Option
If the RC5102 is to be used in an application that must address several CPUs, additional load current capability may be required from one of the outputs. For example, consider the Cyrix(R) 6x86 microprocessor. Although its specifications are very similar to those of the Intel Pentium(R) P54, it requires as much as 10A under worst-case conditions. To remedy this situation without adding additional costly pass elements, the RC5102 can be configured to allow both outputs to share the load current. In order to achieve acceptable performance, the layout of the output traces must be carefully routed. If the traces from the emitter of the pass transistors to the point where the two outputs are joined together, both outputs will share the load current equally. If the series impedances of each trace are different however, one output will tend to provide more than 50% of the load current while the other output will not be heavily burdened. Using this option, low cost NPN transistors may be used instead of MOSFETs to deliver up to 10A loads. Again, the overall power limitation will depend heavily upon the level of thermal management for the pass elements. Please consult Fairchild Semiconductor Applications for additional details on this and other possible configurations using the RC5102.
Preliminary Information
7
RC5102
PRODUCT SPECIFICATION
Notes:
Preliminary Information
8
PRODUCT SPECIFICATION
RC5102
Notes:
Preliminary Information
9
RC5102
PRODUCT SPECIFICATION
Notes:
Preliminary Information
10
PRODUCT SPECIFICATION
RC5102
Mechanical Dimensions - 8 Lead SOIC
Symbol A A1 B C D E e H h L N a ccc Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
.053 .069 .004 .010 .013 .020 .008 .010 .189 .197 .150 .158 .050 BSC .228 .010 .016 8 0 -- 8 .004 .244 .020 .050
1.35 1.75 0.10 0.25 0.33 0.51 0.20 0.25 4.80 5.00 3.81 4.01 1.27 BSC 5.79 0.25 0.40 8 0 -- 8 0.10 6.20 0.50 1.27
3 6
Preliminary Information
8
5
E
H
1
4
D A1 A SEATING PLANE B -C- LEAD COPLANARITY ccc C a
h x 45 C
e
L
11
PRODUCT SPECIFICATION
RC5102
Ordering Information
Product Number RC5102M Package 8 pin SOIC
Preliminary Information
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS30005102 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC5201
Chemistry Independent Intelligent Battery Charger
Features
* * * * * * * * * * * * * * * * * * * * * * * * Chemistry independent charging SMBusTM 2-wire serial interface controlled Single and dual battery systems 8 bit output voltage DAC 8 bit current DAC 4 bit power DAC 6A max charging current 19V max battery voltage 24V max input voltage 6V min input voltage 3.3V, 1% over temperature "keep alive" precision reference 5V keep-alive regulator controller onboard 100% maximum duty-cycle Synchronous rectification Voltage mode control System soft start protects during adapter hot plug-ins System current limit protection Output overvoltage crowbar protection Undervoltage (UVLO) shutdown Charger output soft start implemented digitally Input Isolation P-FET open with un-powered adapter Battery backfeed prevented Available in SSOP 24 package and TSSOP24 Optimized response for each control loop (current, voltage and power) * 90% efficiency for minimum heat dissipation * Power down driven by SMBus or by adapter not available * Controlled drive of discrete FETs minimizes switching power dissipation * Logic signal ACAV indicates presence of AC adapter (adjustable threshold) * Average current control * Remote sense input * Voltage feed forward
Advanced Information
Applications
* Notebooks' fast chargers * PDAs * Hand-held portable instruments
Description
The RC5201 is a smart battery charger IC controller for Li+ and Ni based battery chemistries. The charger (slave) together with the host controller and smart battery constitutes a smart battery system that communicates via the SMBus protocol, a two wire serial communication system. An innovative power control loop allows operation from line power and battery charging (with residual power) without exceeding the max input power programmed according to the AC adapter power rating.
Block Diagram
14 17 15 16 18 13 11 3 10 9 8 7 6 5
SSIN/ILIM
PSIN+
PSIN-
INISO
3.3V
IFB
HIDRV
LODRV
PSIN
BAT
VFB
DCIN
REF IthILIM
19
IthINISO
COMP
+ -
Vth
- +
DRV
SGND VTRIANG
5V
4
PSIN
PGND
20
12
ACAV
- + - +
P_DAC
V_DAC
Digital Soft Start I_OUT
I_DAC
- +
2
SM_BUS
SCL
1
SDA CompP
65-5201-03 21
CompV
22 23
CompI
NC
24
SMBus is a trademark of Intel Corporation
Rev. 0.5.7
ADVANCED INFORMATION describes products that are in the planning or early design stage. Specifications may change in any manner without notice. Contact Fairchild Semiconductor for current information.
www.fairchildsemi.com
RC5230
System Electronics Regulator for Mobile PC's
Features
* * * * * * * * * * Synchronous rectification High precision High efficiency Input and output voltage feedback 6V to 20V input voltage range 10% current limit precision TSSOP24 5V, 5V-Always, 12V and 3.3V outputs UVLO OVP
Description
The RC5230 is a high efficiency and high precision DC/DC controller for notebooks. Double voltage modeinput and output voltage feedback- allows for fast loop response over a wide range of input and output variations. This scheme also allows for minimum power dissipation as a small value for the sense resistor is selected to set current (as opposed to having to sense current over the entire current range as required in other schemes). The tightly controller current limit threshold allows for a tight design of magnetics and discrete transistors for minimum cost and space at maximum performance.
Target Specifications
Applications
* Notebook and PDA PC's * Hand-held portable instruments
Block Diagram
6-20V 1 Vin 3.3V 2 HSD3.3 3 LSD3.3 4 IFB3.3+ 5 VFB3.3- VSB3.3 COMP3.3 SS/ONOFF3.3 FPWM 5VALWAYS PGOOD 6 7 8 9 10 11 16 12 S D W N 13 P G N D S G N D 14 15 SS ON OFF 12 IFB5+ 22 21 I FB5RC 5230 VSB5 20 TSSOP24 COMP5 19 SS/ONOFF5 18 17 SW12 12 V HSD5 24 LSD5 23 5V
VFB12
S/DWN12
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RC5231
CPU Voltage Regulator for Mobile PC's
Features
* * * * * * * * * * Synchronous rectification High precision High efficiency Voltage mode 6V to 20V input voltage range 10% current limit precision TSSOP20 1.7V CPU and 1.8V CACHE UVLO OVP
Description
The RC5231 is a high efficiency and high precision DC/DC controller for notebooks. The tightly controller current limit threshold allows for a tight design of magnetics and discrete transistors for minimum cost and space at maximum performance.
Preliminary Information
Applications
* Notebook and PDA PC's * Hand-held portable instruments
Block Diagram
6-20V
ONOFF/SS
1
20 RC5231 TSSOP20 19 18 17 ONOFF/SS
Vccp =1.8V, 0.5A 2
16 15 14 3 13 12 11 10 8 9 FORCEPWM PGOOD
Vcc =1.7V, 6.9A
D0 D1 D2 D3
4 5 6 7
RC5231
PRODUCT SPECIFICATION
Pin Assignments
I/O SW node I/O voltage feedback (Vccp) I/O on/off1 D0 D1 D2 D3 Analog ground Power ground Power good 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Vin Vcc on/off Rsense Boost Hi side driver Vcc SW node Low side driver Voltage feedback (Vcc) Low side driver Forced PWM
Preliminary Information
Pin Description
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin Name I/O SW node I/O voltage feedback (Vccp) I/O on/off1 D0 D1 D2 D3 Analog ground Power ground Power good Forced PWM Low side driver Voltage feedback (Vcc) Low side driver Vcc SW node Hi side driver Boost Rsense Vcc on/off Vin
2
PRODUCT SPECIFICATION
RC5231
Absolute Maximum Ratings (Beyond which the device may be damaged)1
Parameter Vs Ambient Temperature, Ta Conditions Input Supply Voltage 0 Min. Typ. Max. 30 70 Units V Deg. C
Note: 1. Functional Operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded.
Operating Conditions (DCIN = 19VV, Ta = 0-70C unless otherwise specified)
Parameter Supply and Regulator Vs Input Supply Voltage Input Quiescent Current 5V regulator accuracy Operation Sleep 0 to 70 Deg. C -2 6 20 2 1 +2 V Conditions Min. Typ. Max. Units
Preliminary Information
mA A %
Note: 1. Functional Operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded.
Applications
Figure 1 below shows the system block diagram.
6-20V
ONOFF/SS
1
20 RC5231 TSSOP20 19 18 17 ONOFF/SS
Vccp =1.8V, 0.5A 2
16 15 14 3 13 12 11 10 8 9 FORCEPWM PGOOD
Vcc =1.7V, 6.9A
D0 D1 D2 D3
4 5 6 7
Figure 1
3
RC5231
PRODUCT SPECIFICATION
Notes:
Preliminary Information
4
PRODUCT SPECIFICATION
RC5231
Notes:
Preliminary Information
5
RC5231
PRODUCT SPECIFICATION
Notes:
Preliminary Information
6
PRODUCT SPECIFICATION
RC5231
Mechanical Dimensions
20 Lead TSSOP
Symbol A A1 A2 B C D E E1 e L N ccc Inches Min. -- .002 .031 .007 .004 .250 .240 .168 Max. .047 .006 .041 .012 .008 .257 .264 .176 Millimeters Min. -- 0.05 0.80 0.19 0.09 6.40 6.10 4.30 Max. 1.20 0.15 1.05 0.30 0.20 6.60 6.70 4.50 5 5 2, 4 Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E1" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5. "B" & "C" dimensions include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
.026 BSC .018 .029 20 0 -- 10 .004
0.65 BSC 0.45 0.75 20 0 -- 10 0.10
Preliminary Information
3 6
D
E1 E
A2 A1 SEATING PLANE -C- LEAD COPLANARITY ccc C L C
A B e
7
RC5231
PRODUCT SPECIFICATION
Preliminary Information
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com 1/20/99 0.0m 002 Stock#DS30005231 (c) 1998 Fairchild Semiconductor Corporation
www.fairchildsemi.com
RC5501
4 Watt Stereo Sound Driver
Features
* * * * * Up to 4W/channel Drives 8W and 4W non-powered speakers NO-POP during power-up/power-down and mute Internal thermal limiting circuitry Total Harmonic Distortion < 0.1%
Applications
* Multimedia PC motherboards and add-in sound cards * Companion chip to sigma-delta sound codecs * Sound Channel back-end in set-top boxes
Preliminary Information
Description
The RC5501 is a stereo power amplifier used for directly powering speaker and headphone sets.
Block Diagram
RC5501
SPKMUTE SPKAMPINR Soft Start Thermal Logic SPKAMPINL -4 SFTSTART SPKOUTL -4 SPKOUTR
65-5501-01
Rev. 0.9.1
PRELIMINARY INFORMATION describes products that are not in full production at the time of printing. Specifications are based on design goals and limited characterization. They may change without notice. Contact Fairchild Semiconductor for current information.
PRODUCT SPECIFICATION
RC5501
Functional Description
The RC5501 stereo sound driver is an audio device that can be used on PC motherboards and add-in sound cards. It consists of stereo output drivers for headphone or speakers with a mute feature and circuitry that eliminates popping at power on, power off, mute enable, and mute disable. The output drivers can deliver up to 2 Watts peak and 4 Watts peak into 8W and 4W speakers, respectively, from a 12V source. The drivers use class AB amplifiers and maintain a low bias current. To help prevent turn-on speaker pop, a delay is provided to these output drivers to allow settling before speaker activation. The time constant is user-defined through an external capacitor (CDELAY) on the SFTSTART pin. The thermal limiting circuitry activates if the chip temperature typically exceeds 150C.
Pin Assignments
Preliminary Information
RC5501 PGNDL SPKOUTL VCCL SPKRMUTE SPKAMPINL VCC N/C
1 2 3 4 5 6 7 14 13 12 11 10 9 8
65-5501-02
PGNDR SPKOUTR SFTSTART VCCR SPKAMPINR N/C GND
Pin Definitions
Pin Name PGNDL SPKOUTL VCCL SPKRMUTE SPKAMPINL VCC N/C GND SPKAMPINR VCCR SFTSTART SPKOUTR PGNDR Pin Number 1 2 3 4 5 6 7, 9 8 10 11 12 13 14 Pin Function Description Left speaker ground. Left speaker output. Left speaker 12V power supply. Speaker mute. Left channel power amp input. 12V power supply input. No connection. Ground. Right channel power amp input. Right speaker 12V power supply. Soft start timing capacitor. Right speaker output. Right speaker ground.
2
RC5501
PRODUCT SPECIFICATION
Absolute Maximum Ratings
(beyond which the device may be damaged)1 Parameter VCC Power supply voltage VCCR VCCL Min Typ Max 13.2 Units V
Note: 1. Functional operation under any of these conditions is NOT implied. Performance is guaranteed only if Operating Conditions are not exceeded.
Operating Conditions
Parameter VCC VCCL VCCR VIH VIL Tc Itotal
ESD
Conditions Power Supply
Min 11.2
Typ 12
Max 12.8
Units V
Preliminary Information
Input Voltage Logic High Input Voltage Logic Low Ambient Temperature Maximum Operation Die Temperature Power Supply Current ESD Threshold Overthermal Protection No load Human Body Model
2 0.8 0 150 19 2000 25 70
V V C C mA V
Electrical Characteristics
VCC = VCCL = VCCR = 12V 6%, unless otherwise specified. Parameter Speaker Driver Zin Av L&R Av Vo SNR Po CS THD Noise PSRR Soft Start Delay Anti-Pop Ramp-Up and Ramp-Down time No Pop condition CDELAY = 22mF on SFTSTART 2 sec Input Impedance Voltage Gain Left and Right Gain Matching Output Voltage Signal to Noise Ratio Power Output Per Channel Peak Channel Separation L/R Input Referenced Total Harmonic Distortion Vin = 0.5 Vrms Vout = 4VP-P RL = 4W or 8W, VCC = 12V Input Referenced RL = 4W, VCC = 12V (See Figure 1) Vin = 0.5 Vrms fo = 1KHz, Po = 50mW 20Hz to 20kHz, A-Weighted Power Supply Rejection Ratio f = 100Hz, DVcc = 1.6Vp-p Input Referenced 70 66 0.1 4 80 Conditions Min 100 -3.80 -4.0 0.5 4 85 4 -4.20 Typ Max Units KW V/V % V dB W dB % mVrms dB f = 1KHz, RL = 8W unless otherwise specified
3
PRODUCT SPECIFICATION
RC5501
Applications Discussion
+12V Regulated Input
+ C5 1000F/16V
RC5501
Preliminary Information
PGNDL Left Speaker Output C10 + 470F/16V SPKOUTL VCCL TTL Input Speaker Mute Left Speaker Amp Input SPKRMUTE C6 + 10F/16V SPKAMPINL VCC N/C
PGNDR SPKOUTR SFTSTART VCCR SPKAMPINR N/C GND
65-5501-03
C8 + 470F/16V
Right Speaker Output
C7 + 10F/16V
Right Speaker Amp Input
+ C9 22F/16V
Notes: 1. 4 watt power represents the peak of the audio level and cannot be sustained without correct package thermal considerations. The average audio signal can be sustained by the RC5501 without extra thermal considerations. 2. To improve the thermal resistance of the PDIP package, a heat sink can be used. Figure 1. 4 Ohm Speaker, 4 Watt Application or 8 Ohm Speaker, 2 Watt application
4
RC5501
PRODUCT SPECIFICATION
Notes:
Preliminary Information
5
PRODUCT SPECIFICATION
RC5501
Notes:
Preliminary Information
6
RC5501
PRODUCT SPECIFICATION
Mechanical Dimensions
14 Lead Plastic DIP Package
Inches Min. A A1 A2 B B1 C D D1 E E1 e eB L N -- .015 .115 Max. .210 -- .195 Millimeters Min. -- .38 2.93 Max. 5.33 -- 4.95 Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E1" do not include mold flashing. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. Terminal numbers are shown for reference only. 4. "C" dimension does not include solder finish thickness. 5. Symbol "N" is the maximum number of terminals. 4 2
Symbol
.014 .022 .045 .070 .008 .015 .725 .795 .005 -- .300 .325 .240 .280 .100 BSC -- .430 .115 .200 14
.36 .56 1.14 1.78 .20 .38 18.42 20.19 .13 -- 7.62 8.26 6.10 7.11 2.54 BSC -- 10.92 2.92 5.08 14
Preliminary Information
2
5
D 7 1
E1
D1
8
14
E e A A1 L B1 B eB C
7
PRODUCT SPECIFICATION
RC5501
Ordering Information
Product Number RC5501N Package 14 PDIP
Preliminary Information
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS30005501 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC5502
Dual High Power Audio Amplifier
Features
* * * * * * * 3W/channel into an 8 ohm speaker with VCC=12V No pop during power-up and power-down Speaker mute control pin Internal thermal limiting circuitry User definable gain Self-centering output bias voltage Total Harmonic Distortion < 0.1%
Preliminary Information
Description:
The RC5502 is a stereo audio amplifier for use in directly driving non-powered speakers. The RC5502 amplifier can provide up to 3 watts of peak power into an 8 ohm speaker load from a 12 volt supply. The gain of the RC5502 is user defined by the selection of the appropriate feedback resistors. The RC5502 has internal circuitry for the prevention of "popping" with power-up/power-down and internal thermal limiting circuitry.
Block Diagram
RC5502
INNR - + Soft Start Thermal Logic Mute INNL - + -A SFTSTART CBYPASS (Optional) MUTE CBOOTL OUTL CBOOTR -A OUTR
65-5502-01
Rev. 0.9.3
PRELIMINARY INFORMATION describes products that are not in full production at the time of printing. Specifications are based on design goals and limited characterization. They may change without notice. Contact Fairchild Semiconductor for current information.
RC5502
PRODUCT SPECIFICATION
Functional Description:
The RC5502 stereo sound amplifier is an audio device that can be used on PC motherboards and add-in sound cards. It consists of stereo output amplifiers which can drive 4 and 8 ohm speakers without popping during power-up/powerdown, a mute control pin for disabling the power amplifiers and internal thermal limiting circuitry. The power amplifiers can deliver 3 watts per channel of peak power to an 8 ohm speaker with a 12 volt power supply. This is accomplished by using an external boot strap capacitor to raise the internal base voltage of the output transistor. In this application, the output voltage can swing 5 volts into an 8 ohm speaker load with only a 12 volt supply. The user defines the amplifier gain so the output power level can be optimized based on the input signal level. To prevent turn-on speaker pop, a time delay is provided to the power amplifiers during power-up to allow the output voltage to settle before the amplifiers are activated. This time constant is user defined through an external capacitor on the SFTSTART pin. The positive (+) input signals for both amplifiers are internally biased at approximately 6.2 volts and this sets the "AC ground" reference level for the amplifiers. This reference signal is connected to pin 10. This signal is internally generated, however, an external bypass capacitor can be connected to this pin to improve the L/R channel cross talk. The internal thermal limiting circuitry activates if the chip temperature typically exceeds 150C.
Preliminary Information
Pin Assignments
RC5502 PGNDL OUTL VCCL MUTE INNL CBOOTL VCC GND
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
65-5502-02
PGNDR OUTR SFTSTART VCCR INNR CBOOTR CBYPASS N/C
Pin Definitions
Pin Name PGNDL OUTL VCCL MUTE INNL CBOOTL VCC GND NC CBYPASS CBOOTR INNR VCCR SFTSTART OUTR PGNDR Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Function Description Left Amplifier ground. Left Amplifier output. Left Amplifier 12V power supply. Amplifier mute. (L=Disable, H=Enable) Left Amplifier IN. Left Amplifier VBoot Capacitor. 12V power supply. Ground. No Connection. Bypass Capacitor. (optional) Right Amplifier VBoot Capacitor. Right Amplifier IN. Right Amplifier 12V Power Supply Soft Start Timing Capacitor Right Amplifier Output. Right speaker ground.
2
PRODUCT SPECIFICATION
RC5502
Absolute Maximum Ratings
(beyond which the device may be damaged)1 Parameter VCC Power supply voltage VCCR VCCL Min Typ Max 13.2 Units V
Note: 1. Functional operation under any of these conditions is NOT implied. Performance is guaranteed only if Operating Conditions are not exceeded.
Operating Conditions
Parameter VCC VCCL VCCR VIH VIL Tc Itotal
ESD
Conditions Power Supply
Min 11.2
Typ 12
Max 12.8
Units V
Preliminary Information
Input Voltage Logic High Input Voltage Logic Low Ambient Temperature Maximum Operation Die Temperature Power Supply Current ESD Threshold Overthermal Protection No load Human Body Model
2 0.8 0 150 19 2000 25 70
V V C C mA V
Electrical Characteristics
VCC = VCCL = VCCR = 12V 6%, unless otherwise specified. Parameter Zin Vo SNR Po CS THD Noise PSRR Soft Start Delay Anti-Pop Ramp-Up and Ramp-Down time No Pop condition CDELAY = 22mF on SFTSTART 2 sec Input Impedance Output Voltage Signal to Noise Ratio Power Output Per Channel Peak Channel Separation L/R Input Referenced Total Harmonic Distortion RL = 8W, VCC = 12V Input Referenced RL = 8W, VCC = 12V (See Figure 1) Vin = 0.5 Vrms fo = 1KHz, Po = 50mW 20Hz to 20kHz, A-Weighted Power Supply Rejection Ratio f = 100Hz, DVcc = 1.6Vp-p Input Referenced 70 66 0.1 4 80 Conditions Min 100 5 85 3 Typ Max Units KW V dB W dB % mVrms dB
f = 1KHz, RL = 8W unless otherwise specified
3
RC5502
PRODUCT SPECIFICATION
Applications Discussion
+12V Regulated Input
+ C5 1000F/16V
RC5502
PGNDL PGNDR OUTR SFTSTART RFR 10F RINL VCC CBOOTL CBOOTR GND *CBYPASS
65-5501-03
Preliminary Information
Left Speaker + Output 470F/16V RFL TTL Input Speaker Mute C6 Left Speaker + Amp Input 10F/16V
C10
OUTL VCCL MUTE INNL
C8 + 470F/16V
Right Speaker Output
VCCR INNR RINR 10F C7 + 10F/16V Right Speaker Amp Input
+ C9 22F/16V 1F Optional
Notes: The gain for each amplifier is user defined and is calculated as follows: A = -Rf/Rin with typical values for Rf = 100K. *Cbypass is optional. An external 1mF bypass capacitor will typically improve the L/R channel cross talk by 20dB. Figure 1
4
PRODUCT SPECIFICATION
RC5502
Notes:
Preliminary Information
5
RC5502
PRODUCT SPECIFICATION
Notes:
Preliminary Information
6
PRODUCT SPECIFICATION
RC5502
Mechanical Dimensions
16 Lead Plastic DIP Package
Symbol A A1 A2 B B1 C D D1 E E1 e eB L N Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E1" do not include mold flashing. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. Terminal numbers are shown for reference only. 4. "C" dimension does not include solder finish thickness. 5. Symbol "N" is the maximum number of terminals. 4 2
-- .210 .015 -- .115 .195 .014 .022 .045 .070 .008 .015 .745 .840 .005 -- .300 .325 .240 .280 .100 BSC -- .430 .115 .160 16
-- 5.33 .38 -- 2.93 4.95 .36 .56 1.14 1.78 .20 .38 18.92 21.33 .13 -- 7.62 8.26 6.10 7.11 2.54 BSC -- 10.92 2.92 4.06 16
Preliminary Information
2
5
D 8 1
E1
D1
9
16
E e A A1 L B1 B eB A2 C
7
PRODUCT SPECIFICATION
RC5502
Ordering Information
Product Number RC5502N Package 16 PDIP
Preliminary Information
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonable expected to result in a significant injury of the user.
Fairchild Semiconductor Corporation Americas Customer Response Center Tel:1-888-522-5372 Fairchild Semiconductor Europe Fax: Email: Deutsch Tel: English Tel: Italy Tel: +49 (0) 1 80-530 85 86 europe.support@nsc.com +49 (0) 8 141-35-0 +44 (0) 1 793-85-68-56 +39 (0) 2 57 5631
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
Fairchild Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Center, 5 Canto Rd. Tsimshatsui, Kowloon Hong Kong Tel:+852 2737-7200 Fax:+852 2314-0061
National Semiconductor Japan Ltd. Tel:81-3-5620-6175 Fax:81-3-5620-6179
www.fairchildsemi.com 2/98 0.0m Stock#DS30005502 O 1998 Fairchild Semiconductor Corporation
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RC5512
RAPPERTM Family - 4 Watt Stereo Sound Driver
Features
* * * * * * * * * * * Up to 4W/channel Drives 8W and 4W non-powered speakers NO-POP: during power-up/power-down and mute control Individual control pins to select mute and on/off for headphone, speaker, microphone, and regulator block Provides regulated 5V supply for sound codec, etc. Line output signal-to-noise ratio of 85dB Sleep mode supply current typically 10mA Microphone multiplexing Total harmonic distortion <0.1% Microphone amplifier with AGC 40dB dynamic range Internal Thermal Limiting Circuitry
Description
The RC5512 can be used for driving key functions that are needed in all multimedia PCs and sound cards. These functions include directly powering speakers and headphone sets, providing a microphone pre-amplifier with AGC, and having a 12V to 5V regulator that can isolate the noise from the sound channel. Each function can be controlled individually, thus providing power saving features.
Applications
* * * * Multimedia PC motherboards and add-in sound cards Portable multimedia personal computers Companion chip to Sigma-Delta Sound Codecs Sound Channel back-end in Set-top boxes
Block Diagram
SPKMUTE SPKPD -4 RIN +1 Soft Start Thermal Logic -4 5V Mic Supply +1 LLINE RLINE VCCDROPL VCCDROPR SPKOUTR
SFTSTART SPKOUTL
LIN
+1
MICPD MICIN1 MICIN2
VCC
MUX
*
-10 12 to 5V Regulator
MICOUT REGOUT
AGC
REGPD REGSEN
65-5512-01
RC5512
MICSEL AGCTC
Rev. 1.0.0
RC5512
PRODUCT SPECIFICATION
Functional Description
The Rapper Stereo Sound Driver is an audio device that can be used on PC motherboards and add-in sound cards. It consists of stereo output drivers for headphone or speakers, a low noise microphone amplifier with AGC, and a regulator to provide a clean 5V supply. The RC5512 has two microphone inputs which are user selectable. Each section can be individually put into a shut-down mode and muted by pulling the appropriate pin low. The output drivers can deliver up to 2 watts peak and 4 watts peak into 8W and 4W speakers, respectively, from a 12V source. The drivers use class AB amplifiers and maintain a low bias current. The power-down function is designed to save power and to turn on/off the driver without generating popping signals. To prevent popping signals, when the circuit is activated, a delay is provided to these output drivers. These drivers become active only after their outputs have settled. The time constant is user-defined through an external capacitor (CDELAY) on the SFTSTART pin. The microphone amplifier feeds into an AGC with a dynamic range of 40dB. An external capacitor is used to provide attack and decay features. Attack and decay times can be varied linearly by varying an external capacitor (CAD) on the AGCTC pin. The attack and decay time ratio has been set for pleasant audio quality. The 12 V to 5V voltage regulator can provide up to 20mA of current without external components. It can provide a noisefree regulated voltage supply to the other devices that complete the sound channel. Use of an external transistor can boost the regulator output to 150mA or higher with the appropriate thermal precautions. The line regulation of 50dB improves the cross talk and the power supply rejection ratio of all other audio blocks that are supplied by the 5V source. The thermal limiting circuitry activates if the chip temperature typically exceeds 150C.
Pin Assignments
SPKMUTE
26
REGOUT
REGSEN
28
REGPD GNDREG SPKPD GNDMIC MICPD MICSEL AGCTC
27
4
3
2
1
LLINE
VCCL
VCC
LIN
5 6 7 8 9 10 11 12 13 14 15 16 17 18
25 24 23
VCCDROPL SPKOUTL GNDSPKL GNDSPKR SPKOUTR SFTSTART VCCDROPR
RC5512
22 21 20 19
GNDMIC
MICOUT
MICIN1
MICIN2
RLINE
RIN
VCCR
65-5512-02
2
PRODUCT SPECIFICATION
RC5512
Pin Definitions
Pin Name LIN REGSEN REGOUT VCC REGPD GNDREG SPKPD GNDMIC MICPD MICSEL AGCTC MICIN1 MICIN2 RIN MICOUT VCCR RLINE VCCDROPR SFTSTART SPKOUTR GNDSPKR GNDSPKL SPKOUTL VCCDROPL SPKMUTE LLINE VCCL Pin Number 1 2 3 4 5 6 7 8, 15 9 10 11 12 13 14 16 17 18 19 20 21 22 23 24 25 26 27 28 Description Left Channel Input. Regulator Sense Point. Regulator 5V Output. 12V Power Supply Input. Regulator Power-Down. Regulator Ground. Speaker and Line Driver Power-Down. Microphone Ground. Microphone Power-Down. Microphone Output Select. LOW selects MICIN1, HIGH selects MICIN2. Attack and Decay Capacitor Pin. Microphone Input 1. Microphone Input 2. Right Channel Input. Microphone Output. Right Speaker Supply. Right Line Driver Output. Right Speaker Power Drop Supply. Soft Start Timing Capacitor. Right Speaker Output. Right Speaker Ground. Left Speaker Ground. Left Speaker Output. Left Speaker Power Drop Supply. Speaker Mute. Left Line Driver Output. Left Speaker Supply.
3
RC5512
PRODUCT SPECIFICATION
Absolute Maximum Ratings1
(beyond which the device may be damaged) Parameter VCC Power supply voltage Min. Typ. Max. 13.2 Units V
Note: 1. Functional operation under any of these conditions is NOT implied. Performance is guaranteed only if Operating Conditions are not exceeded.
Operating Conditions
Parameter VCC VCCR VCCL VCCDROPR VCCDROPL VIH VIL Tc Itotal ISD
ESD
Conditions Power Supply
Min. 11.2
Typ. 12
Max. 12.8
Units V
Right and Left Power Drop Supplies Input Voltage Logic High Input Voltage Logic Low Ambient Temperature Maximum Operation Die Temperature Power Supply Current Shut-Down Current ESD Threshold
RDROP = 2W (See Figure 1)
11.2 2
12
12.8
V V
0.8 0 Overthermal Protection No load SPKPD, MICPD, REGPD 0.4V Human Body Model 2000 150 19 10 25 75 70
V C C mA mA V
Electrical Characteristics
VCC = 12V 6%, unless otherwise specified. Parameter Line Driver
Zin
Conditions Input Impedance Voltage Gain Left and Right Gain Matching Output Voltage Total Harmonic Distortion Signal-to-Noise Ratio Speaker Driver and Line Driver Supply Current Input Impedance Voltage Gain Left and Right Gain Matching Output Voltage VIN = 0.5 Vrms VOUT = 4VP-P RL = 4 W or 8W, VCC = 12V VIN = 0.5 Vrms VOUT = 4VP-P RL = 600W VOUT = 4VP-P
Min.
Typ. 10
Max.
Units KW
f = 1KHz,RL = 600W unless otherwise specified 0.95 1.0 0.3 4 0.01 80 86 85 9 100 -3.8 -4.0 0.5 4 -4.2 1.05 V/V % V % dB dB
mA
Av L&R Av Vo THD PSRR SNR Ispk Zin Av L&R Av Vo
Power Supply Rejection Ratio f = 100Hz, DVcc = 0.85Vrms VIN = 2.8Vrms VIN = 0V
Speaker Driver
f = 1KHz, RL = 8W unless otherwise specified
KW V/V % VpK
4
PRODUCT SPECIFICATION
RC5512
Electrical Characteristics (continued)
VCC = 12V 6%, unless otherwise specified. Parameter SNR Po CS XTALK XTALK THD Noise PSRR Signal-to-Noise Ratio Power Output Per Channel Peak Channel Separation L/R Input Referenced Cross Talk L/R to Mic Input Referenced Cross Talk L/R to Reg Input Referenced Total Harmonic Distortion Conditions VIN = 2.8Vrms RL = 4W, VCC = 12V VIN = 0.5 Vrms VIN = 0.5 Vrms VIN = 0.5 Vrms fo = 1KHz, Po = 50mW 20Hz - 20KHz, A-Weighted Power Supply Rejection Ratio f = 100Hz, DVCC = 1.6Vp-p Input Referenced Microphone Amp Supply Current First Amp Input Impedance First Amp Gain Second Amp Gain AGC Dynamic Range Total Harmonic Distortion XTALK from other blocks at MICOUT Input Referenced Voltage Regulator Supply Current Regulator Voltage Tempco Line Regulation Load Regulation Io Output Current Source Source With External 2N2222 Sink Soft Start Delay Anti-Pop Ramp-Up and Ramp-Down time No Pop condition CDELAY = 22mF on SFTSTART 2 sec 4.75 Vin = 5mVP-P, AGC off 20Hz - 20KHz, A-Weighted VIN = 1Vrms at 1KHz f = 100Hz, DVCC = 1.6Vp-p 70 70 1.5 5 0.5 3 2 20 150 100 5.25 VIN = 0V, max gain 70 66 90 75 0.1 4 80 Min. Typ. 85 4 Max. Units dB W dB dB dB % mVrms dB
Microphone Amplifier Imicamp Zin1 Av1 Av2 AGC THD Noise XTALK PSRR Ireg Vreg Tc
f = 1KHz,RL = 10KW unless otherwise specified 4 4.5 1 -10 40 0.1 8 mA KW V/V V/V dB % mVrms dB dB mA V mV/C mV/V mV/mA mA mA mA
Voltage Regulator
5
RC5512
PRODUCT SPECIFICATION
Power-Down Function Table
L = VIL 0.8V, H = VIH 2.0V, X = Don't Care SPKPD L H H L H H MICPD L H L H L H REGPD L H L H H L SPKMUTE X H L X H H Chip Disabled All Sections Enabled Line Driver Enabled, Regulator and Microphone Disabled, Speaker Muted Line Driver and Speaker Disabled, Regulator and Microphone Enabled Microphone Only Disabled Regulator Only Disabled Function
Applications Discussion
12V VCCL LLINE SPKMUTE RDROP = 21/2 0.5W REGIN REGPD GNDREG SPKPD GNDMIC MICPD MICSEL CAD = 1F AGCTC 10F/16V + 10F/16V + 10F/16V + MICIN1 MICIN2 RIN RLINE VCCR 0.47F MICOUT GNDMIC 470F VCCDROPL SPKOUTL GNDSPKL GNDSPKR SPKOUTR SFTSTART VCCDROPR RDROP = 21/2 0.5W + 100F/16V 470F/16V + + CDELAY = 22F/10V 470F/16V + 100F/16V +
10F/16V +
RC5512
LIN REGSEN
2N2222
REGOUT
65-5512-03
Notes: 1. 4 Watt power represents the peak of the audio level and cannot be sustained without correct package thermal considerations. The average audio signal can be sustained by the RC5512 without extra thermal considerations. 2. To improve the thermal resistance of the PLCC 28 package, a heat sink can be used. One possible vendor is: AAVID, P/N CLC12059501. Figure 1. RapperTM RC5512, 4 Ohm Speaker, 4 Watt Application with External Pass Transistor for Voltage Regulator.
6
PRODUCT SPECIFICATION
RC5512
Portable PC Application
Figure 2 shows an application of the RC5512 for portable PCs when a high current, regulated 12 volts is not available. Because the portable PC's battery voltage can exceed the VCC maximum specification of the RC5512, a low drop out linear regulator with power down has been included. The linear regualtor provides 12 volts of regulation even if the battery voltage exceeds 20 volts. In addition, the low drop out regulator allows good sound quality even when the battery voltage drops to 9 volts. The low power down current bias of the regulator minimizes the battery current drain when the RC5512 is in a sleep mode. Alternatively, if a regulated 12 volt supply is available with a minimum current output of 300mA and sufficient by-pass capacitance, no additional regulation is required.
U2 MIC29201 ERROR INPUT GROUND OUTPUT SHUTDWN
TTL Input/Shutdown
+
12345 VBAT
C5 1000F 16V
1 R3 1K Q1 2N2222 2 + C3 100F 16V Left Line Output
Star Ground Left Line Driver Input C13 0.1F
C1 16V 10F +
+5V Regulated Output TTL Input Speaker Power-Down C10 REGOUT REGSEN SPKMT LLINE LIN VCCL 2 R2 21/2/0.5W 1
VCC
0.1 F 25 24 23 22 21 20 19 C9 0.1F +
TTL Input Regulator Power-Down TTL Input Line Out Power-Down TTL Input Microphone Power-Down TTL Input Mic In Select + C6 1F 16V Microphone Ground
5 6 7 8 9 10 11
REGPD GNDREG SPKPD GNDMIC MICPD MICSEL AGCTC GNDMIC MICOUT MICIN1 MICIN2 VCCR
VCCDROPL SPKLOUTL GNDSPKL
+
C7 470F 16V
Left Speaker Output Left Speaker Output Ground
RC5512
GNDSPKR SPKOUTR SFTSTSRT VCCDROPR RLINE
+ C11 16V 22F
Right Speaker Output Ground C8 Right Speaker 16V 470F Output
12 13 14 15 16 17 18
RIN
2 R2 21/2/0.5W 1 + C4 100F 16V
Right Line Output
Microphone Input 1 Microphone Input 2 Right Line Driver Input C15 16V 10F
C14 16V 10F +
+
C12 0.1F 16V + Microphone Output
65-5512-04
C2 16V 10F
Figure 2. RC5512 Portable PC Application.
7
RC5512
PRODUCT SPECIFICATION
Notes:
8
PRODUCT SPECIFICATION
RC5512
Notes:
9
RC5512
PRODUCT SPECIFICATION
Notes:
10
PRODUCT SPECIFICATION
RC5512
Mechanical Dimensions - 28 Lead PLCC Package
Symbol A A1 A2 B B1 D/E D1/E1 D3/E3 e J ND/NE N ccc Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. All dimensions and tolerances conform to ANSI Y14.5M-1982 2. Corner and edge chamfer (J) = 45 3. Dimension D1 and E1 do not include mold protrusion. Allowable protrusion is .101" (.25mm)
.165 .180 .090 .120 .020 -- .013 .021 .026 .032 .485 .495 .450 .456 .300 BSC .050 BSC .042 .048 7 28 -- .004
4.19 4.57 2.29 3.05 .51 -- .33 .53 .66 .81 12.32 12.57 11.43 11.58 7.62 BSC 1.27 BSC 1.07 1.22 7 28 -- 0.10
3
2
E E1 J
D
D1
D3/E3
B1 e J
A A1 A2 B -C- LEAD COPLANARITY
ccc C
11
PRODUCT SPECIFICATION
RC5512
Ordering Information
Product Number RC5512V Package 28 PLCC
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS30005512 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC5513
RAPPERTM Family - 4 Watt Stereo Sound Driver
Features
* * * * * * * * * * Up to 4W/channel Drives 8W and 4W non-powered speakers NO-POP during power-up/power-down and mute Provides regulated 5V supply for sound codec, etc. Line Output signal to noise ratio of 85 dB Microphone amplifier and AGC dynamic range of 40dB Microphone multiplexing Internal thermal limiting circuitry 24 Lead SOIC package Total Harmonic Distortion < 0.1%
Applications
* Multimedia PC motherboards and add-in sound cards * Companion chip to Sigma-Delta Sound Codecs * Sound Channel back-end in Set-top boxes
Description
The Rapper is a stereo sound driver used for driving key functions that are needed in all multimedia PCs and sound cards. These functions include directly powering speakers and headphone sets, providing a microphone pre-amplifier with AGC, and having a 12V to 5V regulator that can isolate the noise from the sound channel.
Block Diagram
RLINE LLINE SPKAMPINR SPKAMPINL -4 +1 Soft Start Thermal Logic -4 5V Mic Supply VCC MICIN1 MICIN2 MUX +1 SPKOUTR
RC5513 RAPPERTM
SPKMUTE RIN
SFTSTART SPKOUTL
LIN
+1
*
-10 12 to 5V Regulator
MICOUT REGOUT REGSEN
AGC
MICSEL
AGCTC
65-5513-01
Rev. 0.9.4
RC5513
PRODUCT SPECIFICATION
Functional Description
The Rapper Stereo Sound Driver is an audio device that can be used on PC motherboards and add-in sound cards. It consists of stereo output drivers for headphone or speakers, a low noise microphone amplifier with AGC, and a regulator to provide a clean 5V supply. The output drivers can deliver up to 2 Watts peak and 4 Watts peak into 8W and 4W speakers, respectively, from a 12V source. The drivers use class AB amplifiers and maintain a low bias current. To help prevent popping signals a delay is provided to these output drivers to allow settling. The time constant is user-defined through an external capacitor (CDELAY) on the SFTSTART pin. The microphone amplifier feeds into an AGC with a dynamic range of 40dB. An external capacitor is used to provide attack and decay features. Attack and decay times can be varied linearly by varying an external capacitor (CAD) on the AGCTC pin. The attack and decay time ratio has been set for pleasant audio quality. The 12 V to 5V voltage regulator can provide up to 20mA of current without external components. It can provide a clean regulated voltage supply to the other devices that complete the sound channel. Use of an external transistor can boost the regulator output to 150mA or higher with the appropriate thermal precautions. The line regulation of 50dB improves the cross talk and the power supply rejection ratio of all other audio blocks that are supplied by the 5V source. The thermal limiting circuitry activates if the chip temperature typically exceeds 150C.
Pin Assignments
LIN REGSEN REGOUT VCC GNDREG GNDMIC MICSEL AGCTC MICIN1 MICIN2 RIN MICOUT
1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13
65-5513-02
RC5513
SPKAMPINL LLINE SPKMUTE VCCL SPKOUTL GNDSPKL GNDSPKR SPKOUTR SFTSTART VCCR RLINE SPKAMPINR
2
PRODUCT SPECIFICATION
RC5513
Pin Definitions
Pin Name LIN REGSEN REGOUT VCC GNDREG GNDMIC MICSEL AGCTC MICIN1 MICIN2 RIN MICOUT SPKAMPINR RLINE VCCR SFTSTART SPKOUTR GNDSPKR GNDSPKL SPKOUTL VCCL SPKMUTE LLINE SPKAMPINL Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Pin Function Description Left Channel Input Regulator Sense Point Regulator 5V Output 12V Power Supply Input Regulator Ground Microphone Ground MICOUT Select. LOW selects MICIN1, HIGH selects MICIN2 Attack and Decay Capacitor Pin Microphone Input 1 Microphone Input 2 Right Channel Input Microphone Output Right Channel Power Amplifier Input Right Line Driver Output Right Speaker Supply Soft Start Timing Capacitor Right Speaker Output Right Speaker Ground Left Speaker Ground Left Speaker Output Left Speaker Supply Speaker Mute Left Line Driver Output Left Channel Power Amplifier Input
3
RC5513
PRODUCT SPECIFICATION
Absolute Maximum Ratings
(beyond which the device may be damaged)1 Parameter VCC Power supply voltage Min Typ Max 13.2 Units V
Note: 1. Functional operation under any of these conditions is NOT implied. Performance is guaranteed only if Operating Conditions are not exceeded.
Operating Conditions
Parameter VCC VCCR VCCL VIH VIL Tc Itotal
ESD
Conditions Power Supply
Min 11.2
Typ 12
Max 12.8
Units V
Input Voltage Logic High Input Voltage Logic Low Ambient Temperature Maximum Operation Die Temperature Power Supply Current ESD Threshold Overthermal Protection No load Human Body Model
2 0.8 0 150 19 2000 25 70
V V C C mA V
Electrical Characteristics
VCC = 12V 6%, unless otherwise specified. Parameter Line Driver
Zin
Conditions Input Impedance Voltage Gain Left and Right Gain Matching Output Voltage Total Harmonic Distortion Power Supply Rejection Ratio Signal to Noise Ratio Speaker Driver Supply Current Input Impedance Voltage Gain Left and Right Gain Matching Output Voltage Signal to Noise Ratio Vin = 0.5 Vrms Vout = 4VP-P RL = 4W or 8W, VCC = 12V Input Referenced Vin = 1 Vrms Vout = 4VP-P RL = 600W Vout = 4VP-P f = 100Hz, DVcc = 0.85Vrms Vin = 2.8V rms Vin = 0V
Min
Typ 10
Max
Units KW
f = 1KHz,RL = 600W unlees otherwise specified 0.95 1.0 0.3 4 0.01 80 86 85 5 100 3.80 -4.0 0.5 4 85 -4.20 1.05 V/V % V % dB dB
mA
Av L&R Av Vo THD PSRR SNR Ispk Zin Av L&R Av Vo SNR
Speaker Driver
f = 1KHz, RL = 8W unless otherwise specified
KW V/V % V dB
4
PRODUCT SPECIFICATION
RC5513
Electrical Characteristics (continued) VCC = 12V 6%, unless otherwise specified.
Parameter Po CS XTALK XTALK THD Noise PSRR Power Supply Rejection Ratio Input Referenced Microphone Amp Supply Current First Amp Input Impedance First Amp Gain Second Amp Gain AGC Dynamic Range Total Harmonic Distortion XTALK from other blocks at MICOUT Input Referenced Voltage Regulator Supply Current Regulator Voltage Tempco Line Regulation Load Regulation Io Output Current Source Source With External 2N2222 Sink Soft Start Delay Anti-Pop Ramp-Up and Ramp-Down time No Pop condition CDELAY = 22mF on SFTSTART 2 sec 4.75 Vin = 5mVP-P, AGC off 20Hz to 20kHz, A-Weighted Vin = 1Vrms at 1KHz f = 100Hz, DVcc = 1.6Vp-p 70 70 1.5 5 0.5 3 2 20 150 100 5.25 Power Output Per Channel Peak Channel Separation L/R Input Referenced Cross Talk L/R to Mic Input Referenced Cross Talk L/R to Reg Input Referenced Total Harmonic Distortion Conditions RL = 4W, VCC = 12V (See Figure 1) Vin = 0.5 Vrms Vin = 1 mVrms Vin = 0.5 Vrms fo = 1KHz, Po = 50mW 20Hz to 20kHz, A-Weighted f = 100Hz, DVcc = 1.6Vp-p 70 66 90 75 0.1 4 80 Min Typ 4 Max Units W dB dB dB % mVrms dB
Microphone Amplifier Imicam p Zin1 Av1 Av2 AGC THD Noise XTALK PSRR Ireg Vreg Tc
f = 1KHz,RL = 10KW unless otherwise specified Vin = 0V, max gain 4 4.5 1 -10 40 0.1 8 mA KW V/V V/V dB % mVrms dB dB mA V mV/C mV/V mV/mA mA mA mA
Voltage Regulator
5
RC5513
PRODUCT SPECIFICATION
Applications Discussion
10F/16V +
RC5513
LIN REGSEN VCCL LLINE SPKAMPINL SPKMUTE SPKOUTL GNDSPKL GNDSPKR SPKOUTR SFTSTART RLINE SPKAMPINR VCCR MICOUT
65-5513-03
12V 100F/16V +
2N2222
REGOUT REGIN GNDREG GNDMIC MICSEL
470F/16V +
470F/16V + + CDELAY = 22F/10V + 100F/16V 0.47F 470F
CAD = 1F 10F/16V + 10F/16V + 10F/16V +
AGCTC MICIN1 MICIN2 RIN
Notes: 1. 4 watt power represents the peak of the audio level and cannot be sustained without correct package thermal considerations. The average audio signal can be sustained by the RC5513 without extra thermal considerations. 2. To improve the thermal resistance of the SOIC package a heat sink can be used. Figure 1. RapperTM RC5513, 4 Ohm Speaker, 4 Watt Application with External Pass Transistor for Voltage Regulator
6
PRODUCT SPECIFICATION
RC5513
Mechanical Dimensions - 24 Lead SOIC Package
Symbol A A1 B C D E e H h L N a ccc Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
.093 .104 .004 .012 .013 .020 .009 .013 .599 .614 .290 .299 .050 BSC .394 .419 .010 .016 24 0 -- 8 .004 .020 .050
2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 15.20 15.60 7.36 7.60 1.27 BSC 10.00 10.65 0.25 0.40 24 0 -- 8 0.10 0.51 1.27
3 6
24
13
E
H
1
12
D A e B A1 SEATING PLANE -C- LEAD COPLANARITY ccc C a L
h x 45 C
7
RC5513
PRODUCT SPECIFICATION
Ordering Information
Product Number RC5513M Package 24 SOIC
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS30005513 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC5532/RC5532A
High Performance Dual Low Noise Operational Amplifier
Features
* * * * * * * * Small signal bandwidth - 10 MHz Output drive capability - 600W, 10 VRMS Input noise voltage - 5 nV/ Hz DC voltage gain - 50,000 AC voltage gain - 2200 at 10 KHz Power bandwidth - 140 KHz Slew rate - 8 V/mS Large supply voltage range - 3V to 20V
Description
The RC5532 is a high performance, dual low noise operational amplifier. Compared to standard dual operational amplifiers, such as the RC747, it shows better noise performance, improved output drive capability, and considerably higher small-signal and power bandwidths. This makes the device especially suitable for application in high quality and professional audio equipment, instrumentation, control circuits, and telephone channel amplifiers. The op amp is internally compensated for gains equal to one. If very low noise is of prime importance, it is recommended that the RC5532A version be used which has guaranteed noise specifications.
Block Diagram
Output A -Input A +VS Output B
A
+Input A -VS
B
-Input B +Input B
65-5532-01
Rev. 1.1.2
RC5532/RC5532A
PRODUCT SPECIFICATION
Pin Assignments
+VS Output (A) Output (A)
8 1 2 3 4 5 7 6
1 2 3 4
8 7 6 5
65-5532-03
+VS Output (B) -Input (B) +Input (B)
Output (B) -Input (A) -Input (B) +Input (A) -VS
-Input (A)
+Input (A)
+Input (B)
65-5532-02
-VS
Absolute Maximum Ratings
(beyond which the device may be damaged)1 Parameter Supply Voltage Input Voltage Differential Input Voltage PDTA < 50C PDIP CerDIP SOIC Junction Temperature Storage Temperature Operating Temperature Lead Soldering Temperature (10 sec) RM5532/A RC5532/A PDIP CerDIP, TO-99 -65 -55 0 Min. Typ. Max. 22 VS 0.5 468 833 658 125 175 150 125 70 300 C C C C Units V V V mW
Notes: 1. Functional operation under any of these conditions is NOT implied. 2. For supply voltages less than 15V, the absolute maximum input voltage is equal to the supply voltage. 3. Short circuit to ground on one amplifier only.
Operating Conditions
Parameter qJC qJA Thermal resistance Thermal resistance CerDIP TO-99 PDIP CerDIP TO-99 For TA > 50C Derate at PDIP CerDIP TO-99 Min. Typ. 45 50 160 150 190 6.25 8.33 5.26 mW/C C/W Max. Units C/W
2
PRODUCT SPECIFICATION
RC5532/RC5532A
DC Electrical Characteristics
(VS = 15V and TA = +25C unless otherwise noted) RM5532/5532A Parameters Input Offset Voltage Over Temperature Input Offset Current Over Temperature Input Bias Current Over Temperature Supply Current Over Temperature Input Voltage Range Common Mode Rejection Ratio Power Supply Rejection Ratio Large Signal Voltage Gain RL 2 KW, VOUT = 10V Over Temperature RL 600W, VOUT = 10V Over Temperature Output Voltage Swing RL 600W RL = 600W, VS = 18V RL 2kW Input Resistance (Diff. Mode) Short Circuit Current 12 80 86 50 25 40 20 12 15 12 13 16 13 300 38 300 38 KW mA 13 100 100 6.0 200 Test Conditions Min. Typ. 0.5 Max. 2.0 3.0 100 200 400 700 11 13 12 70 80 25 15 15 10 12 15 13 16 V 13 100 100 100 50 50 6.0 200 10 RC5532/5532A Min. Typ. 0.5 Max. 4.0 5.0 150 200 800 1000 16 22 Units mV mV nA nA nA nA mA mA V dB dB V/mV
Notes: 1. Diodes protect the inputs against over-voltage. Therefore, unless current-limiting resistors are used, large currents will flow if the differential input voltage exceeds 0.6V. Maximum input current should be limited to 10mA. 2. Over Temperature: RM = 55 C TA 125C; RC = 0C TA 70C
Electrical Characteristics
(VS = 15V and TA = +25C ) RC/RM5532 Parameters Input Noise Voltage Density Input Noise Current Density Channel Separation Test Conditions FO = 30 Hz FO = 1 kHz FO = 30 Hz FO = 1 kHz F = 1 kHz, RS = 5 kW Min. Typ. 8.0 5.0 2.7 0.7 110 Max. RC/RM5532A Min. Typ. 8.0 5.0 2.7 0.7 110 Max. 12 6.0 Units nV/ OHz pA/ OHz dB
3
RC5532/RC5532A
PRODUCT SPECIFICATION
AC Electrical Characteristics
(VS = 15V and TA = +25C ) Parameters Output Resistance Overshoot Gain Gain Bandwidth Product Slew Rate Power Bandwidth VOUT = 10V VOUT = 14V, RL = 600W, VS = 18V Test Conditions AV = 30 dB Closed Loop, F = 10 kHz, RL = 600W Unity Gain, VIN = 100 mVp-p CL = 100 pF, RL = 600W F = 10 KHz CL = 100 pF, RL = 600W Min. Typ. 0.3 10 2.2 10 8.0 140 100 Max. Units W % V/mV MHz V/mS KHz KHz
Test Circuits
3 RS 251/2 VIN RE 2 5532A RF 1 VOUT 2 6001/2 VIN 100 pF 100 pF
65-5532-04
+VS
1K
5532A 3
1 6001/2
VOUT
-VS
65-5532-05
Figure 1. Closed Loop Frequency Response
Figure 2. Follower, Transient Response
4
PRODUCT SPECIFICATION
RC5532/RC5532A
Typical Performance Characteristics
120
VS = 15V TA = +25 C R S = 10 W A V = 40 dB
60
RF = 10 K W RE = 100 W
80 AVOL (dB)
40 AVCL (dB)
40
20
RF = 9 K W R E = 1 k W
65-5532-06
40 10
100
1K
10K F (Hz)
100K
1M
10M
-20 1K
10K
100K
1M F (Hz)
10M
100M
1G
Figure 3. Open Loop Gain vs. Frequency
Figure 4. Closed Loop Gain vs. Frequency
40
VS = 15V
80
VS = 15V
30 VOUT p-P (V)
60 I SC (mA)
20
40
65-5532-08
0 100
1K
10K
100K F (Hz)
1M
10M
100M
0 -55
-25
0
+25 T A ( C)
+50
+75
+150
Figure 5. Output Voltage Swing vs. Frequency
Figure 6. Short Circuit Current vs. Temperature
12
I oUT = 0
1.4
VS = 15V
1.2 I SY (mA) I B ( m A) 8
0.8
4
65-5532-10 65-5532-11
0.4
0 0 10 +VS/-VS (V) Figure 7. Supply Current vs. Supply Voltage 20
30
0 -55
-25
0
+25 T A ( C)
+50
+75
+150
Figure 8. Input Bias Current vs. Temperature
65-5532-09
10
20
65-5532-07
0-
0
RF = 1 K W R E =
8
5
RC5532/RC5532A
PRODUCT SPECIFICATION
Typical Performance Characteristics (continued)
15 10 VOUT P-P (V) 5 0 -5
65-5532-12
15
T A = +25 C T A = +25 C R L = 600 W
10 5 VCM (V) 0 -5 -10 -15 0 5 10 +VS/-VS (V) Figure 10. Common Mode Input Range vs. Supply Voltage 15
65-5532-13
-10 -15 0 5 10 +VS/-VS (V) 15
20
20
Figure 9. Output Voltage Swing vs. Supply Voltage
10 8 6 4 2 0 -2 -4 -6 -8 -10
140
VS = 15V TA = +25 C
120 VOUT (mV) 100 80 60 40
65-5532-14
Output
VOUT (V)
Input
20 0 0 50 100 Time (nS)
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 Time (S)
150
200
Figure 11. Follower Large Signal Pulse Response
Figure 12. Transient Response Output Voltage vs. Time
100
VS = 15V TA = +25 C R S = 10 W A V = 40 dB
en (nV/ Hz)
10
1
65-5532-16
0.1 10
100
1K
10K F (Hz)
100K
1M
Figure 13. Input Noise Density vs. Frequency
6
65-5532-15
VS = 15V TA = +25 C RL = 600 W AV = +1 CL = 100 pF
PRODUCT SPECIFICATION
RC5532/RC5532A
Notes:
7
RC5532/RC5532A
PRODUCT SPECIFICATION
Notes:
8
PRODUCT SPECIFICATION
RC5532/RC5532A
Mechanical Dimensions
8-Lead Ceramic DIP Package
Inches Min. A b1 b2 c1 D E e eA L Q s1 a Max. Millimeters Min. Max. 8 2, 8 8 4 4 5, 9 7 3 6 Notes: Notes 1. Index area: a notch or a pin one identification mark shall be located adjacent to pin one. The manufacturer's identification shall not be used as pin one identification mark. 2. The minimum limit for dimension "b2" may be .023 (.58mm) for leads number 1, 4, 5 and 8 only. 3. Dimension "Q" shall be measured from the seating plane to the base plane. 4. This dimension allows for off-center lid, meniscus and glass overrun. 5. The basic pin spacing is .100 (2.54mm) between centerlines. Each pin centerline shall be located within .010 (.25mm) of its exact longitudinal position relative to pins 1 and 8. 6. Applies to all four corners (leads number 1, 4, 5, and 8). 7. "eA" shall be measured at the center of the lead bends or at the centerline of the leads when "a" is 90. 8. All leads - Increase maximum limit by .003 (.08mm) measured at the center of the flat, when lead finish applied. 9. Six spaces. D 4 1 Note 1 E
Symbol
-- .200 .014 .023 .045 .065 .008 .015 -- .405 .220 .310 .100 BSC .300 BSC .125 .200 .015 .060 .005 -- 90 105
-- 5.08 .36 .58 1.14 1.65 .20 .38 -- 10.29 5.59 7.87 2.54 BSC 7.62 BSC 3.18 5.08 .38 1.52 .13 -- 90 105
5 s1
8
e
eA
A Q L b2 b1 a c1
9
RC5532/RC5532A
PRODUCT SPECIFICATION
Mechanical Dimensions (continued)
8-Lead Plastic DIP Package
Inches Min. A A1 A2 B B1 C D D1 E E1 e eB L N -- .015 .115 .014 .045 .008 .348 .005 .300 .240 Max. .210 -- .195 .022 .070 .015 .430 -- .325 .280 Millimeters Min. -- .38 2.93 .36 1.14 .20 8.84 .13 7.62 6.10 Max. 5.33 -- 4.95 .56 1.78 .38 10.92 -- 8.26 7.11 Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E1" do not include mold flashing. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. Terminal numbers are for reference only. 4. "C" dimension does not include solder finish thickness. 5. Symbol "N" is the maximum number of terminals. 4 2
Symbol
2
.100 BSC -- .430 .115 .160 8
2.54 BSC -- 10.92 2.92 4.06 8 5
D 4 1
E1
D1
5
8
E e A A1 L B1 B eB A2 C
10
PRODUCT SPECIFICATION
RC5532/RC5532A
Mechanical Dimensions (continued)
8-Lead Metal Can IC Header Package
oD Symbol oD1 A ob ob1 oD oD1 oD2 e e1 F k k1 L L1 L2 Q a Notes: e1 1. (All leads) ob applies between L1 & L2. ob1 applies between L2 & .500 (12.70mm) from the reference plane. Diameter is uncontrolled in L1 & beyond .500 (12.70mm) from the reference plane. 2. Measured from the maximum diameter of the product. 3. Leads having a maximum diameter .019 (.48mm) measured in gauging plane, .054 (1.37mm) +.001 (.03mm) -.000 (.00mm) below the reference plane of the product shall be within .007 (.18mm) of their true position relative to a maximum width tab. a 4. The product may be measured by direct methods or by gauge. 5. All leads - increase maximum limit by .003 (.08mm) when lead finish is applied. k k1 Inches Min. Max. Millimeters Min. Max. 1, 5 1, 5
Notes
L1
F
Q
A
L2 L
ob BASE and SEATING PLANE ob1
REFERENCE PLANE
.165 .185 .016 .019 .016 .021 .335 .375 .305 .335 .110 .160 .200 BSC .100 BSC -- .040 .027 .034 .027 .045 .500 .750 -- .050 .250 -- .010 .045 45 BSC
4.19 4.70 .41 .48 .41 .53 8.51 9.52 7.75 8.51 2.79 4.06 5.08 BSC 2.54 BSC -- 1.02 .69 .86 .69 1.14 12.70 19.05 -- 1.27 6.35 -- .25 1.14 45 BSC
2 1 1 1
e
oD2
11
RC5532/RC5532A
PRODUCT SPECIFICATION
Ordering Information
Product Number RC5532D/RC5532AD RC5532N/RC5532AN RM5532D/RM5532AD RM5532D/883B RM5532AD/883B RM5532T/RM5532AT RM5532T/883B RM5532AT/883B Temperature Range 0C to +70C 0C to +70C -55C to +125C -55C to +125C -55C to +125C -55C to +125C -55C to +125C -55C to +125C Screening Commercial Commercial Commercial Military Military Commercial Military Military Package 8 Pin Ceramic DIP 8 Pin Plastic DIP 8 Pin Ceramic DIP 8 Pin Ceramic DIP 8 Pin Ceramic DIP 8 Pin TO-99 Metal Can 8 Pin TO-99 Metal Can 8 Pin TO-99 Metal Can
Note: 1. /883B suffix denotes MIL-STD-883, Par. 1.2.1 compliant device.
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS30005532 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC5534/RC5534A
High Performance Low Noise Operational Amplifier
Features
* * * * Small signal bandwidth - 10 MHz Output drive capability - 600W, 10 VRMS at VS = 18V Input noise voltage - 4 nV/OHz DC voltage gain - 100,000 * * * * AC voltage gain - 6000 at 10 kHz Power bandwidth - 200 kHz Slew rate - 13 V/mS Large supply voltage range - 3V to 20V
Description
The RC5534 is a high performance, low noise operational amplifier. This amplifier features popular pin-out, superior noise performance, and high output drive capability.
Block Diagram
-Input
- Output +
This amplifier also features guaranteed noise performance with substantially higher gain-bandwidth product, power bandwidth, and slew rate which far exceeds that of the 741 type amplifiers. The RC5534 is internally compensated for a gain of three or higher and may be externally compensated for optimizing specific performance requirements of various applications such as unity-gain voltage followers, drivers for capacitive loads or fast settling. The specially designed low noise input transistors allow the RC5534 to be used in very low noise signal processing applications such as audio preamplifiers and servo error amplifiers.
+Input
65-3476-01
Pin Assignments
VOS Trim/Comp VOS Trim VOS Trim -Input
8 1 2 3 4 5 7 6
1 2 3 4
8 7 6 5
65-3476-03
VOS Trim/Comp +VS Output Comp
+VS Output
-Input +Input -VS
+Input
Comp
65-3476-02
-VS
Rev. 1.0.0
PRODUCT SPECIFICATION
RC5534/RC5534A
Absolute Maximum Ratings
(beyond which the device may be damaged)1 Parameter Supply Voltage Input Voltage Differential Input Voltage PDTA < 50C PDIP CerDIP SOIC Junction Temperature Storage Temperature Operating Temperature Lead Soldering Temperature (60 sec) Output Short Circuit Duration
2
Min
Typ
Max 22 VS 0.5 468 833 658 125 175
Units V V V mW
PDIP CerDIP, TO-99 -65 RM5534/A RC5534/A -55 0 Indefinite
C C C C
150 125 70 300
Notes: 1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded. 2. Short circuit may be to ground only. Rating applies to +125C case temperature or +175C junction temperature.
Operating Conditions
Parameter qJC qJA Thermal resistance Thermal resistance CerDIP TO-99 PDIP CerDIP TO-99 For TA > 50C Derate at PDIP CerDIP TO-99 Min Typ 45 50 160 150 190 6.25 8.33 5.26 mW/C C/W Max Units C/W
Operating Conditions
(RM = -55C TA +125C; RC = 0C TA + 70C, VS = 15V) Parameter Input Offset Voltage Input Offset Current Input Bias Current Large Signal Voltage Gain Output Voltage Swing Supply Current RL 600W, VOUT = 10V RL 600W VS = 15V, RL = 25 10 9.0 Test Conditions RS 1 kW RM5534/A 3.0 500 1500 15 10 14 RC5534/A 5.0 400 2000 Units mV nA nA V/mV V mA
2
RC5534/RC5534A
PRODUCT SPECIFICATION
DC Electrical Characteristics
(VS = 15V and TA = +25C unless otherwise noted) RM5534/A Parameters Input Offset Voltage Input Offset Current Input Bias Current Input Resistance (Diff. Mode) Large Signal Voltage Gain Output Voltage Swing Input Voltage Range Common Mode Rejection Ratio Power Supply Rejection Ratio Supply Current Transient Response Rise Time Overshoot Slew Rate Gain Bandwidth Product Power Bandwidth Input Noise Voltage Input Noise Current Channel Separation CC = 0 CC = 22 pF, CL = 100 pF VOUT = 20Vp-p, CC = 0 F = 20 Hz to 20 kHz F = 20 Hz to 20 kHz F = 1 kHz, RS = 5 kW RS 1kW RS 1kW RL = VIN = 50 mV, RL = 600W, CL = 100 pF, CC = 22 pF RL 600W, VOUT = 10V RL 600W 50 12 12 80 86 Test Conditions RS 1kW Min Typ 0.5 10 400 100 100 13 13 100 100 4.0 35 17 13 10 200 1.0 25 110 6.5 25 12 12 70 86 Max 2.0 200 800 RC5534/A Min Typ 0.5 20 500 100 100 13 13 100 100 4.0 35 17 13 10 200 1.0 25 110 8.0 Max 4.0 300 1500 Units mV nA nA kW V/mV V V dB dB mA nS % V/mS MHz kHz mVRMS pARMS dB
AC Electrical Characteristics
(VS = 15V and TA = +25C unless otherwise noted) Parameters Input Noise Voltage Density Input Noise Current Density Broadband Noise Figure Test Conditions FO = 30 Hz FO = 1 kHz FO = 30 Hz FO = 1 kHz F = 10 Hz - 20 kHz, RS = 5 kW RC/RM5534A 5.5 3.5 1.5 0.4 0.9 7.0 4.5 RC/RM5534 7.0 4.0 2.5 0.6 Units nV/ OHz pA/ OHz dB
3
PRODUCT SPECIFICATION
RC5534/RC5534A
Typical Performance Characteristics
0.7 0.6 0.5 IB ( m A) 0.4 0.3 0.2
65-1758
14 12
VS = 15V VS = 15V TA = +25 C
10 SR (V/ m S) 8 6 4
65-1759
0.1 0 0 +10 +20 +30 +40 +50 +60
2 0 0 1 CC (pF) Figure 2. Slew Rate vs. Compensation Capacitor 10
+70
100
TA (C) Figure 1. Input Bias Current vs. Temperature
15 100 10 5 VCM (V) 0 -5
65-1760
TA = +25 C
80 AVOL (dB) 60 40 20 0 0 100 1K -15 4
CC = 22 pF
VS = 15V TA = +25 C C C = 0 pF
6
8
10
12
14
16
18
10K 100K F (Hz)
1M
10M 100M
+VS/-VS (V) Figure 3. Common Mode Input Range vs. Supply Voltage
Figure 4. Open Loop Gain vs. Frequency
15 150
VS = 15V
10 VOUT P-P (V) 5 0 -5
TA = +25 C
AVOL (V/mV)
100
RL = 2 k W
50
65-1762
0 0 +10 +20 +30 +40 +50 +60 TA (C) Figure 5. Open Loop Gain vs. Temperature
+70
-15 4
6
8
10
12
14
16
18
+VS/-VS (V) Figure 6. Output Voltage Swing vs. Supply Voltage
4
65-1763
-10
RL = 2 k W
65-1761
-10
RC5534/RC5534A
PRODUCT SPECIFICATION
Typical Performance Characteristics (continued)
30 26 22 VOUT P-P (V) 18 14 10
65-1764
42 36 VOUT P-P (V)
VS = 15V F = 1 kHz T.H.D. < 1% A V = +10
VS = 15V TA = +25 C RL = 2 kW CC = 0 pF
30 24 18 12 6 0 100 1K 10K F (Hz) Figure 8. Output Voltage Swing vs. Frequency
CC = 27 pF
65-1765
6 2 10 100 RL ( W) 1K
CC = 47 pF
10K
100K
1M
Figure 7. Output Voltage Swing vs. Load Resistance
5 4 VOUT (mV)
TA = +25 C
70 60 50 40 30 20
65-1766
C L = 100 pF CC = 22 pF 90%
CL = 500 pF CC = 47 pF
IQ (mA)
3 2 1 0
0 0
100%
0
3
6
9
12
15
18
50
100
150
200
+VS/-VS (V) Figure 9. Quiescent Current vs. Supply Voltage
Time (nS) Figure 10. Transient Response Output Voltage vs. Time
10 8 6 4 2 0 -2 -4 -6 -8 -10
1000
VS = 15V TA = +25 C C C = 0 pF VS = 15V TA = +25 C RS = 50 W A V = 60 dB
Input
en (nV/ Hz)
VOUT (V)
Output
100
10
65-1769
65-1768
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 Time (S)
1
0
10
100 F (Hz)
1K
10K
100K
Figure 11. Follower Large Signal Pulse Response Output Voltage vs. Time
Figure 12. Input Noise Density vs. Frequency
65-1767
10
VS = 15V T A = +25 C R L = 600 W A V = +1
5
PRODUCT SPECIFICATION
RC5534/RC5534A
Typical Performance Characteristics (continued)
100
VS = 15V TA = +25C RS = 100 kW A V = 60 dB
40 AVGL (dB)
CC = 0, R F = 10 k W; R E = 100W
IN (pA/ Hz)
10
20
C C = 0, R F = 9 k W; R E = 1 kW
1
65-1770
0
CC = 22 pF, R F = 1 k W; R E =
65-1771
0.1
0
10
100 F (Hz)
1K
10K
100K
-20 10K
100K
1M F (Hz)
10M
100M
Figure 13. Input Noise Current Density vs. Frequency
Figure 14. Closed Loop Gain vs. Frequency
0.07 0.06 0.05 THD(%) 0.04 0.03 0.02
65-1773
VS = 15V 20 Hz < F < 20 kHz R L = 600 W C L = 100 pF A V = +10 or -10
0.01 0 0.1 1 VOUT (VRMS )
10
Figure 15. Total Harmonic Distortion vs. Output Voltage
Typical Test Circuits
+VS 22K CC 8
3
VOS Trim 100K
1
CC VOS Trim/ Comp
5 7
RS 2001/2 VIN
5 5534
2
6
-VIN VOUT RL 6001/2 +VIN
65-1772
8 2
Comp
RF CL 100 pF
5534
4
6
VOUT
RE
3
65-1774
-VS
Figure 16. Closed Loop Frequency Response Test Circuit
Figure 17. Offset Voltage Trim Circuit
6
RC5534/RC5534A
PRODUCT SPECIFICATION
Simplified Schematic Diagram
VOS Trim (1) VOS Trim/ Compensation Compensation (5)
+VS (7) C1 100 pF R1 13.3K R2 13.3K R9 5.9K R10 5.9K Q10
R16 570 +Input (3) D2 -Input (2) D1 Q1 Q2 Q3 C2 32 pF Q4 R17 150 Q13 D4 Q14 C3 12 pF R15 4K Q12 Q8 D5 Q19 Q18 Q22 Q11 R18 14
Output (6)
C4 7 pF
R19 14
Q7
R3 3.7K Q5
Q20 Q6 R4 120 R11 180 R12 3K R13 180 R14 1.5K
Q17 Q16 R20 2K
Q15
-VS (4)
65-1726
7
PRODUCT SPECIFICATION
RC5534/RC5534A
Mechanical Dimensions
8-Lead Ceramic DIP Package
Inches Min. A b1 b2 c1 D E e eA L Q s1 a Max. Millimeters Min. Max. 8 2, 8 8 4 4 5, 9 7 3 6 Notes: Notes 1. Index area: a notch or a pin one identification mark shall be located adjacent to pin one. The manufacturer's identification shall not be used as pin one identification mark. 2. The minimum limit for dimension "b2" may be .023 (.58mm) for leads number 1, 4, 5 and 8 only. 3. Dimension "Q" shall be measured from the seating plane to the base plane. 4. This dimension allows for off-center lid, meniscus and glass overrun. 5. The basic pin spacing is .100 (2.54mm) between centerlines. Each pin centerline shall be located within .010 (.25mm) of its exact longitudinal position relative to pins 1 and 8. 6. Applies to all four corners (leads number 1, 4, 5, and 8). 7. "eA" shall be measured at the center of the lead bends or at the centerline of the leads when "a" is 90. 8. All leads - Increase maximum limit by .003 (.08mm) measured at the center of the flat, when lead finish applied. 9. Six spaces. D 4 1 Note 1 E
Symbol
-- .200 .014 .023 .045 .065 .008 .015 -- .405 .220 .310 .100 BSC .300 BSC .125 .200 .015 .060 .005 -- 90 105
-- 5.08 .36 .58 1.14 1.65 .20 .38 -- 10.29 5.59 7.87 2.54 BSC 7.62 BSC 3.18 5.08 .38 1.52 .13 -- 90 105
5 s1
8
e
eA
A Q L b2 b1 a c1
8
RC5534/RC5534A
PRODUCT SPECIFICATION
Mechanical Dimensions (continued)
8-Lead Plastic DIP Package
Inches Min. A A1 A2 B B1 C D D1 E E1 e eB L N -- .015 .115 .014 .045 .008 .348 .005 .300 .240 Max. .210 -- .195 .022 .070 .015 .430 -- .325 .280 Millimeters Min. -- .38 2.93 .36 1.14 .20 8.84 .13 7.62 6.10 Max. 5.33 -- 4.95 .56 1.78 .38 10.92 -- 8.26 7.11 Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E1" do not include mold flashing. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. Terminal numbers are for reference only. 4. "C" dimension does not include solder finish thickness. 5. Symbol "N" is the maximum number of terminals. 4 2
Symbol
2
.100 BSC -- .430 .115 .160 8
2.54 BSC -- 10.92 2.92 4.06 8 5
D 4 1
E1
D1
5
8
E e A A1 L B1 B eB A2 C
9
PRODUCT SPECIFICATION
RC5534/RC5534A
Mechanical Dimensions (continued)
8-Lead Metal Can IC Header Package
oD Symbol oD1 A ob ob1 oD oD1 oD2 e e1 F k k1 L L1 L2 Q a Notes: e1 1. (All leads) ob applies between L1 & L2. ob1 applies between L2 & .500 (12.70mm) from the reference plane. Diameter is uncontrolled in L1 & beyond .500 (12.70mm) from the reference plane. 2. Measured from the maximum diameter of the product. 3. Leads having a maximum diameter .019 (.48mm) measured in gauging plane, .054 (1.37mm) +.001 (.03mm) -.000 (.00mm) below the reference plane of the product shall be within .007 (.18mm) of their true position relative to a maximum width tab. a 4. The product may be measured by direct methods or by gauge. 5. All leads - increase maximum limit by .003 (.08mm) when lead finish is applied. k k1 Inches Min. Max. Millimeters Min. Max. 1, 5 1, 5
Notes
L1
F
Q
A
L2 L
ob BASE and SEATING PLANE ob1
REFERENCE PLANE
.165 .185 .016 .019 .016 .021 .335 .375 .305 .335 .110 .160 .200 BSC .100 BSC -- .040 .027 .034 .027 .045 .500 .750 -- .050 .250 -- .010 .045 45 BSC
4.19 4.70 .41 .48 .41 .53 8.51 9.52 7.75 8.51 2.79 4.06 5.08 BSC 2.54 BSC -- 1.02 .69 .86 .69 1.14 12.70 19.05 -- 1.27 6.35 -- .25 1.14 45 BSC
2 1 1 1
e
oD2
10
PRODUCT SPECIFICATION
RC5534/RC5534A
Ordering Information
Product Number RC5534D/RC5534AD RC5534N/RC5534AN RM5534D/RM5534AD RM5534D/883 RM5534AD/883 RM5534T/RM5534AT RM5534T/883 RM5534AT/883 Temperature Range 0C to +70C 0C to +70C -55C to +125C -55C to +125C -55C to +125C -55C to +125C -55C to +125C -55C to +125C Screening Commercial Commercial Commercial Military Military Commercial Military Military Package 8 Pin Ceramic DIP 8 Pin Plastic DIP 8 Pin Ceramic DIP 8 Pin Plastic DIP 8 Pin Plastic DIP 8 Pin TO-99 Metal Can 8 Pin TO-99 Metal Can 8 Pin TO-99 Metal Can
Note: /883 denotes MIL-STD-883, Par. 1.2.1 compliant device.
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS30005534 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
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RC5X01
CPU Core PWM Controller
Features
* * * * * Maximum efficiency at 5 V - 12V and 3A - 5A 120mV Regulation T = 5msec Ton = 350nsec with 7% minimum DC RDSON = 10 mW 20 Lead TSSPOP Package
Applications
* Notebook PCs * MMOs
Target Specification
Block Diagram
Vin = 5-20V 5%
FORCED PWM (20) PGOOD (19) SDOWN (18) SYNC (17) COMP (16) DAC0 (15) VID0 (14) VID1 (13) VID2 (12) VID3 (11) VTH BUR. ST - +
(1)
(2) IFB
RS
(3) HSD (4) BST 0.1F (5) SW (6) LSD 5 H 770 F Vout 1.6V 5A
DAC
DIGITAL CTRL
(7) VFB OSC COSC (10) PGND (9) OVP OCP DIG. SS
SGND (8)
10/29/97 Rev. 0.0.0
TARGET SPECIFICATION
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RC5X02
Multi PWM Regulator controller
Features
* Efficiency > 80% at 7.8V - 12V * 28 Lead TSSOP Package
Applications
* Notebook PCs * PDAs
Target Specification
Block Diagram
Vin = 5/20V 5%
NC (28) FB5 (27) IFB1 (26) HSD1 (25) 5V 100 mA Audio 3.3V 3.4A I/O RC2951 BST1 (24) 10 H 330 F SW1 (23) LSD1 (22) - + OVP OCP aIFB2
NC (1)
VIN (2) (3) FB12 (4) IFB2 RS 3.3 F RC2951 0.1F 30 H 20 F 10 F 12V 150 mA PCMCIA Vout = 5V 1A HDD+
(5) HSD2 (6) BST2 (7) SW2 DIGITAL CTRL (8) LSD2
REF COMP2
VFB1 (21) ON/OFF1 (20) COMP1 (19) 5V 25mA OSC 5VSTDBY (18) COSC (17)
(9) VFB2 (10) ON/OFF2 (11) COMP2 Vth IFB2 (12) OSCILLATOR SYNC (13) S/D (14) PGOOD
BUR. ST
DIGITAL SS1 SGND (16)
DIGITAL SS2
PGND (15)
10/29/97 Rev. 0.0.0
TARGET SPECIFICATION
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RC6100
Horizontal Genlock
Features
* High speed tracking sync separator easily follows hum or average picture level (APL) fluctuations * Glitch remover for operation in high impulse noise environment * On chip phase-locked loop * Locks and follows VCR sync * Compatible with NTSC and PAL systems * Choice of eight output frequencies * Field ID output * Internal VCO
Description
The RC6100 contains a phase-locked loop (PLL) in a frequency multiplier configuration to generate a highfrequency clock as required for video A/D converter and digital video signal processing. The device accepts composite video, composite sync or component sync signals as input. The output signals generated are: clamp gate, composite sync, horizontal sync, vertical sync, field ID, lock detector output, oscillator output (Clock), and Clock/2. The NTSC output frequency choices are: 27.0, 25.175, 14.318, 13.5, 12.588, 12.273, 7.159, and 6.137 MHz. The PAL frequencies generated are: 27.0, 17.734, 15.0, 14.75, 13.5, 8.867, 7.5, and 7.375 MHz.
Applications
* * * * Digital video signal processing Digital television receivers and VCRs Video conferencing equipment Multimedia computers
Logic Symbol
CVIN FILTOUT FILTIN VSYNC PLLFILTER FHIN S0 S1 NTSC/ PAL FHOUT FIELDID VRESET HRESET CLKDIV2 CLAMP
65-6100-01
SYNC SEPARATOR/ SELECTOR
CSYNC HLOCK HCAP
FREQUENCY SELECT
PLL FREQUENCY MULTIPLIER
CLKOUT
CLKIN
TIMING GENERATOR
Rev. 1.2.1
RC6100
PRODUCT SPECIFICATION
Block Diagram
VSYNC CLAMP FIELDID VRESET S2 HRESET S1 TIMING CLKDIV2 S0 GENERATOR FH HSYNC CLK CSYNC CVIN CV CSYNC SYNC SEPARATOR CSYNC CLAMP FIELDID VRESET HRESET CLKDIV2 FHOUT
FILTOUT OUT FILTIN IN LOWPASS FILTER
FHIN
A0 MULTIPLEXER A1 Y S
V R
UP PHASE DETECTOR DN LDET
UP DN
EXTCAP CHARGE PUMP
PLLFILTER
CLKIN LOCK HLDET DECTECTOR HLCAP LOCK CLK S2 S1 S0 CLKOUT
HCAP HLOCK SELECTION CODE S0 S1 NTSC/PAL
VCONT V25 VCO
65-6100-02
Figure 1.
Functional Description
The RC6100 block diagram is shown in Figure 1. Baseband composite video may be applied to either the FILTIN or CVIN input, depending upon whether the lowpass filter circuit function is desired. Use of the lowpass filter is desirable whenever the input video signal contains impulse noise or glitches that can cause jitter on the sync and clock output signals. Signals that require lowpass filtering should be input at FILTIN and the lowpass filter output (FILTOUT) should be connected to the CVIN input. However, video signals that do not require noise filtering should be input directly at CVIN to optimize performance. The FILTIN and CVIN inputs can also receive composite sync or horizontal sync signals at CMOS or TTL levels. The input VSYNC is intended for those applications in which the horizontal and vertical sync signals have already been separated. In this mode, horizontal sync should be applied to CVIN and vertical sync applied to VSYNC. These two signals will be combined to form CSYNC and used by the timing generator to form HRESET, VRESET, and the other timing control signals. The VSYNC input is active low and is held at logic high via an internal bias network. If VSYNC is left open, there is no effect on signal processing. The sync separator extracts a composite sync signal from the composite video, or creates composite sync from separate horizontal and vertical sync inputs. This signal is available at 2 the CSYNC output. Composite sync is also used to control the timing generator, which is the workhorse function of the RC6100. The timing generator contains programmable dividers for generating and controlling the pixel clock. The selection of pixel clock frequencies is controlled via logic inputs NTSC/ PAL, S0, and S1. Table 1 shows the states of these inputs and the corresponding clock frequencies. The timing generator also provides the following output signals: CLAMP, VRESET, FIELDID, HRESET, FHOUT, and CLKDIV2. The CLAMP output is an active-low rectangular pulse of about 4 ms duration, the origination of which is timed by the risingedge of CSYNC; the pulse is active during the horizontal back-porch interval, as shown in Figure 2. The CLAMP output is also active during the vertical blanking interval. The VRESET output is a short vertical sync signal that is logic low for the duration of the scan line that follows the first serration pulse of the vertical interval, as shown in Figure 3. HRESET is a horizontal sync signal that is set to logic low for one period of the pixel clock (CLKOUT); it is also phase coherent with the pixel clock. FHOUT is a clock signal at the horizontal frequency. It is normally connected to FHIN and used as the VCO (feedback) input to the loop phase comparator. The timing of HRESET relative to FHOUT is shown in Figure 4. (Note: the drawing exaggerates delays t1 and t2.) The FIELDID output goes to logic low immediately after the
PRODUCT SPECIFICATION
RC6100
VRESET pulse for RS170 Field 1 (the odd field) and toggles to logic high at the same time in the next field (see Figure 3). CLOCKDIV2 is the half-frequency pixel clock output; it is a 50-percent duty-cycle waveform. The Selection Codes of Table 1 (NTSC/PAL, S0, and S1) are input to the RC6100 to select the desired clock frequency to be output. The divisors shown in Table 1 indicate on-half the number of pixel clocks in each horizontal line. The pixel clock generator circuit (Figure 5) is formed by the Phase Detector, Charge Pump, external Loop Filter, and the VCO. The loop filter requires only a simple RC lag-lead network. When the PLL is locked, the VCO provides a pixel clock that is equal to 2*N*fH, (two times the horizontal scan frequency where N is the frequency divisor value). CLKOUT is normally connected to CLKIN, the clock input of the timing generator function. Note that a half-frequency pixel clock (CLKDIV2) is also generated. Both pixel clock outputs are 50-percent duty-cycle waveforms.
CHROMA REFERENCE BURST CVIN
ACTIVE VIDEO FRONT PORCH
HOR SYNC PULSE INTERVAL
HORIZONTAL INTERVAL
HOR SYNC BACK PORCH
CSYNC OUTPUT
CLAMP OUTPUT 3 S < tCLAMP < 4.3 S
65-6100-03
Figure 2. CLAMP Output Timing
FIELDS 1 AND 3 VERTICAL BLANKING INTERVAL VERTICAL SYNC INTERVAL 524 525 PRE-EQUALIZATION 3H 1 2 3 SERRATIONS 3H 4 7 7 POST-EQUALIZATION 3H 7 8 9 21 10 19 20 22
CVIN
UVV
UVV
EE
EE
EE
SS
SS
SS
SS
EE
EE
UBB
UBB
UBB
UVV
UVV
CSYNC
VRESET FIELDID
FIELDS 2 AND 4 262 263 264 265 266 267 268 269 270 271 272 273 282 283 284 285
CVIN
UVV UVE EE EE ES SS SS SE EE EE EB UBB UBB UBV UVV UVV
CSYNC
VRESET
FIELDID
65-6100-04
Definitions: UVV: active video ES: half-line equalization pulse, half-line vertical sync pulse UVE: half-line video, half-line equalization pulse SE: half-line vertical sync pulse, half-line equalization pulse EE: equalization pulse UBV: half-line black, half-line video EB: equalization broad pulse UBB: black burst SS: vertical sync pulse with serrations Figure 3. VRESET Output TIming
3
RC6100
PRODUCT SPECIFICATION
Table 1. Clock Frequency Selection
Selection Codes NTSC/ PAL 1 1 1 1 0 0 0 0 S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 System NTSC (CCIR601) NTSC (VGA) NTSC (4fSC/Studio) NTSC (Sq. Pixel) PAL (CCIR601) PAL (4fSC/Studio) PAL PAL (Sq. Pixel) Frequencies (MHz) and Divisors (N) Clock Out 27.0 25.175 14.318 12.273 27.0 17.734 15.0 14.75 Clock/2 Out 13.5 12.588 7.159 6.137 13.5 8.867 7.5 7.375 Divide by N 858 800 455 390 864 567.5 480 472
The timing performance of the phase lock is controlled by an external RC filter, the CSYNC signal, and internallygenerated horizontal sync signals. When the PLL is not locked, CSYNC is selected as the reference input to the phase detector. CSYNC is derived directly from the composite video input, which contains the required horizontal edge information, and is not dependent upon the loop being locked. When the loop is locked, an internally generated horizontal sync signal from the timing generator is used for this reference input. CSYNC is only used as the loop reference input in the unlocked condition, because it contains serration pulses that would contribute undesirable jitter to the VCO output. The lock-detect output signal (HLOCK) indicates when the phase reference and VCO inputs of the phase detector are locked. The response time of the lock detector is controlled by an external capacitor (C3) and, when lock is established, the HLOCK output goes low and the MUX makes the appropriate reference signal choice. The value of C3 was chosen to provide a lock-indication response time that is approximately 15 horizontal lines in duration, and an unlock-indication response time of approximately three horizontal lines in duration. Increasing the value of C3 would result in increasing both the lock and unlock response times. The PLL consists of the phase detector, charge pump, loop filter, VCO, and divide-by-N counter. The phase detector is essentially a control loop summing junction. The charge pump, loop filter, and VCO are in the forward path, and the divide-by-N counter forms the feedback path. Stabilizing this control system consists of choosing the proper component values for the loop filter, such that sufficient phase margin exists at the unity-gain crossover frequency. The filter is a lag-lead network formed by the charge pump, C1, R1, and C2. Increasing the value of C1 moves the pole of the lag network (low pass) closer to the origin (lower frequency). This
WINDOW
CLKOUT
FHOUT
HRESET
CLKOUT
FHOUT t1
HRESET t2 4ns < t1 < 11ns t2 A 4ns
65-6100-05
Figure 4. HRESET Output Timing
will reduce the loop bandwidth, which generally tends to reduce VCO jitter, but at a cost of settling (response) time and (in the extreme) stability. Table 2 shows values for R1, C1, and C2 for all input setings. Increasing the value of either R1 or C2 moves the zero of the lead network (high pass) lower in frequency, which tends to increase loop gain at higher frequencies and can also result in poorer noise performance. The location of the zero is generally determined empirically to adjust the loop transfer function for adequate phase margin for a given desired bandwidth. The RC6100 loop settling time is approximately 400 ms, and lock detection requires about one millisecond.
4
PRODUCT SPECIFICATION
RC6100
LOCK DETECT TIMING
C3 0.01 F HLCAP
LOOP FILTER (LAG-LEAD) PLL FILTER CHARGE PUMP UP DN
C1 0.01F*
R1 4K*
C2 1.0F* * FILTER FOR CODE 111
HLOCK
LOCK DETECTOR
VCO
CLKOUT PIXEL CLOCK OUTPUT
INTERNAL SIGNALS
CSYNC HSYNC
A B
S MUX
fH
LDET
U
D
PHASE DETECTOR
fH
DIVIDE BY N
CLKDIV2
PROGRAM INPUTS (CODE)
3 NTSC/PAL, S0, S1
65-6100-06
Figure 5. Pixel Clock Generator
Table 2. PLL Filter Components
Dividers code 100 101 110 111 000 001 010 011 fin 15734 15734 15734 15734 15625 15625 15625 15625 fosc 27.00E+06 25.18E+06 14.32E+06 12.27E+06 27.00E+06 17.73E+06 15.00E+06 14.75E N 1.00 1.00 2.00 2.00 1.00 2.00 2.00 2.00 M 858 800 455 390 864 567.5 480 472 KVC0 2.66E+07 2.66E+07 2.51E+07 2.51E+07 2.66E+07 3.48E+07 2.48E+07 2.48E+07 KCP 3.82E-05 3.82E-05 3.82E-05 3.82E-05 3.82E-05 3.82E-05 3.82E-05 3.82E-05 R1 4.17E+03 3.89E+03 4.68E+03 4.01E+03 4.17E+03 4.19E+03 4.97E+03 4.89E+03 C2(K/20) 9.69E-07 1.04E-06 8.64E-07 1.01E-06 9.76E-07 9.72E-07 8.19E-07 8.33E-07 C1 9.69E-09 1.04E-08 8.64E-09 1.01E-08 9.76E-09 9.72E-09 8.19E-09 8.33E-09
Note: 1. Table values are ideal; actual values may vary by 20% due to process variations. 2. Code:
Pin Assignments
CVIN FILTOUT FILTIN HLCAP VCC VSYNC HLOCK CLAMP VDD VRESET CLKDIV2 FIELDID
1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13
65-6100-07
PLLFILTER CSYNC GNDA NTSC/PAL CLKOUT CLKIN S1 S0 FHOUT FHIN HRESET VSS
5
RC6100
PRODUCT SPECIFICATION
Pin Descriptions
Pin Name CVIN FILTOUT FILTIN HLCAP VCC VSYNC Pin Number 1 2 3 4 5 6 Description This input accepts composite video. Output of low pass video input filter. This input accepts either composite video, composite sync or horizontal sync signals. The input can be analog (1 Vpp) or TTL/CMOS logic levels. Horizontal lock-detect timing capacitor. +5V power supply for analog circuits. This input accepts vertical sync pulses for use when video input signals do not contain vertical sync components. This input is active low but remains high in normal operation. The input is TTL or CMOS compatible. The locked-loop output indicates that the oscillator is phase-locked to the incoming horizontal sync. Sensitivity and delay time constant are set by an external capacitor. This output is CMOS or TTL compatible. Clamp gate pulse output. This signal is approximately 4 ms in duration and is timed from the trailing edge of composite sync signal. The clamp gate is used by the video ADC and other video processing circuitry for DC restoration. This output is CMOS or TTL compatible. +5V power supply for digital circuits. Vertical sync signal output. This output is low during the line following the first serration pulse in the vertical sync interval. VRESET is CMOS or TTL compatible. CLKOUT divided-by-two output frequency. The field ID output signal is low following the VRESET pulse of RS170 field 1. This output is CMOS or TTL compatible. Digital ground. Horizontal reset signal is decoded from a programmable counter. This signal is coherent with the clock output and is one clock cycle in duration. This output is CMOS or TTL compatible. Horizontal frequency signal input; normally driven by FHOUT. Horizontal frequency signal output. Frequency select inputs. They select one of four possible clock frequencies by providing the appropriate divide-by-N for the frequency-multiplying PLL. Table 1 shows the binary, frequency select codes. These inputs are TTL or CMOS compatible. Clock input for internal timing functions; normally driven by CLKOUT. Buffered VCO output signal. This pin is used to select between NTSC or PAL frequencies of operation. A logic one selects the NTSC frequencies. See Table 1. These inputs are TTL or CMOS compatible. Analog ground. Composite sync signal output. This signal is the sync separated from the video input, and is CMOS or TTL compatible. PLL loop-compensation filter input.
HLOCK
7
CLAMP
8
VDD VRESET CLKDIV2 FIELDID VSS HRESET
9 10 11 12 13 14
FHIN FHOUT S0, S1
15 16 17, 18
CLKIN CLKOUT NTSC/PAL
19 20 21
GNDA CSYNC PLLFILTER
22 23 24
6
PRODUCT SPECIFICATION
RC6100
Absolute Maximum Ratings
(beyond which the device may be damaged)1 Parameter Power Supply Voltage (VCC) Input Voltage Operating Temperature Storage Temperature Junction Temperature Lead Soldering Temperature (10 sec) 0 -40 Min. Typ. Max. 7 70 125 150 300 Units V C C C C
VCC + 0.3V VIN GND - 0.3V
Note: 1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded.
Operating Conditions
Parameter qJA VCC ICC SO-24 thermal resistance Supply voltage Supply current 4.75 Min. Typ. 75 5.0 30 5.25 40 Max. Units C/W V mA
DC Electrical Characteristics
VCC = 5V, TA = 0 to 70C, unless otherwise specified. Symbol Logic Interface VIH VIL VOH VOL IIN VIN IIN HLOCK HLOCK Logic input high voltage Logic input low voltage Logic output high voltage Logic output low voltage Logic input current (VCC VIN GND) Composite video signal (AC coupled) Input current (VIN = VCC-1V) Lo @ 10mA HI 3.5 0.5 1.0 4 0.4 30 2.0 700 1.5 4 0.8 V V V V mA Vp-p mA V V Parameter Min. Typ. Max. Units
Analog Interface
7
RC6100
PRODUCT SPECIFICATION
AC Electrical Characteristics
VCC = 5V, TA = 0 to 70C, unless otherwise specified. Symbol VCS Parameter Composite sync amplitude Test Conditions Maintains lock with horizontal rate jitter THJ of <10 ns CVIN = 1 Vp-p + glitch; Glitch < 50 ns, Neg polarity, Voltage relative to blanking; Test for proper CSYNC output 4.5V < VCCA < 5.5V CVIN horizontal frequency = 15734 Hz nominal 500 750 750 750 300 fclk = 27 MHz 2.5@VCOin code 100 CVin=15.734KHz, Code 100, fclk=27MHz fin=15.734+500Hz to 15.625-500Hz 200 150 3.5 240 350 0.8 6 69 3.0 74 89 4.5 1 12 Min 150 Typ Max 600 Units mVp-p
VIN
Impulse noise immunity
0.3
V
fCLOCK DHFOUT/ DVCC HFPULL tPD (VCS) tPD (VHS) tPD (HCG) tDHS tDCG fclk jitter
Clock range VCO power supply rejection rate HFOUT = 27 MHz PLL Lock/Hold in Range code 100 Video in to CSYNC delay Video in to HRESET delay H sync to CLAMPgate delay Duration of HRESET reset Duration of CLAMPgate DC=2.5v@PLL filter Closed loop Capture Range
12.273
27.0 3.5
MHz %/V Hz Hz ns ns ns ns ms ns ns Hz mA V V
PLLFilter CLDIV
Sink/source current VOL @ 4mA VOH
Typical Application
Figure 6 shows the RC6100 Horizontal Line Genlock used in a video signal-processing system. The part provides the clock that is required to synchronize the various elements of the system. Note that the clamp gate output of the RC6100 is applied to the convert input of the TMC1175 ADC.
VIDEO INPUT 75W
BUFFER
ANTI-ALIASING LOW PASS FILTER3 CONV
18 ADC
DSP SYSTEM
8
DAC
2
SMOOTHING RECONSTRUCTION FILTER3
75W DRIVER
VIDEO OUTPUT
SYSTEM SAMPLE CLOCK Note: 1. Raytheon TMC1175A 2. Raytheon TDC3310 3. Raytheon RC6601
65-6100-08
CVIN
GENLOCK
CLKOUT
RC6100
Figure 6. Application of RC6100 with TMC1175 and TDC3310 in Video Processing System
8
PRODUCT SPECIFICATION
RC6100
Application Circuit with Minimum Parts
CVIN
C9 10F C8 10F
+5V
L1 12H (3) R1 C1 4.68K 8.64nF VDD C2 864nF (2)
C4 0.1F C3 C6 0.1F (1) .01F
1
CVIN FILOUT FILTIN HLCAP VCC VSYNC HLOCK
PLLFILT CSYNC GNDA NTSC CLKOUT CLKIN
24
RC6100
S1 S0 FHOUT FHIN HRESET VSS 13 (2)
65-6100-09
C7 0.1F DECOUPLING
CLAMP (1) VDD VDD VRESET CLKDIV2 12 FIELDID
Notes: 1. Use a separate trace to each power pin and place capacitors C6 and C7 next to part. 2. Use separate ground plane for digital signals and PLL signals.
DIGITAL PLL
3. Place PLL filter components as close as possible to pin 24. Code 110.
9
RC6100
PRODUCT SPECIFICATION
Hook-up for Internal Filter
INPUT VIDEO
C9 10F C8 10F
+5V
75
L1 12H
C4 0.1F C3 .01F (1)
1
CVIN FILOUT FILTIN HLCAP VCC VSYNC HLOCK
PLLFILT CSYNC GNDA NTSC CLKOUT CLKIN
24
(3) R1 C1 4.68K 8.64nF VDD 1 C2 864nF (2) 2 to other devices 74ALS1034 (4) 1 2 to connect to CLKIN 74ALS1034
C5 1.0F C6 0.1F
RC6100
S1 S0 FHOUT FHIN HRESET VSS 13 (2)
C7 0.1F DECOUPLING
CLAMP (1) VDD VDD VRESET CLKDIV2 12 FIELDID
65-6100-10
1. Use a separate trace to each power pin and place capacitors C6 and C7 next to part. 2. Use separate ground plane for digital signals and PLL signals.
DIGITAL PLL
3. Place PLL filter components as close as possible to pin 24. 4. CLKOUT should be buffered for large trace runs or large fanout. Break CLKOUT, CLKIN, SHORT, and add buffers as shown.
10
PRODUCT SPECIFICATION
RC6100
Mechanical Dimensions - 24 Pin SOIC Package
Symbol A A1 B C D E e H h L N a ccc Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
.093 .104 .004 .012 .013 .020 .009 .013 .599 .614 .290 .299 .050 BSC .394 .419 .010 .016 24 0 -- 8 .004 .020 .050
2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 15.20 15.60 7.36 7.60 1.27 BSC 10.00 10.65 0.25 0.40 24 0 -- 8 0.10 0.51 1.27
3 6
24
13
E
H
1
12
D A e B A1 SEATING PLANE -C- LEAD COPLANARITY ccc C a L
h x 45 C
11
PRODUCT SPECIFICATION
RC6100
Ordering Information
Product Number RC6100M Temperature Range 0C to +70C Screening Commercial Package 24 Pin Wide SOIC Package Marking RC6100M
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS30006100 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
Embedded Secure Document
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RC6302
Dual Video Amplifier
Features
* * * * * * * * * * * Unity gain stable 70 MHz -3 dB Bandwidth 20 MHz 0.1 dB gain flatness 0.06% differential gain (RL = 150W) 0.06 differential phase (RL = 150W) High CMRR (100dB), High PSRR (80 dB) Dual 5V power supply Low offset 1.0 mV 8-pin narrow SO package 160 V/ms slew rate Fast settling time: 0.1% in 35 ns
Applications
* Video amplifier * Video instrumentation amplifier * Active filter
Description
The RC6302 consists of two low power, wide band voltage feedback operational amplifiers. Each channel is capable of delivering a load current of at least 35mA. The amplifiers are optimized for video applications where low differential gain and low phase distortion are significant requirements.
Block Diagram
RC6302
OUT1 IN1- IN1+ VEE VCC OUT2 IN2- IN2+
65-7481
Rev. 1.0.0
PRODUCT SPECIFICATION
RC6302
Pin Assignments
OUT1 IN1- IN1+ VEE
1 2 3 4 8 7 6 5
65-3402-01
Pin Definitions
VCC OUT2 IN2- IN2+
Pin Name IN1- IN1+ IN2- IN2+ OUT1 OUT2 VEE VCC
Pin Number 2 3 6 5 1 7 4 8
Pin Function Description Amplifier 1 inverting input Amplifier 1 non-inverting input Amplifier 2 inverting input Amplifier 2 non-inverting input Amplifier 1 output Amplifier 2 output Negative supply voltage Positive supply voltage
Absolute Maximum Ratings
(beyond which the device may be damaged)1 Parameter Positive power supply, VCC Negative power supply, VEE Differential input voltage Operating Temperature Storage Temperature Junction Temperature Lead Soldering Temperature (10 seconds) Operating Temperature 0 Short circuit tolerance: No more than one output can be shorted to ground.
Note: 1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded.
Min
Typ
Max 7 -7 10
Units V V V C C C C C
0 -40
+70 +125 150 300 +70
Operating Conditions
Parameter VCC VEE qJA Power Supply Voltage Negative Supply Voltage SO8 Thermal Resistance Min 4.75 -4.75 Typ 5.0 -5.0 140 Max 5.25 -5.25 Units V V C/W
2
RC6302
PRODUCT SPECIFICATION
DC Electrical Characteristics
VCC = 5V, VEE = -5V, AV = 2, TA = 0C to 70C, RLOAD = 150W, unless otherwise specified. Parameter VOS DVOS/DT IB DIB/DT RIN CIN CMIR CMRR PSRR Is ROUT IOUT VOUT AVOL Input Offset Voltage Offset Voltage Drift Input Bias Current Input Bias Current Drift Input Resistance1 Input Capacitance1 Common Mode Input Range Common Mode Rejection Ratio Power Supply Rejection Ratio Quiescent Supply Current Output Impedance1 Output Current Output Voltage Swing Open-loop Gain No Load RL=150W
Note: 1. Guaranteed by design.
1 1
Conditions No load
Min
Typ 1.0 6.0 1.0 8.0
Max 5 50 5 50 2
Units mV mV/C mA nA/C MW pF V dB dB
1 0.5 2.5 No Load No Load No Load, Whole IC At DC 2.5 2.5 58 70 60 100 80 15 0.2 35 3.0 3.0 68 25
mA W mA V V dB
1-3
PRODUCT SPECIFICATION
RC6302
AC Electrical Characteristics
VCC = 5V, VEE = -5V, RLOAD = 150W, RG = RF = 250W, AV = 2, TA = 0 to 70C, CL = 10 pF, CF = 3 pF unless otherwise specified. Closed Loop. See Typical Test Circuit. Parameter Frequency Response BW Flat Peak XTALK tr1, tf1 ts OS US SR Distortion HD2 HD3 NF SND DG DP 2nd Harmonic Dist. @ 20 MHz1 VOUT = 0.8 Vpp 3nd Harmonic Dist. @ 20 MHz1 VOUT = 0.8 Vpp Noise Floor > 100 KHz1 Spectral Noise Density1 100 kHz to 200 MHz RL = 150W, VOUT = 1.5V RL = 150W, VOUT = 1.5V -50 -50 -140 10 0.06 0.06 dB dB dBm nV/OHz % Deg. -3 dB Bandwidth (AV = 2)1 0.1 dB Bandwidth
1
Conditions VOUT = 0.4 Vpp VOUT = 0.8 Vpp
Min
Typ 70 55
Max
Units MHz MHz MHz DB dB
15
20 0.3
Maximum Small Signal AC Peaking Crosstalk Isolation1 Rise and Fall Time 10% to 90%1 Settling Time to 0.1 %1 Overshoot1 Undershoot1 Slew Rate1 @ 5 MHz 2V Output Step 2V Output Step 2V Output Step 2V Output Step VOUT = 2.0V
60 6 35 13 4 160 8
Time Domain Response ns ns % % V/ms
Equivalent Input Noise
Video Performance Diff. Gain (p-p), NTSC & PAL1 Diff. Phase (p-p), NTSC & PAL1
Note: 1. Guaranteed by design.
4
RC6302
PRODUCT SPECIFICATION
Applications Discussion
Capacitive Load
The RC6302 can drive a capacitive load from 10 to over 100 pF. In back terminated video applications, bandwidth will only be limited by the RC time constants of the external output components. A minimum 10 pF capacitive load is required. When driving a 75W cable, place the 75W source termination resistor as close to the amplifier output as possible.
Feedback Components
Because the RC6302 is a voltage-feedback amplifier, it facilitates using reactive (capacitive and inductive) feedback components for implementing filters, integrators, sample/ hold circuits, etc. The feedback network and the parasitic capacitance at the inverting (summing junction) input create a pole and affect the transfer function of the circuit. For stable operation, minimize the parasitic capacitance and equivalent resistance of the components used in the feedback circuit.
DC Accuracy
Since the RC6302 is a voltage-feedback amplifier, the inverting and non-inverting inputs have similar impedances and bias currents. To minimize offset voltage, match the source resistances seen by inverting and non-inverting inputs.
Circuit Board
High-frequency applications require good grounding, power supply decoupling, low parasitic capacitance and inductance, and good isolation between the three inputs to minimize their crosstalk. Minimal coupling from output to input should exist to prevent positive feedback.
Typical Test Circuit
Video Input RI 250W 1/2 RC6302 RS 75W
Video Output 10 pF CL
RL 75W
RF 250W
RLOAD = RL + RS
65-7482A
5
PRODUCT SPECIFICATION
RC6302
Mechanical Dimensions - 8-Lead SOIC Package
Symbol A A1 B C D E e H h L N a ccc Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
.053 .069 .004 .010 .013 .020 .008 .010 .189 .197 .150 .158 .050 BSC .228 .010 .016 8 0 -- 8 .004 .244 .020 .050
1.35 1.75 0.10 0.25 0.33 0.51 0.20 0.25 4.80 5.00 3.81 4.01 1.27 BSC 5.79 0.25 0.40 8 0 -- 8 0.10 6.20 0.50 1.27
3 6
8
5
E
H
1
4
D A1 A SEATING PLANE B -C- LEAD COPLANARITY ccc C a
h x 45 C
e
L
6
PRODUCT SPECIFICATION
RC6302
Ordering Information
Product Number RC6302M8 Temperature Range 0 to 70C Screening Commercial Package 8 Pin Narrow SOIC Package Marking RC6302M8
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS30006302 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC6303
Triple Video Amplifier
with Separate Enable Inputs Features
* * * * * * * * * * * * * * Triple video amplifier Independently enabled amplifiers 90 MHz -3 dB Bandwidth (AV = 2) 20 MHz 0.1 dB gain flatness Stable at AV 2 0.06% differential gain (AV = 2, RL = 150W) 0.06 differential phase (AV = 2, RL = 150W) High CMRR (100dB), High PSRR (80 dB) Dual 5V power supply Low offset 1.0 mV 16-pin narrow SO package 300 V/ms slew rate Fast settling time: 0.1% in 35 ns TTL or CMOS compatible enable inputs
Applications
* * * * * * RGB amplifier 3:1 crosspoint switch RGB switch Video instrumentation amplifier Selectable gain amplifier Active filter
Description
The RC6303 consists of three low power, wide band voltage feedback operational amplifiers. Each channel is capable of delivering a load current of at least 35mA. Each amplifier can be independently enabled or disabled with a TTL or CMOS signal. When disabled, the amplifier is in a high impedance output state, presenting a very high input to output isolation. The amplifiers are optimized for video applications with gain 2 where low differential gain and low phase distortion are significant requirements. The layout is optimized for minimal crosstalk between amplifiers.
Block Diagram
RC6303
VCC VCCO VEE VEEO OUT1 IN1+ + EN1 IN2- IN2+ - OUT2 + EN2 IN3- IN3+ - OUT3 + EN3
65-3399-01
IN1-
-
Rev. 1.0.0
RC6303
PRODUCT SPECIFICATION
Pin Assignments
IN1- IN1+ VCC IN2- IN2+ VEE IN3- IN3+
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
65-3399-03
Pin Definitions
VCCO OUT1 EN1 OUT2 EN2 OUT3 EN3 VEEO
Pin Name EN1 EN2 EN3 IN1- IN1+ IN2- IN2+ IN3- IN3+ OUT1 OUT2 OUT3 VCC VCCO VEE VEEO
Pin Number 14 12 10 1 2 4 5 7 8 15 13 11 3 16 6 9
Pin Function Description Enables amplifier 1 when low Enables amplifier 2 when low Enables amplifier 3 when low Amplifier 1 inverting input Amplifier 1 non-inverting input Amplifier 2 inverting input Amplifier 2 non-inverting input Amplifier 3 inverting input Amplifier 3 non-inverting input Amplifier 1 output Amplifier 2 output Amplifier 3 output Analog positive supply Positive supply for output stages Analog negative supply Negative supply for output stages
Absolute Maximum Ratings
(beyond which the device may be damaged)1 Parameter Positive power supply, VCC Negative power supply, VEE Differential input voltage Operating Temperature Storage Temperature Junction Temperature Lead Soldering Temperature (10 seconds) Short circuit tolerance: No more than one output can be shorted to ground.
Note: 1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded.
Min
Typ
Max 7 -7 10
Units V V V C C C C
0 -40
+70 +125 150 300
Operating Conditions
Parameter VCC VEE qJA Power Supply Voltage Negative Supply Voltage SO16 thermal resistance Min 4.75 -4.75 Typ 5.0 -5.0 105 Max 5.25 -5.25 Units V V C/W
2
PRODUCT SPECIFICATION
RC6303
DC Characteristics
VCC = 5V, VEE = -5V, AV = 2, RLOAD = 150W, TA = 0C to 70C, unless otherwise specified. Open Loop. Parameter VOS DVOS/DT IB DIB/DT Rin Cin CMIR CMRR PSRR Is Isd ROUT COUT IOUT VOUT AVOL Venh Venl Ien toff ton Iso Input Offset Voltage Offset Voltage Drift Input Bias Current Input Bias Current Drift1 Input Resistance1 Input Capacitance
1 1
Conditions No Load
Min
Typ 1.0 6.0 1.0 8.0
Max 5 50 5 50 2
Units mV mV/C mA nA/C MW pF V dB dB
1 0.5 2.5 No Load No Load No Load, Whole IC Enabled, At DC Disabled, VO = 2V Disabled 35 No Load RL = 150W 2.5 2.5 58 2.4 0.8 3 200 Settling to 1% @ 5 MHz 160 60 10 3.0 3.0 68 10 70 60 100 80 25 3 0.2 200 0.5 2 33 4
Common Mode Input Range Common Mode Rejection Ratio Power Supply Rejection Ratio Quiescent Supply Current Supply Current Disabled Output Impedance (Closed Loop) 1 Output Capacitance1 Output Current Output Voltage Swing Open-loop Gain Enable High Voltage Enable Low Voltage Enable Input Current Disable Time Enable Time
1 1
mA mA W kW pF mA V V dB V V mA ns ns dB
Off Isolation (Input to Output)1
Note: 1. Guaranteed by design.
3
PRODUCT SPECIFICATION
RC6303
AC Characteristics
VCC = 5V, VEE = -5V, AV = 2, TA = 0 to 70C, RLOAD = 150W, RG = RF = 250W, CL = 10 pF, CF = 3 pF unless otherwise specified. Closed Loop. See Typical Test Circuit. Parameter Frequency Response BW Flat Peak XTALK tr1, tf1 ts OS US SR HD2 HD3 NF SND DG DP -3 dB Bandwidth (AV = 2)1 0.1 dB Bandwidth
1
Conditions VOUT = 0.4 Vpp VOUT = 0.8 Vpp
Min
Typ 90
Max
Units MHz MHz MHz dB dB
70 15
85 20 0.3
Maximum Small Signal AC Peaking1 Crosstalk Isolation1 Rise and Fall Time 10% to 90%1 Settling Time to 0.1 % Overshoot1 Undershoot1 Slew Rate1
1
@ 5 MHz 2V Output Step 2V Output Step 2V Output Step 2V Output Step VOUT = 2.0V VOUT = 0.8 Vpp VOUT = 0.8 Vpp 200
60 6 35 13 4 300 -50 -50 -140 8
Time Domain Response ns ns % % V/ms dB dB dBm nV/OHz % Deg.
Distortion 2nd Harmonic Dist. @ 20 MHz1 3nd Harmonic Dist. @ 20 MHz1 Noise Floor > 100 KHz1 Spectral Noise Density1 100 kHz to 200 MHz RL = 150W, VOUT = 1.5V RL = 150W, VOUT = 1.5V
Equivalent Input Noise 10 0.06 0.06
Video Performance Diff. Gain (p-p), NTSC & PAL1 Diff. Phase (p-p), NTSC & PAL1
Note: 1. Guaranteed by design.
Test Circuit
Video Input RG 250W CF 3pF + 1/3 RC6303 - RL 75W 10 pF CL RS 75W Video Output
RF 250W
RLOAD = RL + RS
65-3399-02
4
PRODUCT SPECIFICATION
RC6303
Applications Discussion
Each of the three sections of the RC6303 is provided with an Enable input, thus the part is useful for selecting and multiplexing. A three-channel video multiplexer can be built with just one RC6303 and a decoder, as shown in Figure 1. Note that RC6303 enable time is shorter than its disable time, hence a make-before-break action is provided, minimizing switching transients on the signal output. An RGB switch is shown in Figure 2.
Circuit Board
High-frequency applications require good grounding, power supply decoupling, low parasitic capacitance and inductance, and good isolation between the inputs to minimize their crosstalk. Avoid coupling from output to input to prevent positive feedback.
Channel 1 Input
- + R
Capacitive Load
The RC6303 can drive a capacitive load from 10 to over 100 pF. In back terminated video applications, bandwidth will only be limited by the RC time constants of the external output components. A minimum 10 pF capacitive load is required. When driving a 75W cable, place the 75W source termination resistor as close to the amplifier output as possible.
Channel 2 Input
- + G Output
Channel 3 Input
- + B
Decoder
65-7460
Enable/Disable
The enable pins (10, 12, 14), when pulled to a TTL or CMOS logic low or when tied to ground, activate each amplifier individually. When pulled to a TTL or CMOS logic high, the amplifier is tri-stated and presents a high impedance at its output. When disabled the amplifier's power consumption drops, and the non-inverting input signal is isolated from its respective output.
Figure 1.
Video Busses RGB Channel a Red Input - R + - G + - B + - R + Channel b Red Input
DC Accuracy
Since the RC6303 is a voltage-feedback amplifier, the inverting and non-inverting inputs have similar impedances and bias currents. To minimize offset voltage, match the source resistances seen by inverting and non-inverting inputs.
Channel a Green Input
- G +
Channel b Green Input
Feedback Components
Because the RC6303 is a voltage-feedback amplifier, it facilitates using reactive (capacitive and inductive) feedback components for implementing filters, integrators, sample/ hold circuits, etc. The feedback network and the parasitic capacitance at the inverting (summing junction) input create a pole and affect the transfer function of the circuit. For stable operation, minimize the parasitic capacitance and equivalent resistance of the components used in the feedback circuit.
Channel a Blue Input Channel Select
- B +
Channel b Blue Input
74LS04
65-7461
Figure 2.
5
RC6303
PRODUCT SPECIFICATION
Notes:
6
RC6303
PRODUCT SPECIFICATION
Mechanical DImensions - 16-Lead SOIC Package
Symbol A A1 B C D E e H h L N a ccc Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
.053 .069 .004 .010 .013 .020 .008 .010 .386 .394 .150 .158 .050 BSC .228 .010 .016 16 0 -- 8 .004 .244 .020 .050
1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 9.80 10.00 3.81 4.00 1.27 BSC 5.80 0.25 0.40 16 0 -- 8 0.10 6.20 0.50 1.27
3 6
16
9
E
H
1
8
D A1 A SEATING PLANE -C- LEAD COPLANARITY ccc C a
h x 45 C
e
B
L
7
RC6303
PRODUCT SPECIFICATION
Ordering Information
Product Number RC6303M Temperature Range 0 to 70C Screening Commercial Package 16 Pin Narrow SOIC Package Marking RC6303M
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS30006303 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC6333
Triple Video Amplifier
Features
* * * * * * * * * * * * * Triple video amplifier 175 MHz -3 dB Bandwidth (AV = 2) 50 MHz 0.1 dB gain flatness Unity gain stable 0.06% differential gain (AV = 1, RL = 150W) 0.06 differential phase (AV = 1, RL = 150W) High CMRR (95dB), High PSRR (80 dB) Dual 5V power supply Low offset 3.0 mV typical 14-pin narrow SO package 250V/ms slew rate Fast settling time: 0.1% in 15 ns TTL or CMOS compatible
Applications
* * * * * RGB amplifiers Video instrumentation amplifier Selectable gain amplifier Active filters Set-top Buffers/Drivers
Description
The RC6333 consists of three low power, wide band voltage feedback operational amplifiers. Each channel is capable of delivering a load current of at least 35mA. The amplifiers are optimized for video applications where low differential gain and low phase distortion are significant requirements.
Block Diagram
RC6333
OUT2
- +
IN2IN2+
VCC +
65-3528-01
VEE IN3+ + -
IN1+
IN1- OUT1
-
IN3-
OUT3
Rev. 1.0.1
PRODUCT SPECIFICATION
RC6333
Pin Assignments
RC6333
NC NC NC VCC IN1+ IN1- OUT1
1 2 3 4 5 6 7 14 13 12 11 10 9 8
65-3528-02
Pin Definitions
Pin Name
OUT2 IN2- IN2+ VEE IN3+ IN3- OUT3
Pin Number 6 5 13 12 9 10 1-3 7 14 8 4 11
Pin Function Description Amplifier 1 inverting input Amplifier 1 non-inverting input Amplifier 2 inverting input Amplifier 2 non-inverting input Amplifier 3 inverting input Amplifier 3 non-inverting input Not Connected. Amplifier 1 output Amplifier 2 output Amplifier 3 output Analog positive supply Analog negative supply
IN1- IN1+ IN2- IN2+ IN3- IN3+ NC OUT1 OUT2 OUT3 VCC VEE
Absolute Maximum Ratings
(beyond which the device may be damaged)1 Parameter VCC VEE Positive power supply Negative power supply Differential input voltage Operating Temperature Storage Temperature Junction Temperature Lead Soldering (10 seconds) Short circuit tolerance: No more than one output can be shorted to ground.
Notes: 1. Functional operation under any of these conditions is NOT implied.
Min
Typ
Max 7 -7 10
Units V V V C C C C
0 -40
+70 125 150 240
Operating Conditions
Parameter VCC VEE qJA Power Supply Voltage Negative Supply Voltage SO14 Thermal Resistance Min 4.75 -4.75 Typ 5.0 -5.0 105 Max 5.25 -5.25 Units V V C/W
2
RC6333
PRODUCT SPECIFICATION
DC Characteristics
VCC = 5V, VEE = -5V, AV = 2, RLOAD = 150W, TA = 0C to 70C, unless otherwise specified. Open Loop. Parameter VOS IB DIB/DT Rin Cin CMIR CMRR PSRR Is ROUT IOUT VOUT AVOL Input Offset Voltage
1
Conditions No Load
Min
Typ 3 6 1 8
Max 10 30 5 40 2
Units mV mV/C mA nA/C MW pF V dB dB
DVOS/DT Offset Voltage Drift Input Bias Current
Input Bias Current Drift1 Input Resistance1 Input Capacitance
1
1 0.5 2.5 No Load No Load No Load Loop)1 Enabled, At DC Per Amplifier No Load RL = 150W 35 2.5 2.5 60 3.0 3.0 75 70 65 100 80 26 0.2 40
Common Mode Input Range Common Mode Rejection Ratio Power Supply Rejection Ratio Quiescent Supply Current Output Impedance (Closed Output Current Output Voltage Swing Open-loop Gain
mA W mA V V dB
Note: 1. Guaranteed by design.
AC Characteristics
Parameter Frequency Response BW Flat Peak XTALK tr1, tf1 ts OS US SR HD2 HD3 DG DP NF
VCC = 5V, VEE = -5V, AV = 2, TA = 0 to 70C, RLOAD = 150W, RG = RF = 250W, CL = 10 pF, unless otherwise specified. Closed Loop. Guaranteed by Design. See Typical Test Circuit. Conditions VOUT = 0.4 Vpp VOUT = 0.8 Vpp 0.1 dB Bandwidth Maximum Small Signal AC Peaking Crosstalk Isolation Rise and Fall Time 10% to 90% Settling Time to 0.1% Overshoot Undershoot Slew Rate 2nd Harmonic Dist. @ 20 MHz 3nd Harmonic Dist. @ 20 MHz Diff. Gain (p-p), NTSC & PAL Diff. Phase (p-p), NTSC & PAL Noise Floor VOUT = 0.4 Vpp VOUT = 0.8 Vpp @ 5 MHz 2V Output Step 2V Output Step 2V Output Step 2V Output Step VOUT = 2.0V VOUT = 0.8 Vpp VOUT = 0.8 Vpp RL = 150W, VOUT = 1.5V RL = 150W, VOUT = 1.5V >100kHz 200 75 50 Min Typ +175 90 75 0.01 50 10 15 5 2 250 -48 -56 0.06 0.06 -130 15 Max Units MHz MHz MHz dB dB ns ns % % V/ms dB dB % Deg. dB rms 3
-3 dB Bandwidth (AV = 2)
Time Domain Response
Distortion
Video Performance
PRODUCT SPECIFICATION
RC6333
Test Circuit
Video Input RG 250W 1/3 RC6333 RS 75W Video Output 10 pF CL
RL 75W
RF 250W
RLOAD = RL + RS
65-3528-04
Applications Discussion
Capacitive Load
The RC6333 can drive a capacitive load from 10 to over 50 pF. In back terminated video applications, bandwidth will only be limited by the RC time constants of the external output components. When driving a 75W cable, place the 75W source termination resistor as close to the amplifier output as possible.
Feedback Components
Because the RC6333 is a voltage-feedback amplifier, it facilitates using reactive (capacitive and inductive) feedback components for implementing filters, integrators, sample/ hold circuits, etc. The feedback network and the parasitic capacitance at the inverting (summing junction) input create a pole and affect the transfer function of the circuit. For stable operation, minimize the parasitic capacitance and equivalent resistance of the components used in the feedback circuit.
DC Accuracy
Since the RC6333 is a voltage-feedback amplifier, the inverting and non-inverting inputs have similar impedances and bias currents. To minimize offset voltage, match the source resistances seen by inverting and non-inverting inputs.
Circuit Board
High-frequency applications require good grounding, power supply decoupling, low parasitic capacitance and inductance, and good isolation between the inputs to minimize their crosstalk. Avoid coupling from output to input to prevent positive feedback.
4
RC6333
PRODUCT SPECIFICATION
Notes:
5
PRODUCT SPECIFICATION
RC6333
Notes:
6
RC6333
PRODUCT SPECIFICATION
Mechanical Dimensions - 14 Pin SOIC Package
Symbol A A1 B C D E e H h L N a ccc Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
.053 .069 .004 .010 .013 .020 .008 .010 .336 .345 .150 .158 .050 BSC .228 .244 .010 .016 14 0 -- 8 .004 .020 .050
1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 8.54 8.76 3.81 4.01 1.27 BSC 5.79 6.20 0.25 0.40 14 0 -- 8 0.10 0.50 1.27
3 6
14
8
E
H
1
7
D A1 A SEATING PLANE -C- LEAD COPLANARITY ccc C a
h x 45 C
e
B
L
7
PRODUCT SPECIFICATION
RC6333
Ordering Information
Product Number RC6333M Temperature Range 0 to 70C Screening Commercial Package 14 Pin Narrow SOIC Package Marking RC6333M
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS30006333 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC6334
Quad Video Amplifier
Features
* * * * * * * * * * * * * Quad video amplifier 175 MHz -3 dB Bandwidth (AV = 2) 50 MHz 0.1 dB gain flatness Unity gain stable 0.06% differential gain (AV = 1, RL = 150W) 0.06 differential phase (AV = 1, RL = 150W) High CMRR (95dB), High PSRR (80 dB) Dual 5V power supply Low offset 3.0 mV typical 14-pin narrow SO package 250V/ms slew rate Fast settling time: 0.1% in 15 ns TTL or CMOS compatible
Applications
* * * * * RGB amplifiers Video instrumentation amplifier Selectable gain amplifier Active filters Set-top box Buffers/Drivers
Description
The RC6334 consists of four low power, wide band voltage feedback operational amplifiers. Each channel is capable of delivering a load current of at least 35mA. The amplifiers are optimized for video applications where low differential gain and low phase distortion are significant requirements.
Block Diagram
RC6334
OUT4 OUT2
IN4-
- +
- +
IN2- IN2+ VEE IN3+
IN4+ VCC +
65-3527-01
IN1- OUT1
-
-
+
IN1+
IN3-
OUT3
Rev. 1.0.1
PRODUCT SPECIFICATION
RC6334
Pin Assignments
RC6334
OUT4 IN4- IN4+ VCC IN1+ IN1- OUT1
1 2 3 4 5 6 7 14 13 12 11 10 9 8
65-3527-02
Pin Definitions
Pin Name
OUT2 IN2- IN2+ VEE IN3+ IN3- OUT3
Pin Number 6 5 13 12 9 10 2 3 7 14 8 1 4 11
Pin Function Description Amplifier 1 inverting input Amplifier 1 non-inverting input Amplifier 2 inverting input Amplifier 2 non-inverting input Amplifier 3 inverting input Amplifier 3 non-inverting input Amplifier 4 inverting input Amplifier 4 non-inverting input Amplifier 1 output Amplifier 2 output Amplifier 3 output Amplifier 4 output Analog positive supply Analog negative supply
IN1- IN1+ IN2- IN2+ IN3- IN3+ IN4- IN4+ OUT1 OUT2 OUT3 OUT4 VCC VEE
Absolute Maximum Ratings
(beyond which the device may be damaged)1 Parameter VCC VEE Positive power supply Negative power supply Differential input voltage Operating Temperature Storage Temperature Junction Temperature Lead Soldering (10 seconds) Short circuit tolerance: No more than one output can be shorted to ground.
Notes: 1. Functional operation under any of these conditions is NOT implied.
Min
Typ
Max 7 -7 10
Units V V V C C C C
0 -40
+70 125 150 240
Operating Conditions
Parameter VCC VEE qJA Power Supply Voltage Negative Supply Voltage SO14 Thermal Resistance Min 4.75 -4.75 Typ 5.0 -5.0 105 Max 5.25 -5.25 Units V V C/W
2
RC6334
PRODUCT SPECIFICATION
DC Characteristics
VCC = 5V, VEE = -5V, AV = 2, RLOAD = 150W, TA = 0C to 70C, unless otherwise specified. Open Loop. Parameter VOS IB DIB/DT Rin Cin CMIR CMRR PSRR Is ROUT IOUT VOUT AVOL Input Offset Voltage
1
Conditions No Load
Min
Typ 3 6 1 8
Max 10 30 5 40 2
Units mV mV/C mA nA/C MW pF V dB dB
DVOS/DT Offset Voltage Drift Input Bias Current
Input Bias Current Drift1 Input Resistance1 Input Capacitance
1
1 0.5 2.5 No Load No Load No Load Loop)1 Enabled, At DC Per Amplifier No Load RL = 150W 35 2.5 2.5 60 3.0 3.0 75 70 65 100 80 33 0.2 48
Common Mode Input Range Common Mode Rejection Ratio Power Supply Rejection Ratio Quiescent Supply Current Output Impedance (Closed Output Current Output Voltage Swing Open-loop Gain
mA W mA V V dB
Note: 1. Guaranteed by design.
AC Characteristics
VCC = 5V, VEE = -5V, AV = 2, TA = 0 to 70C, RLOAD = 150W, RG = RF = 250W, CL = 10 pF, unless otherwise specified. Closed Loop. Guaranteed by Design. See Typical Test Circuit. Parameter Frequency Response BW Flat Peak XTALK tr1, tf1 ts OS US SR HD2 HD3 DG DP NF -3 dB Bandwidth (AV = 2) 0.1 dB Bandwidth Maximum Small Signal AC Peaking Crosstalk Isolation Rise and Fall Time 10% to 90% Settling Time to 0.1% Overshoot Undershoot Slew Rate 2nd Harmonic Dist. @ 20 MHz 3nd Harmonic Dist. @ 20 MHz Diff. Gain (p-p), NTSC & PAL Diff. Phase (p-p), NTSC & PAL Noise Floor VOUT = 0.4 Vpp VOUT = 0.8 Vpp VOUT = 0.4 Vpp VOUT = 0.8 Vpp @ 5 MHz 2V Output Step 2V Output Step 2V Output Step 2V Output Step VOUT = 2.0V VOUT = 0.8 Vpp VOUT = 0.8 Vpp RL = 150W, VOUT = 1.5V RL = 150W, VOUT = 1.5V >100kHz 200 75 50 +175 90 60 0.01 50 10 15 5 2 250 -48 -56 0.06 0.06 -130 15 MHz MHz MHz dB dB ns ns % % V/ms dB dB % Deg. dB rms 3 Conditions Min Typ Max Units
Time Domain Response
Distortion
Video Performance
PRODUCT SPECIFICATION
RC6334
Test Circuit
Video Input RG 250W 1/4 RC6334 RS 75W Video Output 10 pF CL
RL 75W
RF 250W
RLOAD = RL + RS
65-3527-04
Applications Discussion
Capacitive Load
The RC6334 can drive a capacitive load from 10 to over 50 pF. In back terminated video applications, bandwidth will only be limited by the RC time constants of the external output components. When driving a 75W cable, place the 75W source termination resistor as close to the amplifier output as possible.
Feedback Components
Because the RC6334 is a voltage-feedback amplifier, it facilitates using reactive (capacitive and inductive) feedback components for implementing filters, integrators, sample/ hold circuits, etc. The feedback network and the parasitic capacitance at the inverting (summing junction) input create a pole and affect the transfer function of the circuit. For stable operation, minimize the parasitic capacitance and equivalent resistance of the components used in the feedback circuit.
DC Accuracy
Since the RC6334 is a voltage-feedback amplifier, the inverting and non-inverting inputs have similar impedances and bias currents. To minimize offset voltage, match the source resistances seen by inverting and non-inverting inputs.
Circuit Board
High-frequency applications require good grounding, power supply decoupling, low parasitic capacitance and inductance, and good isolation between the inputs to minimize their crosstalk. Avoid coupling from output to input to prevent positive feedback.
4
RC6334
PRODUCT SPECIFICATION
Notes:
5
PRODUCT SPECIFICATION
RC6334
Notes:
6
RC6334
PRODUCT SPECIFICATION
Mechanical Dimensions - 14 Pin SOIC Package
Symbol A A1 B C D E e H h L N a ccc Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
.053 .069 .004 .010 .013 .020 .008 .010 .336 .345 .150 .158 .050 BSC .228 .244 .010 .016 14 0 -- 8 .004 .020 .050
1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 8.54 8.76 3.81 4.01 1.27 BSC 5.79 6.20 0.25 0.40 14 0 -- 8 0.10 0.50 1.27
3 6
14
8
E
H
1
7
D A1 A SEATING PLANE -C- LEAD COPLANARITY ccc C a
h x 45 C
e
B
L
7
PRODUCT SPECIFICATION
RC6334
Ordering Information
Product Number RC6334M Temperature Range 0 to 70C Screening Commercial Package 14 Pin Narrow SOIC Package Marking RC6334M
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS30006334 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC6505
Differential IF Front-End
Features
* * * * * * * * * * Integrated Analog IF Front-End Fully differential I/O IF flat bandwidth from 25 MHz to 55 MHz 48dB minimum gain at IF frequency Simple interface to SAW filter 9dB input noise figure Direct interface to A/D converter XTAL oscillator operating to 80MHz More than 50dB IMD3 Industry standard 24-lead SOIC package
Description
The RC6505 incorporates IF gain stages, reference generators and a crystal oscillator on a single chip. The high input impedance enables direct interface to a SAW filter, while maintaining a low noise figure. The IF output can be further filtered externally and fed to the on-chip fully differential buffer/driver. This buffer is extremely useful when driving low impedance terminations like a differential input to an A/D. The RC6505 is specially suited in IF sampling applications for minimizing the parts count and thus achieving smaller board sizes and lower system costs. The IF section works on a 12V supply voltage. The oscillator section runs on 5V supply. The RC6505 is available in a 24 Lead SOIC package.
Preliminary Information
Applications
* * * * * * IF sampling decoders QAM Receivers (up to 256 Constellations) Set-top receivers for digital cable Internet surf boards Cable modems Desktop video Conferencing
Block Diagram
VCC_IF2 IF_OUT+ IF_OUT- GND_IF2 VCC_RF XTL2 XTL1
VCC_IF1 IF_IN+ IFA1 IF_INAv=26 GND_IF1 3.25V Ref + OPA BUF_INBandGap Ref Buffer Av=1.5 BUF_IN+ Av=10 400uA Iref IFA2 XTL OSC XOSCOA Translator RFGND
OUT
INP
VRT
VCC_BUF GND_BUF
BUF_OUT+
BUF_OUT65-6505-01
Rev. 0.9.1
PRELIMINARY INFORMATION describes products that are not in full production at the time of printing. Specifications are based on design goals and limited characterization. They may change without notice. Contact Fairchild Semiconductor for current information.
RC6505
PRODUCT SPECIFICATION
Functional Description
The RC6505 as shown in the block diagram performs several analog signal processing typically required in modern wideband digital receivers. These include: * IF Sections * Bias Voltage Generation * Crystal Oscillator
This output can be filtered externally and fed back into the IC at pins BUF_IN+ & BUF_IN- to enhance the drive capability of the output and also to reduce any `kick-back' from the A/D sampling.
Bias Reference Voltage
The RC6505 has a built-in 3.25V references and an operational amplifier (OPA) with the ability to drive 10mA of load. The OPA will serve as a voltage follower to provide certain flexibility on application. Note that, the 3.25V reference has sourcing capability only.
IF Gain Section
The front end IF section provides greater than 48dB of stable gain at IF frequencies. The input has high impedance while maintaining a low noise figure. The input and output sections are on different supplies to minimize parasitic couplings and prevent oscillations. The differential signal fed at IF_IN + /IF_IN- is available at IF_OUT+ /IF_OUT- after amplification.
Crystal Oscillator
This section has a crystal oscillator that can be used to generate timing signals like an A/D clock. The output level of Crystal Oscillator will be TTL compatible at the XOSCOA terminal.
Preliminary Information
Pin Assignments
IF_INIF_IN+ OUT INP VRT GND_BUF BUF_OUT+ BUF_OUTVCC_BUF BUF_IN+ NC BUF_IN1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13
65-6505-02
VCC_IF1 NC GND_IF1 GND_IF2 IF_OUT+ IF_OUTVCCIF2 VCC_RF XTL2 XTL1 XOSCOA RFGND
Pin Descriptions
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 Pin Name IF_INIF_IN+ OUT INP VRT GND_BUF BUF_OUT+ BUF_OUTVCC_BUF BUF_IN+ NC BUF_INRFGND Description IF Input Complement. IF Input. Output of OPA. Non-Inverting Input of OPA. Output Reference Voltage for Top of A/D Input Range. Ground for Output Buffer. Differential Buffer/Driver Output. Differential Buffer/Driver Output Complement. Supply Voltage for Output Buffer. Differential Buffer/Driver Input. No Connect or Ground. Differential Buffer/Driver Input Complement. Ground for High Frequency Crystal Oscillator.
2
PRODUCT SPECIFICATION
RC6505
Pin Descriptions (continued)
Pin Number 14 15 16 17 18 19 20 21 22 23 24 Pin Name XOSCOA XTL1 XTL2 VCC_RF VCCIF2 IF_OUTIF_OUT+ GND_IF2 GND_IF1 NC VCC_IF1 Description Crystal Oscillator Output (TTL compatible). Crystal Oscillator Frequency Select Circuit Connection. Crystal Oscillator Feedback Pin. Supply Voltage for High Frequency Crystal Oscillator. Supply Voltage for IF Output Sections. IF Output Amplified, Complement. IF Output Amplified. Ground for Amplified IF Output. Ground for IF Input Section.
Preliminary Information
No Connect or Ground. Supply Voltage for IF Input Section.
Absolute Maximum Ratings (Beyond which the device may be damaged)1
Parameter VCC Vin Iin Tstg Tj
QJA
Description Supply Voltages ,VCC_IF1, VCC_IF2, VCC_BUF, VCC-RF Input Voltages IF_IN+, IF_IN-, BUF_IN+, BUF_IN-, XTL1, XTL2 Input Current (Power On or Off) Storage Temperature Junction Temperature SO24 Thermal Resistance 10 seconds No output can be shorted to ground
Min.
Typ.
Max. 13.5
Units V V mA C C C/W C
GND-0.3
VCC+0.3 10
-40 70
125 150 300
Lead soldering Short Circuit Tolerence
Note: 1. Functional Operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded.
Operating Conditions
Parameter VCC_IF1, VCC_IF2, VCC_BUF VCC_RF TA Description Supply Voltages Min. 8.5 Typ. 12 Max. 13 Units V
Supply Voltage Ambient Temperature
4.75 0
5 25
5.25 70
V C
3
RC6505
PRODUCT SPECIFICATION
DC Electrical Characteristics
VCC_RF = 5V; VCC_IF1, VCC_IF2, VCC_BUF = 12V; TA = 0 to 70C, unless otherwise specified. Parameter PW ICCIF1 + ICCIF2 ICCBUF Total Power Consumption IF Gain Stages total Supply Current Buffer Supply Current (Including 10mA allocated for Band-gap Reference and OPA) XTL OSC Supply Current Top Reference Output Voltage Output Drive of OPA Output Offset of OPA Input Bias Current of OPA Power Rejection Ratio of OPA Gain of OPA (Voltage Follower) Input Range of OPA Output Current Drive at IF_OUT+ and IF_OUTOutput Current Drive at BUF_OUT+ and BUF_OUTIFA DC Output Swing at IF_OUT+ and IF_OUT- (Differential) Buffer DC Output Swing at BUF_OUT+ and BUF_OUT- (Differential) High Level Output Voltage of XOSCOA Low Level Output Voltage of XOSCOA High Level Output Current of XOSCOA Low Level Output Current of XOSCOA 8 5 4 4.0 3.0 0.5 -8 VOUT = 2V VINP = 2V VCC_BUF = 8.5 - 13.5V VINP = 2V IO = 1mA 55 0.98 0.6 1.0 1.02 VCC_BUF - 3.0 15 15 V mA mA Vpp Vpp V V mA mA 12V Supply 12V Supply Conditions Min. Typ. 0.72 30 28 Max. 0. 87 35 35 Units W mA mA
ICCRF VRT IOPA
5V Supply @ 5mA output 3.08 -0.1 -8
12 3.25
15 3.45 -15 +8 -5
mA V mA mV mA dB
Preliminary Information
Vos IBIAS PSRR Avf ViOPA IIF2O IBUFO DVIFO DVBUFO VOH VOL IOH IOL
Note: 1. All currents specified herein are quiescent current without loading on outputs.
4
PRODUCT SPECIFICATION
RC6505
AC Electrical Characteristics
VCC_RF = 5V; VCC_IF1, VCC_IF2, VCC_BUF = 12V; TA = 0 to 70C, unless otherwise specified. Parameter ZIFin CIFin Vis ZoIF2 ZiBUF AC Input Impedance of IF Amplifier AC Equivalent Input Cap Input Sensitivity at Maximum Gain AC Output Impedance of IF Amplifier AC Input Impedance of Buffer @36MHz @36MHz 7.5K W// 3.5pF 10 50 W @36MHz IF_IN+ & IF_IN50 10 Conditions Min. 2 6 Typ. Max. Units KW pF dBmV W
ZoIF2 IMD3
AC Output Impedance of Buffer Two Tone Intermodulation
@36MHz Differential Output, BUF_OUT = +10dBm Differential AC Rload = 200W at IF_OUT+ & IF_OUTf1/f2 = 35.5/36.5MHz Diff. Input and diff. Output @36MHz 0.2dB for 10MHz bands 31MHz-41MHz With TBD crystal@57.6MHz from 100Hz - 1MHz @ 10KHz offset XTL Oscillator Output, CL = 10pF XTL Oscillator Output, CL = 10pF 40 25
Preliminary Information
dBc
G NF BW_IF DBW IF FnXTL dt/dv dOSC
IF to Baseband Gain Noise Figure IF Bandwidth Bandwidth Roll-Off Integrated Phase Noise XTAL OSC Phase Noise Output Transition Rise or Fall Rate Duty Cycle of Output Pulse
48 9 36 0.1
55 12 55 0.15 0.5 -100 2.5 60
dB dB MHz dB deg r.m.s dBC/ Hz nS/V %
Performance Curves
Gain (dB) 60 50 40 GAIN 30 20 10 0 10MHz
65-6505-03
30MHz
50MHz
70MHz
90MHz
Figure 1. IF Input Bandwidth
5
RC6505
PRODUCT SPECIFICATION
Application Discussion
The RC6505 is specially suited for use in set-top boxes and cable modems for decoding QAM modulated signals based on IF sub-sampling techniques. The RC6505 simplifies the front-end design and makes it more cost effective by integrating in a single chip all the analog processing functions needed between the standard tuner and high performance A/Ds. The other major components required for the frontend of the modem are the tuner, a SAW filter, crystal and the appropriate DSP demodulator/decoder.
using the crystal oscillator operating in the 3rd overtone mode at 57.6MHz and an external divided by 2 prescaler. The reference signals for A/D are the VRT and OUT outputs. The application is shown with the Fairchild Semiconductor Division's 10-bit ADC TMC1185. Other high performance A/Ds needing fully differential input can also be used. The A/D inputs are referenced to be in the mid-scale using the output from TMC1185. The filtered and buffered IF outputs can be a.c. coupled to the A/D inputs. In this application an external differential band-pass roofing filter is used to bandlimit the signals before conversion. Figure 3 shows details of circuits used to evaluate the performance of RC6505 with the TMC1185 A/D.
DVB Set-top Application
Figure 2 shows the application of RC6505 in IF bandpass sampling decoder for 256QAM cable transmissions. Here, the sampling clock for the A/D conversion can be generated
Preliminary Information
Roofing Filter VCC-IF1&VCC-IF2 OUT INP
12V
BUF_IN+
IF-OUT+
IF-OUT-
BUF_IN-
VCM REFT REFB 256 QAM DSP Demod
BUF_OUT+ IF_INRF_IN Tuner SAW 36MHz IF_IN+ 5V VCC_RF XTL1 XTL2 57.6MHz XOSCOA 12V VCC_BUF /2 28.8Msps TMC1185 RC6505 BUF_OUT2V INP CLK
65-6505-04
Figure 2. RC6505 Application in a Sub-sampling Digital Receiver for 256 QAM
6
PRODUCT SPECIFICATION
RC6505
RC6505 VRT 2.00K 1% OUT INP 10nF IF I/P 51 SAW 10nF XOSCOA XTL1 FB IF_OUTIF_IN+ IF_INIF_OUT+ 0.1 200 78.7p VRM 0.1 2.00K 1% 10nF fo = 36MHz BW=10MHz BPF 4.88H 4.08p .155H .25H .25H 128p 128p 4.08p .155H 2K 2K 0.1 . 10nF + 1F
TMC1185 3.25V REFT
. 1.25V REFB + 1uF
0.1
22p 200 VRM 200
IN
10 B0 ~ B9 Data Out
XTL OSC OUT
0.1 200
78.7p
+5V
+12V
+12V
XTL2 VCC_RF BUF_IN+ BUF_IN+ 10F 10nF BUF_OUT+ FB BUF_OUTVCC_IF1 + 10F 10nF VCC_BUF FB VCC_IF2 + GND_IF1 10F 10nF GND_IF2 GND_BUF RFGND
4.88H
IN 22p 0.1 FB 10nF + 10F +12V +5V 10nF +5V FB 10nF 0.1
Preliminary Information
+5VA + 10F
VDD
+ 10F
VDD CLK OE GND GND
Clk In
* All decoupling caps should be placed as close to part as possible.
65-6505-05
Figure 3. RC6505 interface with Fairchild Semiconductor Division's TMC1185 10-bit 40MSPS ADC (for reference only)
7
RC6505
PRODUCT SPECIFICATION
Crystal Oscillator Operating in Over Tone Mode
RC6505
XOSCOA
XTL OSC O/P
XTL2 58MHz XTL (Over tone mode) XTL1 10n L 59.4nH FB +5V 10nF + 10uF VCC_RF C 126.6p fo = 58MHz
Preliminary Information
65-6505-06
RFGND
Choose Q = 12 then using the following equations to calculate L and C. (Note that, Rin = 260 W and fO is given.) 2p fO = (LC)-1/2 Q = 2p fO C Rin
8
PRODUCT SPECIFICATION
RC6505
Notes:
Preliminary Information
9
RC6505
PRODUCT SPECIFICATION
Notes:
Preliminary Information
10
PRODUCT SPECIFICATION
RC6505
Mechanical Dimensions
24 Lead Small Outline IC (SOIC) - .300" Body Width
Inches Min. A A1 B C D E e H h L N a ccc Max. Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
Symbol
.093 .104 .004 .012 .013 .020 .009 .013 .599 .614 .290 .299 .050 BSC .394 .419 .010 .016 24 0 -- 8 .004 .020 .050
2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 15.20 15.60 7.36 7.60 1.27 BSC 10.00 10.65 0.25 0.40 24 0 -- 8 0.10 0.51 1.27
Preliminary Information
3 6
24
13
E
H
1
12
D A e B A1 SEATING PLANE -C- LEAD COPLANARITY ccc C a L
h x 45 C
11
RC6505
PRODUCT SPECIFICATION
Ordering Information
Product Number RC6505M Temperature Range 0C - 70C Screening Commercial Package 24 Lead SOIC Package Marking RC6505M
Preliminary Information
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS30006505 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC6508
QAM IF Downconverter
Features
* * * * * * * * * Integrated IF Down Converter IF bandwidth from 30 MHz to 80 MHz Operating range between 8.5V to 13.2V 63dB peak conversion gain from IF to baseband 40dB minimum AGC range Simple interface to SAW filter and A/D converter Gain control minimizes noise figure and distortion Tuner control feature interfaces with variety of tuners Industry standard 24 Lead SSOP package
Description
The RC6508 simplifies the front-end design of cable modem and set-top receivers. It is a cost-effective solution, since it integrates IF amplifier, AGC, mixer, amplifier, tuner AGC, VCO, XTAL OSC, and bandgap reference on a single chip. The RC6508 downconverts the IF signal to baseband signal for cable modem and set top receivers. The baseband signal can be digitized and decoded with an external A/D converter and a custom DSP demodulator. The input can directly interface to a SAW filter and maintain a low noise figure. The gain can be controlled over a 40dB range through an external analog input signal. The gain reduction is done in two stages with minimum noise figure and signal distortion. The IF output is then down converted and filtered using a double balanced mixer. The output can be further filtered with an external filter prior to A/D conversion. The RC6508 has an added feature that it provides an optimum tuner AGC control voltage which is used to control the front end tuner gain. The IF and Mixer section works at 9V and the oscillator works on 5V supply. The RC6508 is available in a 24 Lead SSOP package.
Applications
* Digital Set-top Receivers * Cable Modems
Block Diagram
BB_GND VCC_HF HFGND IF_IN+ IF_IN- 45dB VCC_BB BB_Out
RF BB LO
17dB
IF_AGC T_Strt T_AGC
x2
- + XTAL Osc BANDGAP REF
VCO
VCC_RF (5V) XTL_Out GND_XTL VCO_In VCC_XTL XTL_Tnk RFGND VCO_Fs SGND VCC2 VRT
65-6508-01
Rev. 1.1.1
RC6508
PRODUCT SPECIFICATION
Functional Description
The RC6508 shown in the block diagram performs all the IF and baseband signal conversion with the minimal external components. It consists of three general sections: * IF Gain Section * IF Down Conversion and Frequency Synthesis * Reference Voltage
IF Down Conversion and Frequency Synthesis
This is the second stage of the IF-to-Baseband conversion. It consists of a double balanced linear mixer. The output of the front end gain stage is capacitively coupled to the input (RF port) of the mixer. The LO signal for the mixer can be directly driven or synthesized with the Voltage Controlled Oscillator (VCO). This section has also a crystal oscillator that can be used to generate a master clock for the frequency synthesis. The mixer translates the signal to a second IF frequency equal to the symbol rate and passes through an amplifier. The final output is a baseband signal, BB_Out. This signal can be further filtered externally before connecting it to an external ADC and QAM demodulator.
IF Gain Section
This is the first stage of the IF-to-Baseband conversion. The IF input signal is fed into a variable gain control amplifier that is capacitively coupled to the subsequent stages. The gain control amplifier has stabilized gain over temperature and supply variations. The amplifier gain is directly proportional to the IF_AGC voltage. The gain in various stages is not reduced at the same time in order to minimize the noise figure degradation. The transition point is set by the voltage on T_Strt pin. T_strt sets the T_AGC trigger to control the front end tuner gain.
Reference Voltage
The RC6508 has a built-in 2.0V reference with capability of driving 10mA load and can be used to set up A/D reference.
Pin Assignments
VCC_XTL GND_XTL XTL_Tnk XTL_Out RFGND VCC_RF VCO_In VCO_Fs BB_GND NC BB_Out VCC_BB
1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13
65-6508-02
T_Strt IF_AGC T_AGC VCC_HF HFGND IF_IN- IF_IN+ SGND NC VCC2 VRT NC
2
PRODUCT SPECIFICATION
RC6508
Pin Descriptions
Pin Name BB_GND BB_Out GND_XTL HFGND IF_AGC IF_IN+,IF_IN- NC RFGND SGND T_AGC T_Strt VCC_BB VCC2 VCC_HF VCC_RF VCC_XTL VCO_Fs VCO_In VRT XTL_Out XTL_Tnk Pin Number 9 11 2 20 23 18,19 10,13,16 5 17 22 24 12 15 21 6 1 8 7 14 4 3 Pin Function Description Ground Connection. Baseband Voltage output. Crystal Oscillator Ground. Analog Ground Connection. Input Voltage for IF Front End Gain Control. IF inputs. No Connection. Ground Connection for High Frequency Mixed Signal Sections. Analog Ground Connection. Output Voltage for Tuner Gain Control. Threshold Voltage Input for Starting Tuner Gain Control. Baseband Supply Voltage, typically 9V. Analog Supply Voltage (9V). Analog Supply Voltage (9V). Supply Voltage (5V) for High Frequency Mixed Signal Sections. Supply Voltage for Crystal Oscillator. VCO External Frequency Select Circuit Connection. VCO Input, can be used for directly feeding external LO. Output reference voltage for top of A/D input range. Crystal Oscillator Output. Crystal Oscillator Frequency Select Circuit Connection.
Absolute Maximum Ratings
Parameter IF_IN+, IF_IN-, IF_AGC, T_Strt VCC_RF, VCC_BB, VCC_HF, VCC2, VCC_XTL Tstg Input Voltages Analog Supply Voltages Min. GND - 0.3 Typ. Max. VCC + 0.3 13.5 Units V V
Storage Temperature
-40
125
C
Operating Conditions
Parameter VCC VCC_RF VCC_XTL T Analog Supply Voltage Supply Voltage for IF and Mixer Supply Voltage for XTLOSC and VCO Temperature 0 70 C Min. 8.5 4.75 Typ. 9 5 Max. 13.2 5.25 Units V V
3
RC6508
PRODUCT SPECIFICATION
DC Electrical Characteristics
VCC_RF, VCC_XTL = 5V; VCC_HF, VCC_BB, VCC2 = 9V; TA = 0 to 70C, unless otherwise specified. Parameter PWIF ICCHF ICCBB ICCRF VRT DVBBo Tagc_hi Tagc_lo Power Consumption in IF Front End Supply Current Back and Baseband Current RF Supply Current Reference Output Voltage Baseband DC Output Swing Tuner AGC for Maximum Gain Tuner AGC for Minimum Gain IF_AGC = 5V IF_AGC = 2V 9V Supply 12V Supply 9V Supply 5V Supply 1.95 3.5 7.5 2 Conditions Min. Typ. 0.4 20 27 21 6 2.05 Max. 0.5 25 35 25 10 2.15 mA mA V Vpp V V Units W mA
VCC_XTL, VCC_RF = 5V; VCC_HF, VCC_BB = 9V; IF_AGC = 2V; Tsrt = 5V; TA = 0 to 70C, unless otherwise specified. Parameter ZIFin CIFin Vis IMD3 AC Input Impedance AC Equivalent Input Cap Input Sensitivity at Maximum Gain Two Tone Intermodulation Conditions @43.75MHz IF_IN Vagc=2.5V f1/f2 = 43.75/42.75 MHz, IF_IN = -16dBm, VCO_IN = 0.1Vpp, LO = 38.75MHz1 IF_AGC = 2V IF_AGC = 0V-4V T_Strt = 5V, F_AGC = 0.8V-4V 0.1dB for 10MHz bands 0.1dB for 5MHz bands fLO FnLO FnXTL Down Conversion Frequency VCO Phase Noise XTAL OSC Phase Noise VCO-IN=0.1Vpp @ 10KHz offset @ 3KHz offset 30 30 35 40 Min. 2 6 250 45 Typ. Max. Units KW pF mV dB
AC Electrical Characteristics
G NF Ragc Sagc BW_IF
IF to Baseband Gain Noise Figure (Maximum Gain) AGC Gain Range AGC Sensitivity Average Slope IF Bandwidth
40 9 43 10 43.75 75 80 100 -80 -80
dB dB dB dB/V MHz MHz dBC/Hz dBC/Hz
Note: 1. With the application of antialiasing filter as load.
4
PRODUCT SPECIFICATION
RC6508
Typical Performance Characteristics
70 60 50 70 60 50 40 30 20
65-6508-03
Gain (dB)
30 20 10 0 0V 0.5V 1.0V 1.5V
Gain (dB)
40
10 0 40MHz 60MHz 80MHz
2.0V 2.5V 3.0V 3.5V 4.0V
100MHz
IF_AGC Figure 1. Typical IF_AGC Control Characteristics Figure 2. IF Input Bandwidth
60 55 50
36 34 32
45
S/N (dB)
40
30 28 26 24
SFDR
35 30 25 20
65-6508-05
15 10 20 30 40 50 60
22 20
70
-70 -68 -67 -66 -64 -60 -55 -49 -43 -30 -24
IF Gain, dB Figure 3. SFDR vs. RC6508/TMC1175AM7C40 (Fairchild Semiconductor Demo Board with 64 QAM demodulator)
IF Input Power, dBm Figure 4. S/N vs. IF Input Power RC6508/TMC1175AM7C40 (A/D IN = 2Vpp) (Fairchild Semiconductor Demo Board with 64 QAM demodulator)
65-6508-06
65-6508-04
5
GND2
GND1
The RC6508 is designed to down convert QAM IF signals. It interfaces easily with Fairchild Semiconducto's TMC1175A A/D converter and a DSP.
6
T.P. IF_AGC From DSP T.P. T_AGC Postamplifier C22 4.7 C23 .1F C28 1n
RC6508
Applications
Voltage Gain Control Input from DSP R92 R100 R97 1000 C95 .1F C202 .1F Antialiasing Filter L9 3.9 Q1 2N3904 R12 3K R6 470 R7 470 Cx C18 100p R19 No load Q2 2N3904 C200 .1F C13 .1F R11 10K R10 1.2K L21 10 IF_GND IF_GND 200 C16 68p R17 IF_GND 1000 C103 .1F L210 10 R101 +9V Analog VCCO 0 1000 C98 .1F IF_GND L7 1 C47 1n IF_GND R15 390 R16 390 C53 .1F C52 1n
+9V Analog
J3 In 2 IF_GND IF_GND C185 .1F R29 1000 4 23 IF_AGC 22 T_AGC 18 IF+ 19 IF- VCC_BB BB_OUT VRT 12 11 14 24 T_STRT C31 .1F C37 4.7 Out
MAR-7 SM Mini Circuit MSA-0785-Amplifier Hewlett Packard C34 .1F
IF_GND R13 3.6k
J4 BB_Out
1
IF_INPUT FO=43.75MHz BW=5MHz QAM 64
C57 1n IF_GND IF_GND L106 10 R94 3.9K C107 .1F IF_GND C86 .1F C8 220p 7 VCO_In VCO_Fs 8 C85 22pF L83 560n 6 VCC_RF VCC_XTL BBGND RFGND GND_XTL 3 XTL_Tnk XTL_Out SGND 17 HFGND 20 4 IF_GND 2 5 9 1 C203 .01F IF_GND IF_GND C186 .1F VCC2 R32 1000 IF_GND R93 750 D1 MMBV105G L74 +5V Analog C79 4.7 C78 .1F C81 1n 10 IF_GND C92 .1F 47K 1000 C90 .1F R91 IF_GND R87 C109 .1F 15 C108 4.7 21 R115 5.6K VCC_HF C114 .1F C201 .01F C110 1n 6.8K
Siemens Matsushita Components 43.75MHz SAW Filter C43 X6964M 1n 1 4 Input Output 2 Input-ground 5 3 Output GND C45 1n IF_GND R111 +5V DC
IF_GND
+9V Analog
C226 10F
C225 .01F
1V DC, 2Vpp AC (QAM64)
IF_GND
TMC1175 RC6508G
IF_GND 13 14 15 16 17 18 19 20 21 22 23 24 VDDD2 VDDA1 VDDA2 VR+ RT VDDA3 VIN AGND1 AGND2 VR- RB DGND2 IF_GND L63 C67 .01F DGND 10 C61 4.7 C60 .1F C59 1n IF_GND +5V Digital CONV VDDD1 D7 D6 D5 D4 D3 D2 D1 D0 DGND1 OE 12 11 10 9 8 7 6 5 4 3 2 1 To DSP CLK
VCO Frequency Control Input from DSP pin 9
R81
0
+5V
C80 .01F
FB2
IF_GND
1
IF_GND
2 +5V 10 C205 .01F DGND L63
+9V P.S.
3
DGND
4 C206 10 DGND DGND +5V C71 .01F DGND DGND 10 C72 4.7 C73 .1F L79 C205 .01F
+5V P.S.
J1
DGND
DGND
DGND
T.P. VCO_VC VCO_VC
DGND
+5V Analog
From DSP
PRODUCT SPECIFICATION
Figure 5. Application of RC6508 in Cable Modem Receivers (Fairchild Semiconductor Demo Board with 64 QAM Demod-
PRODUCT SPECIFICATION
RC6508
VCO Internal Schematic
L2 33H L1 1H VCO_FS(8) VCC_RF (6) 0.1F C4 1nF 4.7F C6 C5 0.1F C7 1nF C8 +5V 1F C9
IC = 0.9MA 10pF C1 5pF C2 Q1 VCO-In (7) + - Q5 220pF C3 47.71/2 Internal RFGND(5) Q3 Q4 TO MIXER
The VCO can be designed as a Colpitts oscillator. The above circuit application shows VCO with adjustable typical value of 38.75 MHz. The frequency is controlled by the external resonance circuit. The oscillating transistor is Q1 in common
base configuration. To inject signal in the mixer in place of LO, the VCO_Fs must be open. The signal on the pin VCO_In should be under 100mVp-p and AC coupled.
Crystal Oscillator Internal Schematic
L2 1nF 1F 33H 0.1F +5V C6 1nF 1F C7 C8
0.1F VCC-XTL (1)
C3
C4
C5
L3
8H 3.2K 3.2K Q18 VCO-IN (7) 2K VCC-XTL (1) 100pF XTL-OUT(4)
6.8K XTL-Tnk(3) Q7 Q10 Q11 Q12
Q17
130A
230A
130A 450A 450A Internal
GND-XTL (2) 47pF C2 2001/2
The crystal oscillator is an ECL inverter. It is necessary to bias the XTL-Tnk with a choke to 5V VCC_XTL power supply. The output is about 0.7V DC lower than VCC_XTL with
an approximate swing of 0.5Vpp at the output. If the oscillator is not used, it is good to ground XTL_Tnk pin.
7
PRODUCT SPECIFICATION
RC6508
Notes:
8
PRODUCT SPECIFICATION
RC6508
Notes:
9
RC6508
PRODUCT SPECIFICATION
Notes:
10
PRODUCT SPECIFICATION
RC6508
Mechanical Dimensions
24 Lead SSOP Package (5.3mm Body Width)
Inches Min. A A1 A2 b c D E E1 e L N a ccc Max. Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .006 inch (0.15mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
Symbol
-- .0.78 .002 -- .065 .073 .010 .015 .0035 .010 .311 .335 .291 .323 .197 .220 .026 BSC .022 .037 24 0 -- 8 .004
-- 2.00 0.05 -- 1.65 1.85 0.22 0.38 0.09 0.25 7.90 8.50 7.40 8.20 5.00 5.60 0.65 BSC 0.55 0.95 24 0 -- 8 0.10
D 24 13
E1 INDEX AREA
E
1
12
A A2 e b A1 -CSEATING PLANE LEAD COPLANARITY d ccc C a L c
11
RC6508
PRODUCT SPECIFICATION
Ordering Information
Product Number RC6508G Temperature Range 0C-70C Screening Commercial Package 24 Lead SSOP Package Marking RC6508G
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS30006508 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC6516
IF Demodulator for Vestigial Side Band Receivers
Features
* * * * * * * Demodulates 16 level to 2 level VSB signals Versatile delayed AGC & Tuner Controls 60dB Gain from IF to baseband 45dB AGC range with a digital control <1% distortion @ 2 Vpp baseband output 50dB typical IMD3 On-chip low phase noise VCO (100dBc/Hz @ 20KHz from 200MHz) * * * * * * Wideband Quadrature Prescalers <2 Quadrature phase error Programmable Video Filter-Amplifier Direct input interface for SAW filters 9dB input Noise Figure at max gain On-chip band gap reference and temperature compensation * Available in 28 lead PLCC package
Preliminary Information
Description
The RC6516 is fully integrated IF Demodulator customized for Vestigal Side Band (VSB) receivers. As shown in the Block Diagram, the IC performs IF amplification with gain control, synchronous demodulation of I & Q channels and carrier recovery using a Frequency & Phase Lock Loop (FPLL). The RC6516 directly provides delayed AGC control for a front end tuner. The demodulated output is filtered and amplified. The device accepts direct digital control inputs from a microprocessor for gain control, calibration and shut down functions. The IC is packaged in a 28-pin PLCC.
Block Diagram
GND2 VCC2(12V) XTAL1 XTAL2 XTAL EN CP LNA
26 EN
BANDGAP REF VCC1 (12V) GND1 IN+ IN- GNDP TAGC CAGC DLY ADJ IF
RFLT AFC+ 3.5dB IDAT+
FILTER-BQD
VGA
20 ds
ds
RF
16dB
LO
IMX+ IMX- AGC CONTROL RF
EN EEV 16dB
PD IF
PL
LO GUP GDN SHUT DOWN AFC-SWT SHUT DOWN OF AFC DEFEAT LOGIC 90 +4 VCO 0
- LIM +
AFC- AFC+
CP
QADJ
VC01 VC02 NOTE: Arrows indicate current mode signals VCC3(5V) GND3
PDO
65-7563
Rev. 0.9.0
PRELIMINARY INFORMATION describes products that are not in full production at the time of printing. Specifications are based on design goals and limited characterization. They may change without notice. Contact Fairchild Semiconductor for current information.
PRODUCT SPECIFICATION
RC6516
Functional Description
The block diagram of the RC6516 consists of three general sections: 1. 2. 3. IF amplifiers with gain control Synchronous demodulator Frequency phase lock loop (FPLL) and auxiliary circuits
The FPLL Section
The FPLL consists of a VCO working at 4 times the pilot frequency. The frequency is set by external LC components and also controlled with a varactor. This VCO signal is passed through a divide by 4 prescaler to provide two signals in quadrature at the frequency of the pilot. These signals are used by the I & Q multipliers. The VCO is frequency and phase locked to the 4x pilot frequency which is typically 46.69MHz. The VCO thus operates at 186.7MHz in a typical 16 VSB decoder. Frequency acquisition is possible by means of the third multiplier on chip and AFC filter off-chip. The PLL circuit is formed by the Q channel mixer, third multiplier-charge pump, external PLL filter and the VCO. Due to component variations, the VCO frequency may not be within the pull in range of the FPLL. The AFCSW signal is used for activating this start up calibration. An auxiliary crystal oscillator signal at the pilot frequency of 46.6MHz is injected into the input port of the mixers, to pull the VCO to the desired frequency during the start up mode. During this mode the XTAL oscillator and the I-channel charge pump are activated and the IF gain stages are disabled. There is also the shutdown mode during which the VCO, the crystal oscillator and the tuner control are disabled. These various states are determined as shown in Table 1.
The IF Section
There are two IF amplifiers capacitatively coupled to each other and the subsequent stages. The first amplifier has a maximum gain of 24dB and an AGC range of more than 14dB. The second amplifier has a maximum gain of 16dB and gain reduction capability of 30dB. To minimize the Noise Figure degradation with gain reduction the second stage fully gain reduces before the first stage gain reduces. The transition point is set by the voltage on the DLYADJ pin. The voltage on CAGC pin directly determines the gain of the two IF stages. When the voltage on CAGC is lower the IF gain is lower. When the CGAC voltage is higher than the DLYADJ the gain reduction is primarily in the second stage. When the CAGC voltage is lower than DLYADJ, only the first stage gain is reduced at a much slower rate. The tuner AGC control voltage TAGC also changes this range to gain reduce the external tuner. This avoids the amplifiers from being overdriven into distortion. During AFC defeat mode these IF amplifiers are disabled with more than 50dB of signal isolation.
Preliminary Information
Table 1. Truth Table for Digital Circuitry
VCC3 = 5V, VCC1,2 = 12V, TA = 0 to 70C unless otherwise specified AGC Control GUP LO HI LO HI AFC Control AFC_SWT LO X HI SHTDWN LO HI LO Description Crystal is OFF, VCO is ON Crystal is OFF, VCO is OFF, Tuner AGC is Hi-Z Crystal is ON, VCO is on, I-channel Charge Pump is ON for acquisition GDN LO LO HI HI Description No Gain Change (over symbol period) Increase Gain Decrease Gain Disallowed
Gain Control
The gain control signal is developed on the capacitor at the CAGC pin, by charge pump and AGC control circuits. TTL/ CMOS signals on the GUP, GDN pins build the voltage through the charge pump current at CAGC pin. Continuous pulses on GUP pin increases the CAGC voltage and pulses on the GDN pin reduces the CAGC voltage. Table 1 shows the truth table for gain control.
Synchronous Demodulator
This section consists of In-phase (I) and Quadrature (Q) multipliers/mixers. During normal operation the incoming signal processed by the two IF stages is capacitatively coupled to the linear (RF) port of both the mixers. The signals for the LO port of the I & Q mixers come from the FPLL section. The switching signals are in quadrature and phase locked to a small pilot present in the IF signal. The signal levels for this multiplying port use limiting amplitudes. The I channel output is then filtered to reject the high frequency components while not distorting the video band signals. The filtered output is also amplified to cover the full range of A/D converter that follows. The Q channel signal is used by the FPLL section described below.
2
RC6516
PRODUCT SPECIFICATION
Pin Assignments
CAGC VCC1 (12V) GNDP IN- IN+ GNDN TAGC SHUT DOWN GUP GDN AFCSWT XTL1 XTL2 GND3
4 3 2 1 28 27 26 5 6 7 8 9 10 11 12 13 14 15 16 17 18 25 24 23 22 21 20 19
DLY ADJ RFILT VCC2 (12V) GND2 IDAT+ IMX+ IMX-
VCC3 (5V) VCO1 VCO2 PDO QADJ AFC- AFC+
Preliminary Information
65-3686-01
Pin Descriptions
Pin Name AFC+, AFC- AFCSWT Pin Number 18, 17 8 Description Inputs to the limiter that sets the polarity of the third multiplier in the FPLL loop. This digital input is LO during normal operation. A TTL/CMOS high input enable the crystal oscillator and an extra I-channel charge pump, while disabling the IF input sections. The crystal oscillator outputs are switched into the input ports of the quadrature mixers. The VCO then locks to 4 x crystal frequency. An internal charge pump will develop a voltage across any capacitance on this pin. Voltage on this node directly determines the front end IF gain. When operating on a 12 volt supply, moving this voltage from 9V to 2V reduces the gain by at least 40dB. The input voltage on this pin determines the transition point for delayed AGC. A TTL/CMOS high level input on this pin activates internal charge up to decrease the voltage on the CAGC pin. Ground line for backend. Also the substrate connection to the IC. Should be at the lowest potential to the IC. Ground line for digital section. Shield ground for input. Ground signals for front end sections. A TTL/CMOS high level input on this pin activates internal charge up to increase the voltage on the CAGC pin. Demodulated & filtered output to be ac coupled to A/D converter. Demodulated output before filtering. DC coupled back to AFC limiter inputs AFC+/AFC- though an external low pass filter. IF inputs to be demodulated. Internal dc restoration. External ac coupling required. Usually interfaced to a SAW filter. Charge pump output from third multiplier. This output can be fed to an external lead-lag filter to develop the voltage required to drive the varactor in feedback till a lock is established with the pilot.
CAGC
4
DLYADJ GDN GND2 GND3 GNDN GNDP GUP IDAT+ IMX+, IMX- IN+, IN- PDO
25 7 22 11 27 2 6 21 20, 19 28, 1 15
3
PRODUCT SPECIFICATION
RC6516
Pin Descriptions (continued)
Pin Name QADJ RFILT Pin Number 16 24 Description Offset adjust input pin effectively corrects quadrature phase error. A 20KW variable resistor to ground can cover the range of correction. Resistor at this pin sets the dominant filter cut-off frequency for the filter internal to the chip between IMX and IDAT pins. A 4KW at this pin gives a 3dB point of 8.3MHz. This digital input should be LOW during normal operation. A TTL/CMOS high input on this pin shuts down all the oscillators This voltage output can be used to gain control the tuner front-end. Supply voltage for front end sections. Usually 12V. Supply voltage for the synchronous demodulator and backend sections. Usually 12V. Supply for digital logic, prescalers and oscillators. Usually 5V. The frequency setting network and the varactor are connected at these pins. Crystal oscillator pins.
SHUTDOWN TAGC VCC1
5 26 3 23 12 13, 14 9, 10
Preliminary Information
VCC2 VCC3 VCO1, VCO2 XTL1, XTL2
Absolute Maximum Ratings
Parameter Positive power supply, VCC Negative power supply, VEE Differential input voltage Operating temperature Storage temperature Lead temperature (10 seconds soldering) Thermal resistance, QJA Short circuit tolerance: One output can be shorted to ground.
Note: 1. Absolute maximum ratings are those beyond which operation and reliability of the device cannot be guaranteed. Subjecting devices to these limits for extended periods of time may result in actual failure of the device.
Min
Max 7 -7 10
Unit V V V C C C C/W
0 -40
70 125 300 90
Operating Conditions
Symbol VCC1, VCC2 VCC3 Parameter Analog supply voltages HF supply voltage Min 10.8 4.5 Typ 12 5 Max 13.2 5.5 Units V V
4
RC6516
PRODUCT SPECIFICATION
DC Characteristics
VCC3 = 5V, VCC1,2 = 12V, AFC_SWT = OFF, TA = 0 to 70C unless otherwise specified Symbol ICC1 ICC2 ICC3 Pw Viout VImix dVImix dAFC VIoff ZIout DIPDO dIPDO Parameters Front-end Supply Current Backend Supply Current HF Supply Current Total Power Consumption I-Data Output I-channel mixer ouput dc I-channel mixer output Differential Offset AFC limiter input Offset Total I-channel Offset I-Filter Output impedance PDO charge-pump current swing PDO charge-pump offset current with offset null over temperature. AFC charge pump current swing AFC charge pump offset AFC charge pump leakage VCO external current VCO voltage Compliance Xtal Oscillator Input AGC charge current swing AGC charge pump leakage IF input DC levels Input impedance Tuner AGC for maximum gain Tuner AGC for minimum gain Tuner AGC for shutdown Tuner Impedance during shutdown RLmax=4K,VCC=10.8, VDLY=6V, CAGC=10V VDLY=6V, CAGC=2V VDLY=6V, CAGC=2-10 SHUTDWN=H VDLY=6V, CAGC=2-10 2 60 Toggle GUP & GDN. Measure current @ 5V GUP & GDN = LO AFC_SWT=LO VCO1=VCC3 0.6 2.9 1 125 8 3 10 2 10 250 0.5 1 4.9 PDO to 5V with 10K Minimized by adjusting 12K variable resistor on Qadj pin. Rs = 2K to 5V. Test Conditions VCC1=13.2V AFC_SW=OFF, AFC_SW=ON, VCC2=13.2 AFC_SW=OFF, AFC_SW=ON VCC1,2=13.2V, VCC3=5.5 4.5 3 -16 -4 -15 5 50 200 Min Typ 32 28 16 0.88 6 4 Max 40 34 20 1 7 5 16 4 15 10 Units mA mA mA W V V mV mV mV Ohms mA nA
ICC - Supply Currents
Signals - DC Compliance
Preliminary Information
DIAFC dIAFC IOAFC IVCO1 VCO2 VX2 DIAGC IOAGC IN Rin Tagc_hi Tagc_lo Tagc_off ZTagc
0.6 10 1.0
mA mA mA mA V V mA nA V KW V V V KW
IF - Signals
5
PRODUCT SPECIFICATION
RC6516
Digital Signal Characteristics for GUP, GDN, AFC_SWT, SHUTDOWN
VCC3 = 5V, VCC1,2 = 12V, TA = 0 to 70C unless otherwise specified Symbol Vth HI-VG+ LO-VG+ I(vg) Parameters Logic Threshold Gain Control Input Logic High Gain Control Input Logic Low Logic Input Currents Test Conditions VCC3 = 4.5V, 5.5V VCC3 = 4.5V, 5.5V VCC3 = 4.5V, 5.5V VCC3 = 4.5V, 5.5V 2.4 Min Typ 1.4 3.6 V 0.8 10 V mA Max Units V
AC Characteristics
VCC3 = 5V, VCC1,2 = 12V, AFC_SWT = OFF, TA = 0 to 70C unless otherwise specified. Refer to Figure 2.
Preliminary Information
Symbol IF input Rin Rin Cin NF Vins IMD3
Parameters AC Input imp. @ Max Gain AC Input imp.@ minimum gain Ac equivalent input cap Noise Figure @ Max Gain Input Sensitivity @ Max Gain Inter-modulation Distortion for two-tone input
Test Conditions 44MHz 44MHz Rs = 75W, 44MHz 44 MHz VCO=4x46.69, f1/f2=41.69/42.69MHz, Idat=0.7Vpp Vin=-30dBmV@ 44MHz Vin-30 to +30 dBmV, Cagc=2V to 10V V@ Cagc=8.5V to 9.5V DLYADJ=6V V@ Cagc=3.5V to 4.5V DLYADJ=6V From GUP/GDN edge to CAGC current change Cagc 10V, with SAW DLYADJ = 6V Cagc = 6V, with SAW DLYADJ = 6V Cagc = 3C, with SAW DLYADJ = 6V V = 1Vpp, 1MHz
Min 1.5 1.5
Typ
Max
Units KW KW
6 8.2 1000 -50 -45 10
pF dB mVpp dBC
Gain Control Characteristics Gmax Ragc Sagc1 Sagc2 TPagc NF0 NF25 NF40 S/N IF to baseband max Gain AGC gain range AGC sensitivity to gain control at maximum slope AGC sensitivity to gain control Response time of AGC circuit Noise figure at no gain reduction Noise figure at 25dB gain reduction Noise figure at 40dB gain reduction Signal-to-noise at min. gain 57 40 60 46 15 3 20 10 12 14 30 45 47 22 63 dB dB dB/V dB/V nS dB dB dB dB
6
RC6516
PRODUCT SPECIFICATION
AC Characteristics
VCC3 = 5V, VCC1,2 = 12V, AFC_SWT=OFF, TA = 0 to 70C unless otherwise specified Symbol LO BW_Mx BW_IFO DCG Vo1dB VoqdB ephase APB f-3dB GF A90 A46 VO1DB VOQDB TSfc Svco dVafc Parameters 4 x Demodulating Freq. Mixer input bandwidth (+0.1dB) IF output from AGC into QDMD Differential Conversion Gain IMixer Vout @1dB compression IMixer Vout @ 0.25 dB compression I & Q phase error Pass Band Attn. @5.8MHz -3db Frequency Filter gain Diff In/Single Out Attenuation @ IF+LO Attenuation @ 46.69MHz Ida compression @2Vpp Idat compression @0.75Vpp VCO Long Term Stability VCO sensitivity AFC limiter input beat note see 14.1, (46.69+41.69) Vout=1.4Vpp @1MHz Diff Output @ 1MHz, Diff Output @ 1MHz fc=186.76MHz,Vpll1=6 fc=186.76MHz,Vpll1=6 Pilot In = 46.69MHz, IMx=88mVpp, Vco @ (46.69M75K) Xtal @ 46.69MHz Vco @ (46.69M750K) At 20KHz offset 2.2 50 Imix = 88mVpp, 1KHz PDO connected with 10K resistor to 5V. With Offset Adjust -4 4.5 fc-500 400 50 50 8.1 3.5 54 5 1 0.25 fc+500 Diff Output, Df=1MHz Diff Output, Df=1MHz On-chip -2 Over 6MHz bands Test Conditions Min 100 30 30 10.8 1.5 0.75 2 0.5 Typ 186.76 Max 250 60 60 Units MHz MHz MHz dB Vpp Vpp deg dB MHz dB dB mVpp dB Vpp KHz KHz/V mVpp
QMDD04 - Quadrature Demodulator
Preliminary Information
I-channel Filtering at Baseband
FPLL Characteristics
DVafc fn BWpll DIPDO Gpd
AFC limiter input with Crystal ON i.e. AFC_SWT=ON VCO phase noise PLL Bandwidth PLL Output Current Swing Phase Detector Gain
100 -105
mVpp dBC/Hz KHz uA uA/rad
TGpd edc
PD Gain temperature Coeff. Static Phase Error due to Prescaler & DC offsets Crystal Oscillator Freq Crystal Temperature Stability Crystal Turn On Time Crystal Turn OFF Time
1000 4
ppm/K deg
Auxiliary Section (see Figure 1) fXCL TfXCL TXon TXon Series , 3rd Overtone See Figure 1 from AFC_SWT=HI (on) frm AFC_SWT=LO (off) 46.69056 50 100 100 MHz ppm/C ns ns
7
PRODUCT SPECIFICATION
RC6516
Applications Discussion
System Overview
The RC6516 is used in a Zenith Digital Cable Modem using multi-level VSB formats. The RC6516 performs IF amplification with gain control, synchronous demodulation of I and Q channels and carrier recovery using a Frequency and Phase Lock Loop. The I Channel analog output is digitized in an A/D converter at a rate of 10.76 MHz. The digital data is then used by the Digital Logic IC to perform segment sync recovery, signal polarity correction, symbol clock recovery, AGC and AFC control, channel equalization, phase error tracking, data de-interleaving, Reed Solomon error control and data slicing. (The block diagram of a typical receiver system using RC6516 is shown in Figure 1. The RC6516 is between a SAW filter and an A/D. The RC6516 output is AC coupled to an 8 bit or 10 bit A/D. An FPLL circuit is used for carrier recovery and synchronous demodulation. A small pilot signal is present in the received signal to aid in carrier recovery. A microprocessor is used to tune the two local oscillators, initialize the system during start up and monitor system performance. Figure 2 shows the typical external components and connections required for the operation of the RC6516.
Preliminary Information
RF SIGNAL
TUNER GAIN = 32 dB
1LO. 2LO. SYNTHESIZERS
RC6516
SAW FILTER LOSS = 20 dB 41-47 MHz IF AMPLIFIER DEMODULATOR START UP
1175A A/D
8 BITS
8
DIGITAL LOGIC
DATA
DELAYED AGC BUS AFC DFT BUS
AGC CONTROL 2
MICRO PROCESSOR
65-7564
Figure 1. VSB Receiver Front End
Table 2. Signal Levels and Gain Distribution in Receiver Front-End
VCC3 = 15V, VCC1,2 = 12V, TA = 0 to 70C unless otherwise specified. Parameter Tuner Input Tuner Gain SAW Filter Gain (-Loss) IF Input (Diff-in) LNA Gain VGA Gain Mixer Input (Diff-in) Mixer Input rms Mixer Gain Max. Output (Diff-out) Filter Amp (Diff-in Sng-out) GAIN Iout+ Output (rms) Iout (peak-to-peak) Max. Level -28.9 34 -18 -12.9 25.8 19.6 32.5 42.2 10.9 148 3.6 224 1 High Level -21.3 34 -18 -5.3 25.8 12.0 32.5 42.2 10.9 148 3.6 224 1 Mean Level -1.3 33.5 -18 14.2 25.8 -7.5 32.5 42.2 10.9 148 3.6 224 1 Low Level 18.7 21.4 -18 22.1 22.8 -12.4 32.5 42.2 10.9 148 3.6 224 1 Min Level 23.7 19.1 -18 24.8 20.1 -12.4 32.5 42.2 10.9 148 3.6 224 1 Unit dBmV dB dB dBmV dB dB dBmV mVrms dB mVrms dB mVrms Vpp
8
RC6516
PRODUCT SPECIFICATION
12V
.01p
.01p TO INPUT ADC 680 680 200pF 680 680 680
10F ~6-9V Input 4K RFILT VCC2 (12V)
200pF IDAT+ MXO+ MXO- GND2 680 5K 5K
EXT TUNER 12V 4K TAGC GNDN + SAW FILTER OUT - 0.01 IN+ TP 0.01 TP IN- 1 GNDP 2 12V 0.01 VCC1 (12V) 3 CAGC .039F 4 27 28 26
DLY ADJ
25
24
23
22
21
20
19 18 17 16 AFC+ AFC- QADJ 20K PDO VCO1 VC02 VCC3 (5V) 0.01 0.01F CBYPASS 75pF 10K 2pF 5V 30NH 3pF 22K 0.05pF 10pF 1300pF 1300pF
Preliminary Information
RC6516
15 14 13 12
13K
5V
5 SHUT DOWN
6 GUP
7 GDN
8 AFC_SWT
9 XOSC1
10 XOSC2
11 GND3
46.69055 MHz 3RD OT 18pF 10pF
0.58H
65-7566
TTL MICROPROCESSOR INPUTS
Figure 2. Typical External Components for RC6516
9
PRODUCT SPECIFICATION
RC6516
Notes:
Preliminary Information
10
RC6516
PRODUCT SPECIFICATION
Mechanical Dimensions - 28-Lead PLCC (QA) Package
E E1 J Symbol A A1 A2 B B1 D/E D1/E1 D3/E3 e J ND/NE N ccc B1 e J Inches Min. Max. Millimeters Min. Max. Notes
D
D1
D3/E3
.165 .180 .090 .120 .020 -- .013 .021 .026 .032 .485 .495 .450 .456 .300 BSC .050 BSC .042 .048 7 28 .004
4.19 4.57 2.29 3.04 .51 -- .33 .53 .66 .81 12.32 12.57 11.43 11.58 7.62 BSC 1.27 BSC 1.07 1.22 7 28 0.10
8
Preliminary Information
A A1 A2 B -C- LEAD COPLANARITY ccc C
Notes: 1. Cavity mismatch = .004 (0.10mm) 2. Cavity frame offset = .002 (0.05mm) excluding leadframe tolerances. 3. Mold protrusions: Parting Line = .006 (0.15mm), Top or Bottom = .001 (0.025mm) 4. Variation in lead position = .005 (0.13mm) 5. Shoulder instrusions & protrusions: Intrusions = .002 (0.05mm), Protrusions = .003 (0.08mm) 6. Package warpage, WARP FACTOR = 2.5 = 7. Ejector pin depth = .010 (0.25mm) maximum. 8. Corner and edge chamfer = 45C. WARP (mils) PACKAGE LENGTH (inches)
11
PRODUCT SPECIFICATION
RC6516
Ordering Information
Product Number RC6516 Temperature Range 0 to 70C Screening Commercial Packaging 28 Pin PLCC Package Marking RC6516V
Preliminary Information
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonable expected to result in a significant injury of the user.
Fairchild Semiconductor Corporation Americas Customer Response Center Tel:1-888-522-5372 Fairchild Semiconductor Europe Fax: Email: Deutsch Tel: English Tel: Italy Tel: +49 (0) 1 80-530 85 86 europe.support@nsc.com +49 (0) 8 141-35-0 +44 (0) 1 793-85-68-56 +39 (0) 2 57 5631
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
Fairchild Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Center, 5 Canto Rd. Tsimshatsui, Kowloon Hong Kong Tel:+852 2737-7200 Fax:+852 2314-0061
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www.fairchildsemi.com 2/98 0.0m Stock#DS30006516 O 1998 Fairchild Semiconductor Corporation
www.fairchildsemi.com
RC6564
IF-to-DigitalTM Converter
Features
* * * * * * * * * * * * * * Integrates almost all active components for conversion Simple interface to SAW filter and digital demodulator Gain control minimizes noise figure and distortion Tuner control feature interfaces with variety of tuners Demodulation of 64QAM constellations 40Msps ADC with >7.4 EFB @ 20Msps Low phase noise LO generation Crystal oscillator for fundamental or 3rd overtone mode 63dB peak conversion gain from IF to baseband 30dB minimum AGC range 45dB IMD3 end-to-end 9dB input noise figure at maximum gain On-chip stable voltage reference 44-pin PLCC package
Applications
* * * * * * * QAM receivers Set-top receivers for digital cable Internet surf-boards Cable modems ITV transceivers Desktop video conferencing IF sampling decoders
Preliminary Information
General Description
The RC6564 is a single chip solution for downconverting and digitizing QAM signals so that they can be decoded in the digital domain by custom DSP demodulators. The RC6564 performs IF amplification with gain control, frequency down conversion, frequency synthesis for mixer Local Oscillator (LO) & system clock generation, and baseband quantization with an Analog to Digital converter. The input can directly interface to a SAW filter and maintain low noise figure. Depending on the signal input level the gain may be controlled over a 30dB range through an external analog input signal. The gain reduction is done in two stages and orchestrated in such a manner as to minimize noise figure and signal distortion. The IF output is then down converted and filtered using a double balanced mixer. This output may be filtered even further, externally, before being quantized by the on-chip A/D converter.The digital data output can be processed to derive information for automatic gain control (AGC) and automatic frequency control (AFC). RC6564 is optimized to work with DSP decoders based on IF sampling. The RC6564 also provides an optimum tuner AGC control voltage useful for controlling the front-end tuner gain. For best performance Analog sections work on 12V & 5V supplies. The digital sections work on a regulated 5V supply. RC6564 is available in a single 44-pin PLCC package.
Rev. 0.9.0
PRELIMINARY INFORMATION data sheets provide specification for products not yet complete or characterized. They provide design target information for customer planning purposes.
RC6564
PRODUCT SPECIFICATION
Block Diagram
VDDD1,2 (5V) VDDA (5V) DGND1,2 DEC & DRIVERS VCC_BB BBGND AGND VREF MATRIX IF_AGC T_Strt T_AGC VCO
65-6564-02
BB_Out
LP FILTER
VCC_HF HFGND IF_IN+
RF BB LO
AD_In T/H
4.6dB 17dB
COARSE A/D
IF_IN-
D0-D7
Preliminary Information
x2
- + XTAL Osc BANDGAP REF FINE A/D
OE
VCC_RF (5V)
XTL_Out
VCO_In
XTL_Tnk
GND_XTL
VCC_XTL
VCO_Fs
RFGND
VRT RT RB
Functional Description
The RC6564 performs all the IF and baseband signal processing/conversion with the help of external filters. As shown in the Block Diagram, the RC6564 consists of three general sections: 1. 2. 3. IF Gain blocks with Gain Control IF down conversion with LO & Clock Generation Analog to Digital Conversion port) of the mixer. The mixer output is further amplified. The signals for the Local Oscillator (LO) port of the mixer can be directly driven or synthesized through the VCO (Voltage Controlled Oscillator). The mixer output is partially filtered on-chip but may need to be further filtered externally before being fed to the A/D input. The RC6564 also has a crystal oscillator circuit that can be used for generating a master clock for frequency synthesis. Analog-to-Digital Converter: The analog-to-digital converter employs a two-step 9-bit architecture to convert analog signals into digital words at sample rates up to 40 Msps (Mega samples per second). An integral Track/Hold circuit delivers excellent performance on signals with full-scale components up to 12MHz. A dynamic performance of more than 7.4 effective bits is delivered at the outputs D0 through D7. The A/D digital outputs are three-state and TTL/CMOS compatible. The down converted output at BB_OUT can be externally filtered and directly connected to the A/D input. Sampling of the applied input signals takes place on the falling edge of the AD_CLK. The output word is delayed by 2.5 AD_CLK cycles. An output enable control OE places the outputs in high impedance state when HIGH. The outputs are enabled when OE is LOW as described in the Timing Diagrams section.
The IF Section: The signal input is into a variable gain amplifier capacitively coupled to the subsequent stages. When the voltage on IF_AGC pin is higher, the gain is higher and when it is lower the gain is lower too. To minimize the noise figure degradation with gain reduction the gains in various stages are not reduced simultaneously. The transition point is set by the voltage on T_Strt pin. When the IF_AGC voltage is higher than half the T_Strt voltage the gain reduction rate is steepest. When the IF_AGC voltage is lower than roughly half the T_Strt voltage the gain reduction is at a slower rate. The T_AGC output voltage also changes and can be used to gain reduce the front-end tuner. The gain control amplifier has stabilized gain over temperature and supply variations. IF Down Conversion & Frequency Synthesis: This section consists of a double balanced linear mixer. The output of the front-end gain stage is capacitively coupled to the input (RF
2
AD_CLK
SGND
VCC2
PRODUCT SPECIFICATION
RC6564
Pin Assignments
VCO_Fs VCO_In VCC_RF RFGND XTL_Out XTL_Tnk GND_XTL VCC_XTL T_STRT IF_AGC T_AGC
6 5 4 3 2 1 44 43 42 41 40
BBGND BB_Out VCC_BB VDDA AD_In AGND RB DGND1 OE DGND2 D0
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
39 38 37 36 35 34 33 32 31 30 29
VCC_HF HFGND IF_IN- IF_IN+ SGND VCC2 VRT RT NC VDDD1 AD_CLK
Preliminary Information
D1 D2 D3 NC D4 D5 D6 D7 NC VDDD2 NC
65-6564-03
Pin Descriptions
Pin Name AD_CLK AGND AD_In BBGND BB_Out D0-D3 D4-D7 DGND1 DGND2 GND_XTL HFGND IF_AGC IF_IN+, IF_IN- N/C OE RB RFGND RT SGND T_AGC T_STRT VCC_BB Pin Number 29 12 11 7 8 17, 18, 19, 20 22, 23, 24, 25 14 16 44 38 41 36, 37 21, 26, 28, 31 15 13 3 32 35 40 42 9 Pin Function Description Clock input for A/D converter. AD_In sampled on the falling edge. Analog Ground Connection Analog Input to the A/D Converter section. Ground Connection Base-band Voltage Output Output Lower Significant Bits. Valid data on rising edge of AD_CLK. Output Upper Significant Bits. Valid data on rising edge of AD_CLK. Ground Connection. Ground Connection Crystal Oscillator Ground Analog Ground Connection Input Voltage for IF front end gain control IF inputs. No Connection Input for enabling digital outputs. When LOW, D0-D7 are enabled. When HIGH D0-D7 are in high impedance state. Input Reference Voltage for A/D Conversion Ground Connection for High Frequency Mixed Signal Sections Input Reference Voltage for A/D Conversion Range Top (see also RB, pin #13) Analog Ground Connection Output Voltage for Tuner Gain Control Threshold Voltage Input for Starting Tuner Gain Control Baseband Supply Voltage, typically 12V
3
RC6564
PRODUCT SPECIFICATION
Pin Descriptions (continued)
Pin Name VCC2 VCC_HF VCC_RF VCC_XTL VCO_Fs VCO_In VDDD1 VDDD2 VDDA Pin Number 34 39 4 43 6 5 30 27 10 33 2 1 Pin Function Description Analog Supply Voltage (12V) Analog Supply Voltage (12V) Supply Voltage (5V) for High Frequency Mixed Signal Sections Supply voltage for Crystal Oscillator VCO External Frequency Select Circuit Connection VCO Input. Can be used for directly feeding external LO. +5V Digital supply +5V Digital supply +5V power supply voltage Output reference voltage for top of A/D input range Crystal Oscillator Output Crystal Oscillator Frequency Select Circuit Connection
Preliminary Information
VRT XTL_Out XTL_Tnk
VCO Internal Schematic
VCC-RF(4)
VCO-FS(4)
TO MIXER Q1 VCO-IN (5) Q4 + - Q5 Q3
IC=0.9mA
47.71/2
GND-VCO
The VCO is designed as a Colpitts oscillator. The frequency is controlled by the external resonance circuit. The oscillating transistor is Q1 in common base configuration. In case it is
necessary to inject the signal in place of LO in the mixer pin VCO_Fs is recommended to be open and the injected signal on pin VCO_In to be under 100mVpp.
4
PRODUCT SPECIFICATION
RC6564
Crystal Oscillator Internal Schematic
VCC-XTL (43)
3.2K
3.2K Q18 Q17
XTL-INK(1)
Q7 Q10 Q11 Q12 XTL-OUT(2)
Preliminary Information
130A
230A
130A 450A
450A
GND-XTL (44)
The crystal oscillator is an ECL inverter. In order to function correctly it needs to bias the XTL-Tnk with a choke to 5V VCC_XTL power supply. The output is about 0.7V DC lower
than VCC_XTL with an approximate swing of 0.5Vpp at the output. If the oscillator is note used, it is necessary to ground XTL_Tnk with a decoupling capacitor. This minimizes the high frequency parasitic oscillations at the XTL_Out.
Logic Feedthrough
The Logic Feedthrough in the IF section can be minimized by taking the following precautions: 1. The digital ground of ADC should be separate from analog ground of IF section. 2. All logic circuits in the neighborhood of RC6564 must be decoupled with a T-filter (choke and capacitors). This will minimize the noize radiated from the logic circuits. All logic lines from the ADC must be surrounded be a good ground plane.
3.
Absolute Maximum Ratings (beyond which the device may be damaged)1
Parameter IF_IN+, IF_IN-, IF_AGC, T_Strt AD_IN VCCRF, VCCBB, VCCHF, VCC2 VDDA, VDDD 1,2 Input Voltages A/D input voltage Analog Supply Voltages Conditions Min Gnd-0.3 AGND Typ Max VCC+0.3 VDDA 13.5 Units V V V
Digital Supply Voltages
7
V
Note: 1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded.
5
RC6564
PRODUCT SPECIFICATION
Operating Conditions
Parameter VCC Vcc3 VDDA,D T RT RB VIN VIH VIL Analog Supply Voltage HF Supply Voltage Digital Supply Voltages Temperature A/D Top Reference Voltage A/D Bottom ref. Voltage Analog input to A/D Digital Inputs - Logic HIGH Digital Input - Logic LO Thermal Coefficient Junction to Ambient Thermal Coefficient Junction to Case RB 0.7VDDD GND 43 16 Conditions Min 10.8 4.5 4.75 0 1 2.5 0 0.7 RT VDDD 0.3VDDD Typ 12 5 5 Max 13.2 5.5 5.25 70 Units V V V C V V V V V C/W C/W
Preliminary Information
qJA qJC
DC Electrical Characteristics
VCCRF, VCC_XTL = 5V; VCCHF, VCC_BB, VCC2 = 12V; TA = 0 to 70C, unless otherwise specified. Parameter PWIF PWAD ICCDD ICCHF ICCBB ICCRF VRT DVBBo Tagc_hi Tagc_lo RAD_IN VOH VOL IOZ Power Consumption in IF Power Consumption in ADC Digital Supply Current Front End Supply Current Back and Baseband Current RF Supply Current Reference Output Voltage Base-band DC output swing Tuner AGC for max gain Tuner AGC for min gain A/D input impedance Output Voltage, HIGH, D0-D7 Output Voltage, LOW, D0-D7 Hi-Z Output leakage Ioh= 2.5mA Iol=4mA Max Ref. Current Output IF_AGC=5V IF_AGC=2V 500 3.5 0.4 +5 6 7.5 2.3 1000 ADCLK = 20 Msps 5V, 20Msps 12V supply 12V supply 5V supply Conditions Min Typ 0.6 0.1 20 27 16 6 2.0 Max 0.74 0.16 30 35 25 10 Units W W mA mA mA mA V Vpp V V KW V V mA
6
PRODUCT SPECIFICATION
RC6564
AC Electrical Characteristics
VCCRF = 5V; VCCHF, VCC_BB = 12V; IF_AGC = 2V; AD_CLK = 20Msps; Tstrt = 5V; TA = 0 to 70C, unless otherwise specified. Parameter ZIFin CIFin NFmx Vis IMD3 AC Input Impedance AC equivalent input cap Noise Figure at Max gain Input sensitivity at max gain Two tone Intermod Vagc = 2.5V f1/f2=43.75 /42.75 Mhz, IF_IN= -16dBm, VCO_IN = 0.1Vpp, LO=38.75MHz, VBBo=1.35Vpp, Note 1 Vin=-46dBm @ 44MHz IF_AGC=0.8V-2.5V T_Strt=5V, IF_AGC=0.8V-2.5V 0.1dB for 10MHz bands 0.1dB for 5MHz bands VCO_IN = 0.1Vpp @ +10KHz offset @ +10KHz offset 4 +0.5 +0.3 30 AD_CLK = 20MSPS, AD_IN = 5MHz AD_CLK = 20MSPS, AD_IN = 5MHz Cload = 15pF Cload = 15pF 2 5 5 20 8 45 45 +0.75 +0.5 12 30 30 35 30 Conditions @43.75MHz IF_IN Min 2 6 9 250 45 12 Typ Max Units KW pF dB mV dB
Preliminary Information
G Ragc Sagc BW_IF fLO fnLO fnXTL CAD Eli Eld BW Eap SNR SFDR tHO tDo tsto
IF to baseband Max gain AGC Gain range AGC Sensitivity Average Slope IF Bandwidth Down conversion Freq. VCO Phase Noise XTAL OSC Phase Noise ADC input capacitance Integral Linearity Error Differential Linearity Error A/D sine wave Bandwidth Aperture Error Signal-to-Noise ratio Spurious-Free Dynamic Range Output Hold time Output Delay time Sampling time offset
40 35 13 43.75 75 80 100 -100 -100
dB dB dB/V MHz MHz dBC/Hz dBC/Hz pF LSB LSB MHz pS dB dB nS nS nS
Notes: 1. With the application of antialiasing filter as load.
7
RC6564
PRODUCT SPECIFICATION
Analog to Digital Conversion Timing Diagram
tSTO AD_IN Sample N Sample N+1 tPWL AD_CLK tDO tHO D7-0 ORP ORN Hi-Z tPWH 1/fS Sample N+2 Sample N+3
Preliminary Information
Data N-3
Data N-2 tDIS
Data N-1 tENA
Data N
OE
65-6564-04
Typical Performance Characteristics
10 9 70 60 50 8 7 T_AGC
Volts
6 5 4
Gain (dB)
40 30
IF_AGC 3
20 2
65-6564-05
T_Strt/2
65-6564-06
10 0 0V 1V 2V
1 0 0V 1V 2V 3V
3V
IF_AGC Figure 1. Typical IF AGC Control Characteristics
IF_AGC Figure 2. Typical Tuner AGC Control Characteristics
8
PRODUCT SPECIFICATION
RC6564
Typical Performance Characteristics (Continued)
40 35 30 70 60 50
Noise Figure (dB)
25
Gain (dB)
20 15 10
65-6564-07
40 30 20 10 0 40MHz 60MHz 80MHz
65-6564-08
5 0 0V 1V 2V 3V 4V
Preliminary Information
5V
100MHz
IF_AGC Figure 3. Noise Figure over Gain Control Range Figure 4. IF Input Bandwidth
Applications
The RC6564 is specially suited for use in set-top boxes and cable modems for decoding QAM modulated signals based on IF sampling techniques. The RC6564 simplifies the frontend design and makes it more cost effective by integrating in a single chip the IF-to-Digital functionality. The other major components required for the front-end of the modem are the tuner, a SAW filter and the appropriate DSP demodulator/ decoder. provides low-phase noise characteristics. The VCO and VCXO oscillator frequencies can be pulled by the voltage control on VCO_CNTRL and VCXO_CNTRL lines respectively. The sampling clock for the A/D conversion can be derived from the master clock through external frequency synthesis. The full scale reference signal for A/D is conveniently derived from the VRT output. The baseband output is referenced such that the filtered output is automatically in the mid-scale of the A/D input. The filtered output can be a.c. coupled to the AD_In. In the application below an external low-pass filter is used to bandlimit the signals before conversion. The gain is adjusted by the average voltage on the IF_AGC line to keep the signal in the optimum range of the A/D input. The T_AGC output is used to control the tuner gain when the input levels into the RC6564 are too high.
Modem Applications
Figure 5 below shows the application of RC6564 in IF bandpass sampling decoding for cable access. Here, the master clock for the Digital Demodulator can be generated using the crystal oscillator that is configured as a VCXO. The mixer down conversion clock can also be pulled in using the varactor control circuitry shown below. The on-chip VCO
9
RC6564
PRODUCT SPECIFICATION
+12V 100K 500 33pF 33pF 1F 500 390 1F BB_Out 100F 1K RT 1K RB AD_In 1.2K 1F 500
+12V
VRT
8
Preliminary Information
To DSP
RF_IN
Tuner TNR_AGC
SAW T_AGC
RC6564
AD_Clk IF_AGC XTL_Tnk XTL_Out VCO_In VCO_Fs Frm. Freq. Synth. Master Clock
LPF
VCXO_CNTRL
+5V Note: This application shows the need for a 12V supply for peak performance. Similar performance may be achieved at lower supply voltages (like 9V), but may require external buffers/drivers after BB_Out.
+5V LPF VCO_CNTRL
LPF
AGC_CNTRL
65-6564-09
Figure 5. Application of RC6564 in Cable Modem Receivers
10
PRODUCT SPECIFICATION
RC6564
Mechanical Dimensions - 44-Lead PLCC (QB) Package
Symbol A A1 A2 B B1 D/E D1/E1 D3/E3 e J ND/NE N ccc Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. All dimensions and tolerances conform to ANSI Y14.5M-1982 2. Corner and edge chamfer (J) = 45 3. Dimension D1 and E1 do not include mold protrusion. Allowable protrusion is .101" (.25mm)
.165 .180 .090 .120 .020 -- .013 .021 .026 .032 .685 .695 .650 .656 .500 BSC .050 BSC .042 .056 11 44 -- .004
4.19 4.57 2.29 3.05 .51 -- .33 .53 .66 .81 17.40 17.65 16.51 16.66 12.7 BSC 1.27 BSC 1.07 1.42 11 44 -- 0.10
3
2
Preliminary Information
E E1 J
D
D1
D3/E3 B1 e J
A A1 A2 B -C- LEAD COPLANARITY
ccc C
11
RC6564
PRODUCT SPECIFICATION
Ordering Information
Product Number RC6564V Temperature Range 0 C - 70 C
o o
Screening Commercial
Package 44-Lead PLCC
Package Marking RC6564V
Preliminary Information
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonable expected to result in a significant injury of the user.
Fairchild Semiconductor Corporation Americas Customer Response Center Tel:1-888-522-5372 Fairchild Semiconductor Europe Fax: Email: Deutsch Tel: English Tel: Italy Tel: +49 (0) 1 80-530 85 86 europe.support@nsc.com +49 (0) 8 141-35-0 +44 (0) 1 793-85-68-56 +39 (0) 2 57 5631
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
Fairchild Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Center, 5 Canto Rd. Tsimshatsui, Kowloon Hong Kong Tel:+852 2737-7200 Fax:+852 2314-0061
National Semiconductor Japan Ltd. Tel:81-3-5620-6175 Fax:81-3-5620-6179
www.fairchildsemi.com 2/98 0.0m Stock#DS30006564 O 1998 Fairchild Semiconductor Corporation
www.fairchildsemi.com
RC6564A
IF-to-DigitalTM Converter
Features
* * * * * * * * * * * * * * Integrated IF-to-DigitalTM conversion IF bandwidth from 30 to 80MHz 40MHz 8 bit ADC Operating range between 8.5V to 13.2V Demodulation of 64QAM constellations Simple interface to SAW filter and digital demodulator Tuner control feature interfaces with variety of tuners Low phase noise LO generation Crystal oscillator for fundamental or 3rd overtone mode 63dB peak conversion gain from IF to baseband 30dB minimum AGC range 45dB IMD3 end-to-end On-chip 2V stable voltage reference 44-pin PLCC package
Applications
* * * * * * QAM receivers Set-top receivers for digital cable Internet surf-boards Cable modems Desktop video conferencing IF sampling decoders
General Description
The RC6564A is a single chip solution for downconverting and digitizing QAM signals that can be decoded in the digital domain by custom DSP demodulators. The RC6564A performs IF amplification with gain control, frequency down conversion, frequency synthesis for mixer Local Oscillator (LO) and system clock generation, and baseband quantization with an Analog to Digital converter. The input can directly interface to a SAW filter and maintain low noise figure. Depending on the signal input level the gain may be controlled over a 30dB range through an external analog input signal. The gain reduction is done in two stages and orchestrated in such a manner as to minimize noise figure and signal distortion. The IF output is then down converted and filtered using a double balanced mixer. This output can be filtered even further, externally, before being quantized by the on-chip A/D converter.The digital data output can be processed to derive information for automatic gain control (AGC) and automatic frequency control (AFC). RC6564A is optimized to work with DSP decoders based on IF sampling. The RC6564A also provides an optimum tuner AGC control voltage useful for controlling the front-end tuner gain. The IF and mixer section works at 9V. The oscillator works on 5V supply. The A/D converter has one analog 5V supply and two digital 5V supplies. The RC6564A is available in a 44 pin PLCC package.
Rev. 1.0.0
RC6564A
PRODUCT SPECIFICATION
Block Diagram
VDDD1,2 (5V) VDDA (5V) DGND1,2 DEC & DRIVERS VCC_BB BBGND AGND VREF MATRIX IF_AGC T_Strt T_AGC VCO
65-6564-02
BB_Out
LP FILTER
VCC_HF HFGND IF_IN+
RF BB LO
AD_In T/H
46dB 17dB
COARSE A/D
IF_IN-
D0-D7
x2
- + XTAL Osc BANDGAP REF FINE A/D
OE
VCC_RF (5V)
XTL_Out
VCO_In
XTL_Tnk
GND_XTL
VCC_XTL
VCO_Fs
RFGND
VRT RT RB
Functional Description
The RC6564A performs all the IF and baseband signal processing/conversion with minimal external components. As shown in the Block Diagram, the RC6564A consists of three general sections: 1. 2. 3. IF Gain blocks with Gain Control IF down conversion with LO & Clock Generation Analog to Digital Conversion the mixer can be directly driven or synthesized through the VCO (Voltage Controlled Oscillator). The mixer output is partially filtered on-chip but may need to be further filtered externally before being fed to the A/D input. The RC6564A also has a crystal oscillator circuit that can be used for generating a master clock for frequency synthesis.
Analog-to-Digital Converter
The analog-to-digital converter employs a two-step 9-bit architecture to convert analog signals into digital words at sample rates up to 40 Msps (Mega samples per second). An integral Track/Hold circuit delivers excellent performance on signals with full-scale components up to 12MHz. A dynamic performance of more than 7.4 effective bits is delivered at the outputs D0 through D7. The A/D digital outputs are three-state and TTL/CMOS compatible. The down converted output at BB_OUT can be externally filtered and directly connected to the A/D input. Sampling of the applied input signals takes place on the falling edge of the AD_CLK. The output word is delayed by 2.5 AD_CLK cycles. An output enable control OE places the outputs in high impedance state when HIGH. The outputs are enabled when OE is LOW as described in the Timing Diagrams section.
The IF Section
The signal input is fed into a variable gain amplifier capacitively coupled to the subsequent stages. The gain is directly proportional to IF_AGC voltage. To minimize the noise figure degradation with gain reduction the gains in various stages are not reduced simultaneously. The transition point is set by the voltage on T_Strt pin. T_Strt sets the T_AGC trigger to control the front tuner gain.
IF Down Conversion & Frequency Synthesis
This section consists of a double balanced linear mixer. The output of the front-end gain stage is capacitively coupled to the input (RF port) of the mixer. The mixer output is further amplified. The signals for the Local Oscillator (LO) port of
2
AD_CLK
SGND
VCC2
PRODUCT SPECIFICATION
RC6564A
Pin Assignments
VCO_Fs VCO_In VCC_RF RFGND XTL_Out XTL_Tnk GND_XTL VCC_XTL T_STRT IF_AGC T_AGC
6 5 4 3 2 1 44 43 42 41
BBGND BB_Out VCC_BB VDDA AD_In AGND RB DGND1 OE DGND2 D0
40
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
39 38 37 36 35 34 33 32 31 30 29
VCC_HF HFGND IF_IN- IF_IN+ SGND VCC2 VRT RT NC VDDD1 AD_CLK
D1 D2 D3 NC D4 D5 D6 D7 NC VDDD2 NC
65-6564A-03
Pin Descriptions
Pin Name AD_CLK AGND AD_In BBGND BB_Out D0-D3 D4-D7 DGND1 DGND2 GND_XTL HFGND IF_AGC IF_IN+, IF_IN- N/C OE RB RFGND RT SGND T_AGC T_STRT VCC_BB Pin Number 29 12 11 7 8 17, 18, 19, 20 22, 23, 24, 25 14 16 44 38 41 36, 37 21, 26, 28, 31 15 13 3 32 35 40 42 9 Pin Function Description Clock Input for A/D Converter. AD_In sampled on the falling edge. Analog Ground Connection for A/D. Analog Input to the A/D Converter Section. Ground Connection for IF. Base-band Voltage Output. Output Lower Significant Bits. Valid data on rising edge of AD_CLK. Output Upper Significant Bits. Valid data on rising edge of AD_CLK. Ground Connection for A/D. Ground Connection for A/D. Crystal Oscillator Ground for IF. Analog Ground Connection for IF. Input Voltage for IF Front End Gain Control IF Inputs. No Connection Input for Enabling Digital Outputs. When LOW, D0-D7 are enabled. When HIGH D0-D7 are in high impedance state. Bottom Input Reference for A/D. Ground Connection for High Frequency Mixed Signal Sections for IF. Top Input Reference Voltage for A/D. Analog Ground Connection for IF. Output Voltage for Tuner Gain Control. Threshold Voltage Input for Starting Tuner Gain Control. Baseband Supply Voltage. Typically 9V for IF.
3
RC6564A
PRODUCT SPECIFICATION
Pin Descriptions (continued)
Pin Name VCC2 VCC_HF VCC_RF VCC_XTL VCO_Fs VCO_In VDDD1 VDDD2 VDDA VRT XTL_Out XTL_Tnk Pin Number 34 39 4 43 6 5 30 27 10 33 2 1 Pin Function Description Analog Supply Voltage (9V) for IF. Analog Supply Voltage (9V) for IF. Supply Voltage (5V) for High Frequency Mixed Signal Sections for IF. Supply voltage for Crystal Oscillator for IF. VCO External Frequency Select Circuit Connection. VCO Input. Can be used for directly feeding external LOW. +5V Digital Supply for A/D. +5V Digital Supply for A/D. +5V Power Supply Voltage for A/D. Output Reference Voltage from IF for Top of A/D Input Range. Crystal Oscillator Output (inverted). Crystal Oscillator Frequency Select Circuit Connection.
Absolute Maximum Ratings (beyond which the device may be damaged)1
Parameter IF_IN+, IF_IN-, IF_AGC, T_Strt AD_IN VCC_RF, VCC_BB, VCC_HF, VCC2, VCC_XTL VDDA, VDDD 1,2 Tstg Input Voltages A/D input voltage Analog Supply Voltages Conditions Min Gnd-0.3 AGND Typ Max VCC+0.3 VDDA 13.5 Units V V V
Digital Supply Voltages Storage Temperature -40
7 125
V C
Note: 1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded.
Operating Conditions
Parameter VCC VCC_RF, VCC_XTL VDDA,D T RT RB VIN VIH VIL qJA qJC Analog Supply Voltage Supply Voltage for IF and Mixer, Supply Voltage for XTLOSC and VCO Digital Supply Voltages Temperature A/D Top Reference Voltage A/D Bottom Reference Voltage Analog Input to A/D Digital Inputs - Logic HIGH Digital Input - Logic LOW Thermal Coefficient Junction to Ambient Thermal Coefficient Junction to Case RB 0.7VDDD GND 43 16 Min 8.5 4.75 4.75 0 1 2.5 0 0.7 RT VDDD 0.3VDDD Typ 9 5 5 Max 13.2 5.25 5.25 70 Units V V V C V V V V V C/W C/W
4
PRODUCT SPECIFICATION
RC6564A
DC Electrical Characteristics
VCCRF, VCC_XTL = 5V; VCCHF, VCC_BB, VCC2 = 9V; TA = 0 to 70C, unless otherwise specified. Parameter PWIF PWAD ICCDD ICCHF ICCBB ICCRF VRT DVBBo Tagc_hi Tagc_lo RAD_IN VOH VOL IOZ Power Consumption in IF Power Consumption in ADC Digital Supply Current Front End Supply Current Back and Baseband Current RF Supply Current Reference Output Voltage Base-band DC Output Swing Tuner AGC for Maximum Gain Tuner AGC for Minimum Gain A/D Input Impedance Output Voltage, HIGH, D0-D7 Output Voltage, LOW, D0-D7 Hi-Z Output Leakage Ioh = 2.5mA Iol = 4mA Maximum Reference Current Output IF_AGC = 5V IF_AGC = 2V 500 3.5 0.4 +5 ADCLK = 20 Msps 5V, 20Msps 9V Supply 12V Supply 9V Supply 5V Supply 1.95 3.5 7.5 2 1000 Conditions Min Typ 0.4 0.1 20 20 27 21 6 2.05 Max 0.5 0.16 30 25 35 25 10 2.15 mA mA V Vpp V V KW V V mA Units W W mA mA
AC Electrical Characteristics
VCC_XTL, VCC_RF = 5V; VCC_HF, VCC_BB = 9V; IF_AGC = 2V; AD_CLK = 20Msps; Tstrt = 5V; TA = 0 to 70C, unless otherwise specified. Parameter ZIFin CIFin Vis IMD3 AC Input Impedance AC Equivalent Input Cap Input Sensitivity at Maximum Gain Two Tone Intermod f1/f2 = 43.75 /42.75 Mhz, IF_IN= -16dBm, VCO_IN = 0.1Vpp, LO = 38.75MHz, See Note 1 IF_AGC = 2V IF_AGC = 0.8V-4V T_Strt = 5V, IF_AGC = 0.8V-4V 0.1dB for 10MHz Bands 0.1dB for 5MHz Bands VCO_IN = 0.1Vpp @ +10KHz Offset @ +10KHz Offset 4 +0.5 +0.3 +0.75 +0.5 30 30 35 30 Conditions @43.75MHz IF_IN Min 2 6 250 45 Typ Max Units KW pF mV dB
G NF Ragc Sagc BW_IF fLO fnLO fnXTL CAD Eli Eld
IF to Baseband Gain Noise Figure (Maximum Gain) AGC Gain Control Range AGC Sensitivity Average Slope IF Bandwidth Down Conversion Frequency VCO Phase Noise XTAL OSC Phase Noise ADC Input Capacitance Integral Linearity Error Differential Linearity Error
40 9 35 10 43.75 75 80 100 -100 -100
dB dB dB dB/V MHz MHz dBC/Hz dBC/Hz pF LSB LSB
5
RC6564A
PRODUCT SPECIFICATION
AC Electrical Characteristics (continued) VCC_XTL, VCC_RF = 5V; VCC_HF, VCC_BB = 9V; IF_AGC = 2V; AD_CLK = 20Msps; Tstrt = 5V; TA = 0 to 70C, unless otherwise specified.
Parameter BW Eap SNR tHO tDO tSTO A/D sine wave Bandwidth Aperture Error Signal-to-Noise ratio Output Hold time Output Delay time Sampling time offset AD_CLK = 20MSPS, AD_IN = 5MHz Cload = 15pF Cload = 15pF 2 5 5 20 8 30 45 Conditions Min Typ Max 12 Units MHz pS dB nS nS nS
Notes: 1. With the application of antialiasing filter as load and 2Vpp at A/D input.
Analog to Digital Conversion Timing Diagram
tSTO AD_IN Sample N Sample N+1 tPWL AD_CLK tDO tHO D7-0 ORP ORN Data N-3 Data N-2 tDIS Hi-Z Data N-1 tENA Data N tPWH 1/fS Sample N+2 Sample N+3
OE
65-6564-04
Typical Performance Characteristics
70 60 50
70 60 50
Gain (dB)
Gain (dB)
40 30 20 10 0
65-6564A-05
40 30 20 10 0 40MHz 60MHz 80MHz
65-6564A-08
100MHz
0V 0.5V 1.0V 1.5V 2.0V 2.5V 3.0V 3.5V 4.0V
IF_AGC
Figure 1. Typical IF AGC Control Characteristics
Figure 2. IF Input Bandwidth
6
PRODUCT SPECIFICATION
RC6564A
Typical Performance Characteristics (Continued)
SFDR Comparison for RC6564A & RC6508/1175A 60 55 50 45 SFDR 40 S/N 35 30 25 20 15 10 20 25 30 35 40 45 50 IF Gain, dB 55 60 65 10 -60 -50 -40 -30 -20 IF Input Power, dBm -10 0 20 15 25 35 30 40 Comparison of 64 QAM Front End Solutions
Figure 3. SFDR vs RC6564A (Fairchild Semiconductor Demo Board with 64 QAM demodulator)
S/N vs. IF Input Power RC6564 (Fairchild Semiconductor Demo Board with 64 QAM demodulator)
Applications
The RC6564A is specially suited for use in set-top boxes and cable modems for decoding QAM modulated signals based on IF sampling techniques. The RC6564A simplifies the front-end design and makes it more cost effective by integrating in a single chip the IF-to-Digital functionality. The other major components required for the front-end of the modem are the tuner, a SAW filter and the appropriate DSP demodulator/decoder. pling clock for the A/D conversion can be derived from the master clock through external frequency synthesis. The full scale reference signal for A/D is conveniently derived from the VRT output. The baseband output is referenced such that the filtered output is automatically in the mid-scale of the A/ D input. The filtered output can be a.c. coupled to the AD_In. In the application below an external low-pass filter is used to bandlimit the signals before conversion. The gain is adjusted by the average voltage on the IF_AGC line to keep the signal in the optimum range of the A/D input. The T_AGC output is used to control the tuner gain when the input levels into the RC6564A are too high.
Modem Applications
Figure 4 below shows the application of RC6564A in IF bandpass sampling decoding for cable access. The on-chip VCO provides low-phase noise characteristics. The VCO can be pulled by the voltage control on VCO_CNTRL. The sam-
7
8
+9V Analog R101 1000 C53 0.1F C52 .001F C95 0.1F +9V Analog L21 FB Postamplifier Antialiasing Filter R17 200 C16 68pF L9 4H C13 1F R11 9.53K R10 1.2K C22 4.7F Q2 2N3904 C18 100pF IF_GND R12 2.74K R6 470 R7 470 Q1 2N3904 1F C23 0.1F IF_GND C28 0.001F C98 0.1F IF_GND IF_GND C43 1000pF IF_GND C103 0.1F Voltage Gain Control Input R97 1000 R100 1000 Tuner Control Output R15 180 R16 180 IF_GND 33nH L7 IN GND2 GND1 24 C47 1F R11 6.8K VRT 33 RT 32 RB 13 AD_In 11 42 T_STRT C45 1000pF 2V DC Ref C37 4.7F C31 R29 0.1F 1000 ADC_GND +9V Analog IF_GND OUT 3 Siemens Matsushita Components 43.75MHz SAW Filter C47 X6964M 1000pF 1 Input 4 Output 2 Input-ground 3 GND 5 Output 41 IF_AGC 40 T_AGC 36 IF+ 37 IF- VCC_BB 9 BB_OUT 8 C107 0.001F 1000 R94 R91 IF_GND 1000 R87 47K C86 0.1F IF_GND 39 VCC_HF 34 VCC2 +5V DC R112 5.6K IF_GND C110 C108 L106 0.001F 4.7F 33H C109 0.1F
RC6564A
MSA-0785-Amplifier
64QAM Input Signal 5MHz Bandwidth Hewlett Packard Centered on 43.75MHz
1
C57 1000pF
IF_GND
RC6564A
5 VCO_In D[7:0] 18-25 AD_CLK 29 C84 7pF 6 VCO_Fs
VCO_CNTRL R93 1000 C92 0.1F 100pF IF_GND C81 0.001F C79 4.7F +5V Analog C71 4.7F C72 4.7F IF_GND ADC_GND +5V Digital C67 0.001F ADC_GND ADC_GND L83 33H C73 0.1F C78 0.1F L70 33H D88 MMBV809LT1 1H L83 C85 4-25pF C90 0.1F
R32 1000 1V DC +2Vpp AC QAM Signal ADC_GND
IF_GND
L77 33H
+5V Analog
C80 0.001F
OE DGND1 DGND2 AGND
15 14 16 12
ADC Data Bus Outputs to DSP
ADC Sampling Clock Input BBGND RFGND GND_XTL HFGND SGND ADC_GND
IF_GND
4 VCC_RF 43 VCC_XTL 10 VDDA 27 VDDD2 30 VDDD1 1 XTL_Tnk 2 XTL_Out
7 3 44 38 35
IF_GND 65-6564-12 C61 C60 4.7F 0.1F C59 0.001F
Figure 4. Application of RC6564A in Cable Modem Receivers (Fairchild Semiconductor Demo Board with 64 QAM demodulator)
ADC_GND
IF_GND
ADC_GND
PRODUCT SPECIFICATION
NOTE: It is recommended to connect two islands of grounds, IF_GND and ADC_GND to ensure minimum logic feedthrough from ADC to IF.
PRODUCT SPECIFICATION
RC6564A
VCO Internal Schematic
L2 33H L1 1H VCO_FS(6) VCC_RF (4) 0.1F C4 1nF 4.7F C6 C5 0.1F C7 1nF C8 +5V 1F C9
IC = 0.9MA 10pF C1 5pF C2 Q1 VCO-In (5) + - Q5 220pF C3 47.71/2 Internal RFGND(3) Q3 Q4 TO MIXER
The VCO can be designed as a Colpitts oscillator. The above circuit application shows VCO with adjustable typical value of 38.75 MHz. The frequency is controlled by the external resonance circuit. The oscillating transistor is Q1 in
common base configuration. To inject signal in the mixer in place of LO, the VCO_Fs must be open. The signal on the pin VCO_In should be under 100mVp-p and AC coupled.
9
RC6564A
PRODUCT SPECIFICATION
Crystal Oscillator Internal Schematic
L2 1nF 1F 33H 0.1F +5V C6 1nF 1F C7 C8
0.1F VCC-XTL (43)
C3
C4
C5
L3
8H 3.2K 3.2K Q18 Q17 XTL-Tnk(1) Q7 Q10 Q11 Q12 XTL-OUT(2) 100pF VCO-IN (5) 2K VCC-XTL (43)
33pF
C1 130A 230A 130A 450A 450A Internal GND-XTL (44) 47pF C2 2001/2
The crystal oscillator is an ECL inverter. It is necessary to bias the XTL-Tnk with a choke to 5V VCC_XTL power supply. The output is about 0.7V DC lower than VCC_XTL with
an approximate swing of 0.5Vpp at the output. If the oscillator is not used, it is good to ground XTL_Tnk pin.
Logic Feedthrough
The Logic Feedthrough in the IF section can be minimized by taking the following precautions: 1. It is recommended to have a separate isle for the IF section and the A/D section. 3. 2. All logic circuits in the neighborhood of RC6564A must be isolated. This can be accomplished by carefully decoupling all power supplies and all logic layout signals. It is recommended to have as much ground plane as possible on the top and bottom of the board.
10
PRODUCT SPECIFICATION
RC6564A
Mechanical Dimensions - 44-Lead PLCC (QB) Package
Symbol A A1 A2 B B1 D/E D1/E1 D3/E3 e J ND/NE N ccc Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. All dimensions and tolerances conform to ANSI Y14.5M-1982 2. Corner and edge chamfer (J) = 45 3. Dimension D1 and E1 do not include mold protrusion. Allowable protrusion is .101" (.25mm)
.165 .180 .090 .120 .020 -- .013 .021 .026 .032 .685 .695 .650 .656 .500 BSC .050 BSC .042 .056 11 44 -- .004
4.19 4.57 2.29 3.05 .51 -- .33 .53 .66 .81 17.40 17.65 16.51 16.66 12.7 BSC 1.27 BSC 1.07 1.42 11 44 -- 0.10
3
2
E E1 J
D
D1
D3/E3 B1 e J
A A1 A2 B -C- LEAD COPLANARITY
ccc C
11
RC6564A
PRODUCT SPECIFICATION
Ordering Information
Product Number RC6564AV Temperature Range 0 C - 70 C
o o
Screening Commercial
Package 44-Lead PLCC
Package Marking RC6564AV
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonable expected to result in a significant injury of the user.
Fairchild Semiconductor Corporation Americas Customer Response Center Tel:1-888-522-5372 Fairchild Semiconductor Europe Fax: Email: Deutsch Tel: English Tel: Italy Tel: +49 (0) 1 80-530 85 86 europe.support@nsc.com +49 (0) 8 141-35-0 +44 (0) 1 793-85-68-56 +39 (0) 2 57 5631
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
Fairchild Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Center, 5 Canto Rd. Tsimshatsui, Kowloon Hong Kong Tel:+852 2737-7200 Fax:+852 2314-0061
National Semiconductor Japan Ltd. Tel:81-3-5620-6175 Fax:81-3-5620-6179
www.fairchildsemi.com 2/98 0.0m Stock#DS30006564A O 1998 Fairchild Semiconductor Corporation
www.fairchildsemi.com
RC6601
Voltage Programmable Video Filter
Features
* * * * * * * * * * * 250 kHz to 10 MHz minimum programmable range Precision factory-trimmed cutoff frequency of 5.5MHz Approximates CCIR601 digital video standard Phase corrected for minimum group delay variation External voltage or current control of cutoff frequency 0.25 % differential gain, RL = 150W 0.20 differential phase, RL = 150W Minimum external components required Single ended input/output 5V power supply 16-pin SOIC package
Description
The RC6601 is a fully integrated continuous time filter, designed for various video filtering applications. The RC6601 approximates the requirements of the CCIR601 standard for digitizing NTSC and PAL video signals. It provides factory-set pass band ripple of 0.25 dB typical up to 5.5 MHz with a -40 dB stop band, beginning at 8 MHz. The structure of the filter assures wide dynamic range operation with low noise and low distortion. The cutoff frequency is factory set at 5.5 MHz (5% typical). It can be varied over a range of 250 kHz-10 MHz by a user supplied voltage VF. The voltage VF can be readily derived from the on-chip precision reference voltage VREF as shown in the typical application circuit. The RC6601 is packaged in a 300 mil wide body, 16-pin SOIC package. The package dimensions are included in this data sheet.
Applications
* * * * * * Video filtering Communication filters ADC anti-aliasing filter HDTV Set top boxes Satellite modems
Block Diagram
VTRIM
IN 1M VREF VCC 5.5M 10M
OUT ROS1 ROS2
REF
VF VTRIM
GND
65-6601-01
Rev. 1.0.0
RC6601
PRODUCT SPECIFICATION
Functional Description
Digitizing video signals requires high-order anti-aliasing filters that can handle large signal swings with low distortion. CCIR601 standards recommend equi-ripple gain and group delay characteristics for filtering NTSC and PAL signals. RC6601 is a single-chip solution that matches the requirements with less than 0.25dB gain ripple, 20ns group delay variation in the passband, and more than 40dB attenuation in the stop band. The block diagram in Figure 1a shows the direct synthesis of the filter transfer function as a fifth order elliptic with third order phase equalization. The cut-off frequency, nominally set at 5.5MHz, is continuously programmable over a decade. Using current mode techniques, the IC can drive 2Vpp signals into 75W load drawing only 35mA quiescent current. The architecture of the complete filter as illustrated by Figure 1a is a 5th-order elliptic transfer function in tandem with a 3rd-order all-pass phase equalizer. The Cauer-elliptic response function has an equi-ripple passband with a sharp roll-off into stop-band in the magnitude transfer function but causes excessive group delay peaking. The equalizer maintains this magnitude response while compensating for the group delay peaking. These two filters are represented in Figure 1a by a series of 2nd-order expressions that can be realized as biquads using transimpedance-based integrators. Elliptic poles and zeros give a flat magnitude response in passband and a 40dB roll-off from 5.5MHz to 8MHz. The equalizer transfer function corrects group delay to 15ns to 90% of the cut-off frequency. These pole-zero values determine biquad coefficients as shown in Figure 1b. A supplyindependent band-gap cell generates and distributes bias currents for all the transimpedance integrators as in Figure 1b. The cut-off frequency is programmed by globally scaling the currents, using a single external setting. The entire filter, including the programmable bias generators, is integrated on a single chip using complementary bipolar technology. The npn and pnp transistors have a cutoff frequency of 4GHz and of 1.5GHz respectively. Gateoxide-based capacitors and thin film resistors with 0.5% match set filter time constants. At 5.5MHz cut-off, the filter averages 2.5mA/pole. Nearly 15mA of the supply current is used for the output driver. The cut-off frequency is actually programmable beyond the 1-10 MHz, with an external voltage control. Measured differential gain of 0.25% and a differential phase of 0.2 make it well suited for video applications.
Magnitude Selectivity Gain dB Equalizer
Phase Equalization Group Delay ns Elliptic
Elliptic Transfer Equalizer 1MHz 5.5MHz WZ1 WZ 2
5th Order Elliptic Function
3rd Order Bessel Equalizer
YIN
K1 (s2 + wZ12) s2
K2 (s2 + wZ22)
2
KwR
2
s2 - (wA/QA) s + wA2 s2
s - wB s + wB
+ (w1/Q1) s + w1
s2
+ (w2/Q2) s + w2
s + wR
+ (wA/QA) s + wA
2
YOUT
65-6601-02
Figure 1a. Composite Video Filter
2
PRODUCT SPECIFICATION
RC6601
IN
K1(s2 + wz12) s2 + (w1/Q1)s + w12
K2(s2 + wz22) s2 + (w2/Q2)s + w22
R3 s + R3
s2 - (wA/QA)s + wA2 s2 + (wA/QA)s + wA2
s - RA s + RA
OUT
Bias Current Generator
Ref. Gen.
65-6601-03
VTRIM
VF
GND
VCC
VREF
K1, K2 = 0.09293 Q1 = 5.67 Q2 = 1.1776 QA = 0.691
wZ1 = 1.415wc wZ2 = 2.0733wc R3 = 0.59678wc RA = 1.323wc
w1 = 1.046wc w2 = 0.855wc wA = 1.44868wc
where wc = cut off frequency (in radians) e.g. for default filter: wc = 2p * (5.5)106 = 34.5575 x 106 Scaling bias currents directly scales the frequency wc Figure 1b. Internal Programming Architecture
Pin Assignments
VEE1 IN VCOM NC NC NC GND VREF
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
65-6601-04
VCC OUT VEE2 VTRIM ROS2 ROS1 NC VF
Pin Descriptions
Pin Name GND IN NC OUT ROS1 ROS2 VCC VCOM VEE1 VEE2 VF VREF VTRIM Pin Number 7 2 4-6, 10 15 11 12 16 3 1 14 9 8 13 Description Supply Ground Signal Input No Connect Signal Output Offset Adjust 1 Offset Adjust 2 Positive Supply Voltage Common Mode Input Voltage (See Note) Negative Supply Voltage (Input Section) Negative Supply Voltage (Output Section) Filter Control Voltage for Cut-off Frequency Precision Reference Voltage Pass Band Peaking Voltage
Note: VCOM pin is typically connected to ground for 5V supply.
3
RC6601
PRODUCT SPECIFICATION
Absolute Maximum Ratings
(beyond which the device may be damaged)1 Parameter Positive Power Supply (VCC) Negative Power Supply (VEE1, VEE2) Input Voltage Input Current (Power On or Off) Operating Temperature Storage Temperature Junction Temperature Lead Soldering (10 seconds) Short Circuit Tolerance 0 -40 150 300 Min. Typ. Max. 6 -6 (VEE1, VEE2) -0.3 V to VCC to +0.3V 10 70 125 Units V V V mA C C C C
No more than one output may be shorted to ground.
Note: 1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded.
Operating Conditions
Parameter VCC VEE IS qJA Power Supply Voltage Negative Supply Voltage Quiescent Supply Current SO16 Thermal Resistance Min. 4.75 -5.25 Typ. 5.0 -5.0 40 105 Max. 5.25 -4.75 50 Units V V mA C/W
DC Electrical Characteristics
VCC = 5V, VEE1,2 = -5V, CL = 15pF, RL = 150W, TA = 25C, unless otherwise specified. Parameter AV RIN IO VOFF VREF IREF VF RF DC gain accuracy Input resistance Output current Output offset voltage Reference voltage Reference output current Frequency set voltage (FC = 5.5 MHz 10%) Frequency set input resistance Max reference out current IF = 0, Measure VF Without offset adjust With offset adjust -500 -10 2.30 2.48 5 1.24 5.0 DC Conditions VIN = 2 Vpp Min. 0.90 Typ. 1 4 10 +500 +10 2.60 Max. 1.10 Units V/V kW mA mV mV V mA V kW
4
PRODUCT SPECIFICATION
RC6601
AC Electrical Characteristics
VCC = 5V, VEE1,2 = -5V, CL = 15pF, RL = 150W, fPB = 5.5 MHz, TA = 25C, unless otherwise specified. Parameter Filter Characteristics fPB fCA fCT DtGD VIN CIN DG DP en SR RO ATT Passband frequency Filter cutoff accuracy Filter cutoff drift5 Group delay flatness Input signal range Input capacitance Diff. gain, NTSC & PAL Diff. phase, NTSC & PAL RMS output noise voltage Positive slew rate3 Negative slew Attenuation1 Attenuation2 Attenuation2 Attenuation2 Attenuation2 Attenuation1,4 Attenuation2,4 Attenuation2,4 Attenuation2,4 Attenuation2,4 SPW Sensitivity of cutoff frequency vs. supply voltages rate3 Output resistance fin 5.0 MHz, VIN = 1 Vpp fin 5.0 MHz, VIN = 1 Vpp fin = 6.75 MHz, VIN = 1 Vpp fin = 8 MHz, VIN = 1 Vpp 8 MHz < fin < 50 MHz, VIN = 1 Vpp fIN 2.5 MHz, VIN = 1 Vpp fIN 2.5 MHz, VIN = 1 Vpp fIN = 3.375 MHz, VIN = 1 Vpp fIN = 4 MHz, VIN = 1 Vpp 4 MHz < fIN < 50 MHz, VIN = 1 Vpp VS = 5 V, VF = 1.25 V 1 -40 -35 VIN = 286 mVpp, 4.43 MHz VIN = 286 mVpp, 4.43 MHz RS = 75 W, 10 MHz BW(7) VIN = 2 Vpp VIN = 2 Vpp
5,6
Conditions VF 0V VF = VREF 2.5V fPB = 5.5MHz fPB = 5.5MHz fin = 100 kHz to 4,9 MHz THD < 1 %(7)
Min. 10 .25 -5 -5
Typ. 15
Max.
Units MHz
1 +5 +5 20 2 10 .25 .20 1.3 60 60 3 0.10 0.5 -12 -40 -40 0.10 0.5 -35 0.25 1 -8 0.25 1 -8 2.0
MHz % % ns Vpp pF % mV V/ms V/ms W dB dB dB dB dB dB dB dB dB dB %/V
1
Notes: 1. VTRIM adjusted for optimum response. 2. No external adjustments. 3. Guaranteed no slew limit on 2V p-p input at 9 MHz. 4. Filter programmed for 2.75 MHz cutoff, VF = 1.85V. 5. Filter cutoff defined to edge of ripple spec. 6. Initial setpoint accuracy of cutoff, excluding temperature and long term drift. 7. Guaranteed by design.
5
RC6601
PRODUCT SPECIFICATION
Performance Curves
10.0 0 Attenuation (dB)
1 (dB) 350 (ns)
Attenuation (dB)
Group Delay (ns)
0 300 (ns)
-40.0
65-6601-05
-1 (dB) 250 (ns) 1 2 3 4 Frequency (MHz) 5 6
65-6601-06
-60.0 .2 .4 .6.8 1 2 4 6 810 20 40 Frequency (MHz)
Figure 2. Amplitude Response--Default Setting
Figure 3. Attentuation and Group Delay
10.0 0 -10.0
Cutoff Frequency (MHz)
Vf = 0V
15
900 800 700 Passband Group Delay (nS)
-20.0 -30.0 Gain (dB) -40.0 -50.0 -60.0
65-6601-07
10 600 500 400 300 200 0 0 0.2 0.4 0.6 0.8 1 Vf (V) 1.2 1.4 1.6 1.8 2 100
5
-70.0 -80.0 68 1 -90.0 50 KHz 2 4 68 1 2 4 68 1
Vf = 1.9V
2 4 50 MHz
Frequency (Hz)
65-6601-08
Figure 4. Amplitude Responses Over Programming Range
Figure 5. Frequency Programming Using Vf and Passband Group Delay
Application Discussion
The RC6601 is fully integrated in the sense that no critical external components are required for the low pass filtering function. For luminance filtering at a cut-off frequency of 5.5MHz, the only off-chip components are the decoupling capacitors and termination resistors shown in Figure 6. The part also provides temperature and supply independent bandgap reference voltages (2.48V and 1.24V) that can be used for setting the ADC converters or DACs in the system. The programmable feature of the RC6601 makes it versatile for use in applications with other standard cut-off frequencies. There are three ways of changing the cut-off frequency. 1. External Voltage setting on VF: A higher voltage on VF than 1.2V gives a lower frequency than 5.5MHz cutoff. The highest frequency (above 10MHz) is obtained by grounding the VF pin. 2. Potentiometer at VREF (pin 8) and/or VF (pin 9): There is an internal resistor divider of roughly 10K each that sets the default voltage of 1.2V at half the value of VREF. Using a lower value external pot of 1K-2K, the internal setting can be overridden. Current Source/Sink at VF: The typical current output from a DAC can be tied to the VF pin to program the cut-off frequency from a controller.
3.
In applications requiring dynamic programming of the filter cut-off, a combination of above techniques may be used. Use of the RC6601 in such applications eliminates the need for multiplexers and filter banks. The other adjustment possible on the RC6601 is the output d.c. level. The output d.c. level can be adjusted by connecting a potentiometer between pins ROS1 and ROS2 (pins 11 and 12) and taking the center tap to VCC. These adjustments are shown in Figure 7 below.
6
PRODUCT SPECIFICATION
RC6601
4.7F 12H -5V Test Source 751/2 .1F Video Input 1F
3 4 5 6 7 2 1
VEE1
VCC 16 .1F OUT
15 14 13 12 11 10 9
+5V 22F .1F 4.7F Test Source 1501/2
IN
Video Output 1F -5V .1F 1kW
VCOM NC NC NC
RC6601
VEE2 VTRIM ROS2 ROS1 NC VF
65-6601-09
GND 8 VREF
100k .1F
Figure 6. Fixed Configuration CCIR601 (Cutoff frequency is factory set to 5.5MHz)
12H -5V .1F Test Source 751/2 Video Input
1
VEE1
VCC
16
+5V .1F Video Output -5V 1kW 10 kW +5V VOFFSET ADJUST .1F 4.7F Test Load 150W
4.7F
2 IN 3 VCOM 4
22F OUT 14 VEE2 VTRIM 13
15
NC NC NC
5 6 7
RC6601
ROS2 ROS1
12
Frequency Adjust: 10 kW
8
GND
11 10
VREF VF ADJUST
NC VF 9
.1F
65-6601-10
Figure 7. Cutoff Frequency and Offset Tunable Filter
7
RC6601
PRODUCT SPECIFICATION
Notes:
8
PRODUCT SPECIFICATION
RC6601
Notes:
9
RC6601
PRODUCT SPECIFICATION
Notes:
10
PRODUCT SPECIFICATION
RC6601
Mechanical Dimensions - 16 Pin SOIC Package
Symbol A A1 B C D E e H h L N a ccc Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
.093 .104 .004 .012 .013 .020 .009 .013 .398 .413 .291 .299 .050 BSC .394 .010 .016 16 0 -- 8 .004 .419 .020 .050
2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 10.10 10.50 7.40 7.60 1.27 BSC 10.00 0.25 0.40 16 0 -- 8 0.10 10.65 0.51 1.27
3 6
16
9
E
H
1
8
D A e B A1 SEATING PLANE -C- LEAD COPLANARITY ccc C a
h x 45 C
L
11
RC6601
PRODUCT SPECIFICATION
Ordering Information
Product Number RC6601M Temperature Range 0 to 70C Screening Commercial Package 16 Pin Wide SOIC Package Marking RC6601M
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS30006601 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
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RC7100
100MHz Motherboard System Clock
Features
Four copies of CPU clock Eight copies of PCI Clock (Synchronous w/CPU clock) Two copies of IOAPIC clock @ 14.318MHz Two copies of 48MHz clock Three copies of REF clock @ 14.318MHz Reference crystal oscillator (14.318MHz) Spread Spectrum (-0.5%) clocking Power management controls Low frequency test mode
Description
The RC7100 is a clock synthesizer for 100MHz operation on Pentium II based motherboard systems. It contains 4 copies of the CPU clock, 8 copies of the PCI clock, 3 copies of the REF clock, 2 copies of the 48MHz clock and 2 copies of the IOAPIC clock. The CPU and PCI clocks are generated through a phase locked loop and are stable within 3mS after power-up meeting the Pentium II stabilization specifications. The 48MHz clocks are generated through a second phase locked loop. The RC7100 accepts a 14.318MHz crystal as its reference frequency and operates at a core voltage of 3.3V. A 14.318MHz external clock can also be used instead of the
Advanced Information
Applications
100MHz motherboard clock synthesizers for Pentium II CPU based Desktop and Notebook Systems.
Block Diagram
3 REF0:2 VDDref VSSref 2 XTAL_IN/ TCLK 4 CPUCLK0:3 VDDcpu VSScpu SPREAD# PWRDWN# PLL_1 7 PCICLK0:6 VDDpci VSSpci PCICLKF SEL0 SEL1 SEL100/66# PCISTOP# CPUSTOP# 2 48 MHz0:1 PLL_2 VSS48MHz VDDcore VSScore APIC0:1 VDDapic VSSapic
XTAL_OUT
VDD48MHz
Pentium is a registered trademark of Intel Corporation
Rev. 0.5.3
ADVANCED INFORMATION describes products that are not in full production at the time of printing. Specifications are based on design goals and limited characterization. They may change without notice. Contact Fairchild Semiconductor for current information.
RC7100
PRODUCT SPECIFICATION
Description (continued)
crystal. The REF and IOAPIC clocks are generated directly from the reference frequency. The PWRDWN# pin when low powers down the crystal oscillator and the two phase locked loops. Other pins to control power are the CPUSTOP# and PCISTOP#. The CPUSTOP# when low causes the CPU clocks to go to a low state. The PCISTOP# when low causes the PCI clocks with the exception of the PCICLK_F to go to a low state. The PCICLK_F is a free-running clock. All clock outputs will be tristated when SEL0, SEL1 and SEL100/66# are all low. Frequency selection between 100 MHz and 66 MHz can be accomplished with the SEL100/66#. SEL100/66# high will provide the 100 MHz operation and low will provide a clock frequency of 66 MHz. Additional frequency selections including TEST MODE can be had with other combinations of the SEL0 and SEL1 pins. See Table 1 for more details. Spread Spectrum clocking is available for the CPU and PCI clocks. It can be activated by bringing the SPREAD# pin to a low state. the REF, IOAPIC and 48MHz clocks are not affected by the SPREAD#.
Advanced Information
Table 1. Selectable Modes
SEL0 0 1 0 1 0 1 0 1 SEL 1 0 0 1 1 0 0 1 1 SEL100/66 0 0 0 0 1 1 1 1 CPU HI-Z 75 75 66 TC/2 83.3 83.3 100 PCI HI-Z 37.5 30 33 TC/6 41.65 33.3 33 REF HI-Z 14.318 14.318 14.318 TC/2 14.318 14.318 14.318 IOAPIC HI-Z 14.318 14.318 14.318 TC 14.318 14.318 14.318 48 HI-Z 48 48 48 TC 48 48 48
Pin Assignments
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 Pin # Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 REF0 REF1 VSSref XTALIN XTALOUT VSSpci PCICLKF PCICLK0 VDDpci PCICLK1 PCICLK2 VSSpci Pin # Pin Name 13 14 15 16 17 18 19 20 21 22 23 24 PCICLK3 PCICLK4 VDDpci PCICLK5 PCICLK6 VSSpci VDDcore VSScore VDD48MHz 48MHz0 48MHz1 VSS48MHz Pin # Pin Name 25 26 27 28 29 30 31 32 33 34 35 36 SEL100/66# SEL1 SEL0 SPREAD# PWRDWN# CPUSTOP# PCISTOP# VSScore VDDcore VSScpu CPUCLK3 CPUCLK2 Pin # Pin Name 37 38 39 40 41 42 43 44 45 46 47 48 VDDcpu VSScpu CPUCLK1 CPUCLK0 VDDcpu NC VSSapic APIC1 APIC0 VDDapic REF2 VDDref
2
PRODUCT SPECIFICATION
RC7100
Pin Descriptions
Pin Name REF0:2 Pin Number 2, 1, 47 Type OUT Pin Function Description Reference clock outputs running at a fixed frequency equal to the reference crystal or external frequency (14.318MHz). These operate from a 3.3V power source. APIC clocks running at a fixed frequency equal to the reference crystal or external frequency. It is usually 14.318MHz. These operate from a 2.5V power source. CPU clocks used to drive the CPU processor. These clock outputs operate from a 2.5V power source. Free-running PCI clock which is not affected by PCISTOP#. PCI clocks for generating all PCI timing requirements. These clock outputs operate from a 3.3V power source. 48MHz clocks are fixed frequency outputs for USB or super I/O requirements. Crystal oscillator input or external reference generator input. Crystal oscillator output. Selects 100MHz or 66MHz for CPU clocks. When this input is at a "1" level, the CPU frequency will be 100MHz and if at a "0" level the frequency will be 66MHz. Control select pins for selecting different modes of operation. PWRDWN# is an input pin used to power-down the chip when low. Stops PCI clocks at low state when low Stops CPU clocks at a low state when low SPREAD# is active low and when activated the CPU and PCI clocks are spread from 0.5% below the maximum frequency to the maximum frequency. 3.3V supply for PCICLK, PCICLKF, REF, 48MHz drivers and PLL core
APIC0:1
44, 45
OUT
CPUCLK0:3 PCICLKF PCICLK0:6 48MHz0:1 XTALIN XTALOUT SEL100/66#
35, 36, 39, 40 7 8, 10, 11, 13, 14, 16, 17 22, 23 4 5 25
OUT OUT OUT OUT IN OUT IN
Advanced Information
SEL1, SEL0 PWRDWN# PCISTOP# CPUSTOP# SPREAD#
26, 27 29 31 30 28
IN IN IN IN IN
VDDpci, VDDref, VDDcore, VDD48MHz VDDcpu, VDDapic VSSref, VSSpci, VSS48MHz, VSScore, VSScpu, VSSapic NC
9, 15, 19, 21, 33, 48
POWER
37, 41, 46 3, 6, 12, 18, 20, 24, 32, 34, 38, 43
POWER GROUND
2.5V supply for CPU and APIC drivers Ground
42
reserved
No connect - reserved for future use
3
RC7100
PRODUCT SPECIFICATION
Absolute Maximum Ratings
Parameter Supply Voltage, VDD Input Voltage Output, Applied Voltage Junction Temperature Storage Temperature Lead Soldering (10 seconds) -65 Min. -0.5 -0.5 -0.5 Typ. Max. 5 VDD+.5 VDD+.5 140 150 300 Units V V V C C C
Advanced Information
Notes: 1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions. Functional operation under any of these conditions is NOT implied. 2. Applied voltage must be current limited to specified range, and measured with respect to GND. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current, flowing into the device.
Operating Conditions
Parameter VDDapic 2.5V Power Supply Voltage VDDcpu VDDref 3.3V Power Supply Voltage VDD48MHz VDDpci VDDcore Ambient Temperature Min. 2.375 3.135 Typ. 2.5 3.3 Max. 2.625 3.465 Units V V
0
70
C
4
PRODUCT SPECIFICATION
RC7100
Electrical Characteristics
Parameter Logic inputs VIL VIH IIL IIH VOL VOH IOL Input low voltage Input high voltage Input low current Input high current Outputs @ 1mA Outputs @ -1mA CPU0:3@ vol = 1.4V PCI_F, PCI1:7 @ vol = 1.4V APIC0:1 @ vol = 1.4V REF0:2 @ vol = 1.4V 48MHz0:1 @ vol = 1.4V IOH CPU0:3 @ voh = 1.4V PCI_F, PCI1:7 @ voh = 1.4V APIC0:1 @ voh = 1.4V REF0:2 @ voh = 1.4V 48MHz0:1 @ voh = 1.4V Crystal oscillator VTH CLOAD CIN(XIN) CIN COUT LIN Input threshold voltage Load capacitance imposed on external crystal Input capacitance Input Pin Capacitance Output Pin Capacitance Input Pin Inductance 13.5 18 18 22.5 5 6 7 V pF pF pF pF nH 2.4 28 26.5 42 25 25 -24 -31 -36 -27 -27 100 139 150 76 76 -94 -189 -140 -94 -94 -0.3 2.0 0.8 VDD+.3 -5 5 0.4 V V mA mA V V mA mA mA mA mA mA mA mA mA mA Min. Typ. Max. Units
Clock Outputs
Advanced Information
Pin Capacitance/Inductance
5
RC7100
PRODUCT SPECIFICATION
Switching Characteristics
Parameter CPU Clocks CPU0:3 Period High time Low time Tr Tf tjitter Conditions CLOAD = 20pF 100MHz 66MHz 100MHz 66MHz 100MHz 66MHz 100MHz, 66MHz 100MHz, 66MHz 100MHz, 66MHz 100MHz, 66MHz 100MHz, 66MHz 100MHz, 66MHz 100MHz, 66MHz 100MHz, 66MHz 100MHz, 66MHz 100MHz, 66MHz 100MHz, 66MHz 100MHz, 66MHz 100MHz, 66MHz 100MHz, 66MHz 100MHz, 66MHz 100MHz, 66MHz 12.0 12.0 500 3 30.0 500 1.5 1.0 1.0 45 10 15 3.0 5.2 2.8 5.0 0.4 0.4 1.6 1.6 250 55 175 8.0 8.0 3.0 4.0 250 10.5 15.5 nS nS nS nS nS pS % pS nS nS mS nS pS nS pS nS nS pS mS Min. Typ. Max. Units
Advanced Information
6
Duty cycle @ V = 1.25V tskew tpZL, tpZH tpLZ, tpHZ tstabilization toffset (CPU to PCI) IOAPIC APIC0:1 tskew PCI PCICLK_F, PCICLK1:7 tperiod tperiod stability thigh tlow tskew tstabilization
PRODUCT SPECIFICATION
RC7100
Mechanical Dimensions
48 pin SSOP
Symbol A A1 b c D E E1 e L N a ccc Inches Min. .095 .008 Max. .110 .016 Millimeters Min. 2.41 0.20 Max. 2.79 0.41 5 5 2, 4 2 3 6 Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 2. "D" and "E1" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5. "b" & "c" dimensions include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
.0135 .008 .010 .005 .630 .620 .420 .395 .299 .291 .025 BSC .040 .020 48 0 8 --.004
0.34 0.20 0.25 0.13 16.00 15.75 10.67 10.03 7.59 7.39 0.64 BSC 1.02 0.51 48 0 8 --0.13
Advanced Information
E E1
1
D A e b A1 SEATING PLANE -CLEAD COPLANARITY ccc C c a L
7
RC7100
PRODUCT SPECIFICATION
Ordering lnformation
Product Number RC7100 Temperature 0C to 70C Screening Package 48 SSOP Package Marking RC7100
Advanced Information
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS50007100 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC7101
Low Skew Buffers
100MHz SDRAM Clock Buffers Features
* * * * * * 18 skew controlled outputs Supports up to four SDRAM DIMMs Skew between any two outputs is less than 250 pS I2C Serial Interface for programming options Multiple power and ground pins for noise reduction Single 3.3V power supply 48 Pin SSOP package
Description
The RC7101 is a low voltage eighteen output clock buffer which supports 4 DIMMs. The skew between any two outputs is less than 250 pS and the buffers can be individually enabled or disabled by programming via the I2C serial interface. The SDATA and SCLK serial inputs both have internal pull-up resistors. An Output Enable (OE) pin is also provided so that all the outputs can be tri-stated when held low. This pin is normally high and has an internal pull-up resistor.
Advanced Information
Applications
* SDRAM Clock Buffers for Intel's 440BX chip set
OE 0 1
SDRAM0:3 SDRAM4:7 SDRAM8:11 SDRAM12:15 SDRAM16:17 Hi-Z BUF_IN Hi-Z BUF_IN Hi-Z BUF_IN Hi-Z BUF_IN Hi-Z BUF_IN
Block Diagram
SDRAM0 SDATA I2C SCLOCK SDRAM1 SDRAM2 SDRAM3 SDRAM4 SDRAM5 SDRAM6 SDRAM7 SDRAM8 BUF_IN SDRAM9 SDRAM10 SDRAM11 SDRAM12 SDRAM13 SDRAM14 SDRAM15 SDRAM16 SDRAM17 OE
Rev. 0.5.2
ADVANCED INFORMATION describes products that are not in full production at the time of printing. Specifications are based on design goals and limited characterization. They may change without notice. Contact Fairchild Semiconductor for current information.
RC7101
PRODUCT SPECIFICATION
Pin Assignments
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 Pin# 1 2 3 4 5 6 7 8 9 10 11 12 Pin Name NC NC VDD SDRAM0 SDRAM1 VSS VDD SDRAM2 SDRAM3 VSS BUF_IN VDD Pin# 13 14 15 16 17 18 19 20 21 22 23 24 Pin Name SDRAM4 SDRAM5 VSS VDD SDRAM6 SDRAM7 VSS VDD SDRAM16 VSS VDD SDATA Pin# 25 26 27 28 29 30 31 32 33 34 35 36 Pin Name SCLOCK VSS VSS SDRAM17 VDD VSS SDRAM8 SDRAM9 VDD VSS SDRAM10 SDRAM11 Pin# 37 38 39 40 41 42 43 44 45 46 47 48 Pin Name VDD OE VSS SDRAM12 SDRAM13 VDD VSS SDRAM14 SDRAM15 VDD NC NC
Advanced Information
48 Pin SSOP
Pin Descriptions
Pin Name BUF_IN SDRAM0:3 SDRAM4:7 SDRAM8:11 SDRAM12:15 SDRAM16:17 OE SDATA SCLOCK VDD VDD VSS VSS NC Pin Number 11 4, 5, 8, 9 13, 14, 17, 18 31, 32, 35, 36 40, 41, 44, 45 21, 28 38 24 25 3, 7, 12, 16, 20, 29, 33, 37, 42, 46 23 Type IN OUT OUT OUT OUT OUT IN I/O IN Power Power Pin Function Description Input for clock buffers SDRAM Byte 0 clock outputs SDRAM Byte 1 clock outputs SDRAM Byte 2 clock outputs SDRAM Byte 3 clock outputs SDRAM clock outputs Output enable which will tri-state all the outputs when held low Serial Data Line Serial Clock input Power supply at 3.3V for SDRAM buffers Power supply at 3.3V for I2C circuit Ground for SDRAM buffers Ground for I2C circuit No Connections.
6, 10, 15, 19, 22, Ground 27, 30, 34, 39, 43 26 1, 2, 47, 48 Ground NC
2
PRODUCT SPECIFICATION
RC7101
Absolute Maximum Ratings
Parameter Supply Voltage, VDD Input Voltage Output Applied Voltage Junction Temperature Storage Temperature Lead Soldering (10 seconds) -65 Min. -0.5 -0.5 -0.5 Typ. Max. 5 VDD+0.5 VDD+0.5 140 150 300 Units V V V C C C
Notes: 1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions. Functional operation under any of these conditions is NOT implied. 2. Applied voltage must be current limited to specified range, and measured with respect to GND. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current, flowing into the device.
Advanced Information
Operating Conditions
Parameter VDD Ambient Temperature Min. 3.135 0 Typ. 3.3 Max. 3.465 70 Units V
o
C
Electrical Characteristics TA = 0C to 70C, VDD = 3.3V5%
Parameter VIL, Input low voltage VIH, Input high voltage IIL, Input low current (BUF_IN) IIH, Input high current (BUF_IN) IIL, Input low current OE, SDATA, SCLOCK) IIH, Input high current (OE, SDATA, SCLOCK) VOL, Output low voltag VOH, Output high voltage IOL, Output low current IOH, Output high current IDD, Supply current IDD, Supply current IDD, Supply current CIN, Input capacitance FIN, Input frequency IOL = 23mA IOH = -30mA VOL = 0.8V VOH = 2.0V f = 100MHz f = 66MHz OE = 0 5 150 2.6 40 -54 Conditions Min. -0.3 2.0 Typ. Max. 0.8 VDD+0.3 -25 10 -50 10 0.4 Units V V A A A A V V mA mA mA mA mA pF MHz
3
RC7101
PRODUCT SPECIFICATION
Switching Characteristics
Parameter TPD, Propagation delay TR, Rise time TF, Fall time TD, Duty cycle TEN, Output enable time TDIS, Output disable time TSK, Skew ZO, Output impedance Conditions VT = 1.5V 0.4 to 2.4V 2.4 to 0.4V VT = 1.5V VT = 1.5V VT = 1.5V VT = 1.5V 15 Min. 1 0.5 0.5 45 1 1 Typ. Max. 5 1.5 1.5 55 8 8 250 Units ns ns ns % ns ns ps
Advanced Information
Serial Data Interface
Signaling Requirements for the I2C Serial Port
To initiate communications with the serial port, a start bit is invoked. The start bit is defined as the SDATA line is brought low while the SCLOCK is held high. Once the start bit is initiated, valid data can then be sent. Data is considered to be valid when the clock goes to and remains in the high state. The data can change when the clock goes low. To terminate the transmission, a stop bit is invoked. The stop bit occurs when the SDATA line goes from a low to a high state while the SCLOCK is held high. See Figure below.
SDATA
SCLOCK
Start Bit
Data Valid
Change Data
Stop Bit
The data transfer rate is 100kbits/s in the standard mode and 400kbits/s in the fast mode. The serial protocol uses block writes only. Bytes are written with the lowest first and the highest last with the ability to stop after any complete byte
has been transferred. The clock driver is a slave/receiver only and is only capable of receiving data with the exception of sending acknowledgements. It is not capable of sending data.
4
PRODUCT SPECIFICATION
RC7101
Byte writing sequence
The buffer is accessed when the slave address byte is received. Each byte of data is followed by an acknowledge bit. The address bit sequence is 1 1 0 1 0 0 1 followed by the R/W# bit (0). Bits are written with the Most Significant Bit (MSB) first. The MSB Bit is bit 7 and the LSB is bit 0. The Byte writing sequence is as shown in the table below.
Byte Sequence 1 2 3 4 5 6 7 8 9 10
Bit sequence Byte name Slave address Command Code Byte Count Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 Data Byte 4 Data Byte 5 Data Byte 6 X X X X 7 1 X X 6 1 X X 5 0 X X 4 1 X X 3 0 X X 2 0 X X 1 1 X X 0 0 X X
see table below see table below see table below
Advanced Information
X X X X
X X X X
X X X X
X X X X
X X X X
X X X X
X X X X
Data Bytes 0 to 2 Map
Bit Pin Name Description Data Byte 0: SDRAM Active/Inactive Register (1 = enable, 0 = disable) 7 18 SDRAM7 (ACTIVE/INACTIVE) 6 17 SDRAM6 (ACTIVE/INACTIVE) 5 14 SDRAM5 (ACTIVE/INACTIVE) 4 13 SDRAM4 (ACTIVE/INACTIVE) 3 9 SDRAM3 (ACTIVE/INACTIVE) 2 8 SDRAM2 (ACTIVE/INACTIVE) 1 5 SDRAM1 (ACTIVE/INACTIVE) 0 4 SDRAM0 (ACTIVE/INACTIVE) Data Byte 1: SDRAM Active/Inactive Register (1 = enable, 0 = disable) 7 45 SDRAM15 (ACTIVE/INACTIVE) 6 44 SDRAM14 (ACTIVE/INACTIVE) 5 41 SDRAM13 (ACTIVE/INACTIVE) 4 40 SDRAM12 (ACTIVE/INACTIVE) 3 36 SDRAM11 (ACTIVE/INACTIVE) 2 35 SDRAM10 (ACTIVE/INACTIVE) 1 32 SDRAM9 (ACTIVE/INACTIVE) 0 31 SDRAM8 (ACTIVE/INACTIVE) Data Byte 2: SDRAM Active/Inactive Register (1 = enable, 0 = disable) 7 28 SDRAM17 (ACTIVE/INACTIVE) 6 21 SDRAM16 (ACTIVE/INACTIVE) 5 reserved reserved 4 reserved reserved 3 reserved reserved 2 reserved reserved 1 reserved reserved 0 reserved reserved
5
RC7101
PRODUCT SPECIFICATION
RC7101 I2C Interface Write Sequence
Signal from Motherboard Clock Chip START MSB RC7101 Slave Address (First Byte) LSB Command Code (2nd Byte) Byte Count (3rd Byte) Last Data Byte
STOP
SDATA SCLK
1 1
1 2
0 3
1 4
0 5
0 6
1 7
0 8 A
MSB 1 2 3
LSB 8 A
MSB 1 2
LSB 8 A
MSB 1 2
LSB 8 A
SDATA (ACK Signal From Buffer Chip)
Note:
Once the clock detects the start condition and its ADDRESS is matched, the clock chip will pull down the SDATA at every 8th bit. The 8 bit data from SDATA is latched into the Buffer Chip when the ACK is generated. This ACK signal will continue as long as STOP condition is detected The COMMAND CODE and BYTE COUNT is not used by the Buffer Chip.
Advanced Information
Application Circuit
RC7101 Clock Generator CPUCLK Output Enable
22 RS
RC7101 BUF_IN OE
I2C Control
SDATA SCLK SDRAM (0:17) 22 RS*
3.3V Supply
Recommended Isolation VDD
L = 32 @ 100MHz 100F 33F 0.1F Cd* 2.2nF
Multi-Via Ground Connection VSS
*Each VDD pin should be separately decoupled with a 2.2nF capacitor.
6
PRODUCT SPECIFICATION
RC7101
Mechanical Dimensions
48 pin SSOP
Symbol A A1 b c D E E1 e L N a ccc Inches Min. .095 .008 Max. .110 .016 Millimeters Min. 2.41 0.20 Max. 2.79 0.41 5 5 2, 4 2 3 6 Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 2. "D" and "E1" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5. "b" & "c" dimensions include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
.008 .0135 .005 .010 .620 .630 .395 .420 .291 .299 .025 BSC .020 .040 48 8 0 --.004
0.34 0.20 0.13 0.25 16.00 15.75 10.03 10.67 7.39 7.59 0.64 BSC 0.51 1.02 48 8 0 --0.13
Advanced Information
E E1
1
D A e b A1 SEATING PLANE -CLEAD COPLANARITY ccc C c a L
7
RC7101
PRODUCT SPECIFICATION
Ordering lnformation
Product Number RC7101 Temperature 0C to 70C Screening Package 48 SSOP Package Marking RC7101
Advanced Information
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com 1/21/99 0.0m 003 Stock#DS50007101 (c) 1998 Fairchild Semiconductor Corporation
www.fairchildsemi.com
RC7102
BX Spread Spectrum Frequency Synthesizer for Pentium II(R)
Features
* Maximized EMI suppression using Fairchild's proprietary Spread Spectrum Technology * Single chip system frequency synthesizer for Intel BX chip set * Two copies of CPU output * Six copies of PCI output * One 48MHz output for USB * One 24MHz output for SIO * Two buffered reference outputs * One IOAPIC output * Fourteen SDRAM outputs provide support for 3 DIMMs * Supports frequencies up to 150MHz * I2C interface for programming * Power management control inputs * Smooth CPU frequency switching from 66.8
Description
The RC7102 was developed as a single chip device to meet the clocking needs of the Intel BXTM chipset. In addition to the typical outputs provided by standard 100 MHz BXTM FTG's, the RC7102 adds a fourteen output buffer, supporting SDRAM DIMM modules in conjunction with the chipset.
Advanced Information
Fairchild's proprietary spread spectrum frequency synthesis technique is a feature of the CPU and PCI outputs. When enabled, this feature reduces the peak EMI measurements by up to 10dB.
Block Diagram
X1 X2 XTAL OSC C O N T R O L L O G I C
REF0 REF1/FS2 IOAPIC CPU0:1 PCI_F/MODE PCI1:5 48MHz/FS0 24MHz/FS1 SDRAM0 SDRAM12:13 SDRAM10/PCI_STOP# SDRAM11/CPU_STOP#
PLL1
SDATA I2C SCLK
PLL2 SDRAMIN
ADVANCED INFORMATION describes products that are not in full production at the time of printing. Specifications are based on design goals and limited characterization. They may change without notice. Contact Fairchild Semiconductor for current information.
RC7102
PRODUCT SPECIFICATION
Table 1. Mode Input Table Mode 0 1 Pin 17 CPU-STOP# SDRAM11 Pin 18 PCI_STOP# SDRAM10
Table 2. Pin Selectable Frequency Input Address FS2 1 1 1 1 0 0 0 0 FS1 1 1 0 0 1 1 0 0 FS0 1 0 1 0 1 0 1 0 CPU Outputs (MHz) 100 133.3 112 103 66.8 83.3 75 124 PCI Outputs (MHz) 33.3 (CPU/3) 44.4 (CPU/3) 37.3 (CPU/3) 34.3 (CPU/3) 33.4 (CPU/2) 41.7 (CPU/2) 37.5 (CPU/2) 41.3 (CPU/3)
Advanced Information
Pin Assignments
48 pin SSOP
VDDQ3 REF0 GND X1 X2 VDDQ3 PCI_F/MODE PCI1 GND PCI2 PCI3 PCI4 PCI5 VDDQ3 SDRAMIN GND CPU_STOP#/SDRAM11 PCI_STOP#/SDRAM10 VDDQ3 SDRAM9 SDRAM8 GND SDATA I2C SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDQ2 IOAPIC REF1/FS2 GND CPU0 CPU1 VDDQ2 SDRAM13 SDRAM12 GND SDRAM0 SDRAM1 VDDQ3 SDRAM2 SDRAM3 GND SDRAM4 SDRAM5 VDDQ3 SDRAM6 SDRAM7 VDDQ3 48MHz/FS0 24MHz/FS1
2
PRODUCT SPECIFICATION
RC7102
Pin Assignments
Pin Name CPU0:1 PCI1:5 MODE/PCI_F Pin Number 43, 44 8, 10, 11, 12, 13 7 Type OUT OUT IN/OUT Pin Function Description CPU Outputs: The CPU clock outputs are controlled by the CLK_STOP# control pin. PCI Clock Outputs 1 through 5: These five PCI clock outputs are controlled by the PCI_STOP# control pin. Fixed PCI Clock Output: Frequency is set by the FS0:2 inputs or through serial input interface. (see Tables 2 and 6) This output is not affected by the PCI_STOP# input. Upon power-up MODE input will be latched, which will enable or disable SDRAM10 and SDRAM11. (see Tables 1 and 2) CPU_STOP Input: When brought low, the CPU clock outputs are stopped low after completing a full clock cycle. IOAPIC Clock Output: Provides 14.318MHz fixed frequency. The output voltage swing is controlled by VDDQ2.. 48MHz Output: 48MHz is provided in normal operation. In standard systems, this output can be used as the reference for the Universal Serial Bus. Upon power-up FS0 input will be latched, which will set clock frequencies as described in Table 2. 24MHz Output: 24MHz is provided in normal operation. In standard systems, this output can be used as the clock input for a Super I/O chip. Upon power-up FS1 input will be latched, which will set clock frequencies as described in Table 2. I/O Dual Function REF1 and FS2 pin: Upon power-up, FS2 input will be latched which will set clock frequencies as described in Table 2. When an output, this pin provides a fixed clock signal equal in frequency to the reference signal provided at the X1/X2 pins. REF0 output, this pin provides a fixed clock signal equal in frequency to the reference signal provided at the X1/X2 pins. Buffered Input Pin: The signal provided to this input pin is buffered to 14 outputs (SDRAM0:13). Buffered Outputs: These fourteen dedicated outputs provide copies of the signal provided at the SDRAMIN input. The swing is set by VDDQ3, and if the CPU clock is used to drive the SDRAMIN then they are deactivated when CPU_STOP# input is set low. Clock pin for I2C Circuitry. Data pin for I2C Circuitry. Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318MHz crystal connection or as an external reference frequency input. SDRAM10 or PCI_STOP# Pin: Function determined by MODE pin. The PCI_STOP# input enables the PCI 1:5 outputs when high and causes them to remain at logic 0 when low. Crystal Connection: An input connection for an external 14.318MHz crystal. If using an external reference, this pin must be left unconnected. Power Connection: Power supply for core logic, PLL circuitry, SDRAM outputs, PCI outputs, reference outputs, 48MHz output, and 24MHz output. Connect to 3.3V supply
CPU_STOP#/ SDRAM11 IOAPIC 48MHz/FS0
17 47 26
IN/OUT OUT IN/OUT
Advanced Information
24MHz/FS1
25
IN/OUT
REF1/FS2
46
IN/OUT
REF0 SDRAMIN SDRAM0:13
2 15 38, 37, 35, 34, 32, 31, 29, 28, 21, 20, 18, 17, 40, 41 24 23 4
OUT IN OUT
SCLK SDATA X1
IN IN/OUT IN
PCI_STOP#/ SDRAM10 X2
18
IN/OUT
5
IN
VDDQ3
1, 6, 14, 19, 27, 30, 36
POWER
3
RC7102
PRODUCT SPECIFICATION
Pin Assignments (continued)
Pin Name VDDQ2 GND Pin Number 42, 48 3, 9, 16, 22, 33, 39, 45 Type POWER GROUND Pin Function Description Power Connection: Power supply for IOAPIC, CPU_F, and CPU1 output buffers. Connect to 2.5V. Ground Connections: Connect all ground pins to the common system ground plane.
Absolute Maximum Ratings1
(beyond which the device will be damaged) Symbol VDD, VIN Parameter Voltage on any pin with respect to GND Storage Temperature Ambient Temperature under Bias Operating Temperature Input ESD Protection Rating -0.5 to +7.0 -65 to +150 -55 to +125 0 to +70 2 (min) Unit V C C C kV
Advanced Information
TSTG TB TA ESDPROT
Notes: 1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded.
4
PRODUCT SPECIFICATION
RC7102
DC Electrical Characteristics
TA = 0C to +70C; VDDQ3 = 3.3V5%; VDDQ2 = 2.5V5%
Parameter Supply Current IDD 3.3V Supply Current IDD 2.5V Supply Current Min. Typ TBD TBD Max Unit mA mA Test Condition CPU0:1 = 100Mhz Outputs Loaded1 CPU0:1 = 100Mhz Outputs Loaded1
Logic Inputs VIL Input Low Voltage VIH Input High Voltage IIL Input Low Current2 Input High Current2 IIH Clock Outputs VOL Output Low Voltage VOH Output High Voltage VOH Output High Voltage IOL Output Low Current:
GND -.3 2.0
0.8 VDD +.3 -25 10 0.4
V V A A
Advanced Information
IOH
Output High Current
CPU0:1, IOAPIC CPU0:1 IOAPIC PCI_F, PCI1:5 SDRAM0:13 REF0:1 48MHz 24Mhz CPU_F, CPU1 IOAPIC PCI_F, PCI1:5 SDRAM0:13 REF0:1 48MHz 24MHz
2.4 2.0 27 27 26.5 55 25 25 25 -101 -101 -189 -188 -94 -94 -94 1.65 18
93 93 139 152 76 76 76 -26 -26 -31 -50 -27 -27 -27
V V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA V pF
IOL = 1mA IOH = 1mA IOH = -1mA VOL = 1.2V VOL = 1.2V VOL = 1.4V VOL = 1.4V VOL = 1.4V VOL = 1.4V VOL = 1.4V VOH = 1.2V VOH = 1.2V VOH = 1.4V VOH = 1.4V VOH = 1.4V VOH = 1.4V VOH = 1.4V VDDQ3 = 3.3V Pin X2 unconnected Except X1 and X2
Crystal Oscillator VTH X1 Input threshold Voltage (Note 3) CIN,X1 X1 Input Capacitance (Note 5) Pin Capacitance/Inductance Input Pin Capacitance CIN COUT Output Pin Capacitance LIN Input Pin Inductance
5 6 7
pF pF nH
Notes: 1. All clock outputs loaded with 6" 60 ohm traces with 22pF capacitors. 2. RC7102 logic inputs have internal pull-up devices (pull-ups not full CMOS level). 3. X1 input threshold voltage (typical) is VDD/2. 4. The RC7102 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 14pF; this includes typical stray capacitance of short PCB traces to crystal. 5. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
5
RC7102
PRODUCT SPECIFICATION
AC Electrical Characteristics
TA = 0C to +70C; VDDQ3 = 3.3V5%; VDDQ2 = 2.5V5%; f XTL = 14.31818MHz
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output; Spread Spectrum clocking is disabled.
CPU Clock Outputs, CPU0:1 (Lump Capacitance Test Load = 20pF)
CPU = 66.6MHz Parameter tP tH tL tR tF tD tJC Period High Time Low Time Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle 15 5.2 5.0 1 1 45 4 4 55 250 15.5 CPU = 100MHz 10 3.0 2.8 1 1 45 4 4 55 250 10.5 ns ns ns V/ns V/ns % ps Measured on rising edge at 1.25. Duration of clock cycle above 2.0V. Duration of clock cycle below 0.4V. Measured from 0.4V to 2.0V. Measured from 2.0V to 0.4V. Measured on rising and falling edge at 1.25V. Measured on rising edge at 1.25V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.25V. Assumes full supply voltage reached within 1ms from powerup. Average value during switching transition. Used for determining series termination value. Min. Typ. Max. Min. Typ. Max. Units Test Condition/Comments
Advanced Information
tSK fST
Output Skew Frequency Stabilization from Power-up (cold start) AC Output Impedance 20
175 3
175 3
ps ms
Z0
20
ohm
PCI Clock Outputs, PCI_F and PCI_1:5 (Lump Capacitance Test Load = 30pF)
CPU = 66.6/ 100MHz Parameter tP tH tL tR tF tD tJC Period High Time Low Time Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Min. Typ. Max. 30 12.0 12.0 1 1 45 4 4 55 500 Units ns ns ns V/ns V/ns % ps Test Condition/Comments Measured on rising edge at 1.5V. Duration of clock cycle above 2.4V. Duration of clock cycle below 0.4V. Measured from 0.4V to 2.4V. Measured from 2.4V to 0.4V. Measured on rising and falling edge at 1.5V. Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.5V. Covers all CPU/PCI outputs. Measured on rising edge at 1.5V. CPU leads PCI output. Assumes full supply voltage reached within 1ms from power-up.
tSK tO fST
Output Skew CPU to PCI Clock Skew Frequency Stabilization from Power-up (cold start) 1.5
500 4.0
ps ns ms
6
PRODUCT SPECIFICATION
RC7102
PCI Clock Outputs, PCI_F and PCI_1:5 (Lump Capacitance Test Load = 30pF) (continued)
CPU = 66.6/ 100MHz Parameter Z0 AC Output Impedance Min. Typ. Max. 30 Units ohm Test Condition/Comments Average value during switching transition. Used for determining series termination value.
IOAPIC Clock Output (Lump Capacitance Test Load = 20pF)
CPU = 66.6/ 100MHz Parameter f tR tF tD fST Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance 15 1 1 45 Min. Typ. Max. Units 14.3818 4 4 55 1.5 MHz V/ns V/ns % ms Test Condition/Comments Frequency generated by crystal oscillator. Measured from 0.4V to 2.0V.
Advanced Information
Measured from 2.0V to 0.4V. Measured on rising and falling edge at 1.25V. Assumes full supply voltage reached within 1ms from power-up. Average value during switching transition. Used for determining series termination value.
Z0
ohm
REF0:1 Clock Output (Lump Capacitance Test Load = 20pF)
CPU = 66.6/ 100MHz Parameter f tR tF tD fST Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance 40 0.5 0.5 45% Min. Typ. Max. Units 14.3818 2 2 55 3 MHz V/ns V/ns % ms Test Condition/Comments Frequency generated by crystal oscillator. Measured from 0.4V to 2.4V. Measured from 2.4V to 0.4V. Measured on rising and falling edge at 1.5V. Assumes full supply voltage reached within 1ms from power-up. Average value during switching transition. Used for determining series termination value.
Z0
ohm
48MHz Clock Output (Lump Capacitance Test Load = 20pF)
CPU = 66.6MHz Parameter f fD m/n tR tF tD Frequency, Actual Deviation from 48MHz PLL Ratio Output Rise Edge Rate Output Fall Edge Rate Duty Cycle 0.5 0.5 45% Min. Typ. Max. Units 48.008 +167 57/17 2 2 55 V/ns V/ns % MHz ppm Test Condition/Comments Determined by PLL divider ratio (see n/m below). (48.008 - 48)/48 (14.31818MHz x 57/17 = 48.008MHz) Measured from 0.4V to 2.4V. Measured from 2.4V to 0.4V. Measured on rising and falling edge at 1.5V.
7
RC7102
PRODUCT SPECIFICATION
48MHz Clock Output (Lump Capacitance Test Load = 20pF) (continued)
CPU = 66.6MHz Parameter fST Frequency Stabilization from Power-up (cold start) AC Output Impedance 40 Min. Typ. Max. Units 3 ms Test Condition/Comments Assumes full supply voltage reached within 1ms from power-up. Average value during switching transition. Used for determining series termination value.
Z0
ohm
24MHz Clock Output (Lump Capacitance Test Load = 20pF)
CPU = 66.6MHz Parameter Min. Typ. Max. Units 24.004 +167 57/34 0.5 0.5 45% 2 2 55 3 V/ns V/ns % ms MHz ppm Test Condition/Comments Determined by PLL divider ratio (see n/m below). (24.004 - 24)/24 (14.31818MHz x 57/34 = 24.004MHz) Measured from 0.4V to 2.4V. Measured from 2.4V to 0.4V. Measured on rising and falling edge at 1.5V. Assumes full supply voltage reached within 1ms from power-up. Average value during switching transition. Used for determining series termination value.
Advanced Information
f fD m/n tR tF tD fST
Frequency, Actual Deviation from 24MHz PLL Ratio Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance
Z0
40
ohm
SDRAM Clock Outputs, SDRAM0:13 (Lump Capacitance Test Load =30pF)
Parameter fIN tR tF tSR tSF tEN tDIS tPR tPF tD ZO Input Frequency Output Rise Time Output Fall Time Output Skew, Rising Edge Output Skew, Falling Edge Output Enable Time Output Disable Time Rising Edge Propagation Delay Falling Edge Propagation Delay Duty Cycle AC Output Impedance 1.0 1.0 1.0 1.0 45 15 Min. 0 0.5 0.5 Typ. Max. 150 1.33 1.33 250 250 8.0 8.0 5.0 5.0 55 Units MHz nS nS pS pS nS nS nS nS % Measured at 1.5V Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Test Conditions/Comments
8
PRODUCT SPECIFICATION
RC7102
Functional Description
I/O Pin Operation
Pins 7, 17, 18, 25, 26, 46 are dual purpose l/O pins. Upon power up these pins act as logic inputs, allowing the determination of assigned device functions. A short time after power up, the logic state of each pin is latched and the pins become clock outputs. This feature reduces device pin count by combining clock outputs with input select pins. An external 10k ohm "strapping" resistor is connected between the l/O pin and ground or VDD. Connection to ground sets a latch to "0", connection to VDD sets a latch to "1". Figure 1 and Figure 2 show two suggested methods for strapping resistor connections. Upon RC7102 power up, the first 2ms of operation is used for input logic selection. During this period, the six I/O pins(7, 17, 18, 25, 26, 46) are tristated, allowing the output strapping resistor on the l/O pins to pull the pin and their associated capacitive clock load to either a logic high or low state. At the end of the 2ms period, the established logic "0" or "1" condition of the l/O pin is latched. Next the output
buffer is enabled which converts the l/O pins into operating clock outputs. The 2ms timer is started when VDD reaches 2.0V. The input bits can only be reset by turning VDD off and then back on again. It should be noted that the strapping resistors have no significant effect on clock output signal integrity. The drive impedance of clock output is <40 ohms (nominal) which is minimally affected by the 10k ohm strap to ground or VDD. As with the series termination resistor, the output strapping resistor should be placed as close to the l/O pin as possible in order to keep the interconnecting trace short. The trace from the resistor to ground or VDD should be kept less than two inches in length to prevent system noise coupling during input logic sampling. When the clock outputs are enabled following the 2ms input period, the specified output frequency is delivered on the pin, assuming that VDD has stabilized. If VDD has not yet reached full value, output frequency initially may be below target but will increase to target once VDD voltage has stabilized. In either case, a short output clock cycle may be produced from the CPU clock outputs when the outputs are enabled.
Advanced Information
VDD 10k (LOAD OPTION 1) OUTPUT BUFFER 10k (LOAD OPTION 0)
OUTPUT STRAPPING RESISTOR
RC7102
CLOCK LOAD
SERIES TERMINATION RESISTOR
Figure 1. Input Logic Selection through Resistor Load Option
JUMPER OPTIONS OUTPUT STRAPPING RESISTOR
RC7102
OUTPUT BUFFER
10k
RESISTOR VALUE R R
CLOCK LOAD
SERIES TERMINATION RESISTOR
Figure 2. Input Logic Selection through Jumper Option
9
RC7102
PRODUCT SPECIFICATION
Serial Data Interface
The RC7102 features a two-pin, serial data interface that can be used to configure internal register settings that control particular device functions. Upon power-up, the RC7102 initializes with default register settings, therefore the use of this serial data interface is optional. The serial interface is writeonly (to the clock chip) and is the dedicated function of
device pins SDATA and SCLOCK. In motherboard applications, SDATA and SCLOCK are typically driven by two logic outputs of the chipset. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. Table 3 summarizes the control functions of the serial data interface.
Table 3. Serial Data Interface Control Functions Summary Control Function Clock Output Disable Description Any individual clock output(s) can be disabled. Disabled outputs are actively held low. Provides CPU/PCI frequency selections through software. Frequency is changed in a smooth and controlled fashion. Enables or disables spread spectrum clocking. Puts clock output into a high impedance state. Reserved function for future device revision or production device testing. All clock outputs toggle in relation to X1 input, internal PLL is bypassed. Refer to Table 7. Common Applications Unused outputs are disabled to reduce EMI and system power. Examples are clock outputs to unused PCI slots. For alternate microprocessors and power management options. Smooth frequency transition allows CPU frequency change under normal system operation. For EMI reduction. Production PCB testing. No user application. Register bit must be written as 0. Production PCB Testing
Advanced Information
CPU Clock Frequency Selection
Spread Spectrum Enabling Output Tristate (Reserved) Test Mode
Signaling Requirements for the I2C Serial Port
To initiate communications with the serial port, a start bit is invoked. The start bit is defined as the SDATA line is brought low while the SCLOCK is held high. Once the start bit is initiated, valid data can then be sent. Data is considered to be valid when the clock goes to and remains in the high state. The data can change when the clock goes low. To terminate the transmission, a stop bit is invoked. The stop bit occurs when the SDATA line goes from a low to a high state while the SCLOCK is held high. See Figure below.
RC7104 I2C Interface Write Sequence Example
Signal from Motherboard Clock Chip START MSB Slave Address (First Byte) LSB Command Code (2nd Byte) Byte Count (3rd Byte) Last Data Byte
STOP
SDATA SCLK
1 1
1 2
0 3
1 4
0 5
0 6
1 7
0 8 A
MSB 1 2 3
LSB 8 A
MSB 1 2
LSB 8 A
MSB 1 2
LSB 8 A
SDATA (ACK Signal From Buffer Chip)
Note:
Once the clock detects the start condition and its ADDRESS is matched, the clock chip will pull down the SDATA at every 8th bit. The 8 bit data from SDATA is latched into the Buffer Chip when the ACK is generated. This ACK signal will continue as long as STOP condition is detected The COMMAND CODE and BYTE COUNT is not used by the Buffer Chip.
10
PRODUCT SPECIFICATION
RC7102
Operation
Data is written to the RC7102 in eleven bytes of eight bits each. Bytes are written in the order shown in Table 4. Table 4. Byte Writing Sequence Byte Sequence 1 Byte Name Slave Address Bit Sequence 11010010 Byte Description Commands the RC7102 to accept the bits in Data Bytes 0-6 for internal register configuration. Since other devices may exist on the same common serial data bus, it is necessary to have a specific slave address for each potential receiver. The slave receiver address for the RC7102 is 11010010. Register setting will not be made if the Slave Address is not correct (or is for an alternate slave receiver). Unused by the RC7102, therefore bit values are ignored (don't care). This byte must be included in the data write sequence to maintain proper byte allocation. The Command Code Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. Unused by the RC7102, therefore bit values are ignored (don't care). This byte must be included in the data write sequence to maintain proper byte allocation. The Byte Count Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. The data bits in Data Bytes 0-7 set internal RC7102 registers that control device operation. The data bits are only accepted when the Address Byte bit sequence is 11010010, as noted above. For description of bit control functions, refer to Table 5, Data Byte Serial Configuration Map.
2
Command Code
Don't Care
Advanced Information
3
Byte Count
Don't Care
4 5 6 7 8 9
Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 Data Byte 4 Data Byte 5
Refer to Table 6
11
RC7102
PRODUCT SPECIFICATION
Writing Data Bytes
Each bit in Data Bytes 0-5 control a particular device function except for the "reserved" bits which must be written as a logic 0. Bits are written MSB (most significant bit) first, which is bit 7. Table 5 gives the bit formats for registers located in Data Bytes 0-5. Table 5. Data Bytes 0-5 Serial Configuration Map Affected Pin Bit(s) Data Byte 0 7 -- -- -- -- -- -- 7, 8, 10, 11, 12, 13, 43, 44 All Clocks -- -- -- -- 40 41 43 44 -- 7 -- 13 12 11 10 8 CPU and PCI -- -- -- -- CPU and PCI CPU and PCI All Clocks -- -- -- -- SDRAM12 SDRAM13 CPU1 CPU0 -- PCI_F -- PCI5 PCI4 PCI3 PCI2 PCI1 Pin No. Pin Name
Table 6 details additional frequency selections that are available through the serial data interface. Table 7 details the select functions for Byte 0, bits 1 and 0.
Bit Control Control Function Spread Amount - Must equal 1 for Down Spread SEL_2 SEL_1 SEL_0 Hardware/Software Frequency Select Spread Type Spread Spectrum Clock Clock Output Tristate (Reserved) (Reserved) (Reserved) Test Mode Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable (Reserved) Clock Output Disable (Reserved) Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable 0 0.25 1 0.5 Default 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Advanced Information
6 5 4 3 2 1 0 Data Byte 1 7 6 5 4 3 2 1 0 Data Byte 2 7 6 5 4 3 2 1 0
See Table 6 See Table 6 See Table 6 Hardware Center Normal Active -- -- -- Low Low Low Low -- Low -- Low Low Low Low Low see Table 7 Active Active Active Active -- Active -- Active Active Active Active Active Software Down Spread Tristate -- -- --
12
PRODUCT SPECIFICATION
RC7102
Table 5. Data Bytes 0-5 Serial Configuration Map (continued) Affected Pin Bit(s) Data Byte 3 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Data Byte 5 7 6 5 4 3 2 1 0 -- -- -- 47 -- -- 46 2 -- -- -- IOAPIC -- -- REF1 REF0 (Reserved) (Reserved) (Reserved) Clock Output Disable (Reserved) (Reserved) Clock Output Disable Clock Output Disable -- -- -- Low -- -- Low Low -- -- -- Active -- -- Active Active 1 1 1 1 1 1 1 1 -- -- 26 25 -- -- -- 48Mhz 24MHz -- (Reserved) (Reserved) Clock Output Disable Clock Output Disable (Reserved) -- -- Low Low -- Low Low Low -- -- -- -- -- -- -- -- -- -- Active Active -- Active Active Active -- -- -- -- -- -- -- -- 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Pin No. Pin Name Control Function 0 Bit Control 1 Default
21, 20, 18, 17 SDRAM8:11 Clock Output Disable (SDRAM 10, 11 only when MODE=1) 32, 31, 29, 28 SDRAM4:7 38, 37, 35, 34 SDRAM0:3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Clock Output Disable Clock Output Disable (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved)
Advanced Information
Data Byte 4
13
RC7102
PRODUCT SPECIFICATION
Table 6. Additional Frequency Selections through Serial Data Interface Data Bytes Input Conditions Data Byte 0, Bit 3 = 1 Bit 6 SEL_2 1 1 1 1 0 0 Bit 5 SEL_1 1 1 0 0 1 1 0 0 Bit 4 SEL_0 1 0 1 0 1 0 1 0 CPU, SDRAM Clocks (MHz) 100. 2 133.3 112 103 66.8 83.3 75 124 PCI Clocks (MHz) 33.4 44.4 37.3 34.3 33.4 41.65 37.5 41.3 Output Frequency
Advanced Information
0 0 Table 7. Test Mode
Input Conditions Data Byte 1 Function Normal Operation Test Mode Bit 4 1 0 CPU0:1 Note 1 X1/2
Output Frequency PCI_F, PCI1:5 REF, IOAPIC Note 1 CPU/2 or 3 14.318 MHz X1 48MHz 48 MHz X1/2 24MHz 24 MHz X1/4
Note 1: CPU and PCI frequency selections are listed in Table 2 and Table 6.
14
PRODUCT SPECIFICATION
RC7102
Mechanical Dimensions
48 pin SSOP
Symbol A A1 b c D E E1 e L N a ccc Inches Min. .095 .008 Max. .110 .016 Millimeters Min. 2.41 0.20 Max. 2.79 0.41 5 5 2, 4 2 3 6 Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 2. "D" and "E1" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5. "b" & "c" dimensions include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
.008 .0135 .005 .010 .620 .630 .395 .420 .291 .299 .025 BSC .020 .040 48 8 0 --.004
0.20 0.34 0.13 0.25 15.75 16.00 10.03 10.67 7.39 7.59 0.64 BSC 0.51 1.02 48 8 0 --0.13
Advanced Information
E E1
1
D A e b A1 SEATING PLANE -CLEAD COPLANARITY ccc C c a L
15
RC7102
PRODUCT SPECIFICATION
Ordering lnformation
Product Number RC7102 Temperature Screening Package 48 SSOP Package Marking RC7102
Advanced Information
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com 1/20/99 0.0m 002 Stock#DS50007102 (c) 1998 Fairchild Semiconductor Corporation
www.fairchildsemi.com
RC7104
100MHz Spread Spectrum Motherboard Clock
Features
* Employs Fairchild's proprietary Spread Spectrum Technology * Reduces measured EMI by as much as 10dB I2C programmable * Two skew-controlled copies of CPU clock * SEL100/66# selects CPU frequency (100 or 66.8MHz) * Overclocking up to 133MHz * Seven copies of PCI clock (synchronous w/CPU clock) * One copy of 14.31818 MHz IOAPIC clock * One copy of 48MHz USB clock * 24 or 48MHz clock is determined by resistor straps on power up * One copy of 14.31818MHz REF clock
Description
The RC7104 is a clock synthesizer for Pentium II based motherboard systems. The CPU output frequency can be "over driven" through a command to the serial I2C interface.
Advanced Information
Block Diagram
VDDREF REF/SEL48# X1 X2 XTAL OSC PLL Ref Freq VDDCORE1 VDDCPU CPU0 CPU1 GNDCPU GNDREF VDDAPIC IOAPIC
100/66#_SEL
PLL 1 /2//3
VDDPCI PCI_F PCI1 PCI2 PCI3 PCI4
SDATA SCLOCK
I2C LOGIC
PCI5 PCI6 GNDPCI VDD48
PLL 2
48MHz 24/48MHz GND48MHz
Rev. 0.0.9
ADVANCED INFORMATION describes products that are not in full production at the time of printing. Specifications are based on design goals and limited characterization. They may change without notice. Contact Fairchild Semiconductor for current information.
RC7104
PRODUCT SPECIFICATION
Table 1. Pin Selectable Frequency
SEL100/66 1 0 CPU(0:1) 100MHz 66.8MHz PCI 33.3MHz 33.4MHz
Pin Assignments
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Pin # Pin Name 1 2 3 4 5 6 7 X1 X2 GNDPCI PCIF PCI1 PCI2 PCI3 Pin # Pin Name 8 9 10 11 12 13 14 PCI4 VDDPCI PCI5 PCI6 VDD48 48MHz 24/48MHz Pin # Pin Name 15 16 17 18 19 20 21 GND48 SEL100/66# SCLOCK SDATA GNDCPU VDDCORE1 CPU1 Pin # Pin Name 22 23 24 25 26 27 28 CPU0 VDDCPU IOAPIC VDDAPIC VDDREF REF/SEL48# GNDREF
Advanced Information
2
PRODUCT SPECIFICATION
RC7104
Pin Descriptions
Pin Name CPU0:1 PCI_F PCI1:6 IOAPIC 48MHz 24/48MHz REF/SEL48# Pin Number 22, 21 4, 5, 6, 7, 8, 10, 11 24 13 14 27 Type OUT OUT OUT OUT OUT IN/OUT Pin Function Description CPU Clock Outputs 0 through 1: These two CPU clocks run at a frequency set by SEL100/66# and the I2C bus. PCI Bus Clock Outputs 1 through 6 and PCI_F: These seven PCI clock outputs run synchronously to the CPU clock. I/O APIC Clock Output: Provides 14.318MHz fixed frequency. 48MHz Output: Fixed 48MHz USB clock. 24MHz or 48MHz Output: Frequency is set by the state of pin 27 on power up. I/O Dual Function REF and SEL48# pin: Upon power-up, the state of SEL48# is latched. The initial state is set by either a 10K resistor to GND or to VDD. A 10K resistor to GND causes pin 14 to output 48MHz. If the pin is strapped to VDD, pin 14 will output 24MHz. After 2ms, the pin becomes a high drive output that produces a copy of 14.318MHz. Frequency Selection Input: Selects CPU clock frequency as shown in Table 1. I2C Data Pin: Data should be presented to this input as described in the I2C section of this data sheet. Internal 250K ohm pull-up resistor. I2C clock Pin: The I2C Data clock should be presented to this input as described in the I2C section of this data sheet. Crystal Connection or External Reference Frequency Input: Connect to either a 14.318MHz crystal or other reference signal. Crystal Connection: An input connection for an external 14.318MHz crystal. If using an external reference, this pin must be left unconnected. Power Connection: Power supply for core logic and PLL circuitry. Connect to 3.3V supply. Power Connection: Power supply for PCI_F and PCI1:6. Connect to 3.3V supply. Power Connection: Power supply for IOAPIC output buffer. Connect to 2.5V supply. Power Connection: Power supply for CPU0:1 output buffers. Connect to 2.5V supply. Power Connection: Power supply for 48MHz USB clock. Connect to 3.3V supply. Power Connection: Power supply for 14.318MHz ISA clock. Connect to 3.3V supply. Ground Connections: Connect all ground pins to the common system ground plane.
Advanced Information
SEL100/66# SDATA
16 18
IN IN/OUT
SCLOCK X1 X2
17 1 2
IN IN IN
VDDCORE1 VDDPCI VDDAPIC VDDCPU VDD48 VDDREF GNDPCI, GND48, GNDCPU, GNDREF
20 9 25 23 12 26 3, 15, 19, 28
POWER POWER POWER POWER POWER POWER GROUND
3
RC7104
PRODUCT SPECIFICATION
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions
above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability.
Symbol VDD, VIN TSTG TB TA VESD
Parameter Voltage on any pin with respect to GND Storage Temperature Ambient Temperature under Bias Operating Temperature Input ESD Protection
Rating -0.5 to +7.0 -65 to +150 -55 to +125 0 to +70 2 (min)
Units V C C C kV
Advanced Information
4
PRODUCT SPECIFICATION
RC7104
DC Electrical Characteristics
TA = 0C to +70C; VDDREF = VDDPCI = VDD48MHz = 3.3V5%; VDDAPIC = VDDCPU = 2.5V5%
Parameter Supply Current IDD Logic inputs VIL VIH IIL IIH IIL IIH Input Low Voltage Input High Voltage Input Low Current2 Input High Current2 Input Low Current (SEL100/66#) Input High Current (SEL100/66#) Output Low Voltage Output High Voltage CPU0, IOAPIC PCI, REF, 24MHz IOL Output Low Current CPU, IOAPIC PCI REF, 48MHz, 24MHz IOH Output High Current CPU, IOAPIC PCI REF, 48MHz, 24MHz Crystal oscillator VTH CIN, X1 CIN COUT LIN X1 Input threshold Voltage3 X1 Input Capacitance5 Pin X2 unconnected Except X1 and X2 13.5 1.5 18 22.5 5 6 7 V pF pF pF nH VOH = 1.2V VOH = 1.4V VOL = 1.2V VOL = 1.4V IOL = 1mA IOH = 1mA 2 2.4 27 26.5 25 -101 -189 -94 93 139 76 -26 -31 -27 mA mA GND -.3 2.0 0.8 VDD+.3 -25 10 -5 +5 V V A A A Combined 3.3V Supply Current CPUCLK = 100MHz Outputs Loaded1 mA Test Condition Min. Typ. Max. Units
Advanced Information
A
Clock Outputs VOL VOH 0.4 mV V
Pin Capacitance/Inductance Input Pin Capacitance Output Pin Capacitance Input Pin Inductance
Notes: 1. All clock outputs loaded with maximum lump capacitance test load specified in AC Electrical Characteristics section. 2. RC7104 logic inputs have internal pull-up resistors, except SEL100/66#. 3. X1 input threshold voltage (typical) is VDD/2. 4. The RC7104 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 14pF; this includes typical stray capacitance of short PCB traces to crystal. 5. X1 input capacitance is applicable when driven X1 with an external clock source (X2 is left unconnected).
5
RC7104
PRODUCT SPECIFICATION
AC Electrical Characteristics
TA = 0C to +70C; VDDREF = VDDPCI = VDD48MHz = 3.3V5%; VDDAPIC = VDDCPU = 2.5V5%; f XTL = 14.31818MHz
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output; Spread Spectrum clocking is disabled
CPU Clock Outputs, CPU0:1 (Lump Capacitance Test Load = 20pF)
CPU = 66.6MHz Parameter tP tH tL tR tF tD tJC Period High Time Low Time Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle 15 5.2 5.0 .4 .4 45 1.6 1.6 55 200 15.5 CPU = 100MHz 10 3.0 2.8 .4 .4 45 1.6 1.6 55 200 10.5 ns ns ns ns ns % ps Measured on rising edge at 1.25. Duration of clock cycle above 2.0V. Duration of clock cycle below 0.4V. Measured from 0.4V to 2.0V. Measured from 2.0V to 0.4V. Measured on rising and falling edge at 1.25V. Measured on rising edge at 1.25V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.25V. Assumes full supply voltage reached within 1ms from powerup. Average value during switching transition. Used for determining series termination value. Min. Typ. Max. Min. Typ. Max. Units Test Condition/Comments
Advanced Information
tSK fST
Output Skew Frequency Stabilization from Power-up (cold start) AC Output Impedance 20
175 3
175 3
ps ms
Z0
20
PCI Clock Outputs, PCI1:6 and PCI_F (Lump Capacitance Test Load = 30pF)
CPU = 66.6/100MHz Parameter tP tH tL tR tF tD tJC Period High Time Low Time Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Min. 30 12.0 12.0 1 1 45 4 4 55 250 Typ. Max. Units ns ns ns V/ns V/ns % ps Test Condition/Comments Measured on rising edge at 1.5V. Duration of clock cycle above 2.4V. Duration of clock cycle below 0.4V. Measured from 0.4V to 2.4V. Measured from 2.4V to 0.4V. Measured on rising and falling edge at 1.5V. Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.5V. Covers all CPU/PCI outputs. Measured on rising edge at 1.5V. CPU leads PCI output.
tSK tO
Output Skew CPU to PCI Clock Offset 1.5
500 4.0
ps ns
6
PRODUCT SPECIFICATION
RC7104
PCI Clock Outputs, PCI1:6 and PCI_F (Lump Capacitance Test Load = 30pF) (continued)
CPU = 66.6/100MHz Parameter fST Frequency Stabilization from Power-up (cold start) AC Output Impedance 30 Min. Typ. Max. 3 Units ms Test Condition/Comments Assumes full supply voltage reached within 1ms from powerup. Average value during switching transition. Used for determining series termination value.
Z0
IOAPIC Clock Output (Lump Capacitance Test Load = 20pF)
CPU = 66.6/100MHz Parameter f tR tF tD tA Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Jitter, Absolute 1 1 45 Min. Typ. 14.3818 4 4 55 500 Max. Units MHz V/ns V/ns % ps Test Condition/Comments Frequency generated by crystal oscillator. Measured from 0.4V to 2.0V. Measured from 2.0V to 0.4V. Measured on rising and falling edge at 1.25V. Measured on rising edge at 1.25V. Maximum deviation of clock period. Assumes full supply voltage reached within 1ms from power-up. Average value during switching transition. Used for determining series termination value.
Advanced Information
fST
Frequency Stabilization from Power-up (cold start) AC Output Impedance 20
1.5
ms
Z0
REF Clock Output (Lump Capacitance Test Load = 20pF)
CPU = 66.6/100MHz Parameter f tR tF tD tJC Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle 0.5 0.5 45% Min. Typ. 14.3818 2 2 55 500 Max. Units MHz V/ns V/ns % ps Test Condition/Comments Determined by PLL divider ratio (see n/m below). Measured from 0.4V to 2.4V. Measured from 2.4V to 0.4V. Measured on rising and falling edge at 1.5V. Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. Assumes full supply voltage reached within 1ms from powerup. Average value during switching transition. Used for determining series termination value.
fST
Frequency Stabilization from Power-up (cold start) AC Output Impedance 20
3
ms
Z0
7
RC7104
PRODUCT SPECIFICATION
48MHz and 24MHz Clock Output (Lump Capacitance Test Load = 20pF=66.6/100MHz)
CPU = 66.6MHz Parameter f fD n/m tR tF tD Frequency, Actual Deviation from 48MHz PLL Ratio Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle 0.5 0.5 45% Min. Typ. 48.008 24.004 +167 57/17 2 2 55 500 V/ns V/ns % ps Max. Units MHz ppm Test Condition/Comments Determined by PLL divider ratio (see n/m below). (48.008 - 48)/48 (14.31818MHz x 57/17 = 48.008MHz) Measured from 0.4V to 2.4V. Measured from 2.4V to 0.4V. Measured on rising and falling edge at 1.5V. Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. Assumes full supply voltage reached within 1ms from power-up. Average value during switching transition. Used for determining series termination value.
Advanced Information
tJC
fST
Frequency Stabilization from Power-up (cold start) AC Output Impedance 20
3
ms
Z0
ohm
8
PRODUCT SPECIFICATION
RC7104
Functional Description
I/O Pin Operation
Pin 27 is a dual purpose l/O pin. The RC7104 upon power up, the first 2ms of operation is used for input logic selection, (allowing the determination of assigned device functions). During this period, the 48MHz clock output buffer is tristated, allowing the output strapping resistor on the l/O pin to pull the pin and its associated capacitive clock load to either a logic high or low state. At the end of the 2ms period, the established logic "0" or "1" condition of the l/O pin is then latched. Next the output buffer is enabled which converts the l/O pin into an operating clock output. The 2ms timer is started when VDD reaches 2.0V. The input bits can only be re-set by turning VDD off and then back on again. (This feature reduces device pin count by combining clock outputs with input select pins.)
It should be noted that the strapping resistors have no significant effect on clock output signal integrity. The drive impedance of clock output is 20 ohms (nominal) which is minimally affected by the 10 kohm strap to ground or VDD. As with the series termination resistor, the output strapping resistor should be placed as close to the l/O pin as possible in order to keep the interconnecting trace short. The trace from the resistor to ground or VDD should be kept less than two inches in length to prevent system noise coupling during input logic sampling. An external 10 kohm "strapping" resistor is connected between the l/O pin and ground or VDD. Connection to ground sets a "0" bit, connection to VDD sets a "1" bit. Figure 1 and Figure 2 show two suggested methods for strapping resistor connections.
Advanced Information
VDD 10k (LOAD OPTION 1) OUTPUT BUFFER 10k (LOAD OPTION 0)
OUTPUT STRAPPING RESISTOR
RC7104
CLOCK LOAD
SERIES TERMINATION RESISTOR
Figure 1. Input Logic Selection through Resistor Load Option
JUMPER OPTIONS OUTPUT STRAPPING RESISTOR
RC7104
OUTPUT BUFFER
10k
RESISTOR VALUE R R
CLOCK LOAD
SERIES TERMINATION RESISTOR
Figure 2. Input Logic Selection through Jumper Option
Serial Data Interface
The RC7104 features a two-pin, serial data interface that can be used to configure internal register settings that control particular device functions. Upon power-up, the RC7104 initializes with default register settings. Therefore, the use of this serial data interface is optional. The serial interface is write-only (to the clock chip) and is the dedicated function of device pins SDATA and SCLOCK. In motherboard applications, SDATA and SCLOCK are typically driven by two logic outputs of the chipset.
9
RC7104
PRODUCT SPECIFICATION
Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management func-
tions. Table 2 summarizes the control functions of the serial data interface.
Table 2. Serial Data Interface Control Functions Summary Control Function Clock Output Disable Description Any individual clock output(s) can be disabled. Disabled outputs are actively held low. Provides CPU/PCI frequency selections beyond the 100 and 66.66MHz selections that are provided by the SEL100/66# pin. Frequency is changed in a smooth and controlled fashion. Puts all clock outputs into a high impedance state. All clock outputs toggle in relation to X1 input, internal PLL is bypassed. Refer to Table 4. Reserved function for future device revision or production device testing. Common Application Unused outputs are disabled to reduce EMI and system power. Examples are clock outputs to unused PCI slots. For alternate microprocessors and power management options. Smooth frequency transition allows CPU frequency change under normal system operation. Production PCB testing. Production PCB testing.
CPU Clock Frequency Selection
Advanced Information
Output Tristate Test Mode
(Reserved)
No user application. Register bit must be written as 0.
Signaling Requirements for the I2C Serial Port
To initiate communications with the serial port, a start bit is invoked. The start bit is defined as the SDATA line is brought low while the SCLOCK is held high. Once the start bit is initiated, valid data can then be sent. Data is considered to be valid when the clock goes to and remains in the high state. The data can change when the clock goes low. To terminate the transmission, a stop bit is invoked. The stop bit occurs when the SDATA line goes from a low to a high state while the SCLOCK is held high. See Figure below.
RC7104 I2C Interface Write Sequence Example
Signal from Motherboard Clock Chip START MSB RC7101 Slave Address (First Byte) LSB Command Code (2nd Byte) Byte Count (3rd Byte) Last Data Byte
STOP
SDATA SCLK
1 1
1 2
0 3
1 4
0 5
0 6
1 7
0 8 A
MSB 1 2 3
LSB 8 A
MSB 1 2
LSB 8 A
MSB 1 2
LSB 8 A
SDATA (ACK Signal From Buffer Chip)
Note:
Once the clock detects the start condition and its ADDRESS is matched, the clock chip will pull down the SDATA at every 8th bit. The 8 bit data from SDATA is latched into the Buffer Chip when the ACK is generated. This ACK signal will continue as long as STOP condition is detected The COMMAND CODE and BYTE COUNT is not used by the Buffer Chip.
The data transfer rate is 100kbits/s in the standard mode and 400kbits/s in the fast mode. The serial protocol uses block writes only. Bytes are written with the lowest first and the highest last with the ability to stop after any complete byte
has been transferred. The clock driver is a slave/receiver only and is only capable of receiving data with the exception of sending acknowledgements. It is not capable of sending data.
10
PRODUCT SPECIFICATION
RC7104
Operation
The RC7104 is programmed by writing 10 bytes of eight bits each. See Table 3 for byte order. Table 3. Byte Writing Sequence Byte Sequence 1 Byte Name Bit Sequence Byte Description Commands the RC7104 to accept the bits in Data Bytes 3-6 for internal register configuration. Since other devices may exist on the same common serial data bus, it is necessary to have a specific slave address for each potential receiver. The slave receiver address for the RC7104 is 11010010. Register setting will not be made if the Slave Address is not correct (or is for an alternate slave receiver). Unused by the RC7104, therefore bit values are ignored (don' t care). This byte must be included in the data write sequence to maintain proper byte allocation. The Command Code Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. Unused by the RC7104, therefore bit values are ignored (don' t care). This byte must be included in the data write sequence to maintain proper byte allocation. The Byte Count Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. Refer to Fairchild SDRAM Buffers. These bytes are not used by the RC7104.
Slave Address 11010010
2
Command Code
Don' t Care
Advanced Information
3
Byte Count
Don't Care
4 5 6 7 8 9 10
Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 Data Byte 4 Data Byte 5 Data Byte 6
Don' t Care
Refer to Table 5
The data bits in these bytes set internal RC7104 registers that control device operation. The data bits are only accepted when the Address Byte bit sequence is 11010010, as noted above. For description of bit control functions, refer to Table 4, Data Byte Serial Configuration Map.
11
RC7104
PRODUCT SPECIFICATION
Writing Data Bytes
Each bit of the 10 data bytes controls a particular device function except for the "reserved" bits. These must by preserved by writing a logic 0. Bit 7, the MSB, is written first. See Table 4 for bit descriptions of Data Bytes 3-6. Table 4. Data Bytes 3-6 Serial Configuration Map Affected Pin Bit(s) Data Byte 3 7 6 5 4 3 -- -- -- -- -- -- -- -- -- (Reserved) SEL_2 SEL_1 SEL_0 BYT0 _FS# Pin No. Pin Name Control Function
Table 5 shows additional frequency selections that are programmable via the serial data interface. Table 7 shows the mode select functions for Byte 3, bits 1 and 0.
Bit Control 0 -- Refer to Table 5 Refer to Table 5 Refer to Table 5 Frequency Controlled by external SEL100/ 66# pin Bit 0 0 1 0 Frequency Controlled by BYT0 SEL (2:0) -- 1 Default 0 0 0 0 0
Advanced Information
2 1-0
-- -- --
(Reserved) Bit 1 0 0 1 Function (See Table 7 for function details) Normal Operation Test Mode Spread Spectrum on (See Table 6 for frequency & spread selections, when Spread Spectrum is on. See Table 5 for frequency selections when Spread Spectrum is off). All Outputs Tristated -- Low -- -- -- Low -- Low Low Low Low -- Low Low Low Low -- Active -- -- -- Active -- Active Active Active Active -- Active Active Active Active
0 00
1 Data Byte 4 7 6 5 4 3 2 1 0 Data Byte 5 7 6 5 4 3 2 1 0
12
1
-- 14 -- -- -- 21 -- 22 4 11 10 -- 8 7 6 5
-- 24/48MHz -- -- -- CPU1 -- CPU0 PCICLK_F PCI6 PCI5 -- PCI4 PCI3 PCI2 PCI1
(Reserved) Clock Output disable (Reserved) (Reserved) (Reserved) Clock Output disable (Reserved) Clock Output disable Clock Output disable Clock Output disable Clock Output disable (Reserved) Clock Output disable Clock Output disable Clock Output disable Clock Output disable
0 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1
PRODUCT SPECIFICATION
RC7104
Table 4. Data Bytes 3-6 Serial Configuration Map (continued) Affected Pin Bit(s) Data Byte 6 7 6 5 4 3 2 1 0 -- -- 24 -- -- -- 27 -- -- -- IOAPIC -- -- -- REF -- (Reserved) (Reserved) Clock Output disable (Reserved) (Reserved) (Reserved) Clock Output disable (Reserved) -- -- Low -- -- -- Low -- -- -- Active -- -- -- Active -- 0 0 1 0 0 0 1 0 Pin No. Pin Name Control Function 0 Bit Control 1 Default
Advanced Information
Table 5. Additional Frequency Selections through Serial Data Interface Data Bytes when Spread Spectrum is turned off Input Conditions Data Byte 3, Bit 3 = 1 Bit 6 SEL_2 0 0 0 0 1 1 1 1 Bit 5 SEL_1 0 0 1 1 0 0 1 1 Bit 4 SEL_0 0 1 0 1 0 1 0 1 CPU, SDRAM Clocks (MHz) 124.3 75.2 83.5 66.8 103.2 112.3 133.6 100.2 PCI Clocks (MHz) 62.2 37.6 41.8 33.4 34.4 37.4 44.5 33.4 Output Frequency
Table 6. Additional Frequency Selections through Serial Data Interface Data Bytes when Spread Spectrum is turned on Input Conditions Data Byte 3, Bit 3 = 1 Bit 6 SEL_2 0 0 0 0 1 1 1 1 Bit 5 SEL_1 0 0 1 1 0 0 1 1 Bit 4 SEL_0 0 1 0 1 0 1 0 1 CPU, SDRAM Clocks (MHz) 124 75 83.3 66.8 103 112 133.3 100 PCI Clocks (MHz) 41.3 37.5 41.6 33.4 34.25 33.3 44.43 33.3 Spread Percentage 0.25% Center 0.25% Center 0.25% Center 0.25% Center 0.25% Center 0.25% Center 0.25% Center 0.25% Center Output Frequency
13
RC7104
PRODUCT SPECIFICATION
Table 7. Select Function for Data Byte 3, Bits 0:1 Input Conditions Data Byte 3 Function Normal Operation Test Mode Spread Spectrum Tristate Bit 1 0 0 1 1 Bit 0 0 1 0 1 CPU0:1
1
Output Frequency PCI_F, PCI1:6
1
REF, IOAPIC 14.318MHz X1 14.318MHz Hi-Z
48MHz 48MHz X1/2 48MHz Hi-Z
24MHz 24MHz X1/4 24MHz Hi-Z
X1/2 0.5% Hi-Z
CPU/2 or 3 0.5% Hi-Z
Notes: 1. CPU and PCI frequency selections are listed in Table 1 and Table 5.
Advanced Information
14
PRODUCT SPECIFICATION
RC7104
Mechanical Dimensions
28 pin SOIC
Symbol A A1 B C D E e H h L N ccc Inches Min. .093 .004 .013 .009 .697 Max. .104 .012 .020 .013 .713 Millimeters Min. 2.35 0.10 0.33 0.23 17.70 Max. 2.65 0.30 0.51 0.32 18.10 Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5. Symbol "N" is the maximum number of terminals. 2 2
.291 .299 .050 BSC .394 .419 .010 .016 28 0 -- 7 .004 .030 .050
7.40 7.60 1.27 BSC 10.00 10.65 0.25 0.40 28 0 -- 7 0.10 0.75 1.27
Advanced Information
5
28
15
E
H
1
14
D A e B A1 SEATING PLANE -C- LEAD COPLANARITY ccc C L
h x 45 C
15
RC7104
PRODUCT SPECIFICATION
Ordering lnformation
Product Number RC7104 Temperature Screening Package 28 SOIC Package Marking RC7104
Advanced Information
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com 1/20/99 0.0m 002 Stock#DS50007104 (c) 1998 Fairchild Semiconductor Corporation
www.fairchildsemi.com
RC7105
Clock Buffer/Driver
Features
* Thirteen skew controlled CMOS clock outputs (SDRAM0:12) * Drives three SDRAM DIMMs I2C interface * Clock Skew between any two outputs is less than 250 ps * 1 to 5ns propagation delay * DC to 133MHz operation * Single 3.3V supply voltage * Low power CMOS design in a 28-pin, SOIC package
Description
The Fairchild RC7105 is a low-voltage, thirteen-output clock buffer. The skew between any two outputs is less than 250 ps and the buffers can be individually enabled or disabled by programming via the I2C serial interface. Output buffer impedance is approximately 15 which is ideal for driving SDRAM DIMMs.
Advanced Information
Block Diagram
SDA SCL I2C DEVICE CONTROL SDRAM0 SDRAM1 SDRAM2 SDRAM3 SDRAM4 SDRAM5 SDRAM6 SDRAM7 SDRAM8 BUF_IN SDRAM9 SDRAM10 SDRAM11 SDRAM12
I2C is a trademark of Philips Corporation.
Rev. 0.5.1
ADVANCED INFORMATION describes products that are not in full production at the time of printing. Specifications are based on design goals and limited characterization. They may change without notice. Contact Fairchild Semiconductor for current information.
RC7105
PRODUCT SPECIFICATION
Pin Assignments
VDD SDRAM0 SDRAM1 GND VDD SDRAM2 SDRAM3 GND BUF_IN SDRAM4 SDRAM5 SDRAM12 VDD SDA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD SDRAM11 SDRAM10 GND VDD SDRAM9 SDRAM8 GND VDD SDRAM7 SDRAM6 GND GND SCL
Advanced Information
Pin Descriptions
Pin Name SDRAM0:12 Pin Number 2, 3, 6, 7, 10, 11, 18, 19, 22, 23, 26, 27, 12 9 14 15 1, 5, 13, 20, 24, 28 Type OUT Pin Function Description SDRAM Outputs: Provides buffered copy of BUF_IN. The propagation delay from a rising input edge to a rising output edge is 1 to 5ns. All outputs are skew controlled to within 250ps of each other. Clock Input: This clock input has an input threshold voltage of 1.5V (typ). I2C Data input: Data should be presented to this input as described in the I2C section of this data sheet. I2C clock input: The I2C clock should be presented to this input as described in the I2C section of this data sheet. Power Connection: Power supply for core logic and output buffers. Connected to 3.3V supply. Ground Connection: Connect all ground pins to the common system ground plane.
BUF_IN SDA SCL VDD GND
IN IN/OUT IN POWER
4, 8, 16, 17, 21, GROUND 25
2
PRODUCT SPECIFICATION
RC7105
Absolute Maximum Ratings1
(beyond which the device will be damaged) Symbol VDD, VIN TSTG TB TA Parameter Voltage on any pin with respect to GND Storage Temperature Ambient Temperature under Bias Operating Temperature Min. -0.5 to +7.0 -65 to +150 -55 to +125 0 to +70 Units V C C C
Notes: 1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded.
DC Electrical Characteristics
TA = 0C to +70C; VDD = 3.3V5%
Parameter Supply Current IDD Logic Input VIL VIH IILEAK IILEAK VOL VOH IOL IOH CIN COUT LIN Input Low Voltage Input High Voltage Input Leakage Current, BUF_IN Input Leakage Current (Note) Output Low Voltage Output High Voltage Output Low Current Output High Current Input Pin Capacitance Output Pin Capacitance Input Pin Inductance IOL = 1mA IOH = 1mA VOL = 1.4V VOH = 1.4V 2.4 55 -188 159 -50 5 6 7 GND -0.3 2.0 -5 -20 0.8 VDD+.5 +5 +5 0.4 V V A A V V mA mA pF pF nH 3.3V Supply Current BUF_IN = 100MHZ 250 mA Test Condition Min. Typ. Max. Units
Advanced Information
Logic Outputs (SDRAM0:12)
Pin Capacitance/Inductance
Note: SDA and SCL logic pins have an internal pull-up resistor.
3
RC7105
PRODUCT SPECIFICATION
AC Electrical Characteristics
TA = 0C to +70C; VDD = 3.3V5%; (Lump Capacitance Test Load = 30pF)
Parameter fIN tR tF tSR tSF tEN tDIS tPR fPF tD Z0 Input Frequency Output Rise Time Output Fall Time Output Skew, Rising Edges Output Skew, Falling Edges Output Enable Time Output Disable Time Rising Edge Propagation Delay Falling Edge Propagation Delay Duty Cycle AC Output Impedance 1.0 1.0 1.0 1.0 45 15 Min. 0 0.5 0.5 Typ. Max. 133 1.33 1.33 250 250 8.0 8.0 5.0 5.0 55 Units MHz ns ns ps ps ns ns ns ns % Measured at 1.5V Average value during switching transition. Used for determining series termination value. Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Test Condition/Comments
Advanced Information
4
PRODUCT SPECIFICATION
RC7105
How To Use the Serial Data Interface
Electrical Requirements
Figure 1 shows the architecture for the I2C serial interface bus used with the RC7105. Devices on the bus signal with an open drain logic output that actively pulls the bus line low, or lets the bus default to VDD (logic 1). The pull-up resistor on each bus line, SCL and SDA, establishes a default logic 1. Although the RC7105 is a slave device which cannot write data on the bus, it does transmit an "acknowledge" data pulse after each byte is received. Thus, the SDA line is an I/O pin. The pull-up resistor value should be designed to meet the rise and fall times specified in AC parameters, based on total bus line capacitance.
Signaling Requirements
As demonstrated in Figure 2, the I2C protocol defines valid data bits as stable logic 0 or 1 condition on the SDA line during an SCL high (logic 1) pulse. A transitioning SDA line during an SCL high pulse may be read as a start or stop pulse. Figure 3 shows how a "start bit" commands the beginning of a write sequence. The "stop bit" shown signifies that the sequence has ended. The RC7105 sends an "acknowledge" pulse after receiving eight data bits by asserting a low pulse on SDA, as shown in Figure 4.
Advanced Information
SDA
SCL
VALID DATA BIT
CHANGE OF DATA ALLOWED
Figure 2. Serial Data Bus Valid Data Bit
SDA
SCL START BIT STOP BIT
Figure 3. Serial Data Bus Start and Stop Bit
5
RC7105
PRODUCT SPECIFICATION
SIGNALING FROM SYSTEM CORE LOGIC START CONDITION SLAVE ADDRESS (FIRST BYTE)
SDA MSB 1 1 0 1 0 0 1 LSB 0 MSB
STOP CONDITION COMMAND CODE (SECOND BYTE)
LSB
BYTE COUNT (THIRD BYTE)
MSB MSB
LAST DATA BYTE (LAST BYTE)
LSB
SCL
1
2
3
4
5
6
7
8
A
1
2
3
4
5
6
7
8
A
1
2
3
4
1
2
3
4
5
6
7
8
A
SDA
SIGNALING BY CLOCK DEVICE
ACKNOWLEDGMENT BIT FROM CLOCK DEVICE
Figure 4. Serial Data Bus Write Sequence
Advanced Information
6
PRODUCT SPECIFICATION
RC7105
Functional Description
Output Drivers
The RC7105 uses CMOS type output buffers which drive the output rail-to-rail (GND to VDD) into typical capacitive loads. Because of this the outputs are both TTL and CMOS level compatible. Nominal output buffer impedance is 15. Table 1. Byte Writing Sequence Byte Sequence 1 Byte Name Bit Sequence Byte Description Commands the RC7105 to accept the bits in Data Bytes 0-6 for internal register configuration. Since other devices may exist on the same common serial data bus, it is necessary to have a specific slave address for each potential receiver. The slave receiver address for the RC7105 is 11010010. Register setting will not be made if the Slave Address is not correct (or is for an alternate slave receiver). Unused by the RC7105, therefore bit values are ignored (don't care). This byte must be included in the data write sequence to maintain proper byte allocation. The Command Code Byte is part of the standard serial communication protocol and may be used when writing ot another addressed slave receiver on the serial data bus. Unused by the RC7105, therefore bit values are ignored (don' t care). This byte must be included in the data write sequence to maintain proper byte allocation. The Byte Count Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. The data bits in these bytes set internal RC7105 registers that control device operation. The data bits are only accepted when the Address Byte bit sequence is 11010010, as noted above. For description of bit control functions, refer to Table 2, Data Byte Serial Configuration Map. Refer to Fairchild clock drivers.
Operation
The RC7105 is programmed by writing ten bytes of eight bits each. See Table 1 for byte sequence.
Slave Address 11010010
Advanced Information
2
Command Code
Don't Care
3
Byte Count
Don't Care
4 5 6 7 8 9 10
Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 Data Byte 4 Data Byte 5 Data Byte 6
Refer to Table 2
Don't Care
7
RC7105
PRODUCT SPECIFICATION
Writing Data Bytes
Each bit of the 10 data bytes controls a particular device function within the RC7105. Bit 7, the MSB, is written first. See Table 2 for bit descriptions of Data Bytes 0-2. Table 2. Data Bytes 0-2 Serial Configuration Map Affected Pin Bit(s) 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Pin No. 11 10 N/A N/A 7 6 3 2 27 26 23 22 N/A N/A 19 18 N/A 12 N/A N/A N/A N/A N/A N/A Pin Name SDRAM5 SDRAM4 Reserved Reserved SDRAM3 SDRAM2 SDRAM1 SDRAM0 SDRAM11 SDRAM10 SDRAM9 SDRAM8 Reserved Reserved SDRAM7 SDRAM6 Reserved SDRAM12 Reserved Reserved Reserved Reserved Reserved Reserved Control Function Clock Output Disable Clock Output Disable (Reserved) (Reserved) Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable (Reserved) (Reserved) Clock Output Disable Clock Output Disable (Reserved) Clock Output Disable (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) Low Low -- -- Low Low Low Low Low Low Low Low -- -- Low Low -- Low -- -- -- -- -- -- 0 Active Active -- -- Active Active Active Active Active Active Active Active -- -- Active Active -- Active -- -- -- -- -- -- Data Byte 0 SDRAM Active/Inactive Register (1=Enable, 0=Disable) Bit Control 1
Advanced Information
8
Data Byte 1 SDRAM Active/Inactive Register (1=Enable, 0=Disable)
Data Byte 2 SDRAM Active/Inactive Register (1=Enable, 0=Disable)
Note: At power up all SDRAM outputs are enabled and active. Program all reserved bits to a"0".
PRODUCT SPECIFICATION
RC7105
Mechanical Dimensions
28 pin SOIC
Symbol A A1 B C D E e H h L N ccc Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5. Symbol "N" is the maximum number of terminals. 2 2
.093 .104 .004 .012 .013 .020 .009 .013 .697 .713 .291 .299 .050 BSC .394 .419 .010 .016 28 0 -- 7 .004 .030 .050
2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 17.70 18.10 7.40 7.60 1.27 BSC 10.00 10.65 0.25 0.40 28 0 -- 7 0.10 0.75 1.27
Advanced Information
5
28
15
E
H
1
14
D A e B A1 SEATING PLANE -C- LEAD COPLANARITY ccc C L
h x 45 C
9
RC7105
PRODUCT SPECIFICATION
Ordering lnformation
Product Number RC7105 Temperature 0C to +70C Screening Package 28 SOIC Package Marking RC7105
Advanced Information
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com 3/3/99 0.0m 004 Stock#DS50007105 (c) 1999 Fairchild Semiconductor Corporation
www.fairchildsemi.com
RC7106
133MHz Spread Spectrum Clock for Motherboards
Features
* Employs Fairchild's proprietary Spread Spectrum Technology * Reduces measured EMI by as much as 10dB * Supports up to 150MHz I2C programmable * Three skew-controlled copies of the CPU clock * One copy CPU/2 @ 3.3V * Three copies of 3V66 clock * One copy 24MHz or 48MHz clock * One copy 48MHz clock * Three copies IOAPIC * Two copies REF 14.318MHz clock (3.3V) * Eleven copies PCI clock * Power down capability
Description
The RC7106 is a clock synthesizer for motherboard applications. It meets the requirements for 133MHz Camino chipset. The clock frequencies can be set with the 4 select pins or be set via the I2C interface.
Block Diagram
X1 X2 OSC
REF0 SEL24_48#/REF1 IOAPIC0:2 PLL Spread Spectrum CPU/2 CPU0:3 3V66_0:2 PLL USB C O N T R O L PCI4:10 FS0/PCI_F FS1:3/PCI1:3 48MHz/SEL_3V66 24_48MHz/FREQ_APIC
SDATA SCLK
I2C
PWRDWN#
RC7106
PRODUCT SPECIFICATION
Pin Assignments
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
48 SSOP
Pin Assignments
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VSS REF0 SEL24_48#/REF1 VDD X1 X2 VSS FS0/PCI_F FS1/PCI1 VDD FS2/PCI2 FS3/PCI3 VSS PCI4 PCI5 VDD Pin Name Pin # 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PCI6 PCI7 VSS PCI8 PCI9 PCI10 VDD PWRDWN# VSS 24_48MHz/FREQ_APIC 48MHz/SEL_3V66 VDD SCLK SDATA VSS 3V66-2 Pin name Pin # 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Pin Name 3V66-1 3V66-0 VDD VSSL CPU2 CPU1 VDDL CPU0 VSSL CPU/2 VDDL IOAPIC2 VSSL IOAPIC1 IOAPIC0 VDDL
2
PRODUCT SPECIFICATION
RC7106
PWRDWN#
REF, 24MHz, 48MHz LOW ON
PWRDWN# 0 1
CPU LOW ON
SDRAM LOW ON
IOAPIC LOW ON
3V66 LOW ON
PCI LOW ON
OSC. OFF ON
PLL OFF ON
Frequency Selection
3V66 (MHz) FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU CPU/2 MHz MHz 105 75 66.8 110 115 117 120 125 127 133.3 135 137 140 145 150 52.5 37.5 33.4 55 57.5 58.5 60 62.5 63.5 66.5 67.5 68.5 70 72.5 75 PCI MHz 35 37.5 33.4 33.4 36.6 38.3 39 40 41.6 42.3 33.3 33.75 34.25 35 36.25 37.5 3V66_SYNC 3V66_SYNC =0 =1 70 64* 66.6 66.6 64* 64* 64* 64* 64* 64* 66.6 67.5 68.5 70 64* 64* 70 75 66.6 66.6 73.3 76.6 78 80 83.3 84.6 66.6 67.5 68.5 70 72.5 75 IOAPIC (MHz) FREQ_APIC =0 17.5 18.75 16.7 16.67 18.3 19.16 19.5 20 20.8 21.16 16.6 16.8 17.125 17.5 18.125 18.75 FREQ_APIC =1 35 37.5 33.4 33.4 36.6 38.3 39 40 41.6 42.3 33.3 33.75 34.25 35 36.25 37.5
100.3 50.15
*Note: These output frequencies are not synchronous to the CPU Clock and do not have Spread Spectrum modulation.
3
RC7106
PRODUCT SPECIFICATION
Pin Descriptions
Pin Name CPU0:2 CPU/2 PCI4:10 FS0/PCI_F Pin Number 40,38,37 42 14,15,17,18, 20,21,22 8 Type OUT OUT OUT IN/OUT Pin Function Description CPU Clock Outputs: The frequency of these three CPU clocks are determined by the 4 select pins FS0:3 or via the I2C interface. CPU/2 Clock Output: The frequency of this clock is determined by the 4 select pins FS0:3 or via the I2C interface. PCI BUS Clock Outputs: These seven PCI clock outputs run synchronously to the CPU. I/O Dual Function FS0 and PCI_F pin: See table for frequency selection. After power-on, this pin becomes a free-running PCI clock. I/O Dual Function FS1:3 and PCI1:3 pin: See table for frequency selection. After power-on, these pins become normal PCI clock. 3V66 Clock Outputs: See table for frequency selection REF Clock Output: This output provides a 14.318MHz high drive clock . I/O Dual Function SEL24_48# and REF1 Pin: During power-up, if the input is "0", 48MHz would be selected on pin 26. If the input is latched "1", 24MHz would be selected. After power-on, this pin becomes a REF1 output. There is an internal pull-up resistor on this pin. IOAPIC Clock Outputs: See table for frequency selection. I/O Dual Function 24_48MHz and Freq_APIC pin: See table for frequency selection. After power-on the pin becomes a normal 24MHz or 48MHz clock depending on pin 3 during power-up. I/O Dual Function 48MHz and FS3 pin: See table for frequency selection. After power-on the pin becomes a normal 48MHz clock. Crystal Connection: An input connection for an external14.318MHz crystal. Connect to either a 14.318MHz crystal or other reference signal. Crystal Connection: If using an external reference, this pin must be left unconnected. Power-down Input pin: This pin shuts down the clock PLL bring all clocks to a low state. I2C Clock Pin: The I2C clock should be applied to this input as described in the I2C section of this datasheet. I2C Data Pin: Data should be presented to this input as described by the I2C section of this datasheet. There is an internal pull-up resistor on this pin. 3.3V Power Pins: 2.5V Power Pins: Ground Pins:
FS1:3/ PCI1:3 3V66-0:2 REF0 SEL24_48#/ REF1
9,11,12 34,33,32 1 3
IN/OUT OUT OUT IN/OUT
IOAPIC0:2 24_48MHz/ FREQ_APIC 48MHz/ SEL_3V66 X1
47,46,44 26
OUT OUT/IN
27 5
OUT/IN IN
X2 PWRDWN# SCLK SDATA
6 24 29 30
OUT IN IN IN/OUT
VDD VDDL VSS
4,10,16,23, 28,35 39,43,48 1,7,13,19,25, 31,36,41,45
POWER POWER POWER
4
PRODUCT SPECIFICATION
RC7106
Functional Description
I/O Pin Operation
Dual Purpose I/O pins such as pin 8 FS0/PCI_F, act as a logic input upon power up. This allows the determination of assigned device function. For this example, FS0 along with the other three select pins will determine the clock frequencies as shown in the table. A short time after power up, the logic state is latched and the pin becomes a clock output pin. In this case, pin 8 becomes a PCI free-running clock output. This feature reduces device pin count by combining clock outputs with input select pins. An external 10kohm "strapping" resistor is connected between the I/O pin and VDD or VSS (ground). A connection to ground sets a "0" bit and a connection to VDD sets a "1" bit. See Figure 1. Upon power up, the first 2mS of operation is used for input logic selection. The clock output pins are tri-stated, allowing
the output strapping resistor on the I/O pin to pull the pin and its associated capacitive clock load to either a logic high or low state. At the end of the 2mS period, the established logic "0" or "1" condition of the I/O pin is then latched. Next the output buffer is enabled which converts the I/O pin into an operating clock output. The 2mS timer is started when VDD reaches 2.0V. The input bits can only be reset by turning the VDD off and then back on again. It should be noted that the strapping resistors have no significant effect on clock output signal integrity. The drive impedance of clock output is 20 ohms (nominal) which is minimally affected by the 10kohm strap to ground or VDD. As with the series termination resistor, the output strapping resistor should be placed as close to the I/O pin as possible in order to keep the interconnecting trace short. The trace from the resistor to ground or VDD should be kept less than two inches in length to prevent system noise coupling during input logic sampling.
VDD Series Terminating Resistor Clock Load
RC7106
10K Load Option 1
10K Load Option 0
Figure 1. Input Logic Selection through Resistor Load Option
5
RC7106
PRODUCT SPECIFICATION
Serial Data Interface
The RC7106 features a two-pin, serial data interface that can be used to configure internal register settings that control particular device functions. Upon power-up, the RC7106 initializes with default register settings. Therefore, the use of this serial data interface is optional. The serial interface is write-only (to the clock chip) and is the dedicated function of
device pins SDATA and SCLK. In motherboard applications, SDATA and SCLK are typically driven by two logic outputs of the chipset. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. Table 2 summarizes the control functions of the serial data interface.
Table 2. Serial Data Interface Control Functions Summary
Control Function Clock Output Disable Description Any individual clock output(s) can be disabled. Disabled outputs are actively held low. Common Application Unused outputs are disabled to reduce EMI and system power. Examples are clock outputs to unused PCI slots. For alternate microprocessors and power management options. Smooth frequency transition allows CPU frequency change under normal system operation. Production PCB testing. Production PCB testing.
CPU Clock Provides CPU/PCI frequency selections Frequency Selection beyond the 133MHz provided upon poweron. Frequency is changed in a smooth and controlled fashion. Output Tristate Test Mode Puts all clock outputs into a high impedance state. All clock outputs toggle in relation to X1 input, internal PLL is bypassed. Refer to Table 4. Reserved function for future device revision or production device testing.
Reserved
No user application. Register bit must be written as 0.
Signaling Requirements for the I2C Serial Port
To initiate communications with the serial port, a start bit is invoked. The start bit is defined as the SDATA line is brought low while the SCLOCK is held high. Once the start bit is initiated, valid data can then be sent. Data is considered to be valid when the clock goes to and remains in the high state. The data can change when the clock goes low. To terminate the transmission, a stop bit is invoked. The stop bit occurs when the SDATA line goes from a low to a high state while the SCLOCK is held high. See Figure below.
RC7106 I2C Interface Write Sequence Example
Signal from Motherboard Clock Chip START MSB Slave Address (First Byte) LSB Command Code (2nd Byte) Byte Count (3rd Byte) Last Data Byte
STOP
SDATA SCLK
1 1
1 2
0 3
1 4
0 5
0 6
1 7
0 8 A
MSB 1 2 3
LSB 8 A
MSB 1 2
LSB 8 A
MSB 1 2
LSB 8 A
SDATA (ACK Signal From Buffer Chip)
Note:
Once the clock detects the start condition and its ADDRESS is matched, the clock chip will pull down the SDATA at every 8th bit. The 8 bit data from SDATA is latched into the Buffer Chip when the ACK is generated. This ACK signal will continue as long as STOP condition is detected The COMMAND CODE and BYTE COUNT is not used by the Buffer Chip.
6
PRODUCT SPECIFICATION
RC7106
Operation
The RC7106 is programmed by writing 10 bytes of eight bits each. See Table 3 for byte order.
Table 3. Byte Writing Sequence
Byte Sequence 1 Byte Name Slave Address Bit Sequence 11010010 Byte Description Commands the RC7106 to accept the bits in Data Bytes 3-6 for internal register configuration. Since other devices may exist on the same common serial data bus, it is necessary to have a specific slave address for each potential receiver. The slave receiver address for the RC7106 is 11010010. Register setting will not be made if the Slave Address is not correct (or is for an alternate slave receiver). Unused by the RC7106, therefore bit values are ignored (don't care). This byte must be included in the data write sequence to maintain proper byte allocation. The Command Code Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. Unused by the RC7106, therefore bit values are ignored (don't care). This byte must be included in the data write sequence to maintain proper byte allocation. The Byte Count Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. The data bits in these bytes set internal RC7106 registers that control device operation. The data bits are only accepted when the Address Byte bit sequence is 11010010, as noted above. For description of bit control functions, refer to Table 4, Data Byte Serial Configuration Map.
2
Command Code
Don't Care
3
Byte Count
Don't Care
4 5 6 7 8 9 10
Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 Data Byte 4 Data Byte 5 Data Byte 6
Refer to Table 5
7
RC7106
PRODUCT SPECIFICATION
Writing Data Bytes
Each bit of the 10 data bytes controls a particular device function except for the "reserved bits". These must be preserved by writing a logic 0. Bit 7, the MSB, is written first. See Table 4 for bit descriptions of Data Bytes 1-4.
Table 5 shows additional frequency selections that are programmable via the serial data interface. Table 7 shows the mode select functions for Byte 3, bits 1 and 0.
Table 4. Data Bytes 1-4 Serial Configuration Map
Affected Pin Bit(s) Data Byte 1 7 6 5 4 3 2 1 0 Data Byte 2 7 6 5 4 3 2 1 0 Data Byte 3 7 6 5 4 3 2 1 0 Data Byte 4 7 6 5 4 3 2 1 0
8
Bit Control Control Function Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) Clock Output Disable Clock Output Disable (Reserved) Clock Output Disable Clock Output Disable Clock Output Disable (Reserved) (Reserved) 0 Disable Disable Disable Disable Disable Disable Disable Disable Disable Disable Disable Disable Disable Disable Disable Disable Disable Disable Disable Disable Disable Disable Disable Disable 1 Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Default 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 0 1 1 1 0 0
Pin No. 40 38 37 42 47 46 2 3 18 17 15 14 12 11 9 8 34 33 32 26 27 22 21 20 -
Pin Name CPU0 CPU1 CPU2 CPU/2 IOAPIC0 IOAPIC1 REF0 REF1 PCI7 PCI6 PCI5 PCI4 PCI3 PCI2 PCI1 PCI_F 3V66_0 3V66_1 3V66_2 24_48MHz 48MHz PCI10 PCI9 PCI8 -
PRODUCT SPECIFICATION
RC7106
Table 5. Byte 0: Functionality and frequency select register (Default = 0)
Bit Bit 7 Bit (2, 6:4) Bit(2,6:4) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Bit 3 Bit 1 Bit 0 CPU 105 75 100.3 66.8 110 115 117 120 125 127 133.3 135 137 140 145 150 PCI 35 37.5 33.4 33.4 36.6 38.3 39 40 41.6 42.3 33.3 33.75 34.25 35 36.25 37.5 0- 0.25% Center Spread Spectrum 1- Down Spread Spectrum 0 to 3V66 3V66_SEL =0 70 64* 66.6 66.6 64* 64* 64* 64* 64* 64* 66.6 67.5 68.5 70 64* 64* 3V66_SEL =1 70 75 66.6 66.6 73.3 76.6 78 80 83.3 84.6 66.6 67.5 68.5 70 72.5 75 IOAPIC FREQ_APIC FREQ_APIC =0 =1 17.5 18.75 16.7 16.67 18.3 19.16 19.5 20 20.8 21.16 16.6 16.8 17.125 17.5 18.125 18.75 35 37.5 33.4 33.4 36.6 38.3 39 40 41.6 42.3 33.3 33.75 34.25 35 36.25 37.5 0 0 0 Note 1 Description Default 0
0- frequency is selected by hardware select, latched inputs 1- Frequency is selected by Bit 2,6:4 0- Normal 1- Spread Spectrum 0- Enabled 1- Tristate all outputs
Note 1: Default at power-up will be for latched logic inputs to define frequency, Bit 2, 6:4 are defaulted to 0000. *These output frequencies are not synchronous to the CPU Clock and do not have Spread Spectrum modulation.
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Symbol VDD, VIN TSTG TB TA ESDPROT Storage Temperature Ambient Temperature Operating Temperature Input ESD Protection Parameter Voltage on any pin with respect to VSS Ratings -0.5 to +7.0 -65 to +150 -55 to +125 0 to +70 2 (min) Units V
o
C C
oC o
kV
9
RC7106
PRODUCT SPECIFICATION
DC Electrical Characteristics
TA = 0C to +70C; VDD = 3.3V5%; VDDL = 2.5V5% Parameter Supply Current IDD3 IDD2 Combined 3.3V Supply Current Combined 2.5V Supply Current CPU = 133MHz Outputs Loaded CPU = 133MHz Outputs Loaded VSS-0.3 2.0 TBD TBD mA mA Test Condition Min. Typ. Max. Units
Logic Inputs VIL VIH IIL IIH IIL IIH Clock VOL VOH Input Low Voltage Input High Voltage Input Low Current1 Input High Current1 Input Low Current Input High Current Outputs2 Output Low Voltage Output High Voltage CPU, CPU/2 and IOAPIC PCI, 3V66, 24MHz,48MHz,REF IOL Output Low Current CPU, CPU/2 PCI, 3V66 REF, 24MHz,48MHz IOH Output High Current CPU and CPU/2 PCI and 3V66 REF, 24MHz,48MHz Crystal Oscillator VTH CIN CIN COUT LIN X1 Input Threshold Voltage X1 Input Capacitance
5
0.8 VDD+0.3 -25 10 -5 5
V V A A A A V V
IOL=1mA IOH=-1mA 2.0 2.4 VOL=1.2V VOL=1.4V VOH=1.4V VOH=1.4V 27 26.5 25 -101 -189 -94 VDD=3.3V X2 unconnected Except X1 and X2 1.5 18
0.4
93 139 76 -26 -31 -27
mA
mA
V pF 5 6 7 pF pF nH
Pin Capacitance/Inductance Input Pin Capacitance Output Pin Capacitance Input Pin Inductance
Notes: 1. RC7106 logic inputs have internal pull-up resistors. 2. All clock outputs loaded with maximum lump capacitance test load specified in AC Electrical Characteristics section. 3. X1 input threshold voltage (typical) is VDD/2
4. The RC7106 contains an internal crystal load capacitor between X1 and VSS and another between X2 and VSS. The total load placed on the crystal is 18pF; this includes typical stray capacitance of short PCB traces to the crystal. 5. X1 input capacitance is applicable when X1 is driven with an external clock source (X2 is left unconnected).
10
PRODUCT SPECIFICATION
RC7106
AC Electrical Characteristics
TA=0C to 70C; VDD=3.3V5%; VDDL=2.5V5%; fXTL=14.31818MHz AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output; Spread Spectrum clocking is disabled.
CPU Clock Outputs, CPU0:1 (CLOAD=20pF)
CPU=133MHz Parameter tP tH tL tR tF tD tJC tSK fST Period High Time Low Time Output Rise Time Output Fall Time Duty Cycle Jitter, Cycle to Cycle Output Skew Frequency Stabilization from Power-up (cold start) AC output Impedance 20 .4 .4 45 Min. 7.5 2 1.8 1.6 1.6 55 250 175 3 Typ. Max. 8 Units nS nS nS nS nS % pS pS mS Test Condition/Comments Meas. at rising edge at 1.25V. Duration of clock cycle above 2V. Duration of clock cycle below 0.4V 0.4V to 2.0V 2.0V to 0.4V Measured at 1.25V Measured on rising edge at 1.25V. Measured on rising edge at 1.25V. Assumes full supply voltage reached within 1mS from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value.
ZO
11
RC7106
PRODUCT SPECIFICATION
PCI Clock Outputs, PCI0:7 (Lump Capacitance Test Load = 30pF)
PCI = 33.3MHz Parameter tP tH tL tR tF tD tJC tSK tO Period High Time Low Time Output Rise Time Output Fall Time Duty Cycle Jitter, Cycle to Cycle Output Skew CPU to PCI Clock Offset 1.5 Min. 30 12.0 12.0 0.5 0.5 45 2 2 55 500 500 4.0 Typ. Max. Units nS nS nS nS nS % pS pS nS Test Condition/Comment Meas. at rising edge at 1.5V. Duration of clock cycle above 2.4V. Duration of clock cycle below 0.4V 0.4V to 2.4V 2.4V to 0.4V Measured at 1.5V Measured on rising edge at 1.5V. Measured on rising edge at 1.5V. Covers all CPU/PCI outputs. Measured on rising edge at 1.5V. CPU leads PCI output.
3V66 Clock Outputs (Lump Capacitance Test Load = 30pF)
CPU = 133MHz Parameter f tR tF tD tjc tSK fST ZO Frequency Output Rise Time Output Fall Time Duty Cycle Jitter, Cycle-to-cycle Output Skew Frequency Stabilization from Power-up AC Output Impedance 20 0.5 0.5 45 Min. Typ. 66.6 2 2 55 500 250 3 Max. Units MHz nS nS % pS pS mS ohm 0.4V to 2.4V 2.4V to 0.4V Measured at 1.5V Measured on rising edge at 1.5V Measured at 1.5V Assumes full supply voltage reached within 1mS from power-up. Average value during switching transition. Used for determining series termination value. Test Condition/Comment
CPU/2 Clock Output (Lump Capacitance Test Load = 20pF)
CPU = 133MHz Parameter f tR tF tD tjc tSK fST ZO Frequency Output Rise Time Output Fall Time Duty Cycle Jitter, Cycle-to-cycle Output Skew Frequency Stabilization from Power-up AC Output Impedance 20 0.5 0.5 45 Min. Typ. 66.6 2 2 55 250 175 3 Max. Units MHz nS nS % pS pS mS ohm 0.4V to 2.4V 2.4V to 0.4V Measured at 1.5V Measured on rising edge at 1.5V Measured at 1.25V Assumes full supply voltage reached within 1mS from power-up. Average value during switching transition. Used for determining series termination value. Test Condition/Comment
12
PRODUCT SPECIFICATION
RC7106
24MHz and 48MHz Clock Outputs (Lump Capacitance Test Load = 20pF)
CPU = 133MHz Parameter f fD n/m tR tF tD tA fST ZO Output Rise Time Output Fall Time Duty Cycle Jitter, Absolute Frequency Stabilization from Power-up AC Output Impedance 20 Frequency Frequency deviation 0.5 0.5 45 Min. Typ. 48.008 24.004 +167 57/17, 114/17 2 2 55 500 3 Max. Units MHz ppm nS nS % pS mS ohm 0.4V to 2.4V 2.4V to 0.4V Measured at 1.5V Measured on rising edge at 1.5V. Assumes full supply voltage reached within 1mS from power-up. Average value during switching transition. Used for determining series termination value. Test Condition/Comment Determined by PLL divider ratio. (48.008-48)/48
IOAPIC Clock Output (Lump Capacitance Test Load = 20pF)
CPU = 133MHz Parameter f tR tF tD tA tSK fST ZO Frequency Output Rise Time Output Fall Time Duty Cycle Jitter, Absolute Output Skew Frequency Stabilization from Power-up AC Output Impedance 20 0.4 0.4 45 Min. Typ. 33.3 1.6 1.6 55 500 175 1.5 Max. Units MHz nS nS % pS pS mS ohm Test Condition/Comment Frequency generated by crystal oscillator. 0.4V to 2.0V 2.0V to 0.4V Measured at 1.25V Measured on rising edge at 1.25V. Measured at 1.25V Assumes full supply voltage reached within 1mS from power-up. Average value during switching transition. Used for determining series termination value.
REF Clock Output (Lump Capacitance Test Load = 20pF)
CPU = 133MHz Parameter f tR tF tD tjc tSK fST ZO Frequency Output Rise Time Output Fall Time Duty Cycle Jitter, Cycle-to-cycle Output Skew Frequency Stabilization from Power-up AC Output Impedance 20 0.5 0.5 45 Min. Typ. 14.31818 2 2 55 1 1 3 Max. Units MHz nS nS % nS nS mS ohm Test Condition/Comment Frequency generated by crystal oscillator. 0.4V to 2.4V 2.4V to 0.4V Measured at 1.5V Measured on rising edge at 1.5V. Measured at 1.5V Assumes full supply voltage reached within 1mS from power-up. Average value during switching transition. Used for determining series termination value.
13
RC7106
PRODUCT SPECIFICATION
Group Skews (CPU and IOAPIC load = 20pF; PCI, 3V66 load = 30pF)
CPU = 133MHz Parameter tCPU-3V66 t3V66-PCI tCPU-IOAPIC CPU (66.6MHz) to 3V66 3V66 to PCI CPU to IOAPIC Min. 0 1.5 1.5 2.1 2.1 Typ. Max. Units 1.5 4 4 nS nS nS Test Condition/Comment CPU @ 1.25V and 3V66 @ 1.5V 3V66 and PCI @ 1.5V, 3V66 Leads CPU and IOAPIC @ 1.25V, CPU Leads
14
PRODUCT SPECIFICATION
RC7106
Mechanical Dimensions
48 pin SSOP
Symbol A A1 b c D E E1 e L N a ccc Inches Min. .095 .008 Max. .110 .016 Millimeters Min. 2.41 0.20 Max. 2.79 0.41 5 5 2, 4 2 3 6 Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 2. "D" and "E1" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5. "b" & "c" dimensions include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
.008 .0135 .005 .010 .620 .630 .395 .420 .291 .299 .025 BSC .020 .040 48 8 0 --.004
0.20 0.34 0.13 0.25 15.75 16.00 10.03 10.67 7.39 7.59 0.64 BSC 0.51 1.02 48 8 0 --0.13
E E1
1
D A e b A1 SEATING PLANE -CLEAD COPLANARITY ccc C c a L
15
RC7106
PRODUCT SPECIFICATION
Ordering Information
Product Number RC7106 Temperature Screening Package 48 SSOP Package Marking RC7106
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com 1/20/99 0.0m 008 Stock#DS30005057 (c) 1998 Fairchild Semiconductor Corporation
www.fairchildsemi.com
RC7108
133MHz Spread Spectrum Clock for Motherboards
Features
* Employs Fairchild's proprietary Spread Spectrum Technology * Reduces measured EMI by as much as 10dB * Supports up to 150MHz * Two skew-controlled copies of the CPU clock I2C programmable * Two copies of 3V66 clock * One copy 24MHz clock * One copy 48MHz clock * One copy IOAPIC * Two copy REF 14.318MHz clock (3.3V) * Eight copies PCI clock * Nine copies of SDRAM clock with one Free-running * Power down capability
Description
The RC7108 is a clock synthesizer for motherboard applications. It meets the requirements for 133MHz Whiting chipset. The clock frequencies can be set with the 4 select pins and/or be set via the I2C interface.
Block Diagram
X1 X2 XTAL OSC REF1 REF0/FREQ_APIC IOAPIC/SEL_3V66 PLL1 Spread Spectrum
PLL2 USB
C O N T R O L L O G I C
CPU0:1 3V660:1 FS0/PCI0 FS1/PCI1 PCI2:7 SDRAM0:7,_F 24MHz/FS2
SCLK SDATA
I2C Registers
PWRDWN#
48MHz/FS3
RC7108
PRODUCT SPECIFICATION
Pin Assignments
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
Pin Assignments
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 REF1 VDD X1 X2 VSS VSS 3V66-0 3V66-1 VDD VDD FS0/PCI0 FS1/PCI1 PCI2 VSS PCI3 PCI4 Pin Name Pin # 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PCI5 VDD PCI6 PCI7 VSS PWRDWN# SCLK SDATA VDD 48MHz/FS3 24MHz/FS2 VSS VDD SDRAM_F SDRAM7 SDRAM6 Pin name Pin # 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 VSS SDRAM5 SDRAM4 SDRAM3 VDD SDRAM2 SDRAM1 SDRAM0 VSS VSSL CPU1 CPU0 VDDL IOAPIC/SEL_3V66 VDDL REF0/FREQ_APIC Pin Name
2
PRODUCT SPECIFICATION
RC7108
PWRDWN#
REF, 24MHz, 48MHz LOW ON
PWRDWN# 0 1
CPU LOW ON
SDRAM LOW ON
IOAPIC LOW ON
3V66 LOW ON
PCI LOW ON
OSC. OFF ON
PLL OFF ON
Frequency Selection
3V66 (MHz) FS3 FS2 FS1 FS0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU MHz 100.3 100.9 105 115 120 124 133.3 133.3 140 150 66.8 70 75 83.3 90 95 SDRAM MHz 100.3 100.9 105 115 120 124 133.3 133.3 140 150 100.2 105 112.5 124.5 90 95 PCI MHz 33.3 33.67 35 38.33 40 41.33 44.33 33.3 35 37.5 33.4 35 37.5 41.5 30 31.67 3V66_SYNC =0 66.6 67.34 70 64* 64* 64* 64* 66.6 70 64* 66.6 70 64* 64* 60 63.34 3V66_SYNC =1 66.6 67.34 70 76.66 80 82.66 88.66 66.6 70 75 66.6 70 75 83 60 63.34 IOAPIC (MHz) FREQ_APIC =0 16.67 16.84 17.5 19.17 20 20.67 22.17 16.67 17.5 18.75 16.67 17.5 18.75 20.75 15 15.84 FREQ_APIC =1 33.3 33.67 35 38.33 40 41.33 44.33 33.3 35 37.5 3.3 35 37.5 41.5 30 31.67
*Note: These output frequencies are not synchronous to the CPU Clock and do not have Spread Spectrum modulation.
3
RC7108
PRODUCT SPECIFICATION
Pin Descriptions
Pin Name CPU0:1 PCI2:7 PCI0/FS0 PCI1/FS1 3V66-0:1 REF1 REF0/ FREQ_APIC Pin Number 44,43 13,15,16, 17,19,20 11 12 7,8 1 48 Type OUT OUT OUT/IN OUT/IN OUT OUT OUT/IN Pin Function Description CPU Clock Outputs: These two CPU clocks are determined by the 4 select pins FS0:3 PCI BUS Clock Outputs: These 6 PCI clock outputs run synchronously to the CPU. I/O Dual Function PCI0 and FS0 pin: See table for frequency selection. After power-on, this pin becomes a normal PCI clock. I/O Dual Function PCI1 and FS1 pin: See table for frequency selection. After power-on, this pin becomes a normal PCI clock. 3V66 Clock Outputs: These 2 outputs are fixed at 66MHz operating from 3.3V. REF Clock Output: This output provides a 14.318MHz high drive clock . I/O Dual Function REF0 and FREQ_APIC Pin: During power-up, if the input is "0", the IOAPIC output would operate at 16.67MHz. If the input is latched "1", the IOAPIC output would operate at 33.3MHz. After power-on, this pin becomes a REF0 output. There is an internal pull-up resistor on this pin. I/O Dual Function IOAPIC and SEL_3V66 Pin: See table for frequency selection. SDRAM Clock Outputs: SDRAM0:7 clocks are determined by FS0:FS3. SDRAM_F is a free-running clock which is not controlled by the I2C. I/O Dual Function 24MHz and FS2 pin: See table for frequency selection. After power-on the pin becomes a normal 24MHz clock. I/O Dual Function 48MHz and FS3 pin: See table for frequency selection. After power-on the pin becomes a normal 48MHz clock. Crystal Connection: An input connection for an external14.318MHz crystal. If using an external reference, this pin must be left unconnected. Crystal Connection or External Reference Frequency Input: Connect to either a 14.318MHz crystal or other reference signal. Power-down Input pin: This pin shuts down the clock PLL bring all clocks to a low state. I2C Clock Pin: The I2C clock should be applied to this input as described in the I2C section of this datasheet. I2C Data Pin: Data should be presented to this input as described by the I2C section of this datasheet. There is an internal pull-up resistor on this pin. 3.3V Power Pins: 2.5V Power Pins: Ground Pins:
IOAPIC/ SEL_3V66 SDRAM0:7 SDRAM_F 24MHz/FS2 48MHz/FS3 X1
46 40,39,38,36, 35,34,32,31, 30 27 26 3
OUT/IN OUT
OUT/IN OUT/IN IN
X2 PWRDWN# SCLK SDATA
4 22 23 24
OUT IN IN IN/OUT
VDD VDDL VSS
2,9,10,18,25, 29,37 45,47 5,6,14,21,28, 33,41,42
POWER POWER POWER
4
PRODUCT SPECIFICATION
RC7108
Functional Description
I/O Pin Operation
Dual Purpose I/O pins such as pin 11 FS0/PCI0, act as a logic input upon power up. This allows the determination of assigned device function. For this example, FS0 along with the other three select pins will determine the clock frequencies as shown in the table. A short time after power up, the logic state is latched and the pin becomes a clock output pin. In this case, pin 11 becomes a PCI clock output. This feature reduces device pin count by combining clock outputs with input select pins. An external 10kohm "strapping" resistor is connected between the I/O pin and VDD or VSS (ground). A connection to ground sets a "0" bit and a connection to VDD sets a "1" bit. See Figure 1. Upon power up, the first 2mS of operation is used for input logic selection. The clock output pins are tri-stated, allowing
the output strapping resistor on the I/O pin to pull the pin and its associated capacitive clock load to either a logic high or low state. At the end of the 2mS period, the established logic "0" or "1" condition of the I/O pin is then latched. Next the output buffer is enabled which converts the I/O pin into an operating clock output. The 2mS timer is started when VDD reaches 2.0V. The input bits can only be reset by turning the VDD off and then back on again. It should be noted that the strapping resistors have no significant effect on clock output signal integrity. The drive impedance of clock output is 20 ohms (nominal) which is minimally affected by the 10kohm strap to ground or VDD. As with the series termination resistor, the output strapping resistor should be placed as close to the I/O pin as possible in order to keep the interconnecting trace short. The trace from the resistor to ground or VDD should be kept less than two inches in length to prevent system noise coupling during input logic sampling.
VDD Series Terminating Resistor Clock Load
RC7108
10K Load Option 1
10K Load Option 0
Figure 1. Input Logic Selection through Resistor Load Option
5
RC7108
PRODUCT SPECIFICATION
Serial Data Interface
The RC7108 features a two-pin, serial data interface that can be used to configure internal register settings that control particular device functions. Upon power-up, the RC7108 initializes with default register settings. Therefore, the use of this serial data interface is optional. The serial interface is write-only (to the clock chip) and is the dedicated function of
device pins SDATA and SCLK. In motherboard applications, SDATA and SCLK are typically driven by two logic outputs of the chipset. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. Table 2 summarizes the control functions of the serial data interface.
Table 2. Serial Data Interface Control Functions Summary
Control Function Clock Output Disable Description Any individual clock output(s) can be disabled. Disabled outputs are actively held low. Common Application Unused outputs are disabled to reduce EMI and system power. Examples are clock outputs to unused PCI slots. For alternate microprocessors and power management options. Smooth frequency transition allows CPU frequency change under normal system operation. Production PCB testing. Production PCB testing.
CPU Clock Provides CPU/PCI frequency selections Frequency Selection beyond the 133MHz provided upon poweron. Frequency is changed in a smooth and controlled fashion. Output Tristate Test Mode Puts all clock outputs into a high impedance state. All clock outputs toggle in relation to X1 input, internal PLL is bypassed. Refer to Table 4. Reserved function for future device revision or production device testing.
Reserved
No user application. Register bit must be written as 0.
6
PRODUCT SPECIFICATION
RC7108
Operation
The RC7108 is programmed by writing 10 bytes of eight bits each. See Table 3 for byte order.
Table 3. Byte Writing Sequence
Byte Sequence 1 Byte Name Slave Address Bit Sequence 11010010 Byte Description Commands the RC7108 to accept the bits in Data Bytes 3-6 for internal register configuration. Since other devices may exist on the same common serial data bus, it is necessary to have a specific slave address for each potential receiver. The slave receiver address for the RC7108 is 11010010. Register setting will not be made if the Slave Address is not correct (or is for an alternate slave receiver). Unused by the RC7108, therefore bit values are ignored (don't care). This byte must be included in the data write sequence to maintain proper byte allocation. The Command Code Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. Unused by the RC7108, therefore bit values are ignored (don't care). This byte must be included in the data write sequence to maintain proper byte allocation. The Byte Count Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. The data bits in these bytes set internal RC7108 registers that control device operation. The data bits are only accepted when the Address Byte bit sequence is 11010010, as noted above. For description of bit control functions, refer to Table 4, Data Byte Serial Configuration Map.
2
Command Code
Don't Care
3
Byte Count
Don't Care
4 5 6 7 8 9 10
Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 Data Byte 4 Data Byte 5 Data Byte 6
Refer to Table 5
7
RC7108
PRODUCT SPECIFICATION
Writing Data Bytes
Each bit of the 10 data bytes controls a particular device function except for the "reserved bits". These must be preserved by writing a logic 0. Bit 7, the MSB, is written first. See Table 4 for bit descriptions of Data Bytes 1-4.
Table 5 shows additional frequency selections that are programmable via the serial data interface. Table 7 shows the mode select functions for Byte 3, bits 1 and 0.
Table 4. Data Bytes 1-4 Serial Configuration Map
Affected Pin Bit(s) Data Byte 1 7 6 5 4 3 2 1 0 Data Byte 2 7 6 5 4 3 2 1 0 Data Byte 3 7 6 5 4 3 2 1 0 Data Byte 4 7 6 5 4 3 2 1 0
8
Bit Control Control Function (Reserved) (Reserved) (Reserved) Clock Output Disable Clock Output Disable (Reserved) (Reserved) (Reserved) Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable (Reserved) Clock Output Disable Clock Output Disable (Reserved) Clock Output Disable (Reserved) Clock Output Disable Clock Output Disable 0 Disable Disable Disable Disable Disable Disable Disable Disable Disable Disable Disable Disable Disable Disable Disable Disable Disable Disable Disable Disable Disable Disable Disable 1 Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Enable Default 0 0 0 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 1 0 1 1
Pin No. 27 26 31 32 34 35 36 38 39 40 20 19 17 16 15 13 12 11 8 7 46 43 44
Pin Name 24MHz 48MHz SDRAM7 SDRAM6 SDRAM5 SDRAM4 SDRAM3 SDRAM2 SDRAM1 SDRAM0 PCI7 PCI6 PCI5 PCI4 PCI3 PCI2 PCI1 PCI0 3V66-1 3V66-0 IOAPIC CPU1 CPU0
PRODUCT SPECIFICATION
RC7108
Table 5. Byte 0: Functionality and frequency select register (Default = 0)
Bit Bit 7 Bit (2, 6:4) Bit(2,6:4) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Bit 3 Bit 1 Bit 0 CPU 100.3 100.9 105 115 120 124 133.3 133.3 140 150 66.8 70 75 83.3 90 95 SDRAM 100.3 100.9 105 115 120 124 133.3 133.3 140 150 100.2 105 112.5 124.5 90 95 PCI 33.3 33.67 35 38.33 40 41.33 44.33 33.3 35 37.5 33.4 35 37.5 41.5 30 31.67 0- +0.25% Center Spread Spectrum 1- Down Spread Spectrum 0 to -0.5% 3V66 IOAPIC Note 1 3V66_SEL 3V66_SEL FREQ_APIC FREQ_APIC =0 =1 =0 =1 66.6 67.34 70 64* 64* 64* 64* 66.6 70 64* 66.6 70 64* 64* 60 63.34 66.6 67.34 70 76.66 80 82.66 88.66 66.6 70 75 66.6 70 75 83 60 63.34 16.67 16.84 17.5 19.17 20 20.67 22.17 16.67 17.5 18.75 16.67 17.5 18.75 20.75 15 15.84 33.3 33.67 35 38.33 40 41.33 44.33 33.3 35 37.5 3.3 35 37.5 41.5 30 31.67 0 0 0 Description Default 0
0- frequency is selected by hardware select, latched inputs 1- Frequency is selected by Bit 2,6:4 0- Normal 1- Spread Spectrum 0- Enabled 1- Tristate all outputs
Note 1: Default at power-up will be for latched logic inputs to define frequency, Bit 2, 6:4 are defaulted to 0000. *These output frequencies are not synchronous to the CPU Clock and do not have Spread Spectrum modulation.
9
RC7108
PRODUCT SPECIFICATION
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions Symbol VDD, VIN TSTG TB TA ESDPROT Storage Temperature Ambient Temperature Operating Temperature Input ESD Protection Parameter Voltage on any pin with respect to VSS above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Ratings -0.5 to +7.0 -65 to +150 -55 to +125 0 to +70 2 (min) Units V
oC o
C
oC
kV
DC Electrical Characteristics
TA = 0C to +70C; VDD = 3.3V5%; VDDL = 2.5V5% Parameter Supply Current IDD3 IDD2 Combined 3.3V Supply Current Combined 2.5V Supply Current CPU = 133MHz Outputs Loaded CPU = 133MHz Outputs Loaded VSS-0.3 2.0 TBD TBD mA mA Test Condition Min. Typ. Max. Units
Logic Inputs VIL VIH IIL IIH IIL IIH Clock VOL VOH Input Low Voltage Input High Voltage Input Low Input High Current1 Current1 0.8 VDD+0.3 -25 10 -5 5 IOL=1mA IOH=-1mA 2.0 2.4 VOL=1.2V 27 40 VOL=1.4V 26.5 25 61 93 138 139 76 152 mA 0.4 V V A A A A V V
Input Low Current Input High Current Outputs2 Output Low Voltage Output High Voltage CPU and IOAPIC PCI, SDRAM, 3V66, 24MHz,48MHz,REF
IOL
Output Low Current CPU IOAPIC PCI, 3V66 REF, 24MHz,48MHz SDRAM
10
PRODUCT SPECIFICATION
RC7108
DC Electrical Characteristics (Continued)
TA = 0C to +70C; VDD = 3.3V5%; VDDL = 2.5V5% Parameter IOH Output High Current CPU IOAPIC PCI, 3V66 REF, 24MHz,48MHz SDRAM Crystal oscillator VTH CLOAD CIN CIN COUT LIN X1 Input Threshold Voltage3 Load Capacitance, as seen by external Xtal.4 X1 Input Capacitance5 Input Pin Capacitance Output Pin Capacitance Input Pin Inductance X2 unconnected Except X1 and X2 VDD=3.3V 1.5 18 28 5 6 7 V pF pF PF pF NH VOH=1.4V Test Condition VOH=1.2V Min. -26 -39 -31 -27 -68 Typ. Max. -101 -150 -189 -94 -188 Units mA
Pin Capacitance/Inductance
Notes: 1. RC7108 logic inputs have internal pull-up resistors. 2. All clock outputs loaded with maximum lump capacitance test load specified in AC Electrical Characteristics section. 3. X1 input threshold voltage (typical) is VDD/2 4. The RC7108 contains an internal crystal load capacitor between X1 and VSS and another between X2 and VSS. The total load placed on the crystal is 18pF; this includes typical stray capacitance of short PCB traces to the crystal. 5. X1 input capacitance is applicable when X1 is driven with an external clock source (X2 is left unconnected).
AC Electrical Characteristics
TA=0C to 70C; VDD=3.3V5%; VDDL=2.5V5%; fXTL=14.31818MHz AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output; Spread Spectrum clocking is disabled.
CPU Clock Outputs, CPU0:1 (CLOAD=20pF)
CPU=133MHz Parameter tP tH tL tR tF tD tJC tSK fST Period High Time Low Time Output Rise Time Output Fall Time Duty Cycle Jitter, Cycle to Cycle Output Skew Frequency Stabilization from Power-up (cold start) AC output Impedance 20 .4 .4 45 Min. 7.5 2 1.8 1.6 1.6 55 250 175 3 Typ. Max. 8 Units nS nS nS nS nS % pS pS mS Test Condition/Comments Meas. at rising edge at 1.25V. Duration of clock cycle above 2V. Duration of clock cycle below 0.4V 0.4V to 2.0V 2.0V to 0.4V Measured at 1.25V Measured on rising edge at 1.25V. Measured on rising edge at 1.25V. Assumes full supply voltage reached within 1mS from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value.
ZO
11
RC7108
PRODUCT SPECIFICATION
PCI Clock Outputs, PCI0:7 (Lump Capacitance Test Load = 30pF)
PCI = 33.3MHz Parameter tP tH tL tR tF tD tJC tSK tO Period High Time Low Time Output Rise Time Output Fall Time Duty Cycle Jitter, Cycle to Cycle Output Skew CPU to PCI Clock Offset 1.5 Min. 30 12.0 12.0 0.5 0.5 45 2 2 55 500 500 4.0 Typ. Max. Units nS nS nS nS nS % pS pS nS Test Condition/Comment Meas. at rising edge at 1.5V. Duration of clock cycle above 2.4V. Duration of clock cycle below 0.4V 0.4V to 2.4V 2.4V to 0.4V Measured at 1.5V Measured on rising edge at 1.5V. Measured on rising edge at 1.5V. Covers all CPU/PCI outputs. Measured on rising edge at 1.5V. CPU leads PCI output.
3V66 Clock Outputs (Lump Capacitance Test Load = 30pF)
CPU = 133MHz Parameter f tR tF tD tjc tSK fST ZO Frequency Output Rise Time Output Fall Time Duty Cycle Jitter, Cycle-to-cycle Output Skew Frequency Stabilization from Power-up AC Output Impedance 20 0.5 0.5 45 Min. Typ. 66.6 2 2 55 500 250 3 Max. Units MHz nS nS % pS pS mS ohm 0.4V to 2.4V 2.4V to 0.4V Measured at 1.5V Measured on rising edge at 1.5V Measured at 1.5V Assumes full supply voltage reached within 1mS from power-up. Average value during switching transition. Used for determining series termination value. Test Condition/Comment
SDRAM Clock Output (Lump Capacitance Test Load = 20pF)
CPU = 133MHz Parameter f tR tF tD tjc tSK fST ZO Frequency Output Rise Time Output Fall Time Duty Cycle Jitter, Cycle-to-cycle Output Skew Frequency Stabilization from Power-up AC Output Impedance 20 0.5 0.5 45 Min. Typ. 66.6 2 2 55 250 250 3 Max. Units MHz nS nS % pS pS mS ohm 0.4V to 2.4V 2.4V to 0.4V Measured at 1.5V Measured on rising edge at 1.5V Measured at 1.5V Assumes full supply voltage reached within 1mS from power-up. Average value during switching transition. Used for determining series termination value. Test Condition/Comment
12
PRODUCT SPECIFICATION
RC7108
24MHz and 48MHz Clock Outputs (Lump Capacitance Test Load = 20pF)
CPU = 133MHz Parameter f fD n/m tR tF tD tA fST ZO Output Rise Time Output Fall Time Duty Cycle Jitter, Absolute Frequency Stabilization from Power-up AC Output Impedance 20 Frequency Frequency deviation 0.5 0.5 45 Min. Typ. 48.008 24.004 +167 57/17, 114/17 2 2 55 500 3 Max. Units MHz ppm nS nS % pS mS ohm 0.4V to 2.4V 2.4V to 0.4V Measured at 1.5V Measured on rising edge at 1.5V. Assumes full supply voltage reached within 1mS from power-up. Average value during switching transition. Used for determining series termination value. Test Condition/Comment Determined by PLL divider ratio. (48.008-48)/48
IOAPIC Clock Output (Lump Capacitance Test Load = 20pF)
CPU = 133MHz Parameter f tR tF tD tA fST ZO Frequency Output Rise Time Output Fall Time Duty Cycle Jitter, Absolute Frequency Stabilization from Power-up AC Output Impedance 20 0.4 0.4 45 Min. Typ. 14.31818 1.6 1.6 55 500 1.5 Max. Units MHz nS nS % pS mS ohm Test Condition/Comment Frequency generated by crystal oscillator. 0.4V to 2.0V 2.0V to 0.4V Measured at 1.25V Measured on rising edge at 1.25V. Assumes full supply voltage reached within 1mS from power-up. Average value during switching transition. Used for determining series termination value.
REF Clock Output (Lump Capacitance Test Load = 20pF)
CPU = 133MHz Parameter f tR tF tD tjc fST ZO Frequency Output Rise Time Output Fall Time Duty Cycle Jitter, Cycle-to-cycle Frequency Stabilization from Power-up AC Output Impedance 20 0.5 0.5 45 Min. Typ. 14.31818 2 2 55 500 3 Max. Units MHz nS nS % nS mS ohm Test Condition/Comment Frequency generated by crystal oscillator. 0.4V to 2.4V 2.4V to 0.4V Measured at 1.5V Measured on rising edge at 1.5V. Assumes full supply voltage reached within 1mS from power-up. Average value during switching transition. Used for determining series termination value.
13
RC7108
PRODUCT SPECIFICATION
Group Skews (CPU and IOAPIC load = 20pF; PCI, SDRAM, 3V66 load = 30pF)
CPU = 133MHz Parameter tCPU-3V66 tCPU-SDRAM t3V66-PCI tIOAPIC-PCI CPU (66.6MHz) to 3V66 CPU (133MHz) to SDRAM 3V66 to PCI IOAPIC to PCI 1.5 2.1 Min. Typ. Max. Units 500 500 4 500 pS pS nS pS Test Condition/Comment CPU @ 1.25V and 3V66 @ 1.5V Note 180o offset between outputs CPU @ 1.25V and SDRAM @1.5V Note 180o offset between outputs 3V66 and PCI @ 1.5V ( prefer 2.0 to 2.5nS) IOAPIC @ 1.25V and PCI @ 1.5V
14
PRODUCT SPECIFICATION
RC7108
Mechanical Dimensions
48 pin SSOP
Symbol A A1 b c D E E1 e L N a ccc Inches Min. .095 .008 Max. .110 .016 Millimeters Min. 2.41 0.20 Max. 2.79 0.41 5 5 2, 4 2 3 6 Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 2. "D" and "E1" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5. "b" & "c" dimensions include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
.008 .0135 .005 .010 .620 .630 .395 .420 .291 .299 .025 BSC .020 .040 48 8 0 --.004
0.20 0.34 0.13 0.25 15.75 16.00 10.03 10.67 7.39 7.59 0.64 BSC 0.51 1.02 48 8 0 --0.13
E E1
1
D A e b A1 SEATING PLANE -CLEAD COPLANARITY ccc C c a L
15
RC7108
PRODUCT SPECIFICATION
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com 1/20/99 0.0m 008 Stock#DS30005057 (c) 1998 Fairchild Semiconductor Corporation
www.fairchildsemi.com
RC7144
133MHz Spread Spectrum Motherboard Integrated Clock/Buffer
Features
* Employs Fairchild's proprietary Spread Spectrum Technology * Reduces measured EMI by as much as 10dB * Supports up to 150MHz I2C programmable * Two copies of CPU clock with one free running * One copy 24MHz clock * One copy 48MHz clock * One copy IOAPIC * Two copy REF 14.318MHz clock (3.3V) * Six copies PCI clock * Thirteen copies of SDRAM clock with one free running * PCI/CPU stop capability
Description
The RC7144 is a clock synthesizer for motherboard applications. It meets the requirements for the 133MHz 13x/zx chipset. The clock frequencies can be set with the 4 select pins or can be set via the I2C interface.
Preliminary Information
Block Diagram
X1 X2 XTAL OSC REF1/FS2 REF0/PCI_STOP# IOAPIC PLL1 Spread Spectrum
PLL2 USB SDRAMIN SCL SDA I2C Registers
C O N T R O L L O G I C
CPU1 CPU_F PCI_F/MODE PCI1/FS3 PCI2:5 SDRAM_F SDRAM0:11
CLK_STOP# 24MHz/FS1 48MHz/FS0
I2C is a trademark of Philips Corporation
Rev. 0.8.2
Preliminary Specification describes products that are not in full production at the time of printing. Specifications are based on design goals and limited characterization. They may change without notice. Contact Fairchild Semiconductor for current information.
RC7144
PRODUCT SPECIFICATION
Pin Assignments
VDDQ3 REF0/PCI_STOP# GND X1 X2 VDDQ3 PCI_F/MODE PCI1/FS3 GND PC12 PC13 PC14 PC15 VDDQ3 SDRAMIN GND SDRAM11 SDRAM10 VDDQ3 SDRAM9 SDRAM8 GND SDA 2C I SCL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDQ2 IOAPIC REF1/FS2* GND CPU_F CPU1 VDDQ2 CLK_STOP# SDRAM_F GND SDRAM0 SDRAM1 VDDQ3 SDRAM2 SDRAM3 GND SDRAM4 SDRAM5 VDDQ3 SDRAM6 SDRAM7 VDDQ3 48MHz/FS0* 24MHz/FS1*
RC7144
Preliminary Information
{
2
PRODUCT SPECIFICATION
RC7144
Pin Description
Pin Name VDDQ3 Pin # 1, 6, 14, 19, 27, 30, 36 2 Pin Type PWR Pin Function Power connection: Power supply for core logic, PLL circuitry SDRAM outputs, PCI outputs, reference, 48 & 24 MHz outputs. Connect to 3.3 Volts. I/O Dual function REF0 & PCI_STOP#: Function determined by MODE pin. When high, this pin is an output with 14.31818 MHz of reference clock. When MODE is low, PCI_STOP# stops all the PCI clocks. Ground connection: Connect all ground pins to the common system ground plane. Crystal Connection: An input connection for an external 14.318 MHz crystal. 18 pF internal cap.
REF0/ PCI_STOP#
OUT/IN
GND X1 X2
3, 9, 16, 22, 33, 39, 45 4 5
PWR IN OUT
Preliminary Information
Crystal Connection or External Reference Frequency: This pin has dual functions. It can be used as an external 14.318 MHz crystal connection or as an external reference frequency input. Fixed PCI clock output: Upon power up MODE input will be latched, which will enable or disable REF0. PCI clock output: Upon power up FS3 input will be latched, which will set clock frequencies as frequency selection table. This pin has internal pull down. PCI clock output 2 through 5: These five PCI clock outputs are controlled by the PCI_STOP# control pin. Buffered input pin: The signal provided to this input pin is buffered to 13 outputs. SDRAM Clock Ouputs: SDRAM0:11 clock are determined by FS0: FS3. SDRAM_F is a free running clock which is not controlled by the I2C. Data pin for I2C circuitry. Clock pin for I2C circuitry. 24 MHz clock output: 24 MHz is provided in normal operation. In standard systems, this output can be used as the clock input for Super I/O chip. Upon power up FS1 input will be latched, which will set clock frequencies as frequency selection table. 48 MHz clock output: 48 MHz is provided in normal operation. In standard systems, this output can be used as the reference for universal Serial Bus. Upon power up FS0 input will be latched, which will set clock frequencies as frequency selection table. CLK_STOP# Input: When 0, this pin stops the CPU outputs after completing a full clock cycle. This pin does not effect CPU_F. Power supply for IOAPIC & all CPU outputs. Connect to 2.5 or 3.3 Volts. CPU output clocks: VDDQ2 controls output Voltage. Stopped when CLK_STOP# is 0. CPU_F is not affected by CLK_STOP#. Reference Clock output: 14.31818 MHz reference output. Upon power up FS2 input will be latched, which will set clock frequencies as frequency selection table. IOAPIC clock: Provides 14.31818 MHz fixed clock. VDDQ2 contols the output Voltage.
PCI_F/MODE PCI1/FS3
7 8
OUT/IN OUT/IN
PCI2:5 SDRAM_IN SDRAM0:11; SDRAM_F
10, 11, 12, 13 15 17, 18, 20, 21, 28, 29, 31, 32, 34, 35, 37, 38, 40 23 24 25
OUT IN OUT
SDA SCL 24MHz/FS1
IN/OUT IN OUT/IN
48MHz/FS0
26
OUT/IN
CLK_STOP# VDDQ2 CPU1, CPU_F REF1/FS2
41 42, 48 43, 44 46
IN PWR OUT OUT/IN
IOAPIC
47
OUT
3
RC7144
PRODUCT SPECIFICATION
Frequency Selection Table
Input Address FS3 1 1 1 1 1 1 1 1 FS2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 FS1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 FS0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 CPU (MHz) 133.3 124 150 140 105 110 115 120 100 133.3 112 103 66.8 83.3 75 124 PCI (MHz) 33.3 31 37.5 35 35 36.7 38.3 40 33.3 44.43 37.3 34.3 33.4 41.7 37.5 41.3
Preliminary Information
0 0 0 0 0 0 0 0
Power Management Control
Mode 0 0 1 PCI_STOP# 0 1 X PCI Stopped Running Running REF0 Disable Disable Running PCI_F Running Running Running
CLK_STOP# 0 1
CPU Stopped Running
CPU_F Running Running
REF1, 24/48MHZ, SDRAM 0:11 Running Running
4
PRODUCT SPECIFICATION
RC7144
Functional Description
I/O Pin Operation
Dual Purpose I/O pins such as pin 8 FS3/PCI1, act as a logic input upon power up. This allows the determination of assigned device function. For example, FS3 along with the other three select pins will determine the clock frequencies as shown in the table. A short time after power up, the logic state is latched and the pin becomes a clock output pin. For example, pin 8 becomes a PCI clock output. This feature reduces device pin count by combining clock outputs with input select pins. An external 10k ohm "strapping" resistor is connected between the I/O pin and VDD or VSS (ground). A connection to ground sets a "0" bit and a connection to VDD sets a "1" bit. See Figure 1. Upon power up, the first 2mS of operation is used for input logic selection. The clock output pins are tri-stated, allowing
VDD
the output strapping resistor on the I/O pin to pull the pin and its associated capacitive clock load to either a logic high or low state. At the end of the 2mS period, the established logic "0" or "1" condition of the I/O pin is then latched. Next the output buffer is enabled which converts the I/O pin into an operating clock output. The 2mS timer is started when VDD (3.3V) reaches 2.0V. The input bits can only be reset by turning the VDD off and then back on again. It should be noted that the strapping resistors have no significant effect on clock output signal integrity. The drive impedance of outputs is 20 ohms (nominal) which is minimally affected by the 10kohm strap to ground or VDD. As with the series termination resistor, the output strapping resistor should be placed as close to the I/O pin as possible in order to keep the interconnecting trace short. The trace from the resistor to ground or VDD should be kept less than two inches in length to prevent system noise coupling during input logic sampling.
Preliminary Information
RC7144
10K Load Option 1
Series Terminating Resistor Clock Load
10K Load Option 0
Figure 1. Input Logic Selection through Resistor Load Option
5
RC7144
PRODUCT SPECIFICATION
I2C Interface Information
The RC7144 features a two-pin, serial data interface that can be used to configure internal register settings that control particular device functions. Upon power-up, the RC7144 initializes with default register settings therefore, the use of this serial data interface is optional. The serial interface is writeonly (to the clock chip) and is the dedicated function of
device pins SDA and SCL. In motherboard applications, SDA and SCL are typically driven by two logic outputs of the chipset. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. Table 1 summarizes the control functions of the serial data interface.
Table 1. Serial Data Interface Control Functions Summary
Control Function Clock Output Disable Description Any individual clock output(s) can be disabled. Disabled outputs are actively held low. Common Application Unused outputs are disabled to reduce EMI and system power. Examples are clock outputs to unused PCI slots. For alternate microprocessors and power management options. Smooth frequency transition allows CPU frequency change under normal system operation. EMI reduction. Production PCB testing. Production PCB testing.
Preliminary Information
CPU Clock Provides CPU/PCI frequency selections Frequency Selection other than the 100MHz provided upon power-on. Frequency is changed in a smooth and controlled fashion. Spread Spectrum Enabling Output Tristate Test Mode Turns spread spectrum on or off. Puts all clock outputs into a high impedance state. All clock ouputs toggle in relation to X1 input, internal PLL is bypassed. Refer to Table 6. Reserved function for future device revision or production device testing.
Reserved
No user application. Register bit must be written as 0.
RC7144 I2C Interface Write Sequence Example
Signal from Motherboard Clock Chip START MSB Slave Address (First Byte) LSB Command Code (2nd Byte) Byte Count (3rd Byte) Last Data Byte STOP
SDA SCL
1 1
1 2
0 3
1 4
0 5
0 6
1 7
0 8 A
MSB 1 2 3
LSB 8 A
MSB 1 2
LSB 8 A
MSB 1 2
LSB 8 A
SDA (ACK Signal From Buffer Chip)
Note:
Once the clock detects the start condition and its ADDRESS is matched, the clock chip will pull down the SDA at every 8th bit. The 8 bit data from SDA is latched into the Buffer Chip when the ACK is generated. This ACK signal will continue as long as STOP condition is detected The COMMAND CODE and BYTE COUNT is not used by the Buffer Chip.
6
PRODUCT SPECIFICATION
RC7144
I2C Register Operation
The RC7144 is programmed by writing 10 bytes of eight bits each. See Table 2 for byte order.
Table 2. Byte Writing Sequence
Byte Sequence 1 Byte Name Slave Address Bit Sequence 11010010 Byte Description Commands the RC7144 to accept the bits in Data Bytes 0-6 or internal register configuration. Since other devices may exist on the same common serial data bus, it is necessary to have a specific slave address for each potential receiver. The slave receiver address for the RC7144 is 11010010. Register setting will not be made if the Slave Address is not correct (or is for an alternate slave receiver). Unused by the RC7144, therefore, bit values are ignored (don't care). This byte must be included in the data write sequence to maintain proper byte allocation. The Command Code Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. Unused by the RC7144, therefore, bit values are ignored (don't care). This byte must be included in the data write sequence to maintain proper byte allocation. The Byte Count Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. The data bits in these bytes set internal RC7144 registers that control device operation. The data bits are only accepted when the Address Byte bit sequence is 11010010, as noted above. For description of bit control functions, refer to Table 5, Data Byte Serial Configuration Map.
2
Command Code
Don't Care
Preliminary Information
3
Byte Count
Don't Care
4 5 6 7 8 9 10
Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 Data Byte 4 Data Byte 5 Data Byte 6
Refer to Table 3
7
RC7144
PRODUCT SPECIFICATION
Writing Data Bytes
Each bit of the 8 data bytes controls a particular device function except for the "reserved bits". These must be preserved by writing a logic 0. Bit 7, the MSB, is written first. See Table 3 for bit descriptions of Data Bytes 1-4.
Table 5 shows additional frequency selections that are programmable via the serial data interface. Table 4 shows the mode select for byte 0, Bit 1and 0.
Table 3. Data Bytes 0-7 Serial Configuration Map
Affected Pin Bit(s) 7 6 Pin No. Pin Name Control Function Spread Mode FS 2 FS 1 FS 0 Hardware/Software Frequency Select FS3 Bit 1 0 0 1 1 Bit 0 0 1 0 0 0 Center Hardware Function (see Table 4) Normal Operation Reserved Spread Spectrum on All Outputs Tristated Test Mode Low Low Low Low Low Low Low Low Low Low Low Normal Active Active Active Active Active Active Active Active Active Active Active Data Byte 0 Down Software 0 0 0 0 0 0 00 Bit Control 1 Default
Preliminary Information
5 4 3 2 1-0
Data Byte 1 7 6 5 4 3 2 1 0 Data Byte 2 7 6 5 4 3 2 1 0 Data Byte 3 7 6 5 4 3
8
40 43 44 7 13 12 11 10 8 26 25 -
SDRAM_F CPU1 CPU_F PCI_F PCI5 PCI4 PCI3 PCI2 PCI1 48 MHz 24MHz -
Reserved Reserved Reserved Test Mode Clock Output Disabled Reserved Clock Output Disabled Clock Output Disabled Reserved Clock Output Disabled Reserved Clock Output Disabled Clock Output Disabled Clock Output Disabled Clock Output Disabled Clock Output Disabled Reserved Reserved Clock Output Disabled Clock Output Disabled Reserved
0 0 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 1 1 0
PRODUCT SPECIFICATION
RC7144
Table 3. Data Bytes 0-7 Serial Configuration Map (Continued)
Affected Pin Bit(s) 2 1 0 7 6 5 4 3 2 1 0 Data Byte 5 7 6 5 4 3 2 1 0 Data Byte 6 7 6 5 4 3 2 1 0 Data Byte 7 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0 0 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0 0 0 0 0 0 0 0 47 46 2 IOAPIC REF1 REF0 Reserved Reserved Reserved Clock Output Disabled Reserved Reserved Clock Output Disabled Clock Output Disabled Low Low Low Active Active Active 0 0 0 1 0 0 1 1 Pin No. 21, 20, 18, 17 32, 31, 29, 28 38, 37, 35, 34 Pin Name SDRAM8:11 SDRAM4:7 SDRAM0:3 Control Function Clock Output Disabled Clock Output Disabled Clock Output Disabled Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0 Low Low Low Bit Control 1 Active Active Active Default 1 1 1 0 0 0 0
Data Byte 4
Preliminary Information
9
0 0 0 0
RC7144
PRODUCT SPECIFICATION
Table 4. Select Function for Data Byte 0, Bits 0:1
Input Conditions Data Byte 0 Function Normal Operation Spread Spectrum Tristate Bit 1 0 1 1 Bit 0 0 0 1 CPU NOTE 1 0.5% Hi-Z PC1 NOTE 1 0.5% Hi-Z Output Conditons IOAPIC REF0:1 14.318 M 14.318 M Hi-Z 48 MHz 48 M 48 M Hi-Z 24 MHz 24 M 24 M Hi-Z
Table 5. Frequency Selection Table Through I2C Programming
Input Conditons
Preliminary Information
Data Byte 0, Bit 3 = 1 Bit 2 FS3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 Bit 6 FS2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 Bit 5 FS1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 Bit 4 FS0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 CPU (MHz) 133.3 124 150 140 105 110 115 120 100 133.3 112 103 66.8 83.3 75 124 PCI (MHz) 33.3 31 37.5 35 35 36.7 38.3 40 33.3 44.43 37.3 34.3 33.4 41.7 37.5 41.3
Table 6. Test Mode
Function Normal Test Mode Input Condition Data Byte4 1 0 CPU Note 1 X1 PCI Note 1 CPU/2 or 3 REF, IOAPIC 14.318 X1 48MHz 48 X1/2 24MHz 24 X1/4
Note: 1. See table 5 for frequency selection.
10
PRODUCT SPECIFICATION
RC7144
Absolute Maximum Ratings
Symbol VDD, VIN TSTG TB TA ESDPROT Storage Temperature Ambient Temperature Operating Temperature Input ESD Protection Parameter Voltage on any pin with respect to ground Ratings -0.5 to 7.0 -65 to 150 -55 to 125 0 to 70 2 (min) Units V
oC oC o
C
kV
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability.
Electrical Characteristics--Common Parameters
TA = 0C to 70C; Supply Voltage 3.3V5% (unless otherwise stated) Symbol VIL VIH IIL IIH CIN COUT LIN VTH IDD IDDL TSTAB TCPU-PCI Clock Stabilization1 Skew1 Parameter Input Low Voltage Input High Voltage Input Low Current Input High Current Input Capacitance1 VIN=0; inputs with no pull-up resistors VIN=0; inputs with pull-up resistors VIN=VDD All except X1 and X2. X1 and X2 Pins. X2 unconnected. Output Capacitance1 Input Pin Inductance1 Crystal Input Threshold1 VDD=3.3V Freq=100M: CL max. on all outputs VDD=2.5V 0.5%; Freq-100M From VDD=3.3V to 1% Target VDDL=2.5V; VDD=3.3V; CPU VTH=1.25V, PCI VTH=1.5V 1.5 1.5 300 24 3 4 Supply Current 18 6 7 -5 Test Condition Min. VSS-0.3 2.0 -5 Typ. Max. 0.8 VDD+0.3 5 -25 -5 5 Units V V A A A pF pF pF nH V mA mA mS nS
Preliminary Information
Note: 1. Guaranteed by design, not subject to 100% production testing.
11
RC7144
PRODUCT SPECIFICATION
Electrical Characteristics--CPU Outputs
TA=0C to 70C; Supply Voltage VDD=3.3V5%; VDDL=2.5V5% (unless otherwise stated) Symbol VOL VOH IOL IOH TR TF DT TJIT TSK ZO Parameter Output Low Voltage Output High Voltage Output Low Current Output High Currents Rise Time Duty Jitter
1
Test Condition IOL=1 mA IOH=-1 mA VOL=1.2 V VOH=1.2 V 0.4 to 2.0 V: CL=20 pF 2.0 to 0.4 V; CL=20 pF VTH=1.25 V; CL=20 pF VTH=1.25 V; CL=20 pF VTH=1.25 V; CL=20 pF Impedance1
Min. 2.0 27 -101 0.4 0.4 45
Typ.
Max. 0.5 93 -25 1.6 1.6 55 200 175
Units V V mA mA nS nS % pS pS
Fall Time1 Cycle1 (Cycle-cycle)1
Preliminary Information
Skew1 AC Output
20
Note: 1. Guaranteed by design, not subject to 100% production testing.
Electrical Characteristics--IOAPIC Outputs
TA=0C to 70C; Supply Voltage VDD=3.3V5%; VDDL=2.5V5% (unless otherwise stated) Symbol VOL VOH IOL IOH TR TF DT TJIT ZO Parameter Output Low Voltage Output High Voltage Output Low Current Output High Currents Rise Fall Duty Time1 Cycle1 Time1 Test Condition IOL=1 mA IOH=-1 mA VOL=1.25 V VOH=1.2 V 0.4 to 2.0 V: CL=20 pF 2.0 to 0.4 V; CL=20 pF VTH=1.25 V; CL=20 pF VTH=1.25 V; CL=20 pF 15 2.0 27 -101 0.4 0.4 45 93 -25 1.6 1.6 55 500 Min. Typ. Max. 0.5 Units V V mA mA nS nS % pS
Jitter (Cycle-cycle)1 AC Output Impedance1
Note: 1. Guaranteed by design, not subject to 100% production testing.
12
PRODUCT SPECIFICATION
RC7144
Electrical Characteristics--PCI Outputs
TA=0C to 70C; Supply Voltage VDD=3.3V5%; VDDL=2.5V5% (unless otherwise stated) Symbol VOL VOH IOL IOH TR TF DT TJIT TSK ZO Parameter Output Low Voltage Output High Voltage Output Low Current Output High Currents Rise Time Duty Jitter
1
Test Condition IOL=1 mA IOH=-1 mA VOL=1.5 V VOH=1.5 V 0.4 to 2.4 V: CL=30 pF 2.4 to 0.4 V; CL=30 pF VTH=1.5 V; CL=30 pF VTH=1.5 V; CL=30 pF VTH=1.5 V; CL=30 pF Impedance1
Min. 2.4 26 -189 0.5 0.5 45
Typ.
Max. 0.5 139 -31 2.0 2.0 55 250 500
Units V V mA mA nS nS % pS
Fall Time1 Cycle1 (Cycle-cycle)1
Preliminary Information
Skew1 AC Output
pS
30
Note: 1. Guaranteed by design, not subject to 100% production testing.
Electrical Characteristics--REF Outputs
TA=0C to 70C; Supply Voltage VDD=3.3V5%; VDDL=2.5V5% (unless otherwise stated) Symbol VOL VOH IOL IOH TR TF DT TJIT ZO Parameter Output Low Voltage Output High Voltage Output Low Current Output High Currents Rise Fall Duty Time1 Cycle1 Time1 Test Condition IOL=1 mA IOH=-1 mA VOL=1.5 V VOH=1.5 V 0.4 to 2.4 V: CL=20 pF 2.4 to 0.4 V; CL=20 pF VTH=1.5 V; CL=20 pF VTH=1.5 V; CL=20 pF 30 2.4 25 -94 1 1 45 76 -27 4 4 55 500 Min. Typ. Max. 0.5 Units V V mA mA nS nS % pS
Jitter (Cycle-cycle)1 AC Output Impedance1
Note: 1. Guaranteed by design, not subject to 100% production testing.
13
RC7144
PRODUCT SPECIFICATION
Electrical Characteristics--48/24 MHz Outputs
TA=0C to 70C; Supply Voltage VDD=3.3V5%; VDDL=2.5V5% (unless otherwise stated) Symbol VOL VOH IOL IOH FACCU TR TF DT ZO Parameter Output Low Voltage Output High Voltage Output Low Current Output High Currents Frequency Accuracy Rise Time1 Fall Time1 Cycle1 Impedance1 Duty
1
Test Condition IOL=1 mA IOH=-1 mA VOL=1.5 V VOH=1.5 V 0.4 to 2.4 V: CL=20 pF 2.4 to 0.4 V; CL=20 pF VTH=1.5 V; CL=20 pF
Min. 2.4 25 -94 1 1 45
Typ.
Max. 0.5 76 -27 167 4.0 4.0 55
Units V V mA mA ppm nS nS %
Preliminary Information
AC Output
40
Note: 1. Guaranteed by design, not subject to 100% production testing.
Electrical Characteristics--SDRAM outputs
TA=0C to 70C; Supply Voltage VDD=3.3V5%; VDDL=2.5V5% (unless otherwise stated) Symbol VOL VOH IOL IOH TR TF DT TJIT TSK ZO Parameter Output Low Voltage Output High Voltage Output Low Current Output High Currents Rise Fall Duty Time1 Cycle1 Cycle)1 Time1 Test Condition IOL=1 mA IOH=-1 mA VOL=0.4 V VOH=2.0 V 0.4 to 2.4 V: CL=30 pF 2.4 to 0.4 V; CL=30 pF VTH=1.5 V; CL=30 pF VTH=1.5 V; CL=30 pF VTH=1.5 V; CL=30 pF Impedance1 40 0.5 0.5 45 2.4 53 -54 1.6 1.6 55 250 250 Min. Typ. Max. 0.5 Units V V mA mA nS nS % pS pS
Jitter (Cycle to Skew1 AC Output
Note: 1. Guaranteed by design, not subject to 100% production testing.
14
PRODUCT SPECIFICATION
RC7144
Mechanical Dimensions
48 pin SSOP
Symbol A A1 b c D E E1 e L N a ccc Inches Min. .095 .008 Max. .110 .016 Millimeters Min. 2.41 0.20 Max. 2.79 0.41 5 5 2, 4 2 3 6 Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 2. "D" and "E1" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5. "b" & "c" dimensions include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
.0135 .008 .005 .010 .620 .630 .395 .420 .291 .299 .025 BSC .020 .040 48 0 8 --.004
0.34 0.20 0.25 0.13 16.00 15.75 10.67 10.03 7.59 7.39 0.64 BSC 0.51 1.02 48 0 8 --0.13
Preliminary Information
E E1
1
D A e b A1 SEATING PLANE -CLEAD COPLANARITY ccc C c a L
15
RC7144
PRODUCT SPECIFICATION
Ordering Information
Product Number RC7144 Package 48 pin SSOP
Preliminary Information
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com 8/6/99 0.0m 009 Stock#DS30005057 (c) 1998 Fairchild Semiconductor Corporation
www.fairchildsemi.com
RC7310
High Speed Driver
Features
* High output slew rate (1.2 V/ns minimum) * Wide output voltage range (-3.0V to +8V), and up to 10 Vp-p swings * 250 MHz minimum operation for ECL swings * Wide input common mode range for ease of interface to ECL as well as TTL and CMOS * Output short-circuit protection with current limiter and thermal shutdown * 100 mA dynamic switching current drive * Absolute slew rate control * Low output voltage offset (30 mV typ.) and output offset drift (0.1 mV/C typ.) * Low input bias current (1 mA typ.) and current drift (40 nA/C typ.) for output level program voltage allows direct coupling to a DAC output * Available in 28-pin PLCC
Description
The RC7310 is a low cost High Speed Driver capable of over 250 MHz operation at ECL levels and greater than 1.2 V/ns slew rate for 5 Vp-p output. The driver offers programmable output levels between -3.0V and +8V and an output amplitude up to 10 Vp-p. It is therefore capable of driving any logic family such as ECL, TTL and CMOS. The high and low limits of the output swing are set through the program pins VH and VL, respectively. The transfer characteristic from the program pins to the output pin is unity gain with low offset (30 mV typical) and offset drift (0.1 mV/C typical). The VH and VL inputs have been buffered to operate with low bias currents (1.0 mA typical) allowing direct coupling to the output of a DAC. The RC7310 is normally driven by ECL levels. However, the input common mode range, -2V to +6V, is wide enough to accommodate TTL or CMOS input signals. When driven with a single ended signal the other input of the RC7310 must be tied to the appropriate threshold voltage. The RC7310 is specified at nominal power supply values of 10V and -5.2V, and commensurate output voltage swing limits of -3.0V and +8V.
Applications
* * * * * * Differential line driver/receiver Precision waveform generator Level translator Switch driver Laser driver CRT preamplifier
Block Diagram
VCC VEE SRCA SRCM VCCO
Refs & Temp Compensation VH VHC VIN+ VIN-
AbsoluteSlew Rate Control
Slew Rate Control Match OF
Buf
Offset Control and Switching
Output Buffer
VO (RC7311) RC7311T Only VOTERM (RC7311T)
VLC VL Gnd TST
Buf Temperature Sensing
VEEO
TS
65-7310-01
Rev. 1.0.0
RC7310
PRODUCT SPECIFICATION
Description (continued)
The supply rails may be raised by 2V to achieve an output high level (VOH) of +1 0V, or towered by 2V to achieve an output low level (VOL) of -5V. At all times there must be at least a 2V margin between the positive supply and the maxi-
mum value of VOH, and between the negative supply and the minimum value of VOL. The RC7310 is implemented using Fairchild Semiconductor's high performance precision Complementary Bipolar Process (CBiP).
Pin Assignments
CIM2 CIM1 OF VO GND NC NC
28 27
TST NC VCCO VCC VHC VLC SRCM
26
4
3
2
1
5 6 7 8 9 10 11 12 13 14 15 16 17 18
25 24 23 22 21 20 19
TS NC VEEO VEE NC NC VL
SRCA NC VIN- VIN+ GND NC VH
65-7310-02
Pin Definitions
Pin Name CIM1, CIM2 Pin Number 3, 4 Pin Function Description An optional 10,000 pF chip capacitor could be placed between CIM1 and CIM2 to improve impedance matching across different voltage swings. With this capacitor, output impedance stays more constant with changes in voltage swings. If not used, leave pins CIM1 and CIM2 open. Chip ground. These pins should be connected to the printed circuit board's ground plane at the pins. On chip filter to improve output waveform (optional). This pin connection is optional and should be left unconnected if not used. When used, the OF pin should be fed to the termination node that is directly connected to the DUT. Absolute slew rate control. By applying current at this pin, small changes in slew rate can be programmed with an external DAC. This control pin affects both positive and negative edge rates. If this slew rate control is not desired this pin should be left open. Slew rate control matching. By applying current at this pin, small changes in slew rate can be programmed with an external DAC. This control pin adjusts the match between positive and negative edges . If this slew rate control is not desired this pin should be left open. Active low output notifies thermal shutdown has occurred. In the event of a shortcircuit or other fault that causes the die temperature to rise between 115C and 160C, the thermal shutdown will activate. If the fault persists, the device will toggle back and forth between shutdown and normal operation at a frequency in the tens of Hertz. TS is an open collector output capable of driving two standard TTL loads. The TS pins of several drivers may be wired together and input to a latch to indicate an alarm condition. Pin used for factory testing the thermal characteristics of the device. The pin should be left unconnected or tied to GND.
GND OF
16, 28 2
SRCA
12
SRCM
11
TS
25
TST
5
2
PRODUCT SPECIFICATION
RC7310
Pin Definitions (continued)
Pin Name VCC Pin Number 8 Pin Function Description Quiet positive supply. The nominal value is 10V 3%. For output high voltage levels (VOH) greater than the nominal value of +8V, VCC should be raised 2V above the maximum VOH value. Whenever VEE is lowered to provide margin at the output low level, VCC should also be lowered by the same amount. VCC should be bypassed to the ground plane with a 10,000 pF chip capacitor placed as close to the pin as possible. Positive supply for the output stage. This supply is brought out separately to minimize the supply noise generated when the output switches. VCCO should be bypassed to the ground plane with a 10,000 pF chip capacitor placed as close to the pin as possible and then immediately connected to VCC. Quiet negative supply. The nominal value is -5.2V to 5%. For output low voltage levels (VOL) less than 3V, VEE should be lowered 2V below the minimum VOL value. Whenever VCC is raised to provide margin at the output high level, VEE should be raised by the same amount. VEE should be bypassed to ground with a 10,000 pF chip capacitor placed as close to the pins as possible. Negative supply for the output stage. This supply is brought out separately to minimize the supply noise generated when the output switches. VEEO should be bypassed to the ground plane with a 10,000 pF chip capacitor placed as close to the pin as possible and then immediately connected to VEE. Analog program input that sets the output high level (VOH). The transfer characteristic from VH to VOH is nominally unity gain. Bypass for analog program input high, VH. VHC should be bypassed to the ground plane with a 1000 pF chip capacitor placed as close to the pin as possible. Differential digital inputs. The output will toggle between the two levels dictated by VH and VL as the differential signal is switched. Although these inputs will normally be driven by ECL signals, they have a wide enough common mode range that any one of the inputs may be driven by a TTL or CMOS signal provided that the other input is tied to the appropriate threshold voltage. Analog program input that sets the output low level (VOL). The transfer characteristic from VL to VOL is nominally unity gain. Bypass for analog program input low, VL. VLC should be bypassed to the ground plane with a 1000 pF chip capacitor placed as close to the pin as possible. Driver output of RC7310. The output impedance is 12.6W 1.5W. The output is usually back terminated in the characteristic impedance of the driven transmission line. For a 50W line, a 37.4W 1% or better resistor should be placed externally as close to the output pin as possible to minimize reflections and ringing. The resistor should also be able to dissipate 0.8W to sustain the short circuit current of the output. No connection.
VCCO
7
VEE
22
VEEO
23
VH VHC VIN+, VIN-
18 9 15, 14
VL VLC VO
19 10 1
NC
6, 13, 17, 20, 21, 24, 26, 27
3
RC7310
PRODUCT SPECIFICATION
Absolute Maximum Ratings1
Parameter Positive power supply, VCC Negative power supply, VEE Difference between VCC and VEE Input voltage at VIN+, VIN- Input voltage at VH, VL Differential input voltage, IVIN+ - VIN-I Difference between VH and VL, (IVH - VLI) Driver output voltage Output voltage at TS Duration of short-circuit to ground Operating temperature range Storage temperature range Lead temperature range (soldering 10 seconds) 0 -65 VCC VEE -13 +13 7 Indefinite 70 +125 300 C C C V VCC VEE VCC VEE -13 +13 6 13 V V V -12 +12 V Min. Max. 13 -8.2 16 Unit V V V V
Notes: 1. Absolute Maximum Ratings are those beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. If the device is subjected to the limits in the absolute maximum ratings for extended periods, its reliability may be impaired. The tables of Electrical Characteristics provide conditions for actual device operation.
4
PRODUCT SPECIFICATION
RC7310
Operating Conditions
Symbol TC VCC VEE VCC - VEE VOH, VOL Parameter Case operating temperature Positive supply voltage Negative supply voltage Difference between positive and negative supply Range for output high level and output low level Output amplitude Output back-termination resistor for RC7310 VEE+2 0.4 37.4
1
Min. 0 9.7 -5.45
Typ. 10.0 -5.2 15.2
Max. 70 10.3 -4.95 15.8 VCC-2 10.0
Unit C V V V V V W
IVOH - VOLI
RT
Note: 1. With air flow >300 lfpm.
DC Electrical Characteristics
VCC = 10V 3%, VEE = -5.2V 5%, TA = 25C (still air), no load, unless otherwise specified. Symbol VIN+, VIN- VID IIN+, IIN- VSRCA ISRCA %SLRMax %SLRMax VSRCM ISRCM %SLR VH Parameter Absolute Input Voltage Differential Input Range Bias Current Compliance Voltage Range Control Current Range %SLR Absolute Change %SLR Absolute Change Compliance Voltage Range Control Current Range Max % SLR Matching Change VH Range VCC = 10V, VEE = -5.2V VCC = 12V, VEE = -3.2V VCC = 8V, VEE = -7.2V VL VL Range VCC = 10V, VEE = -5.2V VCC = 12V, VEE = -3.2V VCC = 8V, VEE = -7.2V VA IH IL TCIH TCIL -1.0 +1.0 -3.0 -3.0 -1.0 -5.0 0.40 -1.0 -1.0 Vcom = -2.0 Vcom = -2.4 VH = +5V, VL= 0V 0.4 -0.5 30 +8.0 +10.0 +6.0 +5.5 +7.5 +3.5 10 -5.0 -5.0 40 40 Test Conditions Min. -2.0 Typ. Max. +6.0 ECL -100 -2.3 -1.0 -20 -40/+25 0.6 0.9 +0.5 -1.6 5.0 -250 -0.9 +1.0 Unit V V mA V mA % % V mA % V V V V V V V mA mA nA/C nA/C
Differential Inputs, VIN+, VIN-
IVIN+ - VIN-I
-2V VIN +6V VH = +5V, VL= 0V
0.4
Absolute SLR Control, SRCA
Matching SLR Control, SRCM
Voltage Program Inputs VH, VL
IVOH - VOLI
Bias Current @ VH Bias Current @ VL Max. Temperature Drift in IH Max. Temperature Drift in IL
Output Voltage Amplitude -1.0V VH +8V; VL = -3.0V -3V VL +5.5V; VH +8.0V VH = 7.0V; 25C TA 70C; (output not switching) VL = -2.0V; 25C TC 70C; (output not switching)
5
RC7310
PRODUCT SPECIFICATION
DC Electrical Characteristics (continued)
VCC = 10V 3%, VEE = -5.2V 5%, TA = 25C (still air), no load, unless otherwise specified. Symbol DIBDC Parameter Variation in IH, IL with Power Supply and DC Voltage at VH or VL VH,L BW Test Conditions VH = -1.0V to +8V; VL = -3V to +5.5V -3 dB point from VH,LBW to VOUT VCC = 10V, VEE = -5.2V VCC = 12V, VEE = -3.2V VCC = 8V, VEE = -7.2V VOL Range for Low Level Voltage VCC = 10V, VEE = -5.2V VCC = 12V, VEE = -3.2V VCC = 8V, VEE = -7.2V dVOH Offset to Output High Level dVOH = IVH - VOHI, VH = 0V, VL = -3V, -1.0V VH +8V, VL = -2V dVOL = IVL - VOLI, VH = 8V, VL = 0V, -3V VL +5.5V, VL = +7V -3V VL +5.5V, -1.0V VH +8V -3.0V VL +5.5V, VH = +8V, -1.0V VH +7.5V, VL = -3V 0V VL +5V, VH = +8V, 0V VH +5V, VL = -3V -3.0V VL +5.5V, VH = +8V, -1.0V VH +7.5V, VL = -3V ZOUT IAC IDC VOL ICL TS Other ICC IEE PSRVO PSRVSL TA Positive Supply Current Negative Supply Current Output Level to Power Supply Rejection Ratio Output Slew Rate to Power Supply Rejection Ratio Operating Temperature Range VCC; DVCC = 2.5% VEE; DVEE = 2.5% VCC; DVCC = 200mV VEE; DVEE = 200mV Still Air Air Flow > 300 lfpm 0 0 25 25 40 40 4 4 50 70 60 60 mA mA dB dB % % C C Output Impedance AC Current Drive DC Current Drive Output Low Level DC Current Limit Shutdown Die Temperature IOL = 4 mA 70 115 110 130 VO (RC7310) 70 50 0.5 130 160 -1.0 -0.3 -0.5 12.6 100 -1.0 +1.0 -3.0 -3.0 +1.0 -5.0 30 Min. -2.0 Typ. Max. +2.0 Unit mA
VH,LBW
50
kHz
Signal Output VO, VOTERM VOH Range for High Level Voltage +8.0 +10.0 +6.0 +5.5 +7.5 +3.5 100 V V V V V V mV
dVOL
Offset to Output Low Level
30
100
mV
VTC eG eL
Output Voltage Drift Gain Error Linearity Error
0.1
0.5
mV/C
+1.0 %VSET +0.3 %VSET +0.5 %VSET W mA mA V mA C
Thermal Shutdown Output (TS)
6
PRODUCT SPECIFICATION
RC7310
AC Electrical Characteristics
VCC = 10V 3%, VEE = -5.2V 5%, TA = 25C (still air) and the load is a 50W transmission line with 2.0 ns one-way delay, unless otherwise specified. The transmission line should be back-terminated in 50W (1%) using an extemal resistor. The measurement probe is a high impedance FET probe with capacitance no greater than 6 pF and resistance no smaller than 10 kW. Symbol SLR Parameter Slew Rate (SRCM and SRCA Adjusted) Slew Rate (No SRCM and SRCA Adjustment) Rise Time and Fall Time (SRCM and SRCA Adjusted) Test Conditions With probe only as load With probe and transmission line With probe only as load With probe and transmission line Load is Probe Only Amplitude = 0.8V (20% to 80%) 3V (10% to 90%) 5V (10% to 90%) 9V (10% to 90%) tR, tF Rise Time and Fall Time (No SRCM and SRCA Adjustment) Load is Probe Only Amplitude = 0.8V (20% to 80%) 3V (10% to 90%) 5V (10% to 90%) 9V (10% to 90%) f Toggle Rate Amplitude = 0.8V Amplitude = 5.0V Propagation Delay tPLH tPHL DtP DtPTC tPWMIN Low to High High to Low Matching ItPLH - tPHLI Temperature Coefficient Minimum Pulse Width VH - VL = 2.0V; Pulse Width at which amplitude drops by 50mV, measured between 50% points 2ns < PW < 98ns; f = 10 MHz; VOH = +0.4V; VOL = -0.4V 0.5V < IVOH - VOLI < 5V 0.5V < IVOH - VOLI < 5V 2.0 f = 10 MHz; VOH = +0.4V; VOL= -0.4V 1.6 1.6 150 2 2.0 2.0 175 ns ns ps ps/C ns 250 105 0.7 2.0 2.8 4.8 270 110 1.0 2.4 3.6 ns ns ns ns MHz MHz 0.6 1.7 2.4 4.0 0.8 2.0 2.9 4.8 ns ns ns ns Min. 1.2 1.1 1.0 1.0 Typ. 1.6 1.5 1.4 1.4 Max. Unit V/ns V/ns V/ns V/ns
VH - VL = 5V; measured between 20% and 80% points
SLR
VH - VL = 5V; measured between 20% and 80% points
tR, tF
DtPPW PS OS tS
Propagation Delay Variation with Pulse Width Preshoot Overshoot Output Setting Time
-75 15 mV + 3% of VA 50 mV + 4% of VA 5 10
+75
ps mV mV
IVOH - VOLI = 5V To within 3% of IVOH - VOLI To within 1% of IVOH - VOLI
ns ns
7
RC7310
PRODUCT SPECIFICATION
Notes:
8
PRODUCT SPECIFICATION
RC7310
Notes:
9
RC7310
PRODUCT SPECIFICATION
Notes:
10
PRODUCT SPECIFICATION
RC7310
Mechanical Dimensions
28-Lead PLCC
Inches Min. A A1 A2 B B1 D/E D1/E1 D3/E3 e J ND/NE N ccc Max. Millimeters Min. Max. Notes: Notes 1. All dimensions and tolerances conform to ANSI Y14.5M-1982 2. Corner and edge chamfer (J) = 45 3. Dimension D1 and E1 do not include mold protrusion. Allowable protrusion is .101" (.25mm)
Symbol
.165 .180 .090 .120 .020 -- .013 .021 .026 .032 .485 .495 .450 .456 .300 BSC .050 BSC .042 .048 7 28 -- .004
4.19 4.57 2.29 3.05 .51 -- .33 .53 .66 .81 12.32 12.57 11.43 11.58 7.62 BSC 1.27 BSC 1.07 1.22 7 28 -- 0.10
3
2
E E1 J
D
D1
D3/E3
B1 e J
A A1 A2 B -C- LEAD COPLANARITY
ccc C
11
RC7310
PRODUCT SPECIFICATION
Ordering Information
Part Number RC7310QA Package 28-Pin PLCC Operating Temperature Range 0C to +70C
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS30007310 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC7311
250MHz ATE Pin Electronics Driver
Features
* High output slew rate (1.8 V/ns typical) * Wide output voltage range (-3.0V to +8V), and up to 10 Vp-p swings * 250MHz minimum operation for ECL swings * Wide input common mode range for ease of interface to ECL as well as TTL and CMOS * Output short-circuit protection with current limiter and thermal shutdown * 100mA dynamic switching current drive * Absolute slew rate control * Available in 28-Lead PLCC * Low output voltage offset (30mV) and output offset drift (0.1 mV/C typ.) * Low input bias current (1 mA typical) and current drift (40 nA/C) for output level program allows direct coupling to a DAC output
Description
The RC7311 Pin Electronics Driver is an economical alternative to standard pin electronics drivers in applications that do not require three state capability in the driver. An example of such an application would be the large number of input address pins found in memory testers. The driver output levels are programmable between -3.0V and +8V to drive ECL, TTL and CMOS logic families. The peak to peak output swing can vary from values lower than 300mV to values as high as 10V. With toggle rates greater than 250MHz for ECL signals and typical slew rates of 2 V/ns for 5 Vp-p signal amplitudes, the RC7311 is comparable with the requirements of state-of-the-art testers. The high and low limits of the output swing are set through the program pins VH and VL, respectively. The transfer characteristic from the program pins to the output pin is unity gain with low offset (30mV) and offset drift (0.1 mV/C typical). The VH and VL inputs have been buffered to operate with low bias currents (1.0 mA typical) allowing direct coupling to the output of a DAC. The RC7311 is provided with high speed differential ECL inputs for ease of interface with the differential ECL outputs of a timing generator. The inputs have a wide voltage range, -2V to +6V, so that if required, an input may be driven by TTL or CMOS devices provided that the other input is tied to the appropriate threshold value.
Applications
* * * * * * * * ATE pin electronics driver Precision waveform generator Level translator Differential line receiver General purpose driver Switch driver Laser driver CRT preamplifier
Block Diagram
VCC VEE +SRC -SRC VCCO
Refs & Temp Compensation VHC VH Buf
Positive Slew Rate Control
Negative Slew Rate Control OF
Offset Control and Switching
CIM1 Output Buffer VO CIM2 VEEO
VIN+ VIN-
VL VLC Gnd TST
Buf Temperature Sensing
TS
65-7311-01
Rev. 1.0.0
RC7311
PRODUCT SPECIFICATION
Description (continued)
The RC7311 is specified at nominal power supply values of 10V and -5.2V, and commensurate output voltage swing limits of -3.0V and +8V. The supply rails may be raised by 2V to achieve an output high level (VOH) of +10V, or lowered by 2V to achieve an output low level (VOL) of -5V. At all
times there must be at least a 2V margin between the positive supply and the maximum value of VOH, and between the negative supply and the minimum value of VOL. The RC7311 is implemented using Fairchild Semiconductor's high performance precision complementary bipolar process.
Pin Assignments
28 27 26 4 3 2 1
TST NC VCCO VCC VHC VLC SRCM
CIM2 CIM1 OF VO GND NC NC
5 6 7 8 9 10 11 12 13 14 15 16 17 18
25 24 23 22 21 20 19
TS NC VEEO VEE NC NC VL
SRCA NC VIN- VIN+ GND NC VH
65-7311-02
Pin Definitions
Pin Name CIM1, CIM2 Pin Number 3, 4 Pin Function Description An optional 10,000 pF chip capacitor could be placed between CIM1 and CIM2 to improve impedance matching across different voltage swings. With this capacitor, output impedance stays more constant with changes in voltage swings. If not used, leave pins CIM1 and CIM2 open. Chip ground. These pins should be connected to the printed circuit board's ground plane at the pins. On chip filter to improve output waveform (optional). This pin connection is optional and should be left unconnected if not used. When used, the OF pin should be fed to the termination node that is directly connected to the DUT. Absolute slew rate control. By applying current at this pin, small changes in slew rate can be programmed with an external DAC. This control pin affects both positive and negative edge rates. If this slew rate control is not desired this pin should be left open. Slew rate control matching. By applying current at this pin, small changes in slew rate can be programmed with an external DAC. This control pin adjusts the match between positive and negative edges . If this slew rate control is not desired this pin should be left open. Active low output notifies thermal shutdown has occurred. In the event of a shortcircuit or other fault that causes the die temperature to rise between 115C and 160C, the thermal shutdown will activate. If the fault persists, the device will toggle back and forth between shutdown and normal operation at a frequency in the tens of Hertz. TS is an open collector output capable of driving two standard TTL loads. The TS pins of several drivers may be wired together and input to a latch to indicate an alarm condition. Pin used for factory testing the thermal characteristics of the device. The pin should be left unconnected or tied to GND.
GND OF
16, 28 2
SRCA
12
SRCM
11
TS
25
TST
5
2
PRODUCT SPECIFICATION
RC7311
Pin Definitions (continued)
Pin Name VCC Pin Number 8 Pin Function Description Quiet positive supply. The nominal value is 10V 3%. For output high voltage levels (VOH) greater than the nominal value of +8V, VCC should be raised 2V above the maximum VOH value. Whenever VEE is lowered to provide margin at the output low level, VCC should also be lowered by the same amount. VCC should be bypassed to the ground plane with a 10,000 pF chip capacitor placed as close to the pin as possible. Positive supply for the output stage. This supply is brought out separately to minimize the supply noise generated when the output switches. VCCO should be bypassed to the ground plane with a 10,000 pF chip capacitor placed as close to the pin as possible and then immediately connected to VCC. Quiet negative supply. The nominal value is -5.2V to 5%. For output low voltage levels (VOL) less than 3V, VEE should be lowered 2V below the minimum VOL value. Whenever VCC is raised to provide margin at the output high level, VEE should be raised by the same amount. VEE should be bypassed to ground with a 10,000 pF chip capacitor placed as close to the pins as possible. Negative supply for the output stage. This supply is brought out separately to minimize the supply noise generated when the output switches. VEEO should be bypassed to the ground plane with a 10,000 pF chip capacitor placed as close to the pin as possible and then immediately connected to VEE. Analog program input that sets the output high level (VOH). The transfer characteristic from VH to VOH is nominally unity gain. Bypass for analog program input high, VH. VHC should be bypassed to the ground plane with a 1000 pF chip capacitor placed as close to the pin as possible. Differential digital inputs. The output will toggle between the two levels dictated by VH and VL as the differential signal is switched. Although these inputs will normally be driven by ECL signals, they have a wide enough common mode range that any one of the inputs may be driven by a TTL or CMOS signal provided that the other input is tied to the appropriate threshold voltage. Analog program input that sets the output low level (VOL). The transfer characteristic from VL to VOL is nominally unity gain. Bypass for analog program input low, VL. VLC should be bypassed to the ground plane with a 1000 pF chip capacitor placed as close to the pin as possible. Driver output of RC7311. The output impedance is 12.6W 1.5W. The output is usually back terminated in the characteristic impedance of the driven transmission line. For a 50W line, a 37.4W 1% or better resistor should be placed externally as close to the output pin as possible to minimize reflections and ringing. The resistor should also be able to dissipate 0.8W to sustain the short circuit current of the output. No connection.
VCCO
7
VEE
22
VEEO
23
VH VHC VIN+, VIN-
18 9 15, 14
VL VLC VO
19 10 1
NC
6, 13, 17, 20, 21, 24, 26, 27
3
RC7311
PRODUCT SPECIFICATION
Absolute Maximum Ratings1
Parameter Positive power supply, VCC Negative power supply, VEE Difference between VCC and VEE Input voltage at VIN+, VIN- Input voltage at VH, VL Differential input voltage, IVIN+ - VIN-I Difference between VH and VL, (IVH - VLI) Driver output voltage Output voltage at TS Duration of short-circuit to ground Operating temperature range Storage temperature range Lead temperature range (soldering 10 seconds) 0 -65 VCC VEE -13 +13 7 Indefinite 70 +125 300 C C C V VCC VEE VCC VEE -13 +13 6 13 V V V -12 +12 V Min. Max. 13 -8.2 16 Unit V V V V
Notes: 1. Absolute Maximum Ratings are those beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. If the device is subjected to the limits in the absolute maximum ratings for extended periods, its reliability may be impaired. The tables of Electrical Characteristics provide conditions for actual device operation.
Operating Conditions
Symbol TC VCC VEE VCC - VEE VOH, VOL Parameter Case operating temperature1 Positive supply voltage Negative supply voltage Difference between positive and negative supply Range for output high level and output low level Output amplitude Output back-termination resistor for RC7310 VEE+2 0.4 37.4 Min. 0 9.7 -5.45 10.0 -5.2 15.2 Typ. Max. 70 10.3 -4.95 15.8 VCC-2 10.0 Unit C V V V V V W
IVOH - VOLI
RT
Note: 1. With air flow >300 lfpm.
4
PRODUCT SPECIFICATION
RC7311
DC Electrical Characteristics
VCC = 10V 3%, VEE = -5.2V 5%, TA = 25C (still air), no load, unless otherwise specified. Symbol VIN+, VIN- VID IIN+, IIN- VSRCA ISRCA %SLRMax %SLRMax VSRCM ISRCM %SLR VH Parameter Absolute Input Voltage Differential Input Range Bias Current Compliance Voltage Range Control Current Range %SLR Absolute Change %SLR Absolute Change Compliance Voltage Range Control Current Range Max % SLR Matching Change VH Range VCC = 10V, VEE = -5.2V VCC = 12V, VEE = -3.2V VCC = 8V, VEE = -7.2V VL VL Range VCC = 10V, VEE = -5.2V VCC = 12V, VEE = -3.2V VCC = 8V, VEE = -7.2V VA IH IL TCIH TCIL DIBDC -1.0 +1.0 -3.0 -3.0 -1.0 -5.0 0.30 -1.0 -1.0 Vcom = -2.0 Vcom = -2.4 VH = +5V, VL= 0V 0.3 -0.5 30 +8.0 +10.0 +6.0 +5.5 +7.5 +3.5 10 -5.0 -5.0 40 40 -1.8 +1.8 Test Conditions Min. -2.0 Typ. Max. +6.0 ECL -100 -2.3 -1.5 -20 -40/+25 0.6 0.9 +0.5 -1.6 5.0 -250 -0.9 +1.5 Unit V V mA V mA % % V mA % V V V V V V V mA mA nA/C nA/C mA
Differential Inputs, VIN+, VIN-
IVIN+ - VIN-I
-2V VIN +6V VH = +5V, VL= 0V
0.4
Absolute SLR Control, SRCA
Matching SLR Control, SRCM
Voltage Program Inputs VH, VL
IVOH - VOLI
Bias Current @ VH Bias Current @ VL Max. Temperature Drift in IH Max. Temperature Drift in IL Variation in IH, IL with Power Supply and DC Voltage at VH or VL VH,L BW
Output Voltage Amplitude -1.0V VH +8V; VL = -3.0V -3V VL +5.5V; VH +8.0V VH = 7.0V; 25C TA 70C; (output not switching) VL = -2.0V; 25C TC 70C; (output not switching) VH = -1.0V to +8V; VL = -3V to +5.5V -3 dB point from VH,LBW to VOUT VCC = 10V, VEE = -5.2V VCC = 12V, VEE = -3.2V VCC = 8V, VEE = -7.2V
VH,LBW
50
kHz
Signal Output VO, VOTERM VOH Range for High Level Voltage -1.0 +1.0 -3.0 -3.0 +1.0 -5.0 30 +8.0 +10.0 +6.0 +5.5 +7.5 +3.5 50 V V V V V V mV
VOL
Range for Low Level Voltage
VCC = 10V, VEE = -5.2V VCC = 12V, VEE = -3.2V VCC = 8V, VEE = -7.2V
dVOH
Offset to Output High Level
dVOH = IVH - VOHI, VH = 0V, VL = -3V, -1.0V VH +8V, VL = -2V
5
RC7311
PRODUCT SPECIFICATION
DC Electrical Characteristics (continued)
VCC = 10V 3%, VEE = -5.2V 5%, TA = 25C (still air), no load, unless otherwise specified. Symbol dVOL Parameter Offset to Output Low Level Test Conditions dVOL = IVL - VOLI, VH = 8V, VL = 0V, -3V VL +5.5V, VL = +7V -3V VL +5.5V, -1.0V VH +8V -3.0V VL +5.5V, VH = +8V, -1.0V VH +7.5V, VL = -3V 0V VL +5V, VH = +8V, 0V VH +5V, VL = -3V -3.0V VL +5.5V, VH = +8V, -1.0V VH +7.5V, VL = -3V ZOUT IAC IDC VOL ICL TS Other ICC IEE PSRVO PSRVSL TA Positive Supply Current Negative Supply Current Output Level to Power Supply Rejection Ratio Output Slew Rate to Power Supply Rejection Ratio Operating Temperature Range VCC; DVCC = 2.5% VEE; DVEE = 2.5% VCC; DVCC = 200mV VEE; DVEE = 200mV Still Air Air Flow > 300 lfpm 0 0 25 25 40 40 4 4 50 70 60 60 mA mA dB dB % % C C Output Impedance AC Current Drive DC Current Drive Output Low Level DC Current Limit Shutdown Die Temperature IOL = 4 mA 70 115 110 130 VO (RC7311) 70 50 0.5 130 160 -1.0 -0.3 -0.5 12.6 100 Min. Typ. 30 Max. 50 Unit mV
VTC eG eL
Output Voltage Drift Gain Error Linearity Error
0.1
0.5
mV/C
+1.0 %VSET +0.3 %VSET +0.5 %VSET W mA mA V mA C
Thermal Shutdown Output (TS)
6
PRODUCT SPECIFICATION
RC7311
AC Electrical Characteristics
VCC = 10V 3%, VEE = -5.2V 5%, TA = 25C (still air) and the load is a 50W transmission line with 2.0 ns one-way delay, unless otherwise specified. The transmission line should be back-terminated in 50W (1%) using an extemal resistor. The measurement probe is a high impedance FET probe with capacitance no greater than 6 pF and resistance no smaller than 10 kW. Symbol SLR Parameter Slew Rate (SRCM and SRCA Adjusted) Slew Rate (No SRCM and SRCA Adjustment) Rise Time and Fall Time (SRCM and SRCA Adjusted) Test Conditions With probe only as load With probe and transmission line With probe only as load With probe and transmission line Load is Probe Only Amplitude = 0.8V (20% to 80%) Amplitude = 3V (10% to 90%) Amplitude = 5V (10% to 90%) Amplitude = 9V (10% to 90%) tR, tF Rise Time and Fall Time (No SRCM and SRCA Adjustment) Load is Probe Only Amplitude = 0.8V (20% to 80%) Amplitude = 3V (10% to 90%) Amplitude = 5V (10% to 90%) Amplitude = 9V (10% to 90%) f Toggle Rate Amplitude = 0.8V Amplitude = 5.0V Propagation Delay tPLH tPHL DtP DtPTC tPWMIN Low to High High to Low Matching ItPLH - tPHLI Temperature Coefficient Minimum Pulse Width VH - VL = 2.0V; Pulse Width at which amplitude drops by 50mV, measured between 50% points 2ns < PW < 98ns; f = 10 MHz; VOH = +0.4V; VOL = -0.4V 0.5V < IVOH - VOLI < 5V 0.5V < IVOH - VOLI < 5V 2.0 f = 10 MHz; VOH = +0.4V; VOL= -0.4V 1.6 1.6 150 2 1.9 1.9 ns ns ps ps/C ns 250 105 0.7 1.8 2.6 4.5 270 110 0.9 2.2 3.2 5.2 ns ns ns ns MHz MHz 0.60 1.7 2.4 4.0 0.5 1.9 2.8 4.5 ns ns ns ns Min. 1.6 1.5 1.4 1.35 Typ. 1.8 1.7 1.6 1.5 Max. Unit V/ns V/ns V/ns V/ns
VH - VL = 5V; measured between 20% and 80% points
SLR
VH - VL = 5V; measured between 20% and 80% points
tR, tF
DtPPW PS OS tS
Propagation Delay Variation with Pulse Width Preshoot Overshoot Output Setting Time
-75
+75 15 mV + 3% of VA 50 mV + 4% of VA 5 10
ps mV mV
IVOH - VOLI = 5V To within 3% of IVOH - VOLI To within 1% of IVOH - VOLI
ns ns
7
RC7311
PRODUCT SPECIFICATION
Notes:
8
PRODUCT SPECIFICATION
RC7311
Notes:
9
RC7311
PRODUCT SPECIFICATION
Notes:
10
PRODUCT SPECIFICATION
RC7311
Mechanical Dimensions
28-Lead PLCC
Inches Min. A A1 A2 B B1 D/E D1/E1 D3/E3 e J ND/NE N ccc Max. Millimeters Min. Max. Notes: Notes 1. All dimensions and tolerances conform to ANSI Y14.5M-1982 2. Corner and edge chamfer (J) = 45 3. Dimension D1 and E1 do not include mold protrusion. Allowable protrusion is .101" (.25mm)
Symbol
.165 .180 .090 .120 .020 -- .013 .021 .026 .032 .485 .495 .450 .456 .300 BSC .050 BSC .042 .048 7 28 -- .004
4.19 4.57 2.29 3.05 .51 -- .33 .53 .66 .81 12.32 12.57 11.43 11.58 7.62 BSC 1.27 BSC 1.07 1.22 7 28 -- 0.10
3
2
E E1 J
D
D1
D3/E3
B1 e J
A A1 A2 B -C- LEAD COPLANARITY
ccc C
11
RC7311
PRODUCT SPECIFICATION
Ordering Information
Part Number RC7311QA Package 28-Pin PLCC Operating Temperature Range 0C to +70C
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS30007311 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC7315
Three-State ATE Pin Electronics Driver
Features
* High output slew rate (1.8 V/ns typical) * Wide output voltage range (-2.5V to +7V), and up to 9.5 Vp-p swings * Three-state/high impedance output * High repetition rate (250 MHz for ECL swings) * Low output offset (20 mV typical) and output offset drift (0.1 mV/C typical). * Low leakage (10 nA typical) and low output capacitance (3 pF typical) in high impedance inhibit mode * High speed differential inputs with wide common mode range for ease of interface to ECL as well as TTL and CMOS levels * Output short circuit protection (Safe Operating Area protection with current limiting and thermal shutdown) * 100 mA typical dynamic current drive capability * Absolute slew rate control * Available in 28-pin PLCC * Packaged parts available in unterminated configurations
Description
The RC7315 Pin Electronics Driver is designed for use in all high speed ATE systems which require pin drivers with three state capability and high slew rates. The RC7315 has the ability to drive a 50W transmission line of up to 2 feet in length with a slew rate of 1.8 V/ns and repetition rate of over 250 MHz for ECL output levels. These features, combined with a maximum output swing of 9.5 Vp-p over the range of -2.5V to +7V, provide this circuit with the ability to test TTL, CMOS, ECL and GaAs devices. The high and low limits of the output swing are set through the program pins VH and VL, respectively. The transfer characteristic from the program pins to the output pin is unity gain with very low offset drift. The VH and VL inputs have been buffered to operate with low bias currents (1 mA typical) allowing direct coupling to the output of a DAC. When the RC7315 is used on an I/O pin, it may be forced into the high impedance state through the INH+ and INHdifferential inputs. In the high impedance state, excellent isolation is provided between the output of the disabled driver and the pin by virtue of low driver output capacitance (3.0 pF typical) and low output leakage (10 nA typical). The RC7315 is provided with high speed differential ECL inputs for ease of interface with the differential ECL outputs of a timing generator. The inputs have a voltage range of -2V to +6V, so that if required, an input may be driven by TTL or CMOS devices provided that the other input is fed to the appropriate threshold value. The RC7315 is implemented using Fairchild Semiconductor's high frequency complementary bipolar process.
Applications
* * * * * * * ATE pin electronics driver Precision waveform generator Level translator Differential line receiver General purpose driver Laser driver CRT preamplifier
Block Diagram
RC7315 VH Buf Feedback Circuit Offset Control and Switching Slew Rate Control Output Buffer Temperature Sensing Buf Driver Inhibit Circuit VO VCCO VEEO TS Refs & Temp Compensation VCC VEE GND +VSRC -VSRC
VIN+ VIN- CVOL VL INH+ INH-
Rev. 1.1.0
RC7315
PRODUCT SPECIFICATION
Pin Assignments
VEE SRCM VCC GND NC NC VEE
432 1 28 27 26 25 24 23 22 21 20 19
VEE VOUT SRCA NC VCCO VEEO VEE
5 6 7 8 9 10 11
28-Pin PLCC (Top View)
VEE INH+ INHVIN+ VINCVOH VEE
12 13 14 15 16 17 18
Pin Description
Name CVOL, CVOH GND INH+ INHPin Number 17 Function Bypass capacitor for VOH and VOL respectively. Pins CVOL and CVOH should be bypassed to the ground plane with a 1,000 pF chip capacitor placed as close to the pin as possible. Chip ground. Should be connected to the printed circuit board's ground plane at the pin. Differential digital inputs. When INH is true (i.e. INH+ > INH-) the driver is forced into the high impedance state. Although these inputs are normally driven by ECL signals, they have a wide enough common mode range that any one of the inputs may be driven by a TTL or CMOS signal provided that the other input is tied to the appropriate threshold voltage. Slew rate control for both edges. Slew rate of both rising and falling edges decreases as the control current is changed from 0 mA to -0.5 mA. SRC can be programmed with a current DAC or set to a fixed value using a resistor. Increases the speed of the falling edge to match the rising edge. Active low output notifies thermal shutdown has occurred. In the event of a short circuit or other fault that causes the die temperature to become excessively large, the thermal shutdown will kick in at a die temperature between 115C and 160C. If the fault persists, the device will toggle back and forth between shutdown and normal operation at a frequency in the tens of Hertz. TS is an open collector output capable of driving two standard TTL loads. The TS pins of several drivers may be wire-ORed together and input to a latch to indicate an alarm condition. Quiet positive supply. The nominal value is 10V 3%. For output high voltage levels (VOH) greater than the nominal value of +7V, VCC should be raised 3V above the maximum value of VOH. Whenever VEE is lowered to provide margin at the output low level, VCC should also be lowered by the same amount. VCC should be bypassed to ground with a 10,000 pF chip capacitor placed as close to the pins as possible. Positive supply for the RC7315 output stage. This supply is brought out separately to minimize the supply noise generated when the output switches. VCCO should be bypassed to the ground plane with a 10,000 pF chip capacitor placed as close to the pin as possible and then immediately connected to VCC. Quiet negative supply. The nominal value is -5.2V 5%. For output low voltage levels (VOL) less than the nominal value of -2.2V, VEE should be lowered 3V below the minimum value of VOL. Whenever VCC is raised to provide margin at the output high level, VEE should also be raised by the same amount. VEE should be bypassed to ground with a 10,000 pF chip capacitor placed as close to the pins as possible.
1 23, 24
SRCA
7
SRCM TS
3 15
VCC
2
VCCO
9
VEE
4, 5, 11, 12, 18, 19, 25, 26
2
VEE VL NC TS VH CVOL VEE
PRODUCT SPECIFICATION
RC7315
Pin Descriptions (continued)
Name VEEO Pin Number 10 Function Negative supply for the RC7315 output stage. This supply is brought out separately to minimize the supply noise generated when the output switches. VEEO should be bypassed to the ground plane with a 10,000 pF chip capacitor placed as close to the pin as possible and then immediately connected to VEE. Analog program input that sets the output high level (VOH). The transfer characteristic from VH to VOH is nominally unity gain. Differential digital inputs. The output will toggle between the two levels dictated by VH and VL as the differential signal is switched. Although these inputs are normally driven by ECL signals, they have a wide enough common mode range that any one of the inputs may be driven by a TTL or CMOS signal provided that the other input is tied to the appropriate threshold voltage. Analog program input that sets the output low level (VOL). The transfer characteristic from VLto VOL is nominally unity gain. Driver output on RC7315. The output impedance is 8W 2W. The output is usually back terminated in the characteristic impedance of the transmission line it drives. For a 50W line, a 40W 1% resistor should be placed externally as close to the output pin as possible to minimize reflections and ringing. The resistor should also be able to dissipate 0.8W to sustain the short circuit current of the output. 8, 14, 27, 28 No connection.
VH VIN+, VIN-
16 21, 22
VL VO
13
NC
Absolute Maximum Ratings1
Parameter Positive power supply, VCC Negative power supply, VEE Difference between VCC and VEE Input voltage at VIN+, VIN-, INH+, and INHInput Voltage at VH, VL Differential input voltage, cVIN+ - VIN- c, cVINH+ - VINH- c Difference between VH & VL (cVH - VL c) Input voltage at SRCA Slew rate control current Driver Output Voltage Output voltage at TS Duration of short-circuit to ground Operating temperature range Storage temperature range Lead temperature range (Soldering 10 seconds) Min. -8.2 VCC-12 VCC-13 17 VEE+12 VEE+13 6 11 +7 VEE+13 5 Indefinite 70 +125 300 Max. 13 Units V V V V V V V V mA V V C C C
-3 -2.0 VCC-13
0 -65
Notes: 1. "Absolute maximum ratings" are those beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. If the device is subjected to the limits in the absolute maximum ratings for extended periods, its reliability may be impaired. The tables of Electrical Characteristics provide conditions for actual device operation.
3
PRODUCT SPECIFICATION
RC7315
Recommended Operating Conditions
Symbol TC VCC VEE VCC-VEE VOH, VOL VOH-VOL Parameters Case operating temperature Positive supply voltage Negative supply voltage Difference between positive and negative supply Range for output high level and output low level Output amplitude -2.0 0.1 9.7 -5.45 Min. Typ. 25 10.0 -5.2 15.2 10.3 -4.95 15.8 7.0 10.0 Max. Units C C V V V V
DC Electrical Characteristics
VCC = 10V 3%, VEE = -5.2V 5%, TA = 25C (still air) and the load is a 50W transmission line with 2.0 ns one-way delay, unless otherwise specified. The transmission line is back-terminated in 50W (5%) using an external resistor. Symbol VIN+, VINVINH+, VINHVID VDINH IIN+, IINIINH+, IINHVSRCA ISRCA VSRCM ISRCM VH Parameters Absolute Voltage @ Data Inputs Absolute Voltage @ Inhibit Inputs INH+, INHDifferential Input Range Differential Inhibit Input Range Input Bias Current @ Data Inputs Input Bias Current @ Inhibit Inputs Compliance Voltage Range Control Current Range Compliance Voltage Range Control Current Range VH Range VCC = 10V; VEE = -5.2V VCC = 12V; VEE = -3.2V VCC = 8V; VEE = -7.2V VL VL Range VCC = 10V; VEE = -5.2V VCC = 12V; VEE = -3.2V VCC = 8V; VEE = -7.2V IH IL TCIH TCIL VH,LBW Bias Current @ VH Bias Current @ VL Temperature Drift in IH Temperature Drift in IL -3 dB bandwidth from VH or VL to the output -1V VH +7V; VL = -2.0V -2V VL +5V; VH = 6.0V VH = 7.0V; 25C TC 70C output not switching VL= -2.0V; 25C TC 70C output not switching -1V VH +7V; -2V VL +6V; VH-VL= 2.0V 50 cVIN+ - VIN- c cVINH+ - VINH c -2V VIN+, VIN- +6V -2V VINH+, VINH- +5V -2.0 -0.5 -2.0 -0.5 -2.0 0 -4.0 -2.5 -0.5 -4.5 -1 -1 0.1 0.1 Test Conditions Min. -2.0 -2.0 0.4 0.4 ECL ECL -100 -100 +2.0 +0.5 +2.0 +0.5 +7.0 +9.0 +5.0 +6.0 +8.0 +4.0 Typ. Max. Units +6.0 +6.0 5.0 5.0 V V V V mA mA V V V V V V V V V V mA mA mA/C mA/C kHz
Differential Inputs VIN+, VIN-, VINH+, VINH-
Absolute Slew Rate Control lnput SRCA
Matching Slew Rate Control lnput SRCM
Voltage Program Inputs VH, VL
4
RC7315
PRODUCT SPECIFICATION
DC Electrical Characteristics (continued)
Symbol VO Parameters Output Voltage Range Test Conditions VCC = 10V; VEE = -5.2V VCC = 12V; VEE = -3.2V VCC = 8V; VEE = -7.2V VA dVOH dVOL VTC eG eL ZOUT IZL IDC IAC ICL VTS TTS Other VS MAX VCC VEE ICC IEE PSRVO PSRVSL Maximum Rail to Rail Supply Voltage Positive Supply Negative Supply Positive Supply Current Negative Supply Current Output Level Power Supply Rejection Ratio Output Slew Rate Power Supply Rejection Ratio @ VCC Rejection Ratio @ VEE TA Operating Temperature Range VCC; DVCC = 2.5% VEE; DVEE = 2.5% VH = 5V and VL = 0V Still Air Air Flow > 300 lfpm DVCC = 200 mV DVEE = 200 mV 0 0 4 4 25 25 40 70 % C C 40 40 VCC - VEE 16 +8.0 +10.0 +12.0 -7.2 -5.2 85 90 -3.2 V V V mA mA dB dB Amplitude Offset to Output High Level Offset to Output Low Level Output Voltage Drift Gain Error Linearity Error Output Impedance IOUT 50 mA Output Leakage Current in Inhibit Mode DC Current Drive AC Current Drive Short Circuit Current Limit TS Flag Output Level Shutdown Die Temperature lOL = 4 mA 145 IVOH - VOLI VH = 0, no load; VL = -2V dVOH = IVH - VOHI VH = 0, no load; VH = +7V dVOL = IVL - VOLI -1V VOH +7V; -2V VOL +6V; -1V VOH +7V; -2V VOL +6V -2V VOUTPUT +7 VO -2.0V VO +7V 50 70 100 145 0.5 0.1 0.1 1 1 0.7 8 0.5 2
%VSET
Min. -2.5 -0.5 -4.5 0.3
Typ.
Max. Units +7.0 +9.0 +5.0 9.5 V V V V mV mV mV/C 2
%VSET
Signal Output VO, VOTERM
30 30
W mA mA mA mA V C
Thermal Shutdown Output (TS)
5
PRODUCT SPECIFICATION
RC7315
AC Electrical Characteristics
VCC = 10V 3%, VEE = -5.2V 5%, TA = 25C (still air) and the load is a 50W transmission line with 2.0 ns one-way delay, unless otherwise specified. The transmission line is back-terminated in 50W (5%) using an external resistor. The measurement probe is a high impedance FET probe with capacitance no greater than 3 pF and resistance no smaller than 10 kW. Symbol SLR Parameters Slew Rate (Slew rate not adjusted) Test Conditions VH - VL = 5V; Measured between 20% and 80% points. With probe only as load With probe and transmission line Load is Probe Only; VA = 1V (20% to 80%) VA = 3V (10% to 90%) VA = 5V (10% to 90%) Amplitude = 0.8 Vp-p Amplitude = 5.0 Vp-p f = 10 MHz; VOH = +0.4V; VOL = -0.4V f = 10 MHz; VOH = +0.4V; VOL = -0.4V ItPLH - tPHLI Min. Typ. Max. Units
1.3 1.2
1.8 1.7 0.6 1.6 2.5
V/ns V/ns ns ns ns MHz MHz ns ns ps ps/C ns
tR, tF
Rise Time, and Fall Time (Slew rate not adjusted) Toggle Rate Low to High Propagation Delay High to Low Propagation Delay Propagation Delay Match Propagation Delay Temperature Coefficient Minimum Pulse Width
f tPLH tPHL DtP tPTC tPWmin
250 125 1.6 1.4 200 2 2.0
DtPPW
Propagation Delay Variation with Pulse Width Preshoot
VH - VL - 2.0V; pulsewidth at which amplitude drops by 50 mV, measured between 50% points. 2 ns < PW < 98 ns; f = 10 MHz; VOH = +0.4V; VOL = -0.4V 0.5V < VA < 5.0V
75
ps
tPS
tOS
Overshoot
0.5V < VA < 5.0V
15mV + 3% of VA 50mV + 4% of VA 8 10 2.9 2.9 2.9 2.9 3 ns ns ns ns ns ns pF
tS
Output Settling Time
tPHZ tPLZ tPZH tPZL CZ
Propagation Delay from Logic High to Inhibit Mode Propagation Delay from Logic Low to Inhibit Mode Propagation Delay from Inhibit Mode from Logic High Propagation Delay from Inhibit Mode to Logic Low Output capacitance in Inhibit Mode
VA < 5V; To within 3% of VA To within 1% of VA VOH = 1V; VOL = -1V Load = 100W // 15pF Propagation delay is measured to the point at which voltage has changed by 200 mV.
6
RC7315
PRODUCT SPECIFICATION
Mechanical Dimensions -- 28-pin PLCC
Symbol A A1 A2 B B1 D/E D1/E1 D3/E3 e J ND/NE N ccc Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. All dimensions and tolerances conform to ANSI Y14.5M-1982 2. Corner and edge chamfer (J) = 45 3. Dimension D1 and E1 do not include mold protrusion. Allowable protrusion is .101" (.25mm)
.165 .180 .090 .120 .020 -- .013 .021 .026 .032 .485 .495 .450 .456 .300 BSC .050 BSC .042 .048 7 28 -- .004
4.19 4.57 2.29 3.05 .51 -- .33 .53 .66 .81 12.32 12.57 11.43 11.58 7.62 BSC 1.27 BSC 1.07 1.22 7 28 -- 0.10
3
2
E E1 J
D
D1
D3/E3
B1 e J
A A1 A2 B -C- LEAD COPLANARITY
ccc C
7
RC7315
PRODUCT SPECIFICATION
Ordering Information
Part Number RC7315QF Package 28-pin PLCC Operating Temperature Range 0C to +70C
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS30007315 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC7316
Three-State ATE Pin Electronics Driver
Features
* High output slew rate (3.2 V/ns) typical driving coax * Wide output voltage range (-2.0V to +7V), and up to 9 Vp-p swings * Three-state/high impedance output * High repetition rate (550 MHz for ECL swings) * Low output offset (40 mV typical) and output offset drift (0.1 mV/C typical * Low leakage (10 nA typical) and low output capacitance (3.0 pF typical) in high impedance inhibit mode * 100 mA typical dynamic current drive capability * High speed differential inputs with wide common mode range for ease of interface to ECL as well as TTL and CMOS levels * Output short circuit protection (Safe Operating Area protection with current limiting and thermal shutdown) * Available in 16 Lead Hybrid Flatpack * RC7316TEL is pin-for-pin compatible with AD1321, AD1322, and AD1324
Description
The RC7316 Pin Electronics Driver is designed for use in ultra high speed ATE systems which require pin drivers with three state capability and high slew rates. The RC7316 has the ability to drive a 50W transmission line of up to 2 feet in length with a slew rate of 3.2 V/ns and repetition rate of over 550 MHz for ECL output levels. These features, combined with a maximum output swing of 9.5 Vp-p over the range of -3.0V to +7V, provide this circuit with the ability to test TTL, CMOS, ECL and GaAs devices. The high and low limits of the output swing are set through the program pins VH and VL, respectively. The transfer characteristic from the program pins to the output pin is unity gain with very low offset drift. The VH and VL inputs have been buffered to operate with low bias currents (1 mA typical) allowing direct coupling to the output of a DAC. When the RC7316 is used on an I/O pin, it may be forced into the high impedance state through the INH+ and INHdifferential inputs. In the high impedance state, excellent isolation is provided between the output of the disabled driver and the pin by virtue of low driver output capacitance (3.0 pF typical) and low output leakage (10 nA typical). The RC7316 is provided with high speed differential ECL inputs for ease of interface with the differential ECL outputs of a timing generator. The inputs have a voltage range of -2V to +6V, so that if required, an input may be driven by TTL or CMOS devices provided that the other input is fed to the appropriate threshold value.
Applications
* * * * * * * ATE pin electronics driver Precision waveform generator Level translator Differential line receiver General purpose driver Laser driver CRT preamplifier
Block Diagram
VH CVOH VIN+ VIN- CVOL VL INH+ INH- RC7316 Buf Driver Inhibit Circuit Offset Control and Switching Buf Feedback Circuit Slew Rate Control Output Buffer Temperature Sensing TS Refs & Temp Compensation
65-7316-01
GND +SRC -SRC VOTERM
VCC VEE
Rev 1.0.0
RC7316
PRODUCT SPECIFICATION
Description (continued)
The pin driver is available in 50W series terminated RC7316 (TEL) configurations. The RC7316TEL is pin-for-pin compatible with Analog Devices' AD1321, AD1322 and AD1324 drivers. The RC7316 is implemented using Fairchild Semiconductor's high frequency BiCMOS process.
Pin Assignments
GND -SRC VOTERM +SRC CVOH CVOL VL TS
1 2 3 4 5 6 7 8 16
RC7316TEL 16-Lead Hybrid Flatpack (Top View)
15 14 13 12 11 10 9
VCC VEE INH+ INHVIN+ VIN- VH GND
65-7316-02
Pin Descriptions
Pin Name CVOL, CVOH Pin Number 6, 5 Pin Function Description Bypass capacitor for VOH and VOL respectively. Pins CVOL and CVOH should be bypassed to the ground plane with a 1,000 pF chip capacitor placed as close to the pin as possible. Chip ground. Should be connected to the printed circuit board's ground plane at the pin. Differential digital inputs. When INH is true (i.e. INH+ > INH-) the driver is forced into the high impedance state. Although these inputs are normally driven by ECL signals, they have a wide enough common mode range that any one of the inputs may be driven by a TTL or CMOS signal provided that the other input is tied to the appropriate threshold voltage. Slew rate control for the positive edge. Slew rate of the positive edge changes as the control voltage is changed from -2.0V to +2.0V. +SRC can also be programmed with a current DAC or set to a fixed value using a resistor. Optionally, pin 4 can be NC. (No Connection) Slew Rate Control for the negative edge. Slew rate of the negative edge changes as the control voltage is changed from -2.0V to +2.0V. -SRC can also be programmed with a current DAC or set to a fixed value using a resistor. Optionally, pin 2 can be NC. (No Connection) Active low output notifies thermal shutdown has occurred. In the event of a short circuit or other fault that causes the die temperature to become excessively large, the thermal shutdown will kick in at a die temperature between 115C and 160C. If the fault persists, the device will toggle back and forth between shutdown and normal operation at a frequency in the tens of Hertz. TS is an open collector output capable of driving two standard TTL loads. The TS pins of several drivers may be wire-ORed together and input to a latch to indicate an alarm condition. Optionally, pin 8 can be NC. Quiet positive supply. The nominal value is 10V 3%. For output high voltage levels (VOH) greater than the nominal value of +7V, VCC should be raised 3V above the maximum value of VOH. Whenever VEE is lowered to provide margin at the output low level, VCC should also be lowered by the same amount. VCC should be bypassed to ground with a 10,000 pF chip capacitor placed as close to the pins as possible.
GND INH+, INH-
1, 9 13, 14
+SRC
4
-SRC
2
TS
8
VCC
16
2
PRODUCT SPECIFICATION
RC7316
Pin Descriptions (continued)
Pin Name VCCO Pin Number Pin Function Description Positive supply for the RC7316 output stage. This supply is brought out separately to minimize the supply noise generated when the output switches. VCCO should be bypassed to the ground plane with a 10,000 pF chip capacitor placed as close to the pin as possible and then immediately connected to VCC. 15 Quiet negative supply. The nominal value is -5.2V 5%. For output low voltage levels (VOL) less than the nominal value of -2.5V, VEE should be lowered 3V below the minimum value of VOL. Whenever VCC is raised to provide margin at the output high level, VEE should also be raised by the same amount. VEE should be bypassed to ground with a 10,000 pF chip capacitor placed as close to the pins as possible. Negative supply for the RC7316 output stage. This supply is brought out separately to minimize the supply noise generated when the output switches. VEEO should be bypassed to the ground plane with a 10,000 pF chip capacitor placed as close to the pin as possible and then immediately connected to VEE. 10 11,12 Analog program input that sets the output high level (VOH) The transfer characteristic from VH to VOH is nominally unity gain. Differential digital inputs. The output will toggle between the two levels dictated by VH and VL as the differential signal is switched. Although these inputs are normally driven by ECL signals, they have a wide enough common mode range that any one of the inputs may be driven by a TTL or CMOS signal provided that the other input is tied to the appropriate threshold voltage. Analog program input that sets the output low level (VOL). The transfer characteristic from VLto VOL is nominally unity gain. Driver output on RC7316. The output impedance is 10W 2W. The output is usually back terminated in the characteristic impedance of the transmission line it drives. For a 50W line, a 40W 1% resistor should be placed externally as close to the output pin as possible to minimize reflections and ringing. The resistor should also be able to dissipate 0.8W to sustain the short circuit current of the output.
VEE
VEEO
VH VIN+, VIN-
VL VO
7
3
RC7316
PRODUCT SPECIFICATION
Absolute Maximum Ratings1
Parameter Positive power supply, VCC Negative power supply, VEE Difference between VCC and VEE Input voltage at VIN+, VIN-, INH+, INHInput Voltage at VH, VL Differential input voltage, u VIN+-VIN- u, u VINH+ - VINH- u Difference between VH & VL (uVH - VLu) Input voltage at +SRC, -SRC Slew rate control current Driver Output Voltage Output voltage at TS Duration of short-circuit to ground Operating temperature range Storage temperature range Lead temperature range (Soldering 10 seconds) 0 -65 -3 -2.0 VCC-13 VEE+13 5 Indefinite 70 +125 300 C C C VCC-12 VCC-13 -8.2 16 VEE+12 VEE+13 6 11 +7 Min. Max. 13 Units V V V V V V V V mA V V
Notes: 1. "Absolute maximum ratings" are those beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. If the device is subjected to the limits in the absolute maximum ratings for extended periods, its reliability may be impaired. The tables of Electrical Characteristics provide conditions for actual device operation.
Recommended Operating Conditions
Symbol TC VCC VEE VCC-VEE VOH, VOL VOH-VOL RT Parameters Case operating temperature Positive supply voltage Negative supply voltage Difference between positive and negative supply Range for output high level and output low level Output amplitude Output back-termination resistor -3.0 0.1 41 Min. 0 9.7 -5.45 Typ. 25 10.0 -5.2 15.2 Max. +70 10.3 -4.95 15.8 7.0 9.5 Units C C V V V V
4
PRODUCT SPECIFICATION
RC7316
DC Electrical Characteristics
VCC = 10V 3%, VEE = -5.2V 5%, TA = 25C (flow 300 Lfm) and the load is a 50W transmission line with 2.0 ns one-way delay, unless otherwise specified. The transmission line is back-terminated in 50W (5%) using an external resistor (RC7316). Symbol VIN+, VINVINH+ VINHVID VDINH IIN+, IINIINH+, IINHVH Parameters Absolute Voltage @ Data Inputs Absolute Voltage @ Inhibit Inputs INH+, INHDifferential Input Range Differential Inhibit Input Range Input Bias Current @ Data Inputs Input Bias Current @ Inhibit Inputs VH Range uVIN+ - VIN-u uVINH+ - VINHu -2V VIN+, VIN- +6V -2V VINH+, VINH- +5V VCC = 10V; VEE = -5.2V VCC = 12V; VEE = -3.2V VCC = 8V; VEE = -7.2V VL VL Range VCC = 10V; VEE = -5.2V VCC = 12V; VEE = -3.2V VCC = 8V; VEE = -7.2V IH IL TCIH TCIL DIBDC VH,LBW Bias Current @ VH Bias Current @ VL Temperature Drift in IH Temperature Drift in IL Variation in IH, ILwith power supply and DC voltage at VH or VL -3 dB bandwidth from VH or VL to the output -1V VH +7V; VL = -3.0V -3V VL +5V; VH = 6.0V VH = 7.0V; 25C TC 70C output not switching VL= -3.0V; 25C TC 70C output not switching -1V VH +7V -2V VL + 6V -1V VH +7V; -2V VL +6V; VH-VL= 2.0V VCC = 10V; VEE = -5.2V VCC = 12V; VEE = -3.2V VCC = 8V; VEE = -7.2V VA dVOH dVOL VTC eG eL ZOUT Amplitude Offset to Output High Level Offset to Output Low Level Output Voltage Drift Gain Error Linearity Error Output Impedance uVOH - VOLu -1V VH +6V; VL = -2V dVOH = uVH - VOHu -2V VL +6V; VH = +7V dVOL = uVL - VOLu -1V VOH +7V -2V VOL +7V 0V VOUTPUT +5V -2V VOUTPUT +7V -1.0 -0.5 -1.0 0.1 0.5 0.2 0.6 50 mV/C +1.0 %VSET +0.5 %VSET +1.0 %VSET -100 -40 100 mV -2.0 0 -4.0 0.1 -100 -40 +7.0 +9.0 +5.0 9.5 100 V V V V mV 50 kHz -1 -5.0 -2.0 0.4 0.4 -100 -150 -2.0 0 -4.0 -2.0 0 -4.0 1.0 -1.0 0.1 0.1 1 ECL ECL -35 -50 +7.0 +9.0 +5.0 +6.0 +8.0 +4.0 5.0 +5.0 5.0 5.0 V V V mA mA V V V V V V mA mA mA/C mA/C mA Test Conditions Min. -2.0 Typ. Max. Units +6.0 V
Diffential Inputs VIN+, VIN-, VINH+, VINH-
Voltage Program Inputs VH, VL
Signal Output VO, VOTERM VO Output Voltage Range
5
RC7316
PRODUCT SPECIFICATION
DC Electrical Characteristics (continued)
Symbol IZL IDC IAC ICL VOL TTS Other VS VCC VEE ICC IEE PSRVO PSRVSL Rail to Rail Supply Voltage Positive Supply Negative Supply Positive Supply Current Negative Supply Current Output Level Power Supply Rejection Ratio Output Slew Rate Power Supply Rejection Ratio @ VCC Rejection Ratio @ VEE VCC; DVCC = 2.5% VEE; DVEE = 2.5% VH = 5V and VL = 0V DVCC = 200 mV DVEE = 200 mV 4 4 % VCC - VEE -7.2 -5.2 85 95 40 40 17 +8.0 +10.0 +12.0 -3.2 V V V mA mA dB dB Parameters Output Leakage Current in Inhibit Mode DC Current Drive AC Current Drive DC Current Limit Output Low Level Shutdown Die Temperature lOL = 4 mA 115 135 Test Conditions -2.0V VO +6.5V Min. -200 50 70 70 100 110 130 0.5 160 Typ. 10 Max. Units +200 nA mA mA mA V C
Thermal Shutdown Output (TS) (Open Collector Output)
AC Electrical Characteristics
VCC = 10V 3%, VEE = -5.2V 5%, TA = 25C (still air) and the load is a 50W transmission line with 2.0 ns one-way delay, unless otherwise specified. The transmission line is back-terminated in 50W (5%) using both internal and external termination resistance. The measurement probe is a high impedance FET probe with capacitance no greater than 3 pF and resistance no smaller than 10 kW. Symbol SLR Parameters Slew Rate Test Conditions VH - VL = 5V; Measured between 20% and 80% points. With probe only as load With probe and transmission line +SRC Positive SLR Control + SRC Control Voltage Range Slew Rate Change -SRC Negative SLR Control -SRC Control Voltage Range Slew Rate Change tR, tF Rise Time, and Fall Time CL = 5.0 pF VA = 0.8V (20% to 80%) VA = 3V (10% to 90%) VA = 5V (10% to 90%) 0.5 1.0 1.4 0.8 1.4 1.8 ns ns ns VH = +5V, VL= 0V -2.0 0.5 +2.0 +3.5 V V/ns VH = +5V, VL = 0V -2.0 0.5 +2.0 +3.5 V V/ns Min. Typ. Max. Units
3.0 2.7
3.5 3.2
V/ns V/ns
6
PRODUCT SPECIFICATION
RC7316
AC Electrical Characteristics (continued)
Symbol f Parameters Toggle Rate (Probe only) tPHL DtP tPTC tPWmin High to Low Propagation Delay Propagation Delay Match Propagation Delay Temperature Coefficient Minimum Pulse Width VH - VL - 2.0V; pulsewidth at which amplitude drops by 50 mV, measured between 50% points. CL = 5.0 pF 2 ns < PW < 98 ns; f = 10 MHz; VOH = +0.4V; VOL = -0.4V 0.5V < VA < 5.0V Test Conditions Amplitude = 0.8 Vp-p Amplitude = 3.0 Vp-p Amplitude = 5.0 Vp-p f = 10 MHz; VOH = +0.4V; VOL = -0.4V utPLH - tPHLu 1.7 30 2 1.1 2.0 100 ns ps ps/C ns Min. 500 275 200 Typ. 550 300 220 Max. Units MHz MHz MHz
DtPPW
Propagation Delay Variation with Pulse Width Preshoot
40
150
ps
tPS
15mV + 3% of VA 50mV + 4% of VA 5.0 12.0 1.5 2.0 2.2 2.2 3.0 2.0 2.5 2.5 2.5
ns
tOS
Overshoot
0.5V < VA < 5.0V
ns
tS
Output Settling Time
VA = 5V; To within 3% of VA To within 1% of VA ns ns ns ns ns ns pf
tPHZ tPLZ tPZH tPZL CZ
Propagation Delay from Logic High to Inhibit Mode Propagation Delay from Logic Low to Inhibit Mode Propagation Delay from Inhibit Mode from Logic High Propagation Delay from Inhibit Mode to Logic Low Output Capacitance in Inhibit Mode
VOH = 1V; VOL = -1V Load = 100W to 2.5V; Propagation delay is measured to the point at which voltage has changed by 200 mV.
7
RC7316
PRODUCT SPECIFICATION
Notes:
8
PRODUCT SPECIFICATION
RC7316
Notes:
9
RC7316
PRODUCT SPECIFICATION
Notes:
10
PRODUCT SPECIFICATION
RC7316
Mechanical Dimensions
16-Lead Hybrid Flatpack
Symbol A b c1 D/E e H L s1 a Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. All dimensions and tolerances conform to ANSI Y14.5M-1982. 2. Gold plate 80 " min. nickel over 80 " min. nickel. 3. Leads 1 and 9 connect to ground, seal ring, and heat sink pad.
.072 .088 .013 .017 .007 .010 .442 .458 .050 BSC .675 .685 .050 .065 .005 0 5
1.83 2.24 0.33 0.43 0.18 .15 11.23 11.63 1.27 BSC 17.15 17.40 1.40 1.65 .13 0 5
Index b
D e s1
A
E c1 L H
a
11
RC7316
PRODUCT SPECIFICATION
Ordering Information
Part Number RC7316TEL Package EL Operating Temperature Range 0C to +70C
Notes: TEL = 16 Lead Hybrid Flatpack, 50W termination (AD1322 pinout)
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS30007316 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC7321
Three-State ATE Pin Electronics Driver
Features
* High output slew rate (1.3 V/ns typical) * Wide output voltage range (-2.2V to +7V), and up to 9.2 Vp-p swings * Three-state/high impedance output * High repetition rate (250 MHz for ECL swings) * Low output offset (40 mV typical) and output offset drift (0.1 mV/C typical). * Low leakage (10 nA typical) and low output capacitance (3 pF typical) in high impedance inhibit mode * High speed differential inputs with wide common mode range for ease of interface to ECL as well as TTL and CMOS levels * Output short circuit protection (Safe Operating Area protection with current limiting and thermal shutdown) * 100 mA typical dynamic current drive capability * Absolute slew rate control * Available in 28-pin PLCC
Description
The RC7321 is a low cost Pin Electronics Driver designed for use in all high speed ATE systems which require pin drivers with three state capability and high slew rates. The RC7321 has the ability to drive a 50W transmission line of up to 2 feet in length with a slew rate of 1.2 V/ns and repetition rate of over 250 MHz for ECL output levels. These features, combined with a maximum output swing of 9.5 Vp-p over the range of -2.5V to +7V, provide this circuit with the ability to test TTL, CMOS, ECL and GaAs devices. The high and low limits of the output swing are set through the program pins VH and VL, respectively. The transfer characteristic from the program pins to the output pin is unity gain with very low offset drift. The VH and VL inputs have been buffered to operate with low bias currents (1 mA typical) allowing direct coupling to the output of a DAC. When the RC7321 is used on an I/O pin, it may be forced into the high impedance state through the INH+ and INHdifferential inputs. In the high impedance state, excellent isolation is provided between the output of the disabled driver and the pin by virtue of low driver output capacitance (3.0 pF typical) and low output leakage (10 nA typical). The RC7321 is provided with high speed differential ECL inputs for ease of interface with the differential ECL outputs of a timing generator. The inputs have a voltage range of -2V to +6V, so that if required, an input may be driven by TTL or CMOS devices provided that the other input is tied to the
Applications
* * * * * * * ATE pin electronics driver Precision waveform generator Level translator PCB & Burn-in ATE Driver General purpose driver for PCB & burn-in test systems Laser driver CRT preamplifier
Block Diagram
VH CVOH VIN+ VINCVOL VL INH+ INHBuf Buf
Clamp Circuit Slew Rate Control Offset Control and Switching Temperature Sensing Output Buffer
GND
+SRC -SRC
VO
VCCO VEEO
TS
Driver Inhibit Circuit
Refs &Temp Compensation
65-5284A
VCC VEE
Rev 1.0.1
RC7321
PRODUCT SPECIFICATION
Description (continued)
appropriate threshold value. The pin driver is available in unterminated configuration. The RC7321 is implemented using Fairchild Semiconductor's high frequency complementary bipolar process.
Pin Assignments
VEE SRCM VCC GND NC NC VEE
432 1 28 27 26 25 24 23 22 21 20 19
VEE VOUT SRCA NC VCCO VEEO VEE
5 6 7 8 9 10 11
28-Pin PLCC (Top View)
VEE INH+ INHVIN+ VINCVOH VEE
12 13 14 15 16 17 18
Pin Description
Name CVOL, CVOH GND INH+ INHPin Number Function 17 1 23, 24 Bypass capacitor for VOH and VOL respectively. Pins CVOL and CVOH should be bypassed to the ground plane with a 1,000 pF chip capacitor placed as close to the pin as possible. Chip ground. Should be connected to the printed circuit board's ground plane at the pin. Differential digital inputs. When INH is true (i.e. INH+ > INH-) the driver is forced into the high impedance state. Although these inputs are normally driven by ECL signals, they have a wide enough common mode range that any one of the inputs may be driven by a TTL or CMOS signal provided that the other input is tied to the appropriate threshold voltage. Quiet positive supply. The nominal value is 10V 3%. For output high voltage levels (VOH) greater than the nominal value of +7V, VCC should be raised 3V above the maximum value of VOH. Whenever VEE is lowered to provide margin at the output low level, VCC should also be lowered by the same amount. VCC should be bypassed to ground with a 10,000 pF chip capacitor placed as close to the pins as possible. Positive supply for the RC7321 output stage. This supply is brought out separately to minimize the supply noise generated when the output switches. VCCO should be bypassed to the ground plane with a 10,000 pF chip capacitor placed as close to the pin as possible and then immediately connected to VCC. Quiet negative supply. The nominal value is -5.2V 5%. For output low voltage levels (VOL) less than the nominal value of -2.2V, VEE should be lowered 3V below the minimum value of VOL. Whenever VCC is raised to provide margin at the output high level, VEE should also be raised by the same amount. VEE should be bypassed to ground with a 10,000 pF chip capacitor placed as close to the pins as possible. Negative supply for the RC7321 output stage. This supply is brought out separately to minimize the supply noise generated when the output switches. VEEO should be bypassed to the ground plane with a 10,000 pF chip capacitor placed as close to the pin as possible and then immediately connected to VEE.
VCC
2
VCCO
9
VEE
4, 5, 11, 12, 18, 19, 25, 26 10
VEEO
2
VEE VL NC TS VH CVOL VEE
PRODUCT SPECIFICATION
RC7321
Pin Description (continued)
Name VH VIN+, VINPin Number Function 16 21, 22 Analog program input that sets the output high level (VOH). The transfer characteristic from VH to VOH is nominally unity gain. Differential digital inputs. The output will toggle between the two levels dictated by VH and VL as the differential signal is switched. Although these inputs are normally driven by ECL signals, they have a wide enough common mode range that any one of the inputs may be driven by a TTL or CMOS signal provided that the other input is tied to the appropriate threshold voltage. Analog program input that sets the output low level (VOL). The transfer characteristic from VLto VOL is nominally unity gain. Driver output on RC7321. The output impedance is 8W 2W. The output is usually back terminated in the characteristic impedance of the transmission line it drives. For a 50W line, a 40W1% resistor should be placed externally as close to the output pin as possible to minimize reflections and ringing. The resistor should also be able to dissipate 0.8W to sustain the short circuit current of the output. 7 3 Slew rate control for both edges. Slew rate of both rising and falling edges decreases as the control current is changed from 0 mA to -0.5 mA. SRC can be programmed with a current DAC or set to a fixed value using a resistor. Increases the speed of the falling edge to match the rising edge. Active low output notifies thermal shutdown has occurred. In the event of a short circuit or other fault that causes the die temperature to become excessively large, the thermal shutdown will kick in at a die temperature between 125C and 150C. If the fault persists, the device will toggle back and forth between shutdown and normal operation at a frequency in the tens of Hertz. TS is an open collector output capable of driving two standard TTL loads. The TS pins of several drivers may be wire-ORed together and input to a latch to indicate an alarm condition. No connection.
VL VO
13
SRCA SRCM
TS
15
NC
8, 14, 27, 28
Absolute Maximum Ratings1
Parameter Positive power supply, VCC Negative power supply, VEE Difference between VCC and VEE Input voltage at VIN+, VIN-, INH+, INHInput Voltage at VH, VL Differential input voltage, | VIN+ - VIN- I, | VINH+ - VINH- I Difference between VH & VL (IVH - VLI) Input voltage at SRCA Slew rate control current Driver Output Voltage Output voltage at TS Duration of short-circuit to ground Operating temperature range 0 -3 -2.0 VCC-13 VEE+13 5 Indefinite 70 C VCC-12 VCC-13 -8.2 16 VEE+12 VEE+13 6 11 +7 Min. Max. 13 Units V V V V V V V V mA V V
3
PRODUCT SPECIFICATION
RC7321
Absolute Maximum Ratings1 (continued)
Parameter Storage temperature range Lead temperature range (Soldering 10 seconds) Min. -65 Max. +125 300 Units C C
Notes: 1. "Absolute maximum ratings" are those beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. If the device is subjected to the limits in the absolute maximum ratings for extended periods, its reliability may be impaired. The tables of Electrical Characteristics provide conditions for actual device operation.
Recommended Operating Conditions
Symbol TC VCC VEE VCC-VEE VOH, VOL VOH-VOL Parameters Case operating temperature Positive supply voltage Negative supply voltage Difference between positive and negative supply Range for output high level and output low level Output amplitude -2.0 0.1 9.7 -5.45 Min. Typ. 25 10.0 -5.2 15.2 10.3 -4.95 15.8 7.0 9.5 Max. Units C C V V V V
DC Electrical Characteristics
VCC = 10V 3%, VEE = -5.2V 5%, TA = 25C (still air) and the load is a 50W transmission line with 2.0 ns one-way delay, unless otherwise specified. The transmission line is back-terminated in 50W (5%) using an external resistor. Symbol VIN+, VINVINH+, VINHVID VDINH IIN+, IINIINH+, IINHParameters Absolute Voltage @ Data Inputs Absolute Voltage @ Inhibit Inputs INH+, INHDifferential Input Range Differential Inhibit Input Range Input Bias Current @ Data Inputs Input Bias Current @ Inhibit Inputs Compliance Voltage Range Control Current Range Compliance Voltage Range Control Current Range VH Range VCC = 10V; VEE = -5.2V VCC = 12V; VEE = -3.2V VCC = 8V; VEE = -7.2V VL VL Range VCC = 10V; VEE = -5.2V VCC = 12V; VEE = -3.2V VCC = 8V; VEE = -7.2V Test Conditions Min. -2.0 -2.0 Typ. Max. Units +6.0 +6.0 ECL ECL 100 100 5.0 5.0 200 200 V V V V mA mA Differential Inputs VIN+, VIN-, VINH+,VINH-
|VIN+ - VIN-| |VINH+ - VINH|
-2V VIN+, VIN- +6V -2V VINH+, VINH- +5V
0.4 0.4
Absolute Slew Rate Control Input SRCA VSRCA ISRCA VSRCM ISRCM VH -2.0 -0.5 -2.0 -0.5 -2.0 0 -4.0 -2.5 -0.5 -4.5 +2.0 +0.5 +2.0 +0.5 +7.0 +9.0 +5.0 +6.0 +8.0 +4.0 V V V V V V V V V V
Matching Slew Rate Control Input SRCM
Voltage Program Inputs VH, VL
4
RC7321
PRODUCT SPECIFICATION
DC Electrical Characteristics (continued)
Symbol IH IL TCIH TCIL VH, LBW Parameters Bias Current @ VH Bias Current @ VL Temperature Drift in IH Temperature Drift in IL -3 dB bandwidth from VH or VL to the output Test Conditions -1V VH +7V; VL = -2.0V -2V VL +5V; VH = 6.0V VH = 7.0V; 25C TC 70C output not switching VL= -2.0V; 25C TC 70C output not switching -1V VH +7V -2V VL +6V; VH-VL= 2.0V VCC = 10V; VEE = -5.2V VCC = 12V; VEE = -3.2V VCC = 8V; VEE = -7.2V VA DVOH DVOL DVOH DVOL DVOL DVOH VTC eG eL ZOUT IZL Amplitude Offset to Output High Level Offset to Output Low Level Change in VOH output level with change in VL Change in VOL output level with change in VH Output Voltage Drift Gain Error Linearity Error Output Impedance (IOUT = 50 mA) Output Leakage Current in Inhibit Mode (maintain the following: | VL-1.0V | VO | VH + 1.0V |) DC Current Drive AC Current Drive Short Circuit Current Limit TS Flag Output Level Shutdown Die Temperature Maximum Rail-to-Rail Supply Voltage Positive Supply VCC - VEE lOL = 4 mA 130 -2.0V VO +7V -2.2 -0.5 -4.5 0.3 30 30 10 10 0.1 0.1 1.0 1.0 0.7 7.0 9.0 0.5 2.0 2.0 1.0 11 2.0
%FS %FS
Min.
Typ. 1.0 1.0
Max. Units 2.0 2.0 0.1 0.1 mA mA mA/C mA/C kHz
50
Signal Output VO, VOTERM VO Output Voltage Range +7.0 +9.0 +5.0 9.2 60 60 15 15 V V V V mV mV mV mV mV/C
|VOH - VOL|
VH = 0, no load; VL = -2V DVOH = |VH - VOH| VH = 0, no load; VH = +7V DVOL = |VL - VOL| VOH = +5V, DVL = 0 to +1V VOL = +5V, DVH = +4 to +5V -1V VOH +7V; -2V VOL +6V; -1V VOH +7V; -2V VOL +6V -2V VOUTPUT +7V
W mA
IDC IAC ICL VTS TTS Other VS MAX VCC
50 70 100 145 0.5 145 16 +8.0 +10.0 +12.0
mA mA mA V C V V
Thermal Shutdown Output (TS)
5
PRODUCT SPECIFICATION
RC7321
DC Electrical Characteristics (continued)
Symbol VEE ICC IEE PSRVO PSRVSL Parameters Negative Supply Positive Supply Current Negative Supply Current Output Level Power Supply Rejection Ratio Output Slew Rate Power Supply Rejection Ratio TA Operating Temperature Range VCC; DVCC = 2.5% VEE; DVEE = 2.5% VH = 5V, VL = 0V, DVCC = 200 mV VH = 5V, VL = 0V, DVCC = 200 mV Still Air Air Flow > 300 lfpm 0 0 40 40 4.0 4.0 25 25 40 70 Test Conditions Min. -7.2 Typ. -5.2 85 90 Max. Units -3.2 90 100 V mA mA dB dB % % C C
AC Electrical Characteristics
VCC = 10V 3%, VEE = -5.2V 5%, TA = 25C (still air) and the load is a 50W transmission line with 2.0 ns one-way delay, unless otherwise specified. The transmission line is back-terminated in 50W (5%) using an external resistor. The measurement probe is a high impedance FET probe with capacitance no greater than 3 pF and resistance no smaller than 10 kW. Symbol SLR Parameters Slew Rate Test Conditions VH - VL = 5V; Measured between 20% and 80% points. With probe only as load With probe and transmission line tR, tF Rise Time, and Fall Time (Slew rate not adjusted) f tPLH tPHL DtP tPTC tPWmin Toggle Rate (Probe only) Low to High Propagation Delay High to Low Propagation Delay Propagation Delay Match Propagation Delay Temperature Coefficient Minimum Pulse Width VH - VL - 2.0V; pulsewidth at which amplitude drops by 50 mV, measured between 50% points. 2 ns < PW < 98 ns; f = 10 MHz; VOH = +0.4V; VOL = -0.4V 0.5V < VA < 5.0V Load is Probe Only; VA = 1V (20% to 80%) VA = 3V (10% to 90%) VA = 5V (10% to 90%) Amplitude = 0.8 Vp-p Amplitude = 5.0 Vp-p f = 10 MHz; VOH = +0.4V; VOL = -0.4V f = 10 MHz; VOH = +0.4V; VOL = -0.4V 1.4 200 2.0 2.0 ns ps ps/C ns 1.6 ns 250 125 0.6 1.6 2.5 0.9 2.1 3.0 ns ns ns MHz MHz 1.6 1.5 V/ns V/ns Min. Typ. Max. Units
|tPLH - tPHL|
DtPPW
Propagation Delay Variation with Pulse Width Preshoot
75
ps
tPS
15mV + 3% of VA
mV
6
RC7321
PRODUCT SPECIFICATION
AC Electrical Characteristics (continued)
Symbol tOS Parameters Overshoot Test Conditions 0.5V < VA < 5.0V Min. Typ. Max. Units 50mV + 4% of VA 8 10 2.9 2.9 2.9 2.9 3.0 mV
tS
Output Settling Time
VA < 5V; To within 3% of VA To within 1% of VA ns ns ns ns ns ns pF
tPHZ tPLZ tPZH tPZL CZ
Propagation Delay from Logic High to Inhibit Mode Propagation Delay from Logic Low to Inhibit Mode Propagation Delay from Inhibit Mode from Logic High Propagation Delay from Inhibit Mode to Logic Low Output capacitance in Inhibit Mode
VOH = 1V; VOL = -1V Load = 100W || 15pF Propagation delay is measured to the point at which voltage has changed by 200 mV.
7
PRODUCT SPECIFICATION
RC7321
Notes:
8
PRODUCT SPECIFICATION
RC7321
Notes:
9
RC7321
PRODUCT SPECIFICATION
Notes:
10
RC7321
PRODUCT SPECIFICATION
Mechanical Dimensions -- 28-pin PLCC
Symbol A A1 A2 B B1 D/E D1/E1 D3/E3 e J ND/NE N ccc Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. All dimensions and tolerances conform to ANSI Y14.5M-1982. 2. Corner and edge chamfer (J) = 45. 3. Dimension D1 and E1 do not include mold protrusion. Allowable protrusion is .101" (.25mm).
.165 .180 .090 .120 .020 -- .013 .021 .026 .032 .485 .495 .450 .456 .300 BSC .050 BSC .042 .048 7 28 -- .004
4.19 4.57 2.29 3.05 .51 -- .33 .53 .66 .81 12.32 12.57 11.43 11.58 7.62 BSC 1.27 BSC 1.07 1.22 7 28 -- 0.10
3
2
E E1 J
D
D1
D3/E3
B1 e J
A A1 A2 B -C- LEAD COPLANARITY
ccc C
11
RC7321
PRODUCT SPECIFICATION
Ordering Information
Package 28-pin PLCC Order Number RC7321QF
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS30007321 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC7352
Parametric Measurement Unit
Features
* Force voltage/measure current and force current measure voltage functions * Forced voltage range (-5V to +15V) * Four programmable measured current ranges: Range A = 20mA max Range B = 200mA max Range C = 1.0mA max Range D = 40mA max * High resolution current force/measure 0.05% = 2 bits * Internal control circuitry for selecting ranges * High accuracy: 12 bit linearity and 0.5% gain error * High current range D current limit protection set externally by the value of resistor RDIL * Measurement output voltage can be disabled * Forced current ranges: Range A = 20mA max Range B = 200mA max Range C = 1.0mA max Range D = 40mA max * Measured voltage range: -5V to +15V * High resolution voltage measurement (0.05%) and accuracy: (10mV max. offset) and 0.5% gain error * Internal current limit for ranges (A, B, & C)
Applications
* ATE pin electronics measurements * Instrumentation, meters * Programmable voltage or current supply
Description
The RC7352 is a "Per Pin" Parametric Measurement Unit (PMU) that can force voltage and measure current or force current and measure voltage. The RC7352 forces voltages from +15V to -5V when +VS is 20V and -VS is -10V, or currents up to 40mA. All logic inputs for the RC7352 are TTL compatible, while the open collector logic outputs are TTL/CMOS compatible. Setting the SI/V (Select I/V) pin low puts the RC7352 in the force voltage and measure current mode. The resulting output voltage at the DUT matches the input applied to the
Block Diagram
6 CA 18 25 CB 7 I/VOUT 20 VFB 28 +VS (20V) RANGE A IN OUT 9 RA
V/I FORCE
- + + - I
I SENSE V
- + + - I - + + A=4 - I
VIN
23 CAP_V
4:1 MUX
- I + - + IA
EN RANGEA.SCH RANGE B IN OUT EN RANGEB.SCH
17 I/VIN CAP 11 CAP_I 10 RADJ - + + - I
19 RB
I
I
- +
- + IB
V/I MEAS.
- + + - I
WINDOW COMPARATOR
+ - +I -E + - + -E
I
V
-
RANGE C IN OUT EN RANGEC.SCH
22 RC
V
I: FI/MV V: FV/MI
I
+
- + IC
- +
+ - I
LOGIC & BIAS
I
RANGE D IN OUT D2 RDIL RANGED.SCH EN
24 RD 2 RDIL 1 D
- + /4
I
- + ID
15 I/V M
4 I/V MX 26 I/V MN
27 VLS 5 VHS 13 SI/V
12 RS1 14 RS2
21 VDIS
8 GND
16 -VS (-10V)
3 VEE (-10V)
65-7352-01
Rev. 1.1.2
RC7352
PRODUCT SPECIFICATION
I/VIN pin (please refer to block diagram). The I/VM pin provides a voltage proportional to the DUT current. V(I/VM) = (4 x R x I(DUT)), where R is the external range resistor (0.05% tolerance) and I(DUT) is the current supplied to the load. The resistors in the application circuit were chosen using this formula R range = (2V/Imax), for Range A this is RA = 2/20 mA or 100K. When SI/V is high the RC7352 will force current and measure voltage. The range select pins RS1 and RS2 control the maximum output current (see Table 1), while magnitude of the forced current is given by the expresion I(DUT) = V(I/VIN)/(4 x R) where R is the range resistor. In the FI/MV mode the voltage at the I/VM pin equals the device voltage. The I/VM pin can be connected to an A/D convertor to monitor the current or voltage at the load device. The RC7352 also has a window comparator that can provide upper or lower limit fail information. I/Vmx and I/Vmn are voltage inputs for the upper and lower limits respectively. You must use the formulas listed above to calculate current limits for each range while voltage limits are 1:1. Their corresponding outputs, VHF (V high fail) and VLF (V low fail) can be used individually or "Wire ORed" to obtain a
composite signal. Additionally the VDIS pin can be set high to disable the window comparator and its I/O lines. Although this reduces overall power consumption, it also disables the I/VM output.
Table 1. Maximum Output Current on Pin Select
SI/V RS2 RS1 Mode 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 1 0 0 1 1 0 FV/MI Range A, Imax = 20 mA FV/MI Range B, Imax = 200 mA FV/MI Range C, Imax = 1.0 mA FV/MI Range D, Imax = 40 mA FI/MV Range A, Imax = 20 mA FI/MV Range B, Imax = 200 mA FI/MV Range C, Imax = 1.0 mA FI/MV Range D, Imax = 40 mA
Notes: 1. FV/MI = Force Voltage Measure Current. 2. FI/MV = Force Current Measure Voltage. 3. +VS-5 VOUT -VS+5
Pin Assignments
I/VMX I/VMN
26 25 24 23
RDIL
+VS
28
VEE
4
3
2
1
VHF CA IVOUT GND RA RADJ CAP_I
5 6 7 8 9 10 11 12 13 14 15 16 17
VLF
27
D
CB RD I/VIN RC VDIS VFB RB
RC7352
22 21 20 19 18
I/VM
SI/V
RS1
RS2
-VS
CAP_V
CA
65-7352-02
2
PRODUCT SPECIFICATION
RC7352
Pin Description
Pin Name +VS -VS VEE GND I/VIN Pin Number Pin Description 28 16 3 8 23 +VS should be bypassed to ground with a 10.0 mF tantalium capacitor placed as close to the pin as possible. -VS should be bypassed to ground with a 10.0 mF tantalium capacitor placed as close to the pins as possible. VEE is the negative supply for range D. This pin should be bypassed with a 0.1 mF ceramic capacitor to ground. This pin should be connected to the printed circuit board's ground plane. Input reference voltage for VOUT or IOUT. In the force voltage measure current mode (FV/MI) V(I/VOUT) = V(I/VIN ) and V(I/VM) = 4 x IOUT x R Where IOUT is the device output current and R is the range resistor. In the Force Current/Measure Voltage Mode
V ( I VIN ) I OUT = -----------------------4R
V(I/VM) = V(I/VOUT) I/VOUT 7 The Load or Device under test is connected to I/VOUT. The current to the load is supplied via the appropriate range resistor with I/VOUT serving as the voltage feedback point for the PMUs internal instrumentation amplifier. A TTL/CMOS signal applied to this pin selects either Force Voltage/Measure Current or Force Current/Measure Voltage mode. A TTL/CMOS low level will select Force Voltage/Measure Current function. A TTL/CMOS high level selects Force Current/ Measure Voltage mode. Resistor RA should be placed between RA and I/VOUT. RA tolerance should be better than +0.05% to improve gain error. Maximum current for range A is shown in the equation below.
2V I A = ---------RA
SI/V
13
RA
9
The 2 volts represents the maximum voltage VA across RA. For Range A, IA should not exceed 20 mA, i.e., RA should be higher than or equal to 100 kW. A metal film resistor should be used to reduce inherent resistor noise (schott and pop corn noise) and improve resolution. For maximum stability, a 300 pF capacitor should be connected across RA. RB 19 For Range B, IB should not exceed 200 mA, i.e., RB should be higher than or equal to 10 kW with 0.05% tolerance. For maximum stability a 1,000 pF capacitor should be connected across RB. For Range C, IC should not exceed 1 mA, i.e., RC should be higher than or equal to 2 kW with 0.05% tolerance. For Range D, ID should not exceed 40 mA, i.e., RD should be higher than or equal to 50 W with 0.05% tolerance. Two diodes must be connected between D & RD as shown in the block diagram. A 30pF capacitor placed between these pins will improve stability. Range D output for current limiting. An external resistor is connected between RDIL and D to limit current to a value ILIM = 0.8V/RLM.
RC RD D CA, CB RDIL
22 24 1 6, 25 2
3
RC7352
PRODUCT SPECIFICATION
Pin Description (continued)
Pin Name RS1, RS2 Pin Number Pin Description 12 14 RS1 and RS2 are TTL or CMOS compatible. The truth table below shows the range selection table. RS1 L L H H I/VMX, I/VMN 4 26 RS2 L H H L Range Selected A B C D
The voltage applied to pin 4 sets the upper current or voltage limit for the measurement at pin 15 I/VM. To set the desired limit for current measurement a voltage equaling (4 x IL x R) must be applied on this pin. R is the external resistor of the selected range (A, B, C, or D). For voltage measurement the voltage applied to this pin is the limit. VHF, High Fail, is an open collector output that requires a pull-up to the logic supply. If the voltage at pin 15, I/VM, is greater than the threshold voltage at pin 4, I/VMX, VHF will become a logic low. The open collector structure makes wire-ORing of multiple PMU's possible. Connect a 3,000 pF capacitor to GND to minimize oscillation at the cross-over point. VLF mirror VHF for the lower threshold I/VMN. Connect a 3,000 pF capacitor to GND to minimize oscillation at the cross over point. When VDIS is tied to ground output I/VM, VHF and VLF are enabled. If VDIS is open VHF and VLF will require external pullups to maintain a logic high. And I/VM will be in a high impedance state. In the Force Voltage/Measure Current mode this output voltage is equal to four times the voltage across external resistor R of selected range A, B, C, or D through which the measured current is flowing ((I/V)M = 4.0 x IM x R). In the Force Current/ Measure Voltage mode this output is equal to the voltage at I/V out. This output can be disabled by applying a TTL HI on the VDIS pin. (Pin 21) VFB, voltage feedback, is the buffered output voltage, I/V OUT. This pin should not be loaded. Connect a 50K 1% resistor from VFB to CAP_V. The RADJ pin is provided to adjust the offset for the ISENSE function. The best accuracy for V/IM is obtained when RADJ is shorted to analog ground. The point is terminated with a 100 W resistor in the block diagram. CA is the common point for two 50 pF compensation capacitors that improve the stability of the PMU. These components are optional and can be omitted for some loads.
VHF
5
VLF VDIS
29 21
I/VM
15
VFB RADJ
20 10
CAP_I CAP_V CA
11 18 17
4
RC7352
PRODUCT SPECIFICATION
Absolute Maximum Ratings1
Parameter Absolute Difference, +VS+|-VS| Digital Control Inputs SI/V, RS1, RS2, VDIS Comparator Inputs I/VMN, I/VMX I/VIN I/VMN +VS -VS I/VMX -VS I/VIN +VS V V -2 +6 V Min. Max. 32 Units V
Notes: 1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions. Functional operation under any of these conditions is NOT implied. 2. Applied voltage must be current limited to specified range, and measured with respect to GND. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current flowing into the device.
Recommended Operating Conditions
Symbol TC +VS -VS VEE RA RB RC RD Parameters Case operating temperature Positive supply voltage1 Negative supply voltage1 D2 100 10 2 50 Negative supply voltage for range Resistor for IA current range Resistor for IB current range Resistor for IC current range Resistor for ID current range Min. 0 10.4 -15.75 20.0 -10.0 -VS 2000 200 40 1000 Typ. Max. 70 20.6 -9.5 Units C V V V KW KW KW W
Notes: 1. +VS + |-VS| 30V +VS + |-VS| 24 2. -VS & VEE are always at the same voltage.
5
PRODUCT SPECIFICATION
RC7352
DC Electrical Characteristics
+VS = 20V 3%, -VS = -10V 5% TA = 25C, and external 0.05% tolerance resistors RA = 1000kW, RB = 10kW, RC = 2kW, and RD = 50W unless otherwise specified. Symbol
I/VIN I/VM VMR VOR VGE CMRR1 IOER I/VIN I/VFVOS
Parameters
Input Voltage Range For Setting Forced Current (IF) Measured Voltage Output @ (I/V)M Output Sink/Source Current Voltage Measured Resolution Voltage Measurement Offset Voltage Gain Error IOUT Error Due to Common Mode Load Voltage Force Input Voltage Range Forced Voltage Offset Forced Voltage Linearity Error
Test Conditions
I/VFIN = 4 x IF x R All ranges, full scale current (I/V)M = -5V, +15V I/VIN = 0V; Measured @ I/VM Gain of 4 -5V I/VOUT +15V; Measured @ (I/V)M All ranges, full scale current I/VIN = 0V, measure I/VOUT and VFB -FSR IOUT +FSR; Measured @ (I/V)M All ranges, full scale current All ranges, full scale voltage
Min.
-8 -5 -200 -.05 -6.0 -2.0 45
Typ.
Max.
+8 +15 +200
Units
V V mA mV % dB
Forced Current/Measure Voltage
0.025 +0.05 %FSR 2 +0.5 60 +6.0 +2.0
Forced Voltage/Measure Current -5 -6.0 2 +15 +6.0 V mV
0.025 0.05 FSR% 45 -5 -8 60 +15 +8 dB V V
CMRR2 VLER I/VOUT I/VM
IOUT Measure Error Due to I/VM Common Mode Voltage Forced Output Voltage Range Voltage Output Equivalent to Measured Current: (I/V)M = 4 x IF x R I measured; I = (I/VM)/(4R)
I Range A IA IAMR ILIN lGE IFIOS IMIOS Range B IB IBMR ILIN lGE IFIOS IMIOS
I/VM = -8.0V, +8.0V; full scale
-200
+200
mA
Current Ranges Maximum Full Scale Current Current Measurement Resolution Linearity3 Current Gain Error4 Force Current Offset5 Offset6 I/VIN = 0V I/VIN = 0V RB = 10kW (0.05%) guaranteed by design -2.0 -250 -250 0.025 -0.05 0.025 +0.05 0.5 100 100 +2.0 +250 +250 % nA nA Offset5 Measure Current RA = 100kW (0.05%) guaranteed by design -2.0 -25 -25 0.025 -0.05 0.025 +0.05 0.5 10 10 +2.0 +25 +25 200 % nA nA mA % 20 mA %
Maximum Full Scale Current Current Measurement Resolution Linearity3 Current Gain Error4 Force Current Measure Current Offset6
6
RC7352
PRODUCT SPECIFICATION
DC Electrical Characteristics (continued)
Symbol
Range C IC ICMR ILIN lGE IFIOS IMIOS Range D IC IDMR ILIN lGE IFIOS IMIOS VIH ILH ILL VIH ILH ILL Maximum Full Scale Current Current Measurement Resolution Current Measurement Accuracy Linearity3 Current Gain Error4 Force Current Offset5 Measure Current Offset6 RD = 50W (0.05%) guaranteed by design -0.05 -2.0 -50 -50 0.8 VH = 2.0V VL = 0.8V 0.8 VH = 2.0V VL = 0.8V -8.0 VH = +15V VL = 0.8V RPULLUP = 10kW RPULLUP = 10kW VOUT = 5.0V VOUT = 5.0V No load Range A No load Range A 0.1 1.0 0.1 4.0 4.0 11.0 11.0 3.5 0.8 0.4 0.4 .025 .025 0.5 20 20 1.4 200 2.0 1.4 1.0 2.0 +15 2.0 +0.05 +2.0 +50 +50 2.0 40 mA % % % mA mA V nA nA V mA nA V mA mA V V mA mA mA mA mA Maximum Full Scale Current Current Measurement Resolution Linearity3 Current Gain Error4 Force Current Offset5 Measure Current Offset6 RC = 2kW (0.05%) guaranteed by design -0.05 -2.0 -1.5 -1.5 .025 .025 0.5 0.5 0.5 +0.05 +2.0 +1.5 +1.5 1 mA % % % mA mA
Parameters
Test Conditions
Min.
Typ.
Max.
Units
Digital Control Inputs (SI/V, RS1, RS2) Internal Threshold Voltage Logic High Bias Current Logic Low Bias Current Internal Threshold Voltage Logic High Bias Current Logic Low Bias Current
Digital Control Input VDIS
Comparator Input; I/VMAX, I/VMIN I/VMX,MN Input Voltage Range IH IL VOH VOL IOH IOL IZ Other I+ (1.0) I- (2.0) Positive Supply Current Positive Supply Current Input Bias Current (Logic High) Input Bias Current (Logic Low) Output Voltage (Logic High) Output Voltage (Logic Low) Output Current High Output Current Low Output Leakage Current Disable State
Comparator Status Outputs; VHF, VLF
Notes: 1. CMRR is measured with VL=15V/-5V; R is RA, RB, RC or RD; V1 = constant; This parameter is to define the IOUT current error due to the VL common mode voltage for a constant V1. This parameter is guaranteed to full V1 range. (8V) ae DI OUT 4 Ro CMRR = 20 log c -------------------------------------/ DV L e o
7
RC7352
PRODUCT SPECIFICATION
IOUT
R VL I/VOUT I/VIN V1 FI/MV I/VM
65-7352-03
2. CMRR is measured with V1 = +15V/-5V; R is RA, RB, RC or RD; IOUT = constant. This parameter is to define the current measurement error due to the input voltage V1. It guarantees all ranges and full scale IOUT. ae DV Mo CMRR = 20 log c ----------- / e DV 1 o
IOUT R RL
I/VOUT I/VIN FV/MI V1 I/VM VM
65-7352-04
3. Linearity is measured against two point straight line calibration with five measurement points. 4. Current Gain Error is measured with -full scale current to +full scale current. The ideal gain is 4. VM 2 - VM 1 Current Gain Error = ------------------------------------------------R ( I OUT2 - I OUT1 ) 5. Force current is measured with I/VOUT to ground with I/VIN = 0V. 6. Measured current offset is measured with I/VIN = 0V, Offset = (I/VM)/4R where R is RA, RB, RC, and RD.
8
PRODUCT SPECIFICATION
RC7352
AC Electrical Characteristics
+VS = 20V 3%, -VS = -10V 5%, TA = 25C, and external 0.05% tolerance resistors RA = 100kW, RB = 10kW, RC = 2kW, and RD = 50W unless otherwise specified.
Symbol
Parameters
Response Time High to Low Response Time Low to High Response Time (setting time)1 Force Current/Measure Voltage
Test Conditions
RLOAD = 10k, 5mV Overdrive RLOAD = 10k, 5mV Overdrive Range A Range B Range C Range D Voltage @ I/VM = -5.0V to +15V IF = Max
Min.
Typ.
Max.
Units
Comparator
tHL tLH tMZF 1.1 450 2.4 2.3 2.6 2.6 ms ns ms
Differential Amplifier
tMZF
Response Time (settling time)1 Force Voltage/Measure Current
Ranges A Ranges B Ranges C Ranges D Voltage @ I/VOUT = 5.0V to +15V IM = Max
2.4 2.5 2.6 2.7
ms
tMZF
Response Time (Settling
time)1
Ranges A, B, C, & D Voltage @ I/VOUT = -2.0V to +6.0V 30pF from CA to CB No Load
1.0
3
ms
tDS
Output Disable to Enable Time
20
ms
Notes: 1. Response Time (settling time) for Force Current/Measure Voltage mode is measured with 30pF from CA to CB and I/V IN Voltage Swings from -8.0V to +8.0V, and RL value for Range placed between I/VOUT and 5V. 500KW 50KW 10KW 250W A B C D
9
RC7352
PRODUCT SPECIFICATION
Application Example
C4 1pF RANGE D CURRENT LIMIT D1 1N4148 D2 I/VMX VOUT UPPER LIMIT R15 16 R13 100K VHF VOUT HIGH FAIL C5 3nF GND R17 100 5V R9 R8 R7 C1 1nF 1 2 3 4 5 6 7 8 X0 D1&2 RDIL VEE I/VMX VHF CA I/VOUT GND RA RADJ CAP_I RSI SI/V RS2 1N4148 +VS VLF I/VMN CB RD I/VIN RC VDIS VFB RB CAP_V CAP -VS V/IM 28 27 26 25 24 23 22 21 20 19 18 17 16 15 R16 50K R12 50 R11 2K R10 10K C3 5V R13 100K 6.8uF C7 3nF
*
+20V VPOS +VS C6
5V R13 100K VOUT LOW FAIL VOUT LOW LIMIT C8 1nF VLF I/VMN
*
I/VIN
R18 100K
I/VIN
5V
*
S1
DUT or LOAD
GND DUT GND
9 10 11 12 13 14
*
CV 50pF
1nF C9 300pF R6 100K
VDIS L H
VHS VLS I/VM OUTPUTS ENABLED OUTPUTS DISABLED VOLT/CURRENT MEASUREMENT V/IM
100K
100K
100K
* CI
50pF
RS1
SI/V
RS2
VNEG
-VS C2 6.8uF
-10V
RS1 RS2 RANGE L L A +/-20uA L H B +/-200uA H H C +/-1mA H L D +/-40mA
SI/V FUNCTION L H FORCE VOLTAGE FORCE CURRENT
* OPTIONAL PART SHORT RADJ TO GND FOR BEST DC ACCURACY
65-7352-05
10
PRODUCT SPECIFICATION
RC7352
Mechanical Dimensions
Symbol A A1 A2 B B1 D/E D1/E1 D3/E3 e J ND/NE N ccc Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. All dimensions and tolerances conform to ANSI Y14.5M-1982. 2. Corner and edge chamfer (J) = 45. 3. Dimension D1 and E1 do not include mold protrusion. Allowable protrusion is .101" (.25mm).
.165 .180 .090 .120 .020 -- .013 .021 .026 .032 .485 .495 .450 .456 .300 BSC .050 BSC .042 .048 7 28 -- .004
4.19 4.57 2.29 3.05 .51 -- .33 .53 .66 .81 12.32 12.57 11.43 11.58 7.62 BSC 1.27 BSC 1.07 1.22 7 28 -- 0.10
3
2
E E1 J
D
D1
D3/E3
B1 e J
A A1 A2 B -C- LEAD COPLANARITY
ccc C
11
RC7352
PRODUCT SPECIFICATION
Ordering Information
Part Number RC7352QA Package 28-pin PLCC
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 7/24/98 0.0m 002 Stock#DS30007352 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC73687
High Speed Dual Comparator
2.2 ns Propagation Delay Features
* 12 V max differential input voltage (for VCC = +10V, VEE = -5.2V) * Low propagation delays: -1.8 ns typical * Low delay dispersion (65 ps typical) and drift (4 ps/C typical) * 5 mV maximum input offset and 10 mV/C max. drift * 3 mA typical bias current; 50 pA typ. in disable mode * Common mode rejection 70 dB * Input disable mode (transparent to user) * Latch function * RC73687 is pin-for-pin compatible with 9687 comparators * Available in 16-pin SOIC, 20-pin PLCC or 16-pin PDIP
Description
The RC73687 is a very high speed dual comparator with latched input option and ECL compatible outputs capable of driving 50W terminated lines. The RC73687 is configured as two independent comparators and is pin-for-pin compatible with the industry standard 9687 comparators. The RC73687 low propagation delay (2.2 ns maximum), wide input common range (-4V to +8V) and low bias current (5 mA maximum) makes it ideal for monitoring outputs from TTL, CMOS, ECL and even GaAs devices in ATE applications. The propagation delay dispersion is only 80 ps (typical). The RC73687 features a high impedance input mode (ID) that reduces the bias current to 50 pA (typical), effectively removing the DC electrical load of the comparator inputs. The RC73687 also has a latch function to sample the input waveforms. Latches A and B are controlled by differential latch enable (LEA and LEB) ECL signals. The RC73687 is designed to operate with VCC supply voltages of +5.0V to +10V. Operation at +10V will provide a wider input common mode voltage range, (-4V to +8V) versus (-4V to +3V). It also provides a lower input capacitance (1.0 pF) versus (1.5 pF) The RC73687 is fabricated using Fairchild's high performance complementary bipolar process.
Applications
* * * * ATE pin electronics Threshold/peak voltage detector Level line receiver Limiting amplifier
Block Diagram
LEA RC73687 LEA
VIA+ VIAID VIDTH VIB+ VIB-
+ A - Latch A OA OA
+ B - Latch B OB OB
65-73687-01
VCC
GND
VEE
LEB
LEB
Rev. 1.1.1
RC73687
PRODUCT SPECIFICATION
Pin Assignments
PLCC
OA OA OB OB NC
SOIC and PDIP
3
2
1
20
GND LEA NC LEA VEE
4 5 6 7 8 9 10 11 12
19 18 17
GND LEB VIDTH LEB VCC
RC73687
16 15 14 13
OA OA GND LEA LEA VEE VIAVIA+
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
RC73687
OB OB GND LEB LEB VCC VIBVIB+
Note: Input disable mode not available on RC73687 SOIC package.
65-73687-02
VIA-
VIA+
VIB-
ID
Pin Description
Pin Number Name GND LEA, LEB LEA, LEB PLCC 4, 18 5, 17, 7, 15 SOIC, PDIP 3, 14 4, 13, 5, 12 Function Chip ground. This pin should be connected to the printed circuit board's ground plane at the pin. Differential digital enable inputs for latches A and B. Although these inputs will be normally driven by ECL signals, they have a wide enough common mode range that they may be driven by a TTL or CMOS signal provided the other input is tied to the appropriate threshold. If LEA or LEB inputs are tied to a logic high, then latches A and B are transparent, and output A or B will track changes to comparator A or B respectively. A logic low on LEA or LEB will disable the latch, and the outputs will reflect the input state just prior to the latch disable command. ID is the differential non-inverting input and VIDTH is the inverting input for enabling/disabling the comparator. Although the inputs will normally be driven by ECL signals, they have a wide enough common mode range that they may be driven by a TTL or CMOS signal provided the other input is tied to the appropriate threshold. When ID and VIDTH pins are left open they remain internally biased a +2.5 volt and -1.3 volts respectively and the circuit defaults to a comparator input enable state. A differential voltage of 400 mV must be exceeded to disable the comparator input. The disabled inputs will have a typical bias current of 50 pA. Differential outputs for comparator A. Differential outputs for comparator B. Each comparator can drive 50W terminated lines to 2 VTT. Quiet positive supply. The nominal voltage is 10V 3%. VCC should be bypassed to ground with a 0.01mF chip ceramic capacitor placed as close to the pins as possible. Quiet negative supply. The nominal voltage is -5.2 5%. VEE should be bypassed to ground with a 0.01 mF chip capacitor placed as close to the pins as possible. Differential non-inverting inputs. Differential inverting inputs.
ID, VIDTH
11, 16
--
OA, OA OB, OB VCC
2, 3 20, 19 14
1, 2 16, 15 11
VEE
8
6
VIA+, VIB+ VIA-, VIB-
1, 13 9, 12
8, 9 7, 10
2
VIB+
PRODUCT SPECIFICATION
RC73687
Absolute Maximum Ratings1
Parameter Positive power supply, VCC Negative power supply, VEE Difference between VCC and VEE Input voltage at VIA+, VIB+ Input Voltage at VIA-, VIBDifferential input voltage, cVIA+ - VIA- c, cVIB+ - VIB- c Input voltage at LEA, LEB Input voltage at LEA, LEB Input voltage at ID+, IDDifferential input voltage, cLEA - LEA c cLEB - LEB c Operating temperature range Storage temperature range Lead temperature range (Soldering 10 seconds) -40 -65 +85 +125 +260 C C C VEE-0.7 12 VCC VEE VCC, VEE 7 -6.3 16.6 VCC+0.7 Min. Max. +11.0 Units V V V V V V V V V V
Notes: 1. "Absolute maximum ratings" are those beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. If the device is subjected to the limits in the absolute maximum ratings for extended periods, its reliability may be impaired. The tables of Electrical Characteristics provide conditions for actual device operation.
Recommended Operating Conditions
Symbol TC VCC VEE VCC-VEE RT VTT Parameters Case operating temperature Positive supply voltage Negative supply voltage Difference between positive and negative supply Output termination load resistance Load termination supply voltage 45 -3.0 Min. 0 4.75 -5.45 5.0 -5.2 15.2 50 -2.0 Typ. Max. +70 10.3 -4.95 15.8 100 -2.0 Units C V V V W V
DC Electrical Characteristics (Normal Operating Conditions)
VCC = 5V 3%, VEE = -5.2V 5%, TA = 25C. Symbol Parameters Differential Analog Inputs VIA+, VIA-, VIB+, VIBVIA+, VIAAbsolute Input Voltage VIB+, VIB(Input Common Mode Range) VIAD , VIBD Differential Input Range VO Input Voltage Offset TCVO Input Voltage Offset Drift IIX+, IIXInput Bias Current IBOFFSET Input Bias Current Offset VIA+, VIAAnalog Input Capacitance VIB+, VIBZI Input Impedance CMRR Common Mode Rejection Ratio Test Conditions Min. -4.0 I VIX+ - VIX- I 3 33 5.0 5.0 1.0 500 75 Typ. Max. Units +3.0 7.0 7.0 15 12 2.0 V V mV mV/C mA mA pF KW dB 3
-3.0V to +3.0V Enabled Mode, -3.0V to +3.0V
-3V to +3V
60
PRODUCT SPECIFICATION
RC73687
DC Electrical Characteristics (continued)
Symbol Parameters Digital Inputs (Latch & Disable) VIA+, VIAAbsolute Input Voltage Digital Input Current Digital Outputs VOH Output Voltage High Output Voltage Low VOL Power Supply ICC Positive Supply Current IEE Negative Supply Current PSRR Power Supply Rejection Ratio PD Power Dissipation VID ID Differential Range Test Conditions Min. -2.0 0.4 Typ. Max. Units +5.0 +5.0 35 V V mA V V mA mA dB mW
cVID+ - VID- c
ECL 20
-1.05 -1.55 24 VCC 2.5%, VEE 2.5% VCC = 5.0V, VEE = -5.2V 60 44 80 360 28 50 400
DC Electrical Characteristics (High Supply Voltage Conditions)
VCC = 10V 3%, VEE = -5.2V 5%, TA = 25C. Symbol VIA+, VIAVIB+, VIBVIAD, VIBD VO TCVO IIX+, IIXIBOFFSET VIA+, VIAVIB+, VIBZI CMRR VIA+, VIAVID ID VOH VOL ICC IEE PSRR PD Parameters Absolute Input Voltage (Input Common Mode Range) Differential Input Range Input Voltage Offset Input Voltage Offset Drift Input Bias Current Input Bias Current Offset Analog Input Capacitance Input Impedance Common Mode Rejection Ratio Absolute Input Voltage Differential Range Digital Input Current Output Voltage High Output Voltage Low Positive Supply Current Negative Supply Current Power Supply Rejection Ratio Power Dissipation VCC 2.5%, VEE 2.5% VCC = 10V, VEE = -5.2V 30 55 75 586 700 -1.05 -1.55 35 65 cVID+ - VID- c -3.0V to +7.0V -2.0 0.4 ECL 20 -2.0V to +7.0V -2.0V to +7.0V cVIX+ - VIX- c 5.0 33 7.0 7.0 1.0 500 70 +5.0 +5.0 35 2.0 20 Test Conditions Min. -4.0 Typ. Max. Units +8.0 12 V V mV mV/C mA mA pF K dB V V mA V V mA mA dB mW Differential Analog Inputs VIA+, VIA-, VIB+, VIB-
Digital Inputs (Latch & Disable)
Digital Outputs
Power Supply
4
RC73687
PRODUCT SPECIFICATION
AC Electrical Characteristics
VCC = +10.0V 3%, VEE = -5.2V 5%, TA = 25C. Symbol tPD tS tD Parameters Propagation Delay H to L and L to H Delay Slew Between A and B Sides Delay Dispersion (0.2 V/ns Input slew rate 2.0 V/ns) ECL: VTH = -1V, +0.2V overdrive; VTL = -1.6V, -0.2V underdrive rising and falling edges TTL: VTH = +2.5V, +0.5V overdrive; VTL = 0.5V; -0.5V underdrive rising and falling edges 0.01% and 99.99% duty cycle 50 kHz, VIp-p = 5V, VTH = 2.5V (10 ns between measurements) 0 VS 3V; VTHA = 2.8V, VTHB = 0.2V; tIS = 2.5 V/ns, cVOH - VOL c 600 mVp-p Test Conditions Min. Typ. Max. Units 1.8 100 2.2 200 ns ps
150 150
ps
ps
DtPDTC DtPDTC
Prop. Delay Temp. Drift Delta Prop. Delay with Duty Cycle Minimum Pulse Width
4 50
ps/C ps
tPWmin
1.0
ns
tS tH tIPD tID tIE
Data to latch enable set up time Latch enable to data in hold time Latch enable to output high or low Active to Inhibit Inhibit to Active
1.0 0.5 1.5 5.0 10.0
ns ns ns ns ns
5
RC73687
PRODUCT SPECIFICATION
Notes:
6
PRODUCT SPECIFICATION
RC73687
Notes:
7
RC73687
PRODUCT SPECIFICATION
Notes:
8
PRODUCT SPECIFICATION
RC73687
20 Lead Plastic Leaded Chip Carrier (PLCC)
Symbol A A1 A2 B B1 D/E D1/E1 D3/E3 e J ND/NE N ccc Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. All dimensions and tolerances conform to ANSI Y14.5M-1982. 2. Corner and edge chamfer (J) = 45. 3. Dimension D1 and E1 do not include mold protrusion. Allowable protrusion is .245" (.101mm).
.165 .180 .090 .120 .020 -- .013 .021 .026 .032 .385 .395 .350 .356 .200 BSC .050 BSC .042 .048 5 20 -- .004
4.19 4.57 2.29 3.05 .51 -- .33 .53 .66 .81 9.78 10.03 8.89 9.04 5.08 BSC 1.27 BSC 1.07 1.22 5 20 -- 0.10
3
2
E E1 J
D
D1
D3/E3
e
B1
J
A A1 A2 B -C- LEAD COPLANARITY
ccc C
9
RC73687
PRODUCT SPECIFICATION
16 Lead Small Outline IC (SOIC) - .300" Body Width
Symbol A A1 B C D E e H h L N a ccc Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
.093 .104 .004 .012 .013 .020 .009 .013 .398 .413 .291 .299 .050 BSC .394 .010 .016 16 0 -- 8 .004 .419 .020 .050
2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 10.10 10.50 7.40 7.60 1.27 BSC 10.00 0.25 0.40 16 0 -- 8 0.10 10.65 0.51 1.27
3 6
16
9
E
H
1
8
D A e B A1 SEATING PLANE -C- LEAD COPLANARITY ccc C a
h x 45 C
L
10
PRODUCT SPECIFICATION
RC73687
16 Lead Plastic Dual Inline Package (PDIP) - .300" Body Width
Symbol A A1 A2 B B1 C D D1 E E1 e eB L N Inches Min. -- .015 .115 Max. .210 -- .195 Millimeters Min. -- .38 2.93 Max. 5.33 -- 4.95 Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E1" do not include mold flashing. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. Terminal numbers are shown for reference only. 4. "C" dimension does not include solder finish thickness. 5. Symbol "N" is the maximum number of terminals. 4 2
.014 .022 .045 .070 .008 .015 .745 .840 .005 -- .300 .325 .240 .280 .100 BSC -- .430 .115 .160 16
.36 .56 1.14 1.78 .20 .38 18.92 21.33 .13 -- 7.62 8.26 6.10 7.11 2.54 BSC -- 10.92 2.92 4.06 16
2
5
D 8 1
E1
D1
9
16
E e A A1 L B1 B eB A2 C
11
RC73687
PRODUCT SPECIFICATION
Ordering Information
Part Number RC73687NE RC73687QC RC73687MK Package 16-lead SOIC 20-lead PLCC 16-lead PDIP Operating Temperature Range 0C to +70C 0C to +70C 0C to +70C
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS30073687 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RC7B00
Low Skew Buffers
100MHz SDRAM Clock Buffers Features
18 Skew Controlled Output Supports up to four SDRAM DIMMs Skew between any two outputs is less than 250 pS I2C Serial Interface for Programming options Multiple Power and Ground Pins for Noise Reduction Single 3.3V Power Supply 48 Pin SSOP package
Description
The RC7B00 is a low voltage eighteen output clock buffer which supports 4 DIMMs. The skew between any two outputs is less than 250 pS and the Buffers can be enabled or disabled by programming via the I2C serial interface. The SDATA and SCLK serial inputs both have internal pull-up resistors. An Output Enable (OE) pin is also provided so that all the outputs can be tri-stated when held low. This pin is normally high and has an internal pull-up resistor.
Advanced Information
Applications
SDRAM Clock Buffers for IntelOs 440BX chip set
OE 0 1
SDRAM0:3 SDRAM4:7 SDRAM8:11 SDRAM12:15 SDRAM16:17 Hi-Z BUF_IN Hi-Z BUF_IN Hi-Z BUF_IN Hi-Z BUF_IN Hi-Z BUF_IN
Block Diagram
SDRAM0 SDATA SCLOCK SDRAM1 SDRAM2 SDRAM3 SDRAM4 SDRAM5 SDRAM6 SDRAM7 SDRAM8 BUF_IN SDRAM9 SDRAM10 SDRAM11 SDRAM12 SDRAM13 SDRAM14 SDRAM15 SDRAM16 SDRAM17 OE
Rev. 0.5.0
ADVANCED INFORMATION describes products that are not in full production at the time of printing. Specifications are based on design goals and limited characterization. They may change without notice. Contact Fairchild Semiconductor for current information.
RC7B00
PRODUCT SPECIFICATION
Pin Assignments
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 Pin# 1 2 3 4 5 6 7 8 9 10 11 12 Pin Name NC NC VDD SDRAM0 SDRAM1 VSS VDD SDRAM2 SDRAM3 VSS BUF_IN VDD Pin# 13 14 15 16 17 18 19 20 21 22 23 24 Pin Name SDRAM4 SDRAM5 VSS VDD SDRAM6 SDRAM7 VSS VDD SDRAM16 VSS VDD SDATA Pin# 25 26 27 28 29 30 31 32 33 34 35 36 Pin Name SCLOCK VSS VSS SDRAM17 VDD VSS SDRAM8 SDRAM9 VDD VSS SDRAM10 SDRAM11 Pin# 37 38 39 40 41 42 43 44 45 46 47 48 Pin Name VDD OE VSS SDRAM12 SDRAM13 VDD VSS SDRAM14 SDRAM15 VDD NC NC
Advanced Information
48 Pin SSOP
Pin Descriptions
Pin Name BUF_IN SDRAM0:3 SDRAM4:7 SDRAM8:11 SDRAM12:15 SDRAM16:17 OE SDATA SCLOCK VDD VDD VSS VSS NC Pin Number 11 4, 5, 8, 9 13, 14, 17, 18 31, 32, 35, 36 40, 41, 44, 45 21, 28 38 24 25 3, 7, 12, 16, 20, 29, 33, 37, 42, 46 23 6, 10, 15, 19, 22, 27, 30, 34, 39, 43 26 1, 2, 47, 48 Type IN OUT OUT OUT OUT OUT IN I/O IN Power Power Power Power NC Pin Function Description Input for clock buffers SDRAM Byte 0 clock outputs SDRAM Byte 1 clock outputs SDRAM Byte 2 clock outputs SDRAM Byte 3 clock outputs SDRAM clock outputs Output enable which will tri-state all the outputs when held low Serial Data input Serial Clock input Power supply at 3.3V for SDRAM buffers Power supply at 3.3V for I2C circuit Ground for SDRAM buffers Ground for I2C circuit No Connections.
2
PRODUCT SPECIFICATION
RC7B00
Absolute Maximum Ratings
Parameter Supply Voltage, VDD Input Voltage Output Applied Voltage Junction Temperature Storage Temperature Lead Soldering (10 seconds) -65 Min. -0.5 -0.5 -0.5 Typ. Max. 7 VDD+0.5 VDD+0.5 140 150 300 Units V V V C C C
Notes: 1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions. Functional operation under any of these conditions is NOT implied. 2. Applied voltage must be current limited to specified range, and measured with respect to GND. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current, flowing into the device.
Advanced Information
Operating Conditions
Parameter VDD Ambient Temperature Min. 3.135 0 Typ. 3.3 Max. 3.465 70 Units V
o
C
Electrical Characteristics TA = 0C to 70C, VDD = 3.3V+5%
Parameter VIL, Input low voltage VIH, Input high voltage IIL, Input low current (BUF_IN) IIH, Input high current (BUF_IN) IIL, Input low current (OE, SDATA, SCLOCK) IIH, Input high current (OE, SDATA, SCLOCK) VOL, Output low voltage @ IOL = 23mA VOH, Output high voltage @ IOH = -30mA IOL, Output low current @ VOL = 0.8V IOH, Output high current @ VOH = 2.0V IDD, Supply current @ f = 100MHz IDD, Supply current @ f = 66MHz IDD, Supply current @ OE = 0 CIN, Input capacitance FIN, Input frequency 5 150 2.6 40 -54 -50 5 0.4 Min. VSS-0.3 2.0 -5 5 Typ. Max. 0.8 VDD+0.5 Units V V A A A A V V mA mA mA mA mA pF MHz
3
RC7B00
PRODUCT SPECIFICATION
Switching Characteristics
Parameter TPD, Propagation delay TR, Rise time TF, Fall time TD, Duty cycle TEN, Output enable time TDIS, Output disable time TSK, Skew ZO, Output impedance Conditions VT = 1.5V 0.4 to 2.4V 2.4 to 0.4V VT = 1.5V VT = 1.5V VT = 1.5V VT = 1.5V 15 Min. 1 0.5 0.5 45 1 1 Typ. Max. 5 1.5 1.5 55 8 8 250 Units ns ns ns % ns ns ps
Advanced Information
Serial Data Interface
Signaling Requirements for the I2C Serial Port
To initiate communications with the serial port, a start bit is invoked. The start bit is defined as the SDATA line is brought low while the SCLOCK is held high. Once the start bit is initiated, valid data can then be sent. Data is considered to be valid when the clock goes to and remains in the high state. The data can change when the clock goes low. To terminate the transmission, a stop bit is invoked. The stop bit occurs when the SDATA line goes from a low to a high state while the SCLOCK is held high. See Figure below.
SDATA
SCLOCK
Start Bit
Data Valid
Change Data
Stop Bit
The data transfer rate is 100kbits/s in the standard mode and 400kbits/s in the fast mode. The serial protocol uses block writes only. Bytes are written with the lowest first and the highest last with the ability to stop after any complete byte
has been transferred. The clock driver is a slave/receiver only and is only capable of receiving data with the exception of sending acknowledgements. It is not capable of sending data.
4
PRODUCT SPECIFICATION
RC7B00
Byte writing sequence
The buffer is accessed when the slave address byte is received. Each byte of data is followed by an acknowledge bit. The address bit sequence is 1 1 0 1 0 0 1 followed by the R/W# bit (0). Bits are written with the Most Significant Bit (MSB) first. The MSB Bit is bit 7 and the LSB is bit 0. The Byte writing sequence is as shown in the table below.
Byte Sequence 1 2 3 4 5 6 7 8 9 10
Bit sequence Byte name Slave address Command Code Byte Count Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 Data Byte 4 Data Byte 5 Data Byte 6 X X X X 7 1 X X 6 1 X X 5 0 X X 4 1 X X 3 0 X X 2 0 X X 1 1 X X 0 0 X X
see table below see table below see table below
Advanced Information
X X X X
X X X X
X X X X
X X X X
X X X X
X X X X
X X X X
Data Bytes 0 to 2 Map
Bit Pin Name Description Data Byte0: SDRAM Active/Inactive Register (1 = enable, 0 = disable) 7 18 SDRAM7 (ACTIVE/INACTIVE) 6 17 SDRAM6 (ACTIVE/INACTIVE) 5 14 SDRAM5 (ACTIVE/INACTIVE) 4 13 SDRAM4 (ACTIVE/INACTIVE) 3 9 SDRAM3 (ACTIVE/INACTIVE) 2 8 SDRAM2 (ACTIVE/INACTIVE) 1 5 SDRAM1 (ACTIVE/INACTIVE) 0 4 SDRAM0 (ACTIVE/INACTIVE) Data Byte1: SDRAM Active/Inactive Register (1 = enable, 0 = disable) 7 45 SDRAM15 (ACTIVE/INACTIVE) 6 44 SDRAM14 (ACTIVE/INACTIVE) 5 41 SDRAM13 (ACTIVE/INACTIVE) 4 40 SDRAM12 (ACTIVE/INACTIVE) 3 36 SDRAM11 (ACTIVE/INACTIVE) 2 35 SDRAM10 (ACTIVE/INACTIVE) 1 32 SDRAM9 (ACTIVE/INACTIVE) 0 31 SDRAM8 (ACTIVE/INACTIVE) Data Byte 2: SDRAM Active/Inactive Register (1 = enable, 0=disable) 7 28 SDRAM17 (ACTIVE/INACTIVE) 6 21 SDRAM16 (ACTIVE/INACTIVE) 5 reserved reserved 4 reserved reserved 3 reserved reserved 2 reserved reserved 1 reserved reserved 0 reserved reserved
5
RC7B00
PRODUCT SPECIFICATION
Notes:
Advanced Information
6
PRODUCT SPECIFICATION
RC7B00
Mechanical Dimensions
48 pin SSOP
Symbol A A1 b c D E E1 e L N a ccc Inches Min. .095 .008 Max. .110 .016 Millimeters Min. 2.41 0.20 Max. 2.79 0.41 5 5 2, 4 2 3 6 Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 2. "D" and "E1" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5. "b" & "c" dimensions include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
.008 .0135 .005 .010 .620 .630 .395 .420 .291 .299 .025 BSC .020 .040 48 8 0 --.004
0.20 0.34 0.13 0.25 15.75 16.00 10.03 10.67 7.39 7.59 0.64 BSC 0.51 1.02 48 8 0 --0.13
Advanced Information
E E1
1
D A e b A1 SEATING PLANE -CLEAD COPLANARITY ccc C c a L
7
RC7B00
PRODUCT SPECIFICATION
Ordering lnformation
Product Number RC7B00 Temperature 0C to 70C Screening Package 48 SSOP Package Marking RC7B00
Advanced Information
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonable expected to result in a significant injury of the user.
Fairchild Semiconductor Corporation Americas Customer Response Center Tel:1-888-522-5372 Fairchild Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: Deutsch Tel: English Italy Tel: Tel: europe.support@nsc.com +49 (0) 8 141-35-0 +44 (0) 1 793-85-68-56 +39 (0) 2 57 5631
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
Fairchild Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Center, 5 Canto Rd. Tsimshatsui, Kowloon Hong Kong Tel:+852 2737-7200 Fax:+852 2314-0061
National Semiconductor Japan Ltd. Tel:81-3-5620-6175 Fax:81-3-5620-6179
www.fairchildsemi.com 1/98 0.0m Stock#DS50007B00 (c) 1998 Fairchild Semiconductor Corporation
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RCB001
Voltage Regulator Module (VRM) for Pentium(R) Pro Processors
Features
* * * * * * * * * Programmable 2.0V to 3.5V output from 5V supply Maximum output current 12.4A Typical Efficiency > 84% Total output accuracy typically 3% Short circuit protection Power Good output Output Enable function Excellent transient response Meets Intel Pentium Pro VRM specifications
Description
The RCB001 VRM module is a programmable DC-DC voltage regulator module designed to deliver the selectable processor core voltage required by the Pentium Pro microprocessor family. This VRM module provides the flexibility to board designers to support the entire Pentium Pro processor family with a single motherboard design. The RCB001 design takes full advantage of a proprietary Fairchild programmable DC-DC voltage controller IC which integrates the DAC function as well as the Power Good and Output Enable features. The result is a voltage regulator module that uses a minimum number of external components to achieve high reliability at a competitive cost. The RCB001 provides an extremely well regulated voltage selectable from 2.0V to 3.5V. Voltage selection is accomplished through a 4 bit digital input (VID0 - VID3) and can be incremented in 100mV steps. The Power Good open collector output provides a logic LOW state when an out-of-tolerance voltage is detected at the VRM output. Other features include high efficiency, short circuit protection, output enable and low package weight. The RCB001 VRM module is designed as a point-of-load converter for the Pentium Pro processor, thus minimizing the distribution losses normally occuring when drawing high currents from a centralized power supply.
Applications
* Pentium Pro motherboard VRM module * Programmable power supply module * Template for motherboard implementation
Block Diagram
5V
Vin VccP Vss
CPU
PWRGD
VID3 VID2 VID1 VID0
RCB001
Pentium is a registered trademark of Intel Corporation.
Rev 1.1.1
RCB001
PRODUCT SPECIFICATION
Mechanical Dimensions (mm):
78.74 MAX
6.50 MIN 3.81 TYP
38.1 MAX 7.62 MIN R1.52 TYP
Pin A1
10.67 TYP
1.65 REF
Pin Orientation
(Top View) (socket: AMPMOD2 532956-7 or equivalent)
Table 1. VRM Pin Definitions
Pin# 1 2 3 4
A1 B1
Row A 5VIN 5VIN 5VIN NC1 NC1 NC1 VID0 VID2 NC1 VCCP VSS VCCP VSS VCCP VSS VCCP VSS VCCP VSS VCCP
Row B 5VIN 5VIN 5VIN NC1 NC1 OUTEN2 VID1 VID3 PWRGD VSS VCCP VSS VCCP VSS VCCP VSS VCCP VSS VCCP VSS
5 6 7 8 9 10 11 12 13 14 15 16
A20 B20
17 18 19 20
Notes: 1. Not used on module; no current is drawn. 2. This pin is not used on the RCB001-12A.
2
PRODUCT SPECIFICATION
RCB001
VRM Connector Pin Reference
Pin Name Power-Good (PWRGD) (Open collector TTL output) Input/Output O Function PWRGD = High, output voltage within specifications PWRGD = Low, output voltage not within specifications (nominal or selected voltage 10%) The PWRGD signal will change to the proper state within 5ms of the output coming into or going out of its specified range. OUTEN = Floating or high, output enabled OUTEN = Low, output disabled and PWRGD = Low These four signals are used to indicate the voltage required by the processor. See Table 2. Module supply voltage. Processor core VCC Ground reference voltage.
Output Enable (OUTEN)1 (Open collector TTL input) Voltage Identification (VID0 to VID3) (Open collector TTL input) 5 VIN VCCP VSS
Note: 1. This pin is not used on the RCB001-12A.
I I I O I, O
Electrical Specifications
(VIN = +5V, TA = 0 to 70C unless otherwise specified) Parameter Input Specifications Input Voltage, VIN Output Specifications Output Voltage (VCCP) Range DC Output Current, IOUT Set Point Accuracy1 DC Load Regulation Line Regulation Output Ripple and Noise Output Temperature Drift Load Transient Cumulative Accuracy Efficiency General Specifications Switching Frequency Short Circuit Protection 650 16 kHz A ILOAD = 0.5A to 10A, 30A/mSec VID code 0010 (VCCP =3.3V) All Conditions, see Note 2 ILOAD = 0.5A ILOAD = 10A 40 80 Intel VID code, Table 2 RCB001-12 and RCB001-12A ILOAD = 5.25A, TA = 25C ILOAD = 0.5A to 12.4A 4.75 VIN 5.25 ILOAD = 10A, BW = 20MHz 2.0 0.5 0.8 0.8 0.1 30 +20 100 3 67 84 120 5 3.5 12.4 1.5 1.5 0.2 V A % % % mVpp ppm/C mV % % % Test Conditions Min. 4.75 Typ. 5 Max. 5.25 Units V
Notes: 1. Set Point Accuracy is defined as the static accuracy of the output voltage at 5.25A @ TA = 25 C. 2. Cumulative Accuracy includes Setpoint Accuracy, Output Temperature Drift, Line and Load Regulation, Output Ripple/Noise and Load Transient Response.
3
PRODUCT SPECIFICATION
RCB001
Table 2. Voltage Identification (VID) and Overall Regulation 1
Pentium Pro Processor Pins VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Min. 1.900 V 1.995V 2.090V 2.185V 2.280V 2.375V 2.470V 2.565V 2.660V 2.755V 2.850V 2.945V 3.040V 3.135V 3.230V 3.325V Output (VCCP) Nominal 2.0V 2.1V 2.2V 2.3V 2.4V 2.5V 2.6V 2.7V 2.8V 2.9V 3.0V 3.1V 3.2V 3.3V 3.4V 3.5V
Max.
2.100V 2.205V 2.310V 2.415V 2.520V 2.625V 2.730V 2.835V 2.940V 3.045V 3.150V 3.255V 3.360V 3.465V 3.570V 3.675V
0 = Processor pin connected to VSS 1 = Processor pin open Note: 1. Includes set point accuracy, load transient, ripple and noise, thermal drift, load regulation and line regulation.
Ordering Information
Part Number1 RCB001-12 RCB001-12A Input 5V 5V Maximum DC Output Current 12.4A 12.4A No Output Enable Comments
Note: 1. Please refer to our Application Note 42 (AP-42) for more information on the board level voltage regulator design using Fairchild's DC-DC voltage controllers (RC5040 and RC5042).
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock# DS3000B001 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RCB002
Voltage Regulator Module (VRM) for Pentium(R) P55C and K6TM Processors
Features
* * * * * * * * Fixed 2.8V, 2.9V or 3.2V output from 5V supply Maximum output current 7.5A for RCB002-8 Maximum output current 10A for RCB002-10 Typical efficiencies > 80% Short circuit protection Power Good output Excellent transient response Meets Intel's Pentium P55C and AMD's K6 power specifications
Description
The RCB002 VRM module is a DC-DC voltage regulator module designed to deliver the processor core voltage required by the P55C and K6 microprocessors. It offers board designers the flexibility to support the P55C and K6 processors with a modular add-in power supply. The RCB002 uses a proprietary Fairchild programmable DC-DC controller IC to deliver a precise output voltage to the CPU core without the need for external precision resistors. The result is a voltage regulator module with a minimum number of components to achieve high reliability at a competitive cost. The RCB002-8 can deliver 2.8V or 2.9V (factory preset) of extremely well regulated voltage at 6A of continuous current. This voltage can be used to address the P55C and the 166/200MHz K6. The RCB002-10 delivers 3.2V at 10A for the 233MHz K6. In addition, the Power Good open collector outputs a logic LOW when an out-of-tolerance voltage is detected at the VRM output. Other features include high efficiency, short circuit protection, and low package weight.
Applications
* Pentium and K6 motherboard 30-pin VRM module * Add-in power supply upgrade for P55C and K6 CPUs * Flexible motherboard designs
Block Diagram
5V Supply
3.3V Supply
Motherboard
Ground
RCB002
uP Core Supply
Power Good
Pentium is a registered trademark of Intel Corporation. K6 is a trademark of AMD Corporation.
Rev 1.0.1
RCB002
PRODUCT SPECIFICATION
Mechanical Dimensions (mm) - Viewed from connector side
20.00 max. 3.00 max.
6.50 min. 7.62 max.
45.70 max.
3.81 typ. A1 1.65 ref. 1.575 0.203 65.40 max. 10.67 0.013
Pin Orientation - Top View
(Socket: AMPMOD2 532956-5 or equivalent)
Table 1. VRM Connector Pin Definitions
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Note: 1. Not used by VRM module
Row A GND GND V121 VI/O1 V31 V31 VCORE VCORE GND VCORE PWRGD SENSE1 GND V5 V5
Row B GND GND VI/O1 VI/O1 V31 V31 VCORE VCORE VCORE VCORE UPVRM#1 DISABLE1 GND V5 V5
B1
A1
B15 A15
2
PRODUCT SPECIFICATION
RCB002
VRM Connector Pin Reference
Pin Description V5 V3 Input/ Output I I Function +5V supply voltage to support power to the CPU core. +3.3V supply to support power to the CPU I/O. These pins are connected directly to the VI/O pins so the 3.3V supply can be routed through the module header. If PWRGD = HIGH, the output voltage is within specifications. If PWRGD = LOW, the output voltage not within 10% of nominal. The PWRGD output will change to the proper state within 5ms of the output coming into or going out of its specified range. Processor core VCC. CPU I/O VCC. These pins are connected to the +3.3V input pins. Ground Reference.
PWRGD (Power Good) for Pentium Open collector TTL output VCORE VI/O GND
O
O O I,O
Electrical Specifications
(VIN = +5V, TA = 25C unless otherwise specified.) Parameter Input Specifications Controller supply voltage, VIN Output Specifications (RCB002-8) Output Voltage, VCORE Output Current, ICORE Load Transient1 ICORE = 0.5A to 7.5A, 20A/ms ICORE = 0.5A to 7.5A ICORE = 6A Load Regulation Efficiency Short Circuit Protection Output Specifications (RCB002-10) Output Voltage, VCORE Output Current, ICORE Load Transient Load Regulation Efficiency Short Circuit Protection General Specifications Set Point Accuracy2 Line Regulation Output Temperature Drift Switching Frequency Cumulative Accuracy3 ICORE = 3A VIN = 5.0V 0.25V TA = 0 to 60C ` 1.0 0.1 20 300 50 100 % % ppm/C kHz mV ICORE = 0.5A to 10A, 20A/ms ICORE = 0.5A to 10A ICORE = 8A 3.2 8.5 50 1.0 80 13 10 100 V A mV % % A 2.8 2.9 6 40 0.8 83 10 8.0 100 V V A mV % % A 4.75 5 5.25 V Test Conditions Min. Typ. Max. Units
Notes: 1. Refer to Intel's AP-580 for bulk capacitance decoupling recommendations. Four 100 mF Tantalum capacitors with 25mW ESR are recommended for optimum transient response. 2. Set Point Accurcy is defined as the static accuracy of the output voltage at 3A and TA = 25C. 3. Cumulative Accuracy includes Set Point Accuracy, Output Temperature Drift, Line and Load Regulation, and Output Ripple/Noise.
3
PRODUCT SPECIFICATION
RCB002
Ordering Information
Part Number RCB002-8/2.8 RCB002-8/2.9 RCB002-10 Output Current 8A 8A 10A Output Voltage 2.8V 2.9V 3.2V Input 5V DC 5V DC 5V DC
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock# DS3000B002 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RCB004
Voltage Regulator Module (VRM) for Pentium(R) Pro and Pentium II Processors
Features
* Programmable 1.3V to 3.5V output from 5V supply using 5-bit digital input * Maximum output current 13A * Typical efficiency > 83% * Output initial setpoint tolerance typically 1% * Short circuit protection with current foldback * Power Good output * Output Enable function * Excellent transient response * Meets Intel Pentium II VRM 8.1 specification
Description
The RCB004 is a non-synchronous programmable DC-DC VRM designed to deliver the selectable processor core voltage required by Pentium Pro and Pentium II microprocessors. This VRM offers the flexibility to support both the Pentium Pro and Pentium II processors with a single motherboard design. The RCB004 takes full advantage of a proprietary Fairchild Electronics programmable DC-DC controller IC that integrates the 5-bit DAC function, and Power Good and Output Enable features. The result is a VRM with a minimum number of components that achieves high reliability at a competitive cost. The synchronous counterpart to the RCB004, the RCB005, offers higher efficiency, which can be significant in the lower output range. The RCB004 provides an extremely well regulated selectable output voltage from 1.3V to 3.5V. Voltage selection is accomplished throught a 5-bit digital input (VID0 to VID4). The Power Good open collector outputs a logic LOW when an out-of-tolerance voltage is detected at the VRM output. Other features include high efficiency, short circuit protection, output enable, and low package weight. The RCB004 VRM module is designed as a point-of-load converter for Pentium Pro and Pentium II processors, minimizing the distribution losses normally occuring when drawing high currents from a centralized power supply.
Preliminary Information
Applications
* Motherboard VRM module * Programmable power supply module * Template for motherboard implementation
Block Diagram
5V Supply Ground P Core Supply Power Good
Motherboard
VID4 VID3 VID2 VID1 VID0
RCB004
65-RCB004-01
Pentium is a registered trademark of Intel Corporation.
Rev 0.9.7
PRELIMINARY INFORMATION describes products that are not in full production at the time of printing. Specifications are based on design goals and limited characterization. They may change without notice. Contact Fairchild Semiconductor for current information.
RCB004
PRODUCT SPECIFICATION
Pin Orientation - Top View
(Socket: AMPMOD2 532956-7 or equivalent)
Table 1. RCB004 Pin Definitions
Pin # 1 2 3 4 5 6 7 8 9 Row A 5Vin 5Vin 5Vin 12Vin NC1 NC1 VID0 VID2 VID4 VCCP VSS VCCP VSS VCCP VSS VCCP VSS VCCP VSS VCCP Row B 5Vin 5Vin 5Vin 12Vin NC1 OUTEN VID1 VID3 PWRGD VSS VCCP VSS VCCP VSS VCCP VSS VCCP VSS VCCP VSS
A1
B1
Preliminary Information
10 11 12 13 14 15
A20 B20
16 17 18 19 20
Note: 1. Not used on module; no current is drawn.
VRM Connector Pin Reference
Pin Description PWRGD (Power Good) Open collector TTL output. Input/ Output O Function If PWRGD = HIGH, output voltage withing specifications. If PWRGD = LOW, output voltage not within 10% of nominal. The PWRGD output will change to the proper state within 5ms of the output coming into or going out of its specified range. If OUTEN = HIGH (floating), output enabled. If OUTEN = LOW, output disabled and PWRGD output LOW. These five signals are used to indicate the voltage required by the processor. See Table 2. Primary module supply voltage. MOSFET bias supply voltage Processor core VCC. Ground.
OUTEN (Output Enable) Open collector TTL input. VID0 to VID4 (Voltage ID) Open collector TTL inputs. 5VIN 12VIN VCCP VSS
I I I I O I,O
2
PRODUCT SPECIFICATION
RCB004
Electrical Specifications
airflow, unless otherwise specified.) Parameter Input Specifications Primary Module Supply, 5Vin MOSFET Bias Supply, 12Vin Output Specifications
(VIN = +5V, TA = 0C to 60C, VID4-VID0 = 10111 (VCCP = 2.8V), 100LFM
Test Conditions
Min. 4.75 11.4 1.3 2.74 2.66 1.74 1.70
Typ. 5 12
Max. 5.25 12.6 3.5
Units V V V V V
Output Voltage Range, VccCORE See Table 2 Output Voltage Regulation Steady State1 Transient2 Output Voltage Regulation Steady State1 Transient2 Output Current, IccCORE Initial Voltage Setpoint Load Regulation Line Regulation Output Ripple Output Temperature Drift Efficiency Turn-on Response Time General Specifications Switching Frequency Short Circuit Protection IccCORE = 0.8A IccCORE = 13.2A IccCORE = 6A, TA = 25C IccCORE = 0.8A to 13.2A 5Vin = 4.75V to 5.25V 20MHz BW, IccCORE = 13.2A VccCORE = 2.8V IccCORE = 0.8 to 13.2A, 20A/ms VccCORE = 1.8V IccCORE = 0.8 to 11.7A, 20A/ms
2.80 2.80 1.80 1.80 20 30 2 20 +10
2.90 2.94 1.90 1.90 13.2
Preliminary Information
V V A mV mV mV mVp-p mV %
40 80
67 84 10 300 18
ms KHz A
Notes: 1. Steady State Voltage Regulation includes Initial Voltage Setpoint, DC load regulation, output ripple/noise and temperature drift. 2. The output voltage measured at the converter output will be within the voltage range specified as a result of a load transient occuring at a slew rate of 20A/ms. These specifications assume a minimum of 20 x 0.1mF ceramic capacitors are placed directly next to the CPU in order to provide adequate high-speed decoupling. Additional bulk capacitors may be required directly next to the CPU when using any VRM; see Application Bulletin AB 5 for details.
Mechanical Dimensions (mm)
3.00 MAX 20.00 MAX 78.74 MAX
6.50 MIN 3.81 TYP
38.1 MAX 7.62 MAX R1.52 TYP
Pin A1 1.575 0.203 1.65 REF
10.67 TYP
3
PRODUCT SPECIFICATION
RCB004
Table 2. Output Voltage vs. Voltage Identification Code
Nominal Voltage to CPU (VccCORE) 1.30V 1.35V 1.40V 1.45V 1.50V 1.55V 1.60V 1.65V 1.70V 1.75V 1.80V 1.85V 1.90V 1.95V 2.00V 2.05V Nominal Voltage to CPU (VccCORE) 2.0V 2.1V 2.2V 2.3V 2.4V 2.5V 2.6V 2.7V 2.8V 2.9V 3.0V 3.1V 3.2V 3.3V 3.4V 3.5V
VID4 0 0 0 0 0 0 0
VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
Preliminary Information
0 0 0 0 0 0 0 0 0
Note: 1. "0" indicates processor pin is tied to 0V (VSS), "1" indicates it is tied to 5V or is open.
Ordering Information
Part Number RCB004-12 Input 5V DC Output Current 13A
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 7/24/98 0.0m 001 Stock# DS3000B004 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RCB005-K
5 Bit Voltage Regulator Module (VRM) for Pentium(R) II Processors
For 5V Input Voltage
Features
* * * * * * * * Programmable 1.3V to 3.5V output Output current to 15A 5-bit digital input selects output voltage Current limiting short-circuit protection Power Good output Output Enable function Excellent transient response Meets Intel VRM specifications
Description
The RCB005-K is a programmable DC-DC VRM designed to deliver the selectable processor core voltage required by Pentium II microprocessors. This VRM converts the +5V power supply voltage to the voltage required by the CPU. The RCB005-K takes full advantage of Fairchild's RC5051 programmable DC-DC controller IC, utilizing synchronous architecture for maximum efficiency. This VRM integrates a 5-bit DAC function, Power Good, and Output Enable features. The result is a VRM with a minimum number of components that achieves high reliability at a competitive cost. The RCB005-K provides an extremely well regulated selectable output voltage from 1.3V to 3.5V. Voltage selection is accomplished through a 5-bit digital input. The Power Good output provides a logic LOW when an out-of-tolerance voltage is detected at the VRM output. Other features include high efficiency, short-circuit and over-voltage protection, output enable, and low package weight. The RCB005-K VRM module is designed as a point-of-load converter for Pentium II (Klamath type) processors, minimizing the distribution losses normally occurring when drawing high currents from a centralized power supply.
Applications
* Pentium II (Klamath type) 233--300MHz VRM
Block Diagram
5V Supply Ground P Core Supply Power Good
Motherboard
12V MOSFET Bias VID4 VID3 VID2 VID1 VID0
RCB005-K
65-RCB005-1
Pentium is a registered trademark of Intel Corporation.
Rev 1.0.0
RCB005
PRODUCT SPECIFICATION
Pin Orientation -- Top View
(Socket: AMPMOD2 532956-7 or equivalent)
Table 1. RCB005-K Pin Definitions
Pin # 1 2 3 Row A 5Vin 5Vin 5Vin 12Vin 12Vin NC1 VID0 VID2 VID4 VccCORE Vss VccCORE Vss VccCORE Vss VccCORE Vss VccCORE Vss VccCORE Row B 5Vin 5Vin 5Vin 12Vin NC1 OUTEN VID1 VID3 PWRGD Vss VccCORE Vss VccCORE Vss VccCORE Vss VccCORE Vss VccCORE Vss
A1
B1
4 5 6 7 8 9 10 11 12 13 14 15
A20 B20
65-RCB005-2
16 17 18 19 20
Note: 1. Not used on module; no current is drawn.
VRM Connector Pin Reference
Pin Description 5Vin 12Vin OUTEN (Output Enable) Open collector TTL input. VID0 to VID4 (Voltage Identification Code) Open collector TTL inputs. PWRGD (Power Good) Open collector TTL output. Input/Output I I I I Function Primary module supply voltage. MOSFET bias supply voltage. If OUTEN = HIGH (floating), output enabled.If OUTEN = LOW, output disabled and PWRGD output LOW. These five signals are used to indicate the voltage required by the processor. See Table 2. If PWRGD = HIGH, output voltage within specifications. If PWRGD = LOW, output voltage not within 10% of nominal. The PWRGD output will change to the proper state within 5ms of the output coming into or going out of its specified range. Processor core voltage. Ground.
O
VccCORE Vss
O I, O
2
PRODUCT SPECIFICATION
RCB005
Table 2. Output Voltage vs. Voltage Identification Code
Nominal Voltage to CPU (VccCORE) 1.30V 1.35V 1.40V 1.45V 1.50V 1.55V 1.60V 1.65V 1.70V 1.75V 1.80V 1.85V 1.90V 1.95V 2.00V 2.05V Nominal Voltage to CPU (VccCORE) 2.0V 2.1V 2.2V 2.3V 2.4V 2.5V 2.6V 2.7V 2.8V 2.9V 3.0V 3.1V 3.2V 3.3V 3.4V 3.5V
VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
Note: 1. "0" indicates processor pin is tied to 0V (VSS) "1" indicates it is tied to 5V or is open.
3
RCB005
PRODUCT SPECIFICATION
Electrical Specifications
5Vin = +5V, 12Vin = +12V, TA = 0C to 60C, VccCORE = 2.8V, and airflow of 100LFM, unless otherwise specified. Parameter Input Specifications Primary Module Supply, 5Vin MOSFET Bias Supply, 12Vin Output Specifications Output Voltage Range, VccCORE See Table 2 Output Voltage Regulation Steady State1,2 Transient1,3 Output Current, IccCORE Initial Voltage Setpoint Load Regulation Line Regulation Output Ripple Output Temperature Drift Efficiency Turn-on Response Time General Specifications Switching Frequency Short Circuit Protection 300 18 kHz A IccCORE = 0.5A IccCORE = 14.2A 40 80 IccCORE = 6A, TA = 25C IccCORE = 0.8A to 14.2A 5Vin = 4.75V to 5.25V 20MHz BW, IccCORE = 14.2A VccCORE = 2.8V, IccCORE, Max = 14.2A VccCORE = 2.8V, IccCORE = 1.0 to 14.2A 1.3 2.74 2.67 0.3 20 -40 2 20 +10 67 82 10 2.80 2.80 3.5 2.90 2.93 15 A mV mV mV mVp-p mV % ms V V 4.75 11.4 5 12 5.25 12.6 V V Test Conditions Min. Typ. Max. Units
Notes: 1. The voltage tolerance is measured at the DC-DC converter Header Output on the motherboard. 2. The Steady State Voltage Regulation includes Initial Voltage Setpoint, DC load regulation, Output Ripple and temperature drift, measured with a digital voltmeter with 1mV resolution. IccCORE, MIN = 0.1A unless otherwise specified. 3. The output voltage is measured using the Intel provided EMT Tester (Rev. 1.0). It is assumed that a minimum of 20 x 0.1mF ceramic capacitors are placed directly next to the CPU to provide adequate high-speed decoupling. Additional bulk capacitors may be required as close as possible to the CPU socket on the motherboard when using the VRM. See Application Bulletin AB 5 for details.
4
PRODUCT SPECIFICATION
RCB005
Transient Plots
5
RCB005
PRODUCT SPECIFICATION
Notes:
6
PRODUCT SPECIFICATION
RCB005
Mechanical Dimensions (mm)
3.00 MAX 20.00 MAX 78.74 MAX
6.50 MIN 3.81 TYP
38.1 MAX 7.62 MAX R1.52 TYP
Pin A1 1.575 0.203 1.65 REF
10.67 TYP
7
RCB005
PRODUCT SPECIFICATION
Ordering Information
Part Number RCB005-K Input 5V DC Output Current 15A
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS300B005-K O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RCB005
5 Bit Voltage Regulator Module (VRM) for Pentium(R) II Processors
For 5V Power Supply
Features
* * * * * * * * * * Programmable 1.3V to 3.5V output Output current to 15A 5-bit digital input selects output voltage Typical efficiency > 82% DC output accuracy within 60mV Current limiting short-circuit protection Power Good output Output Enable function Excellent transient response Meets Intel VRM specifications
Description
The RCB005 is a programmable DC-DC VRM designed to deliver the selectable processor core voltage required by Pentium II microprocessors. This VRM converts the +5V power supply voltage to the voltage required by the CPU. The RCB005 takes full advantage of Raytheon's RC5051 programmable DC-DC controller IC, utilizing synchronous architecture for maximum efficiency. This VRM integrates a 5-bit DAC function, Power Good, and Output Enable features. The result is a VRM with a minimum number of components that achieves high reliability at a competitive cost. The RCB005 provides an extremely well regulated selectable output voltage from 1.3V to 3.5V. Voltage selection is accomplished through a 5-bit digital input. The Power Good output provides a logic LOW when an out-of-tolerance voltage is detected at the VRM output. Other features include high efficiency, short-circuit and over-voltage protection, output enable, and low package weight. The RCB005 VRM module is designed as a point-of-load converter for Pentium II processors, minimizing the distribution losses normally occuring when drawing high currents from a centralized power supply.
Applications
* Pentium II Klamath VRM * Next generation Pentium II VRM
Block Diagram
5V Supply Ground P Core Supply Power Good
Motherboard
12V MOSFET Bias VID4 VID3 VID2 VID1 VID0
RCB005
65-RCB005-1
Pentium is a registered trademark of Intel Corporation.
Rev 1.1.0
RCB005
PRODUCT SPECIFICATION
Pin Orientation -- Top View
(Socket: AMPMOD2 532956-7 or equivalent)
Table 1. RCB005 Pin Definitions
Pin # 1 2 3 Row A 5Vin 5Vin 5Vin 12Vin 12Vin NC1 VID0 VID2 VID4 VccCORE Vss VccCORE Vss VccCORE Vss VccCORE Vss VccCORE Vss VccCORE Row B 5Vin 5Vin 5Vin 12Vin NC1 OUTEN VID1 VID3 PWRGD Vss VccCORE Vss VccCORE Vss VccCORE Vss VccCORE Vss VccCORE Vss
A1
B1
4 5 6 7 8 9 10 11 12 13 14 15
A20 B20
65-RCB005-2
16 17 18 19 20
Note: 1. Not used on module; no current is drawn.
VRM Connector Pin Reference
Pin Description 5Vin 12Vin OUTEN (Output Enable) Open collector TTL input. VID0 to VID4 (Voltage Identification Code) Open collector TTL inputs. PWRGD (Power Good) Open collector TTL output. Input/Output I I I I Function Primary module supply voltage. MOSFET bias supply voltage. If OUTEN = HIGH (floating), output enabled.If OUTEN = LOW, output disabled and PWRGD output LOW. These five signals are used to indicate the voltage required by the processor. See Table 2. If PWRGD = HIGH, output voltage within specifications. If PWRGD = LOW, output voltage not within 10% of nominal. The PWRGD output will change to the proper state within 5ms of the output coming into or going out of its specified range. Processor core voltage. Ground.
O
VccCORE Vss
O I, O
2
PRODUCT SPECIFICATION
RCB005
Table 2. Output Voltage vs. Voltage Identification Code
Nominal Voltage to CPU (VccCORE) 1.30V 1.35V 1.40V 1.45V 1.50V 1.55V 1.60V 1.65V 1.70V 1.75V 1.80V 1.85V 1.90V 1.95V 2.00V 2.05V Nominal Voltage to CPU (VccCORE) 2.0V 2.1V 2.2V 2.3V 2.4V 2.5V 2.6V 2.7V 2.8V 2.9V 3.0V 3.1V 3.2V 3.3V 3.4V 3.5V
VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
Note: 1. "0" indicates processor pin is tied to 0V (VSS) "1" indicates it is tied to 5V or is open.
3
PRODUCT SPECIFICATION
RCB005
Electrical Specifications
5Vin = +5V, 12Vin = +12V, TA = 0C to 60C, VccCORE = 2.8V, and airflow of 100LFM, unless otherwise specified. Parameter Input Specifications Primary Module Supply, 5Vin MOSFET Bias Supply, 12Vin Output Specifications Output Voltage Range, VccCORE See Table 2 Output Voltage Regulation Output Voltage Regulation Steady State Transient
3 2 2
Test Conditions
Min. 4.75 11.4 1.3 2.74 2.67 1.94 1.90 0.3
Typ. 5 12
Max. 5.25 12.6 3.5
Units V V V V V A mV mV mV mVp-p mV %
VccCORE = 2.8V, IccCORE, Max = 14.2A VccCORE = 2.8V, IccCORE = 1.0 to 14.2A VccCORE = 2.0V, IccCORE, Max = 11.1A VccCORE = 2.0V, IccCORE = 0.5 to 11.1A IccCORE = 6A, TA = 25C IccCORE = 0.8A to 14.2A 5Vin = 4.75V to 5.25V 20MHz BW, IccCORE = 14.2A IccCORE = 0.5A IccCORE = 14A
2.80 2.80 2.0 2.0 20 -40 2 20 +10
2.90 2.93 2.06 2.10 15
Steady State Transient3
Output Current, IccCORE Initial Voltage Setpoint Load Regulation Line Regulation Output Ripple Output Temperature Drift Efficiency Turn-on Response Time General Specifications Switching Frequency Short Circuit Protection
40 80
67 82 10 300 18
ms kHz A
Notes: 1. The voltage tolerance is measured at the DC-DC converter Header Output on the motherboard. 2. The Steady State Voltage Regulation includes Initial Voltage Setpoint, DC load regulation, Output Ripple and temperature drift, measured with a digital voltmeter with 1mV resolution. IccCORE, MIN = 0.1A unless otherwise specified. 3. The output voltage is measured using the Intel provided EMT Tester (Rev. 1.0). It is assumed that a minimum of 20 x 0.1 F ceramic capacitors are placed directly next to the CPU to provide adequate high-speed decoupling. Additional bulk capacitors may be required as closely as possible to the CPU socket on the motherboard when using the VRM. See Application Bulletin AB 5 for details.
4
PRODUCT SPECIFICATION
RCB005
Transient Plots
5
RCB005
PRODUCT SPECIFICATION
Notes:
6
PRODUCT SPECIFICATION
RCB005
Mechanical Dimensions (mm)
3.00 MAX 20.00 MAX 78.74 MAX
6.50 MIN 3.81 TYP
38.1 MAX 7.62 MAX R1.52 TYP
Pin A1 1.575 0.203 1.65 REF
10.67 TYP
7
RCB005
PRODUCT SPECIFICATION
Ordering Information
Part Number RCB005 Input 5V DC Output Current 15A
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonable expected to result in a significant injury of the user.
Fairchild Semiconductor Corporation Americas Customer Response Center Tel:1-888-522-5372 Fairchild Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: Deutsch Tel: English Italy Tel: Tel: europe.support@nsc.com +49 (0) 8 141-35-0 +44 (0) 1 793-85-68-56 +39 (0) 2 57 5631
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
Fairchild Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Center, 5 Canto Rd. Tsimshatsui, Kowloon Hong Kong Tel:+852 2737-7200 Fax:+852 2314-0061
National Semiconductor Japan Ltd. Tel:81-3-5620-6175 Fax:81-3-5620-6179
www.fairchildsemi.com 2/98 0.0m Stock# DS3000B005 (c) 1998 Fairchild Semiconductor Corporation
www.fairchildsemi.com
RCB006-K
5 Bit Voltage Regulator Module (VRM) for Pentium(R) Pro and Pentium II Processors
For 12V Input Voltage Features
* * * * * * * * Programmable 1.3V to 3.5V output Output current to 15A 5-bit digital input selects output voltage Current limiting short-circuit protection Power Good output Output Enable function Excellent transient response Meets Intel VRM specifications
Description
The RCB006-K is a programmable DC-DC VRM designed to deliver the selectable processor core voltage required by Pentium Pro and Pentium II (Klamath type) processors. This VRM converts the +12V power supply voltage to the voltage required by the CPU core. By taking advantage of Fairchild's RC5051 programmable DC-DC controller IC, the RCB006-K utilizes a synchronous architecture for maximum efficiency. In addition, this VRM integrates a 5-bit DAC function, Power Good, and Output Enable features. The result is a VRM with a minimum number of components that achieves high reliability at a competitive cost. The RCB006-K provides an extremely well regulated selectable output voltage from 1.3V to 3.5V. Voltage selection is accomplished through a 5-bit digital input. The Power Good output provides a logic LOW when an out-of-tolerance voltage is detected at the VRM output. Other features include high efficiency, short-circuit and over-voltage protection, output enable, and low package weight. The RCB006-K has been designed as a point-ofload converter for Pentium II and Pentium Pro processors, minimizing the distribution losses normally occurring when drawing high currents from a centralized power supply.
Applications
* Pentium Pro VRM * Pentium II (Klamath type) VRM
Block Diagram
12V Supply Ground P Core Supply Power Good
Motherboard
VID4 VID3 VID2 VID1 VID0
RCB006-K
65-RCB006-1
Pentium is a registered trademark of Intel Corporation.
Rev 1.0.0
RCB006
PRODUCT SPECIFICATION
Pin Orientation -- Top View
(Socket: AMPMOD2 532956-7 or equivalent)
Table 1. RCB006-K Pin Definitions
Pin # 1 2 3 Row A 5Vin 5Vin 5Vin 12Vin 12Vin NC1 VID0 VID2 VID4 VccCORE Vss VccCORE Vss VccCORE Vss VccCORE Vss VccCORE Vss VccCORE Row B 5Vin 5Vin 5Vin 12Vin NC1 OUTEN VID1 VID3 PWRGD Vss VccCORE Vss VccCORE Vss VccCORE Vss VccCORE Vss VccCORE Vss
A1
B1
4 5 6 7 8 9 10 11 12 13 14 15
A20 B20
65-RCB005-2
16 17 18 19 20
Note: 1. Not used on module; no current is drawn.
VRM Connector Pin Reference
Pin Description 12Vin 5Vin OUTEN (Output Enable) Open collector TTL input. VID0 to VID4 (Voltage Identification Code) Open collector TTL inputs. PWRGD (Power Good) Open collector TTL output. Input/Output I I I I IC bias supply voltage. If OUTEN = HIGH (floating), output enabled.If OUTEN = LOW, output disabled and PWRGD output LOW. These five signals are used to indicate the voltage required by the processor. See Table 2. If PWRGD = HIGH, output voltage within specifications. If PWRGD = LOW, output voltage not within 10% of nominal. The PWRGD output will change to the proper state within 5ms of the output coming into or going out of its specified range. Processor core voltage. Ground. Function Primary module supply voltage.
O
VccCORE Vss
O I, O
2
PRODUCT SPECIFICATION
RCB006
Table 2. Output Voltage vs. Voltage Identification CodeNote:
Nominal Voltage to CPU (VccCORE) 1.30V 1.35V 1.40V 1.45V 1.50V 1.55V 1.60V 1.65V 1.70V 1.75V 1.80V 1.85V 1.90V 1.95V 2.00V 2.05V Nominal Voltage to CPU (VccCORE) 2.0V 2.1V 2.2V 2.3V 2.4V 2.5V 2.6V 2.7V 2.8V 2.9V 3.0V 3.1V 3.2V 3.3V 3.4V 3.5V
VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
Note: 1. "0" indicates processor pin is tied to 0V (VSS) "1" indicates it is tied to 5V or is open.
3
RCB006
PRODUCT SPECIFICATION
Electrical Specifications
5Vin = +5V, 12Vin = +12V, TA = 0C to 60C, VccCORE = 2.8V, and airflow of 100LFM, unless otherwise specified. Parameter Input Specifications Primary Module Supply, 12Vin IC Bias Supply, 5Vin Output Specifications Output Voltage Range, VccCORE See Table 2 Output Voltage Regulation Steady State1,2 Transient1,3 Output Current, IccCORE Initial Voltage Setpoint Load Regulation Line Regulation Output Ripple Output Temperature Drift Efficiency Turn-on Response Time General Specifications Switching Frequency Short Circuit Protection 120 18 kHz A IccCORE = 0.5A IccCORE = 14.2A 40 80 IccCORE = 6A, TA = 25C IccCORE = 0.8A to 14.2A 5Vin = 4.75V to 5.25V 20MHz BW, IccCORE = 14.2A VccCORE = 2.8V, IccCORE, Max = 14.2A VccCORE = 2.8V, IccCORE = 1.0 to 14.2A 1.3 2.74 2.67 0.3 20 -40 2 20 +10 65 82 10 2.80 2.80 3.5 2.90 2.93 15 A mV mV mV mVp-p mV % ms V V 11.4 4.75 12.0 5.0 12.6 5.25 V V Test Conditions Min. Typ. Max. Units
Notes: 1. The voltage tolerance is measured at the DC-DC converter Header Output on the motherboard. 2. The Steady State Voltage Regulation includes Initial Voltage Setpoint, DC load regulation, Output Ripple and temperature drift, measured with a digital voltmeter with 1mV resolution. IccCORE, MIN = 0.1A unless otherwise specified. 3. The output voltage is measured using the Intel provided EMT Tester (Rev. 1.0). It is assumed that a minimum of 20 x 0.1mF ceramic capacitors are placed directly next to the CPU to provide adequate high-speed decoupling. Additional bulk capacitors may be required as close as possible to the CPU socket on the motherboard when using the VRM. See Application Bulletin AB 5 for details.
4
PRODUCT SPECIFICATION
RCB006
Transient Plots
5
RCB006
PRODUCT SPECIFICATION
Notes:
6
PRODUCT SPECIFICATION
RCB006
Mechanical Dimensions (mm)
3.00 MAX 20.00 MAX 78.74 MAX
6.50 MIN 3.81 TYP
38.1 MAX 7.62 MAX R1.52 TYP
Pin A1 1.575 0.203 1.65 REF
10.67 TYP
7
RCB006
PRODUCT SPECIFICATION
Ordering Information
Part Number RCB006-K Input 12V DC Output Current 15A
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 7/24/98 0.0m 002 Stock#DS300B006-K O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RCB006
5 Bit Voltage Regulator Module (VRM) for Pentium(R) II Processors
For 12V Input Voltage Features
* * * * * * * * * * Programmable 1.3V to 3.5V output Output current to 15A 5-bit digital input selects output voltage Typical efficiency > 82% DC output accuracy within 60mV Current limiting short-circuit protection Power Good output Output Enable function Excellent transient response Meets Intel VRM specification 8.2
Description
The RCB006 is a programmable DC-DC VRM designed to deliver the selectable processor core voltage required by Pentium II and Pentium Pro processors. This VRM converts the +12V power supply voltage to the voltage required by the CPU core. By taking advantage of Raytheon's RC5051 programmable DC-DC controller IC, the RCB006 utilizes a synchronous architecture for maximum efficiency. In addition, this VRM integrates a 5-bit DAC function, Power Good, and Output Enable features. The result is a VRM with a minimum number of components that achieves high reliability at a competitive cost. The RCB006 provides an extremely well regulated selectable output voltage from 1.3V to 3.5V. Voltage selection is accomplished through a 5-bit digital input. The Power Good output provides a logic LOW when an out-of-tolerance voltage is detected at the VRM output. Other features include high efficiency, short-circuit and over-voltage protection, output enable, and low package weight. The RCB006 has been designed as a point-of-load converter for Pentium II and Pentium Pro processors, minimizing the distribution losses normally occuring when drawing high currents from a centralized power supply.
Applications
* Pentium II Klamath VRM * Next generation Pentium II VRM
Block Diagram
12V Supply Ground P Core Supply Power Good
Motherboard
VID4 VID3 VID2 VID1 VID0
RCB006
65-RCB006-1
Pentium is a registered trademark of Intel Corporation.
Rev 1.1.0
RCB006
PRODUCT SPECIFICATION
Pin Orientation -- Top View
(Socket: AMPMOD2 532956-7 or equivalent)
Table 1. RCB006 Pin Definitions
Pin # 1 2 3 Row A 5Vin 5Vin 5Vin 12Vin 12Vin NC1 VID0 VID2 VID4 VccCORE Vss VccCORE Vss VccCORE Vss VccCORE Vss VccCORE Vss VccCORE Row B 5Vin 5Vin 5Vin 12Vin NC1 OUTEN VID1 VID3 PWRGD Vss VccCORE Vss VccCORE Vss VccCORE Vss VccCORE Vss VccCORE Vss
A1
B1
4 5 6 7 8 9 10 11 12 13 14 15
A20 B20
65-RCB005-2
16 17 18 19 20
Note: 1. Not used on module; no current is drawn.
VRM Connector Pin Reference
Pin Description 12Vin 5Vin OUTEN (Output Enable) Open collector TTL input. VID0 to VID4 (Voltage Identification Code) Open collector TTL inputs. PWRGD (Power Good) Open collector TTL output. Input/Output I I I I IC bias supply voltage. If OUTEN = HIGH (floating), output enabled.If OUTEN = LOW, output disabled and PWRGD output LOW. These five signals are used to indicate the voltage required by the processor. See Table 2. If PWRGD = HIGH, output voltage within specifications. If PWRGD = LOW, output voltage not within 10% of nominal. The PWRGD output will change to the proper state within 5ms of the output coming into or going out of its specified range. Processor core voltage. Ground. Function Primary module supply voltage.
O
VccCORE Vss
O I, O
2
PRODUCT SPECIFICATION
RCB006
Table 2. Output Voltage vs. Voltage Identification CodeNote:
Nominal Voltage to CPU (VccCORE) 1.30V 1.35V 1.40V 1.45V 1.50V 1.55V 1.60V 1.65V 1.70V 1.75V 1.80V 1.85V 1.90V 1.95V 2.00V 2.05V Nominal Voltage to CPU (VccCORE) 2.0V 2.1V 2.2V 2.3V 2.4V 2.5V 2.6V 2.7V 2.8V 2.9V 3.0V 3.1V 3.2V 3.3V 3.4V 3.5V
VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
Note: 1. "0" indicates processor pin is tied to 0V (VSS) "1" indicates it is tied to 5V or is open.
3
RCB006
PRODUCT SPECIFICATION
Electrical Specifications
5Vin = +5V, 12Vin = +12V, TA = 0C to 60C, VccCORE = 2.8V, and airflow of 100LFM, unless otherwise specified. Parameter Input Specifications Primary Module Supply, 12Vin IC Bias Supply, 5Vin Output Specifications Output Voltage Range, VccCORE See Table 2 Output Voltage Regulation Output Voltage Regulation Steady State Transient
3 2 2
Test Conditions1
Min. 11.4 4.75 1.3 2.74 2.67 1.94 1.90 0.3
Typ. 12.0 5.0
Max. 12.6 5.25 3.5
Units V V V V V A mV mV mV mVp-p mV %
VccCORE = 2.8V, IccCORE, Max = 14.2A VccCORE = 2.8V, IccCORE = 1.0 to 14.2A VccCORE = 2.0V, IccCORE, Max = 11.1A VccCORE = 2.0V, IccCORE = 0.5 to 11.1A IccCORE = 6A, TA = 25C IccCORE = 0.8A to 14.2A 5Vin = 4.75V to 5.25V 20MHz BW, IccCORE = 14.2A IccCORE = 0.5A IccCORE = 14A
2.80 2.80 2.0 2.0 20 -40 2 20 +10
2.90 2.93 2.06 2.10 15
Steady State Transient3
Output Current, IccCORE Initial Voltage Setpoint Load Regulation Line Regulation Output Ripple Output Temperature Drift Efficiency Turn-on Response Time General Specifications Switching Frequency Short Circuit Protection
40 80
65 82 10 120 18
ms kHz A
Notes: 1. The voltage tolerance is measured at the DC-DC converter Header Output on the motherboard. 2. The Steady State Voltage Regulation includes Initial Voltage Setpoint, DC load regulation, Output Ripple and temperature drift, measured with a digital voltmeter with 1mV resolution. IccCORE, MIN = 0.1A unless otherwise specified. 3. The output voltage is measured using the Intel provided EMT Tester (Rev. 1.0). It is assumed that a minimum of 20 x 0.1 F ceramic capacitors are placed directly next to the CPU to provide adequate high-speed decoupling. Additional bulk capacitors may be required as closely as possible to the CPU socket on the motherboard when using the VRM. See Application Bulletin AB 5 for details.
4
PRODUCT SPECIFICATION
RCB006
Transient Plots
5
RCB006
PRODUCT SPECIFICATION
Notes:
6
PRODUCT SPECIFICATION
RCB006
Mechanical Dimensions (mm)
3.00 MAX 20.00 MAX 78.74 MAX
6.50 MIN 3.81 TYP
38.1 MAX 7.62 MAX R1.52 TYP
Pin A1 1.575 0.203 1.65 REF
10.67 TYP
7
RCB006
PRODUCT SPECIFICATION
Ordering Information
Part Number RCB006 Input 12V DC Output Current 15A
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonable expected to result in a significant injury of the user.
Fairchild Semiconductor Corporation Americas Customer Response Center Tel:1-888-522-5372 Fairchild Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: Deutsch Tel: English Italy Tel: Tel: europe.support@nsc.com +49 (0) 8 141-35-0 +44 (0) 1 793-85-68-56 +39 (0) 2 57 5631
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
Fairchild Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Center, 5 Canto Rd. Tsimshatsui, Kowloon Hong Kong Tel:+852 2737-7200 Fax:+852 2314-0061
National Semiconductor Japan Ltd. Tel:81-3-5620-6175 Fax:81-3-5620-6179
www.fairchildsemi.com 2/98 0.0m Stock# DS3000B006 (c) 1998 Fairchild Semiconductor Corporation
www.fairchildsemi.com
RCB007
5 Bit Voltage Regulator Module (VRM) for Pentium(R) II Processors
For 5V Power Supply
Features
* * * * * * * * * * Programmable 1.3V to 3.5V output Output current to 15A 5-bit digital input selects output voltage Typical efficiency > 85% DC output accuracy within 60mV Current limiting short-circuit protection Power Good output Output Enable function Excellent transient response Meets Intel VRM specifications
Description
The RCB007 is a programmable DC-DC VRM designed to deliver the selectable processor core voltage required by Pentium II microprocessors. This VRM allows board designers to support the entire Pentium II processor family with a single motherboard design, by converting the +5V power supply voltage to the voltage required by the CPU. The RCB007 takes full advantage of Raytheon's RC5051 programmable DC-DC controller IC, utilizing synchronous architecture for maximum efficiency. This VRM integrates a 5-bit DAC function, Power Good, and Output Enable features. The result is a VRM with a minimum number of components that achieves high reliability at a competitive cost. The RCB007 provides an extremely well regulated selectable output voltage from 1.3V to 3.5V. Voltage selection is accomplished through a 5-bit digital input. The Power Good output provides a logic LOW when an out-of-tolerance voltage is detected at the VRM output. Other features include high efficiency, short-circuit and over-voltage protection, output enable, and low package weight. The RCB007 VRM module is designed as a point-of-load converter for Pentium II processors, minimizing the distribution losses normally occuring when drawing high currents from a centralized power supply.
Preliminary Information
Applications
* Pentium II motherboard VRM module * Programmable power supply module * Template for motherboard implementation
Block Diagram
5V Supply Ground P Core Supply Power Good
Motherboard
12V MOSFET Bias VID4 VID3 VID2 VID1 VID0
RCB007
65-RCB007-1
Pentium is a registered trademark of Intel Corporation.
Rev 0.9.1
PRELIMINARY INFORMATION describes products that are not in full production at the time of printing. Specifications are based on design goals and limited characterization. They may change without notice. Contact Raytheon Electronics for current information.
RCB007
PRODUCT SPECIFICATION
Pin Orientation --Top View
(Socket: AMPMOD2 532956-7 or equivalent)
Table 1. RCB007 Pin Definitions
Pin # 1 2 3 Row A 5Vin 5Vin 5Vin 12Vin 12Vin NC1 VID0 VID2 VID4 VccCORE Vss VccCORE Vss VccCORE Vss VccCORE Vss VccCORE Vss VccCORE Row B 5Vin 5Vin 5Vin 12Vin NC1 OUTEN VID1 VID3 PWRGD Vss VccCORE Vss VccCORE Vss VccCORE Vss VccCORE Vss VccCORE Vss
A1
B1
4 5 6 7 8 9
Preliminary Information
10 11 12
A20 B20
13 14 15
65-RCB007-2
16 17 18 19 20
Note: 1. Not used on module; no current is drawn.
VRM Connector Pin Reference
Pin Description 5Vin 12Vin OUTEN (Output Enable) Open collector TTL input. VID0 to VID4 (Voltage Identification Code) Open collector TTL inputs. PWRGD (Power Good) Open collector TTL output. Input/Output I I I I Function Primary module supply voltage. MOSFET bias supply voltage. If OUTEN = HIGH (floating), output enabled.If OUTEN = LOW, output disabled and PWRGD output LOW. These five signals are used to indicate the voltage required by the processor. See Table 2. If PWRGD = HIGH, output voltage within specifications. If PWRGD = LOW, output voltage not within 10% of nominal. The PWRGD output will change to the proper state within 5ms of the output coming into or going out of its specified range. Processor core voltage. Ground.
O
VccCORE Vss
O I, O
2
PRODUCT SPECIFICATION
RCB007
Electrical Specifications
5Vin = +5V, 12Vin = +12V, TA = 0C to 60C, VccCORE = 2.8V, and airflow of 100LFM, unless otherwise specified. Parameter Input Specifications Primary Module Supply, 5Vin MOSFET Bias Supply, 12Vin Output Specifications Output Voltage Range, VccCORE See Table 2 Output Voltage Regulation Output Voltage Regulation Steady State Transient
3 2 2
Test Conditions
Min. 4.75 11.4 1.3 2.74 2.67 1.94 1.90 0.3
Typ. 5 12
Max. 5.25 12.6 3.5
Units V V V V V
VccCORE = 2.8V, IccCORE, Max = 14.2A VccCORE = 2.8V, IccCORE = 0.8 to 13.8A VccCORE = 2.0V, IccCORE, Max = 15.0A VccCORE = 2.0V, IccCORE = 0.8 to 14.8A IccCORE = 6A, TA = 25C IccCORE = 0.8A to 15A 5Vin = 4.75V to 5.25V 20MHz BW, IccCORE = 15A IccCORE = 0.5A IccCORE = 15A
2.80 2.80 2.00 2.00 20 -40 2 20 +10
2.90 2.93 2.06 2.10 15
Steady State Transient3
Preliminary Information
Output Current, IccCORE Initial Voltage Setpoint Load Regulation Line Regulation Output Ripple Output Temperature Drift Efficiency Turn-on Response Time General Specifications Switching Frequency Short Circuit Protection
A mV mV mV mVp-p mV %
40 80
67 83 10 300 18
ms kHz A
Notes: 1. The voltage tolerance is measured at the DC-DC converter Header Output on the motherboard. 2. The Steady State Voltage Regulation includes Initial Voltage Setpoint, DC load regulation, Output Ripple and temperature drift, measured with a digital voltmeter with 1mV resolution. IccCORE, MIN = 0.1A unless otherwise specified. 3. The output voltage is measured using the Intel provided EMT Tester (Rev. 1.0). It is assumed that a minimum of 20 x 0.1 F ceramic capacitors are placed directly next to the CPU to provide adequate high-speed decoupling. Additional bulk capacitors may be required as closely as possible to the CPU socket on the motherboard when using the VRM. See Application Bulletin AB 5 for details.
Mechanical Dimensions (mm)
3.00 MAX 20.00 MAX 78.74 MAX
6.50 MIN 3.81 TYP
38.1 MAX 7.62 MAX R1.52 TYP
Pin A1 1.575 0.203 1.65 REF
10.67 TYP
65-RCB007-04
3
RCB007
PRODUCT SPECIFICATION
Table 2. Output Voltage vs. Voltage Identification Code
Nominal Voltage to CPU (VccCORE) 1.30V 1.35V 1.40V 1.45V 1.50V 1.55V 1.60V 1.65V 1.70V 1.75V 1.80V 1.85V 1.90V 1.95V 2.00V 2.05V Nominal Voltage to CPU (VccCORE) 2.0V 2.1V 2.2V 2.3V 2.4V 2.5V 2.6V 2.7V 2.8V 2.9V 3.0V 3.1V 3.2V 3.3V 3.4V 3.5V
VID4 0 0 0 0 0 0 0
VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
Preliminary Information
0 0 0 0 0 0 0 0 0
Note: 1. "0" indicates processor pin is tied to 0V (VSS), "1" indicates it is tied to 5V or is open.
Ordering Information
Part Number RCB007 Input 5V DC Output Current 15A
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonable expected to result in a significant injury of the user.
Fairchild Semiconductor Corporation Americas Customer Response Center Tel:1-888-522-5372 Fairchild Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: Deutsch Tel: English Italy Tel: Tel: europe.support@nsc.com +49 (0) 8 141-35-0 +44 (0) 1 793-85-68-56 +39 (0) 2 57 5631
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
Fairchild Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Center, 5 Canto Rd. Tsimshatsui, Kowloon Hong Kong Tel:+852 2737-7200 Fax:+852 2314-0061
National Semiconductor Japan Ltd. Tel:81-3-5620-6175 Fax:81-3-5620-6179
www.fairchildsemi.com 2/98 0.0m Stock# DS3000B007 (c) 1998 Fairchild Semiconductor Corporation
www.fairchildsemi.com
RCB010
Voltage Regulator Module (VRM) for PowerPCTM Processors
Features
* * * * * * * * 5-bit digital input selects output voltage Programmable 1.3V to 3.5V output from 5V supply Maximum output current 8A Efficiency > 80% Total output accuracy within 3% Short circuit protection Excellent transient response Output voltage set by CPU or preset on VRM.
Description
The RCB010 is a programmable DC-DC Voltage Regulator Module designed to deliver the selectable processor core voltage required by the PowerPC microprocessors. This VRM offers flexibility to board designers to support PowerPC processors with a modular add-in power supply. The RCB010 takes full advantage of a proprietary Raytheon programmable DC-DC controller IC. This IC integrates a 5-bit DAC for automatic output programmability without the need for external precision resistors. The result is a VRM with a minimum number of components that achieves high reliability at a competitive cost. The RCB010 provides an extremely well regulated selectable output voltage from 1.3V to 3.5V. Output voltage selection is accomplished through a 5-bit interface between the processor and the module connector. Other features include high efficiency, short circuit protection, and low package weight.
Applications
* VRM module for PowerPC motherboards * Programmable power supply module
Block Diagram
5V Supply 12V Supply Ground P Core Supply Motherboard VID4 VID3 VID2 VID1 VID0 RCB010
Rev 1.1.0
RCB010
PRODUCT SPECIFICATION
Pin Orientation -- Top View
(Socket: AMPMOD2 532956-5 or equivalent)
RCB010 Pin Definitions
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 Row A GND GND 3.3V 5V 5V VID4 VID3 VID0 GND GND NC* VOUT VOUT VOUT
1
Row B GND GND 3.3V1 3.3V1 5V 5V VID2 VID1 12V GND GND NC* VOUT VOUT VOUT
A1 B1
3.3V1
A15 B15
14 15
Note: 1. Not used on module; no current is drawn.
VRM Connector Pin Reference
Pin Description 5V 3.3V 12V VID0 to VID4 (Voltage Identification) Open collector TTL inputs VOUT GND Input/ Output I I I I Function Supply voltage to support power to the CPU. Alternate supply voltage to support CPU. These pins are not used on this module, but are reserved for possible later use. Supply voltage for MOSFET drivers. These five signals are used to indicate the voltage required by the processor. The output can be programmed from 1.3V to 3.5V by setting the VID pins according to the Output Voltage Programming Codes table. Module output voltage. Ground Reference.
O I, O
Mechanical Dimensions (mm)
3.00 20.00 10.00 11.83 56.33 Notes: 30.96 7.68 Tolerance: 0.20 mm Maximum Component Height in this area is 6.00 mm Maximum Component Height in this area is 10.00 mm 43.17 7.50 29.62 Maximum Component Height in this area is 20.00 mm
15.70 10.50 10.50
14.20
1.60
13.72 63.50
13.72
2
PRODUCT SPECIFICATION
RCB010
Electrical Specifications
(VIN = +5V, TA = 0C to 60C unless otherwise specified.) Parameter Input Specifications Main supply voltage, 5V MOSFET supply voltage, 12V Output Specifications Output Voltage Range, VOUT DC Output Current, IOUT Set Point Accuracy1 Load Regulation Line Regulation Output Temperature Drift Load Transient (See Figure 1) Step Recovery Time3 Output Ripple3 Cumulative Accuracy Efficiency General Specifications Switching Frequency Short Circuit Protection 8 300 9 13 KHz A
2 3
Test Conditions Steady State 100 msec maximum Steady State 100 msec maximum See Output Programming Codes ILOAD = 2A, TA = 25C ILOAD = 0.5A to 7A VIN = 5.0 0.25 V ILOAD = 0.5A to 6A, 20A/sec ILOAD = 0.5A to 6A ILOAD = 6A ILOAD = 8A, VOUT = 1.8V ILOAD = 8A, VOUT = 2.8V
Min. 4.75 11.4
Typ. 5 12
Max. 5.25 6.5 12.6 18
Units V V
1.3 0 5 1.0 30 3 20 10 20 2 75 80 79 82
3.5 8
V A % mV
5 20 100 25 3
mV ppm/C mV sec mVp-p % % %
Notes: 1. Set Point Accurcy is defined as the static accuracy of the output voltage at 2A. 2. Cumulative Accuracy includes Set Point Accuracy, Output Temperature Drift, Line and Load Regulation. 3. Test fixture includes 3 x 100F Tantalum capacitors (ESR < 100m) and 48 x 1F from output to GND at the CPU socket.
20mV Max 100s Max
100s Max
20mV Max
Figure 1. Load Transient
3
RCB010
PRODUCT SPECIFICATION
Output Voltage Programming Codes
VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Vout to CPU 1.30V 1.35V 1.40V 1.45V 1.50V 1.55V 1.60V 1.65V 1.70V 1.75V 1.80V 1.85V 1.90V 1.95V 2.00V 2.05V VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Vout to CPU 2.0V 2.1V 2.2V 2.3V 2.4V 2.5V 2.6V 2.7V 2.8V 2.9V 3.0V 3.1V 3.2V 3.3V 3.4V 3.5V
Note: 1. 0 = processor pin is tied to GND 1 = processor pin is open
Ordering Information
Part Number RCB010 Input 5V DC Output Current 8A
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RCC611
100BaseTX Transceiver
Features
* * * * * * * * * * * * * * * 100 Mbps/125 Mbaud data rates Low power 0.6 micron CMOS technology PLL Clock and data recovery Clock synthesizer Auto-negotiation 4b/5b Encode/Decode FDDI TP/PMD scrambling/descrambling Management Interface for control/status Link Pulse Signalling Conforming to MII interface of IEEE 100baseTX Fast Ethernet Standard(P802.3u/D3) Low Power Dissipation--600 mW typical Single power supply: +5V PECL compatible serial data inputs/outputs Support for external 10 Mbps PHY 100 pin PQFP (20mm x 14mm x 2.7 mm)
* * * * * *
High Speed Point to Point Links Bus Extenders Multimedia High Resolution Graphic Displays Fast Ethernet test equipment FDDI Test Equipment
Advanced Information
Description
The RCC611 is a monolithic 125 Megabaud CMOS transceiver chip. It integrates a complete phase-locked loop clock and data recovery, a phase locked loop clock synthesizer, a 5:1 Serializer, a 1:5 Deserializer, 4B/5B Encoder, 5B/4B Decoder, auto-negotiation and a management interface for link control and status. It also includes scrambler, descrambler for twisted pair copper applications in compliance with FDDI TP-PMD specifications. In conjunction with RCC613 twisted pair transceiver, the chipset can be used for driving with category 5 unshielded twisted pair cable and Type 1 shielded twisted pair cable. The chip meets the physical layer interface requirements of the 100 Base-X Fast Ethernet and FDDI standards. The RCC611 chip operates with a single, +5V power supply.
Applications
* Fast Ethernet Adapter/hub/switch * FDDI Adapter/hub
Block Diagram
NWAYDIS TCLK 100BTFD REPEATER EX10BTFD EX10BTHD 4B5BDIS 4 DI0-DI3 TXEN/DI4 RESET ILSEL TXERR DESCRMB. INITIALIZE 10BTFD 10BTHD MDC MDIO ISOLATE CRS CLSN CLOCK & DATA RECOVERY DATA CLK 2:1 MUX 4B/5B ENCODER SCRAMB 5:1 SERIALIZER NRZ TO NRZI 2 PECL DRIVER 2 DOUT, DOUT TLP 2 HIGH SPEED CLOCK GENERATOR A0-A3 LEDT, LEDR, LEDL LOOP LPEN /5
2
MGMT. INTERFACE
AUTO NEGOTIATION
DIN, DIN
BYTE ALIGNMENT CIRCUIT 4 5B/4B DECODER 1:5 DESERIALIZER NRZI TO NRZ
RXEN
ERROR DO0-DO3 RXDV/DO4 RCLK SDO
DESCRAMBLER
LINK MONITOR
65-611-01
SDI
Rev. 0.5.0A
ADVANCED INFORMATION data sheets provide specification for products not yet complete or characterized. They provide design target information for customer planning purposes.
RCC611
PRODUCT SPECIFICATION
Functional Description
SDO
Transmitter Section
The RCC611 transmitter section includes a phase locked loop synthesizer, 4B/5B encoder, scrambler and 5:1 serializer. The RCC611 accepts a CMOS data nibble (DI0-DI3) and a control bit, TXEN. The data gets strobed on the positive transition of TCLK. The transmitter encodes the data, DI0-DI3 using 4b/5b coding (see Table 1). TXEN is used to denote the transmitter input being active or not. Whenever TXEN=0, IDLE symbol (11111) is encoded and transmitted. When TXEN transitions from 1 to 0, TR byte is sent before transmitting IDLE symbols. The order of transmission of the 4b/5b encoded output (E4..0)is that the most significant bit of the encoded symbol, E4 is transmitted first followed by E3,E2,E1 and E0. When 4B5BDIS is HIGH, the 4b/5b encoder is bypassed. Under that case, TXEN is used as the fifth bit (DI4) of the encoded symbol. The order of transmission of the input when 4B5BDIS is HIGH is DI4 followed by DI3, DI2, DI1 and DI0. The clock generator consists of a frequency multiplying Phase Locked Loop (PLL). The multiplying ratio is 5. The serial output goes through Non-Return-to-Zero (NRZ) to Non-Return-to-Zero Invert on Ones (NRZI) conversion. The NRZ to NRZI converter takes in the serial NRZ stream and puts out a transition for every 1 in the input stream. For zeros, there will be no transition. This will ensure that there is clocking information even when there is a long stream of 1s. The differential NRZI output is enabled to the output pins DOUT, DOUT. The serial Data Stream (DOUT/ DOUT) is transmitted at PECL levels (positive shifted ECL levels, Vth= +3.7 V). The input clock reference for the PLL Clock Generator, TCLK, typically comes from the CMOS protocol layer IC. TXERR=1 is used to force HALT symbol (00100) on the transmit output. The encoded symbol is scrambled as per FDDI's TP-PMD standard. The scrambler used is a stream cipher scrambler. The scrambler polynomial is 1+x9+x11.
SDI 330 Sec of IDLE (min)
TXEN
IDLE TXDAT
65-611-02
Figure 1.
Advanced Information
There is also one more level of loopback provided through the external RCC613 chip. When control register Reg0 bit 14 is HIGH, LOOP output pin is HIGH and the the serial output, DOUT, DOUT goes through the RCC613 TXIP, TXIN inputs and loops back through the RXOP, RXON outputs back to the DIN, DIN of RCC611.
Table 1. 4B/5B Encoding
Symbol 0 1 2 3 4 5 6 7 8 9 A B C D E F T R J K I (IDLE) H (HALT) TXEN 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 DI3-DI0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 xxxx xxxx xxxx xxxx xxxx xxxx Encoded Output (E4-E0) 11110 01001 10100 10101 01010 01011 01110 01111 10010 10011 10110 10111 11010 11011 11100 11101 01101 00111 11000 10001 11111 00100
Descrambler Initialization
The descrambler initialization timing is shown in the accompanying diagram. On powerup, TXEN=0. RCC611 automatically initializes the downstream descrambler by forcing IDLE symbols (11111) which gets scrambled and driven to the medium. Transmitting IDLE continues until TXEN=1. The transmitter has the provision to loopback its output to the receiver input, when ILSEL=1. Under that case, a continuous logic LOW state is sent through the DOUT, DOUT pins.
Note: 1. All the symbols are encoded as per the state diagram provided in Chapter 28 of IEEE802.3.
2
PRODUCT SPECIFICATION
RCC611
Table 2. 5B/4B Decoding
Symbol 0 1 2 3 4 5 6 7 8 9 A B C D E F T R J K I H V V V V V V V V V V Encoded Output 11110 01001 10100 10101 01010 01011 01110 01111 10010 10011 10110 10111 11010 11011 11100 11101 01101 00111 11000 10001 11111 00100 00000 00001 00010 00011 00101 00110 01000 01100 10000 11011 DO3-0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ERROR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
Receiver Section
The RCC611 Receiver section includes a 2 to 1 multiplexer, a complete phase-locked loop clock and data recovery, and decoder. The 2 to 1 Mux is used to choose between the differential PECL receive input data (DIN, DIN) or the transmit output for enabling to the clock and data recovery circuit. The choice of the inputs is made by the ILSEL pin. If ILSEL is HIGH, the transmit output is looped back to the input of the receiver. If ILSEL is LOW, the receive input is chosen. The RCC611 recovers the clock and regenerates the encoded serial data. There is a PECL to CMOS converter for the SDI signal detect PECL input signal. If SDI goes LOW to HIGH, the SDO output goes HIGH after a minimum of 330 microseconds of continuous IDLE symbols to allow for the clock and data recovery and descrambler to synchronize. The recovered encoded data is then converted to 5 parallel data lines via 1:5 De-Serializer. The RCC611 contains a byte alignment circuitry. When the JK symbols are detected in the serial stream, the chip will automatically resynchronize the demultiplexer to byte align with the JK. The data is then decoded into an 4-bit symbol via the 5b/4b decoder as per the 5b/4b Decoding table. The received data is checked during the 5b/4b decoding and violations are flagged by bringing the Error Flag (ERROR) to a level HIGH. The 5b/4b decoder is bypassed for FDDI. The output from the 5b/4b decoder comes out as 4 bits of data, DO0-DO3 and one control bit output, RXDV. When 4B5BDIS is HIGH, the 5b/4b decoder is bypassed and the output come out as DO0-DO4 where DO4 replaces the RXDV signal. The demultiplexed data goes through a descrambler. The descrambler descrambles the data as per the polynomial discussed in the transmit section. CLSN signal is flagged if the chip is transmitting and receiving data as per the IEEE802.3 transmit and receive state diagram in Chapter 24. CRS is flagged if either the chip is transmitting data or receiving data as per the IEEE802.3 transmit and receive state diagram in Chapter 24. Both CLSN and CRS are asynchronous signals.
Advanced Information
Note: 1. All the symbols are decoded as per the state diagram provided in Chapter 28 of IEEE802.3.
3
RCC611
PRODUCT SPECIFICATION
Pin Assignments
100 1 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Name DGND DGND DVCC DVCC NC AGND DGND 4B5BDIS DI0 DI1 DI2 DI3 TXEN/DI4 TXERR DGND TCLK DVCC REPEATER NC MDC MDIO LOOP NC NC DGND Pin 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Name DVCC Pin 51 52 RESET 53 LEDT 54 ISOLATE 55 LEDR 56 LEDL 57 DVCC 58 DGND 59 A0 60 A1 61 A2 62 A3 63 DGND 64 DGND 65 10BTFD 66 10BTHD EX10BTHD 67 EX10BTFD 68 69 CLSN 70 CRS 71 100BTFD 72 TLP 73 DVCC 74 DVCC NWAYDIS 75 Name LPEN RXEN DGND DGND DO3 DO2 DO1 DO0 DVCC DVCC RXDV/DO4 ERROR DGND RCLK SDO AGND DGND DVCC DGND DGND DVCC DVCC DGND DGND DVCC Pin 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Name DVCC NC NC NC NC DIN DIN NC SDI DGND AGND RXAVCC AGND RXAVCC TXAVCC AGND DGND DVCC TXAVCC TXAVCC AGND AGND ILSEL DOUT DOUT
Advanced Information
65-611-03
Pin Descriptions
Pin Name 10BTFD 10BTHD 4B5BDIS A0-A3 Pin Number 40 41 8 34-37 Type CMOS O/P CMOS O/P TTL I/P TTL I/P Description 10BaseT Full Duplex.10BTFD is used to enable or disable a local 10BaseT Full duplex device. 10BaseT Half Duplex. 10BTHD is used to enable or disable a local 10BaseT half duplex physical layer device. 4b/5b disable. This pin is used to disable the 4b/5b encoder and 5b/4b decoder. Address 0-3. A0-A3 pins are used to denote the physical address of the chip for writing or reading of the internal control/ status registers. During reset, if the PHY address are all zeroes (0000) then the MII interface will be tri-stated. Chip ground for Analog circuitry. AGND pins should be connected to the printed circuit board's ground plane at the pins. CMOS O/P Collision. This output is HIGH if the chip is receiving data and at the same time it is transmitting packet data. It is an asynchronous output. CLSN is LOW during Full duplex mode of operation. Carrier Sense. This output is HIGH if the chip is either receiving data or transmitting packet data. It is an asynchronous output. CRS is determined by receive activity during Full duplex mode. Chip ground for digital circuitry. DGND should be connected to the printed circuit board's ground plane at the pins.
AGND CLSN
6, 66, 86, 88, 91, 96, 97 44
CRS
45
CMOS O/P
DGND
1, 2,7,15, 25, 33, 38, 39, 53, 54, 63, 67, 69, 70, 73, 74, 85, 92
4
PRODUCT SPECIFICATION
RCC611
Pin Descriptions (continued)
Pin Name DIN, DIN DO0-DO3 DOUT, DOUT DVCC Pin Number 81, 82 58-55 100, 99 3, 4, 17, 26, 32, 48, 49, 59, 60, 68, 71, 72, 75, 76, 93 9-12 62 TTL I/P CMOS O/P Type PECL I/P CMOS O/P PECL O/P Description Receiver differential input data. Receiver output data. Transmit differential output data. Positive supply for Digital circuitry. The nominal value is 5V 5%. VCC should be bypassed to the ground plane with a 0.1F chip capacitor placed as close to the pin as possible. Transmitter Input data. Error Flag. ERROR goes HIGH to flag 5B/4B decoding violations. It also indicates transition to idle condition from active without end of frame delimiters. 100BaseT Full Duplex. 100BTFD when low is used to activate a LED and indicates that the RCC611 is operating in the 100BaseT Full Duplex mode. 10BaseT Full Duplex. When EX10BTFD is high, it indicates that there is available an external 10BaseT Physical layer device capable of full duplex operation. This input goes directly to Reg1 bit12. 10BaseT Half Duplex. When EX10BTHD is high, it indicates that there is available an external 10BT physical layer device with half duplex capability. This input goes directly to Reg1 bit11. Isolate. ISOLATE is used to indicate that the chip is in the isolate mode. When activated (low), all the MII interfaces will be tristated. Software can be used to override the the ISOLATE bit (Reg0 bit10). Note that the polarity of ISOLATE and Reg0 bit10 are the opposite to each other. See page 10 for more details. LED Link OK. It is used as an active LOW output to indicate that the link is OK as indicated by the FLG signal from the arbitration state machine. LED Receive. It is used as an active LOW output to indicate that the receive is active. It will be LOW if CRS = 1. LED Transmit. It is used as an active LOW output to indicate that the transmit is active. It will be LOW if TXEN = 1. Loop. LOOP is used to enable the loopback input of RCC613 chip. LOOP is active if the control register Reg0 bit 14 is HIGH . Link Pulse Enable. It provides an enable signal to the RCC613 for the transmit link pulse. Loop Select. ILSEL is used for differential loopback for "on-board" diagnostic of the device. When ILSEL is HIGH, the receiver accepts the serial output data from the transmitter section. Connect to GND or leave open when not used. Management Data Input/Output. MDIO is a bidirectional signal between RCC611 and the station management entity. It is used to transfer control and status information. All the read and write transactions are done synchronously with MDC. Management Data Clock. MDC is sourced by the station management entity to RCC611 as a timing reference for transfer of information on MDIO signal. MDC is an aperiodic signal whose minimum high and low times are 200 ns. 5
DI0-DI3 ERROR
Advanced Information
100BTFD
46
CMOS O/P
EX10BTFD
43
TTL I/P
EX10BTHD
42
TTL I/P
ISOLATE
29
CMOS O/P
LEDL
31
CMOS O/P
LEDR LEDT LOOP LPEN ILSEL
30 28 22 51 98
CMOS O/P CMOS O/P CMOS O/P CMOS O/P TTL I/P
MDIO
21
TTL/CMOS I/ O
MDC
20
TTL I/P
RCC611
PRODUCT SPECIFICATION
Pin Descriptions (continued)
Pin Name NWAYDIS Pin Number 50 Type TTL I/P Description Nway Disable. When NWAYDIS is high, the auto-negotiation state machines are disabled and AUTO bit (Reg0 bit12) is set to 0. Software can be used to override the AUTO bit. see page 10 for more details. For manual setting, see Table 3. Receive Clock. It is the recovered byte clock derived from the byte alignment circuitry. It provides timing to DO0-DO3, RXDV and ERROR. Repeater/Node Mode. When in the Repeater (high) mode as in the Full Duplex mode, CRS output is asserted due to activity from the receiver only. When in the Node (low) mode and not Full Duplex mode, CRS is asserted due to either receive or transmit activity. Reset. RESET is an asynchronous input which when LOW is used to reset the state machines inside the chip. RESET needs to be LOW for at least one byte clock. Receive Enable. When activated (high), it enables the outputs D0-D3, CRS, ERROR, RXDV, CLSN and RCLK. When low these outputs are tri-stated. Positive Supply for Receive Analog Circuitry. The nominal value is 5V5%. RXAVCC should be bypassed to the ground plane with a 0.1F chip capacitor placed as close to the pin as possible. CMOS O/P Receive Data Valid. RXDV when HIGH indicates the receive output data being active. When 4B5BDIS is HIGH, this pin is used as DO4, the fifth data output. Signal Detect Input. It is converted to CMOS output level through a PECL to CMOS converter. Signal Detect Output. SDO is the output from the PECL to CMOS converter for the signal detect signal. The signal is asserted 330 microseconds after SDIN goes HIGH. SDO output is made synchronous to RCLK and has the same timing as the DO0-3. Transmit Clock. TCLK is the 25 MHz input reference for the internal high speed bit clock generator. It provides the timing for the input data, DI0..DI3, TXEN and TXERR. Transmit Link Pulse. TLP is HIGH when a link pulse needs to be transmitted. Positive supply for Transmit Analog circuity. The nominal value is 5V 5%. TXAVCC should be bypassed to the ground plane with a 0.1F chip capacitor placed as close to the pin as possible. TTL I/P Transmit Enable . WhenTXEN is HIGH, it indicates that the input data is active. When 4B5BDIS is HIGH, this pin is used as DI4, the fifth data input. Transmit Error. TXERR is used to transmit VIOLATION symbols (00100) on the transmit output.
RCLK
64
CMOS O/P
REPEATER
18
TTL I/P
Advanced Information
RESET
27
TTL I/P
RXEN
52
TTL I/P
RXAVCC
87,89
RXDV/DO4
61
SDI SDO
84 65
PECL I/P CMOS O/P
TCLK
16
TTL I/P
TLP TXAVCC
47 90, 94, 95
CMOS O/P
TXEN/DI4
13
TXERR
14
TLL I/P
6
PRODUCT SPECIFICATION
RCC611
Management Interface
Address Control Register Reg0 (Default) 00000 Address Control Register Reg0 (Default) 00000 Address Status Register Reg1 00001 Address Status Register Reg1 00001 Address PHY ID Register Reg2 00010 Address PHY ID Register Reg3 00011 Address Link Advt Register Reg4 00100 Address Link Partner Register Reg5 00101 Address Expansion Register Reg6 00110 Address Next Page Tx Register Reg7 00111 Address User Register Reg16 10000 Bit 15 NP (0) Bit 15 NP Bit 15 NP Bit 15 ............... Bit 10 11 0001 Bit 14 Ack Bit 14 Ack Bit 13 RF Bit 13 RF Bit 4 PDF Bit 13 MP Bit 12 Ack2 Bit 11 Rsvd Bit 15 Reset (0) Bit 7 Cltest (0) Bit 15 0 (T4) Bit 7 0 Bit 14 1 (TXFD) Bit 6 0 Bit 13 1 (TXHD) Bit 5 Config Bit 12 10TFD Bit 4 Rmtfl (latched) Bit 14 Loop (0) Bit 6 Bit 13 Speed (1) Bit 5 Bit 12 Auto (1) Bit 4 Bit 11 Pwrdn (0) Bit 3 Reserved Bit 11 10THD Bit 3 1 (Auto) Bit 10 0 Bit 2 Bit 9 0 Bit 1 Bit 8 0 Bit 0 R/O Bit 10 Isolate (0) Bit 2 Bit 9 Reconf (0) Bit 1 Bit 8 Duplx (0) Bit 0 R/W R/W
Lnkstat 0 1 (latched) (Jabdet) (Extend) R/O
Advanced Information
Bit 15 .................................................................................... Bit 0 0000 0000 0000 0011 Bit 9 .................. Bit 4 00000 (Model) Bit 12 ............... Bit 5 A7...A0 Bit 12 ............... Bit 5 A7...A0 Bit 3 LPNP Bit 2 1 Bit 3 ...... Bit 0 0000 (Model Rev) Bit 4 ...... Bit 0 S4...S0 Bit 4 ...... Bit 0 S4...S0 Bit 1 Pg rcvd Bit 0 LP able R/O R/O R/W R/O R/O
Bit 15 ............... Bit 5 Reserved Bit 14 Ack (0)
Bit 11 .............................. Bit 0 M11/U11...M0/U0 Bit 10 ............... Bit 1 Reserved Bit 0 Pwrdn1 R/W R/W
Bit 15 ............... Bit 12 Reserved
65-611-04
Register Description
The management interface provides a simple, two wire, serial inteface (MDIO, MDC) to connect the station management entity to the PHY for control and status gathering. MDC is sourced by the station management entity to the PHY as a timing reference for transfer of information on the MDIO signal. MDC is an aperiodic signal with a minimum high and low times of 200 ns. MDIO is a bidirectional signal between PHY and the station management entity. Control information is driven by the station management entity synchronously to MDC and sampled synchronously by PHY. Status information is driven synchronously by PHY and sampled synchronously by the station management. As shown in the figure, there are a total of 9 sixteen bit registers: Reg0, Reg1, through Reg7 and Reg16. Their functions are detailed in the register definitions section. The default values for the registers where applicable are shown in parenthesis. All the status and control transistions occur synchronous to the local clock, TCLK.
7
RCC611
PRODUCT SPECIFICATION
Idle Read: Idle Write: Idle
SOF 01 01
OpCd PHY Addr 10 AAAAA 01 AAAAA
Reg Addr RRRRR RRRRR
Fill Z0 10
Data DDDDDDDDDDDDDDDD DDDDDDDDDDDDDDDD
Management Frame Structure
Management Frame Structure
The management frame structure is as shown in the figure. In between the frames is an Idle condition. The Idle condition on the two wire interface is a logic one through the internal pullup resistor. The open drain driver for MDIO will be disabled. Prior to initiating any transaction, the station management entity will send a sequence of 32 contiguous logic one bits on MDIO with 32 corresponding cycles on MDC to provide the chip with a pattern that it can use to establish synchronization. The frame begins with an SOF field. SOF is indicated by a 01 pattern. The next field is Opcode. The Opcode for a read transaction is 10 and for a write transaction is 01. Next to Opcode is the PHY Address field. The PHY address is 5 bits. The first bit is the most significant bit of the PHY address. The chip will recognize 00000 as its own address. The next field is the register address. The register address is 5 bits. The register accessed at register address zero (00000) is the Register 0 (Reg0) and so on. Next to the Register address is the Turnaround field. An idle bit time during which no device actively drives the MDIO signal is inserted between the Register address field and the Data field of the frame during a Read transaction in order to avoid contention. During a Read transaction, the chip will drive a zero bit onto MDIO for the bit time following the idle bit and preceding the Data field. During a write transaction, the station management entity will fill this idle time with a one bit followed by a zero bit. The data field is 16 bits. The first data bit transmitted and received is the MSB of the data payload.
The information is encapsulated within a burst of closely separated link integrity test pulses that meet 10baseT transmitter waveform for Link test pulses. This burst of pulses is referred to as a Fast Link Pulse (FLP) burst. The chip issues FLP bursts at powerup. The burst consists of alternating clock/data sequence. To maintain interoperability with existing 10baseT devices, the alogrithm also supports the transmission of 10baseT compliant link integrity test pulses. 10baseT pulse is referred to as the Normal Link Pulse (NLP). A device which fails to respond to the FLP sequence and returns only the NLP indication is treated as a 10baseT compatible device.
Advanced Information
Transmit Function
The FLP burst shall contain the Link Code Word (Reg4). FLP bursts consists of 33 pulse positions. The 17 odd numbered pulse positions are always present and represent clock information. The 16 even numbered positions represent data information. A link pulse present in an even numbered position represents a logic one and a link pulse absent from an even numbered pulse position represents a logic zero. The first pulse is a clock pulse. Clock pulses are evenly spaced apart by 12530 microseconds. The data ONE pulse occurs 62.515 microseconds after the clock pulse. The first bit in consecutive FLP bursts shall occur at 168 msec interval. The pulses are sent through the TLP pin. A link pulse enable signal, LPEN, is also provided for convenience.
Receive Function
The receive function detects NLP sequence. In addition, the receive function shall detect FLP bursts and decode the information contained.
Auto-Negotiation Signalling
The chip has the provision to advertise its mode of operation to the remote end of a link segment and detect corresponding operational modes that the other device may be advertising. The auto-negotiation algorithm is performed out of band using a modified 10baseT link integrity pulse sequence. The algorithm allows the devices at both ends of a link segment to request and acknowledge use of the commom modes of operation that both devices share and to reject the use of operational modes that are not shared by both devices. When more than one common mode exists between the two devices, a mechanism is provided to allow the devices to resolve to a single mode of operation using a predetermined priority resolution table.
Arbitration Function
Arbitration function ensures proper sequencing of the autonegotiation algorithm through the transmit and receive function. The arbitration function enables the transmit function to advertise abilities and upon consistent and consecutive reception of the received link code word, advertises acknowledgement. Upon reception of 4 to 6 link code words with acknowledge bit set, the arbitration function determines the highest common denominator using the priority resolution table. If SDO goes active before autonegotiation is complete, a test window timer will be started and at the expiration of the timer, the arbitration function shall indicate that a valid link has been established.
8
PRODUCT SPECIFICATION
RCC611
Table 3. Manual Setting for Non-Auto-Negotiation
Function Auto-negotiation 100BaseT Full Duplex 100BaseT Half Duplex 10BaseT Full Duplex 10BaseT Half Duplex
IDLE SYNC
AUTO Bit (Reg0 Bit12) 1 0 0 0 0
SOF
Speed Bit (Reg0 Bit13) X 1 1 0 0
Write
Duplex Bit (Reg0 Bit8) X 1 0 1 0
IDLE
MDIO
MDC
Advanced Information
200 ns (min) 32 bit times
200 ns (min) 28 bit times
65-611-05
Figure 2. Management Interface Timing during Write to Registers
IDLE
SYNC
SOF
Write
IDLE
MDIO
MDC
tmh 32 bit times
tml 28 bit times
65-611-06
Figure 3. Management Interface Timing during Read from Registers
MDIO (during write) tims MDC tom MDIO (during read)
65-611-07
timh
Figure 4.
9
RCC611
PRODUCT SPECIFICATION
Register Definitions
Control Register (Read/Write) - Address 00000 (Register 0)
15 Reset 7 Cltest All of the control register bits (0 through 15) are read/write. The functions within the Reg0 are as follows: speed, full/half duplex, Isolate, Automatic speed selection, Loopback, Collision test. The individual bit descriptions and the default values are as follows: 14 Loop 6 13 Speed 5 12 Auto 4 11 Pwrdn 3 Reserved 10 Isolate 2 9 Reconfig 1 8 Duplex 0
Advanced Information
Reg 0
Bit 15
Name Reset
Default Description O Reset = 1 resets the PHY, i.e. all the control and status registers are reset to their default states. This function is self-clearing. The default value is zero. Writes to other bits of control register has no effect until the reset process is completed. Loop = 1. This bit is used to enable the LOOP output pin HIGH and thereby enable the local loopback of the RCC611 through the RCC613. The default value is zero. This bit is used to manually set the speed of operation. Speed=1 denotes 100 Mbps mode of operation. Speed=0 denotes 10 Mbps mode of operation. This bit is used to manually set the speed of operation. This bit is effective only if Auto (Reg0, bit 12)=0 (ie. manual speed selection). The default value is one. If bit12 (Auto) of Reg0=0, and Speed=0, 10Mbps operation is enabled and determined by Reg 1 bit 12 and bit 11. If bit12 (Auto) of Reg0=0 and Speed=1, 100 Mbps operation is enabled. Auto = 1 denotes automatic speed selection. Auto=0 denotes manual speed selection. Auto speed selection enables PHY's auto selection algorithm. The default value = 1. Pwrdn = 1 shuts off the power to the chip except the portions involving the management transactions. The default value=0. Both Pwrdn & Pwrdn1 cannot be HIGH at the same time. If so, there will not be any power down. The chip isolates its data path from the parallel (MII) interface when Isolate=1. When Isolate=1, the chip will tristate the CMOS outputs: RXCLK, RXDV, ERROR, RXD3..RXD0, CLSN, & CRS. Also, the TTL inputs (DI0..DI3, TXEN, TXERR, TCLK) are ignored. The default value=0. If A(3..0)=0000, the default value=1. This bit is brought out as ISOLATE pin. This can be used to enable or disable an external additional PHY connected to the same controller. Autolink configuration process will be initiated when Reconfig=1. This bit is self-clearing. When auto-configuration is disabled (Auto=0), Duplex=1 sets the chip for full duplex operation. In this mode, CRS signal is determined by receive activity. Duplex=0 sets the chip for half duplex operation. The default value of Duplex=0. When Cltest=1, CLSN is asserted in response to TXEN. The default value of Cltest=0. These bits are reserved for future definition. They are set equal to zero.
0
14
Loop
O
0
13
Speed
I
0
12
Auto
I
0
11
Pwrdn
O
0
10
Isolate
O
0 0
9 8
Reconfig Duplex
O O
0 0
7 6-0
Cltest Reserved
O O
10
PRODUCT SPECIFICATION
RCC611
Register Definitions (continued)
Status Register (Read Only) - Address 00001 (Register 1)
15 0 (T4) 7 0 14 1 (TXFD) 6 0 13 1 (TXHD) 5 Config 12 10TFD 4 Rmtflt 11 10THD 3 1 (Auto) 10 0 2 Lnkstat 9 0 1 0 (Jabdet) 8 0 0 Extend
The status functions are as follows: information about all the modes of operation supported by the local PHY, the status of auto-negotiation, and if auto-negotiation is supported by the local PHY or not. Reg 1 1 1 1 Bit 15 14 13 12 Name T4 TXFD TXHD 10TFD Default 0 1 1 -- Description T4=1 indicates the mode is 100 base T4 capable. T4 is set to 0 for RCC611 TXFD=1 indicates the mode is capable of full duplex transmission at 100 base TX. TXFD is set to 1 for RCC611 TXHD=1 indicates the mode is capable of half duplex transmission at 100 base TX. TXHD is set to 1 for RCC611 10TFD=1 indicates the local PHY has the ability to perform full duplex link transmission and reception using the 10baseT signalling specification. 10TFD=1 if the input pin EX10BTFD is equal to 1. 10THD=1 indicates the local PHY has the ability to perform half duplex link transmission and reception using the 100baseTX signalling specification. 10THD=1 if the input pin EX10BTHD is equal to 1. Bits10-6 are reserved for future definition. These bits are set to zero. When Config=1, it indicates that the auto link configuration has been completed and the Registers Reg4, Reg5 and Reg6 are valid. When Config=0, it indicates that the auto link configuration has not been completed. If control register bit 12 (Auto) =0, Config is set to zero. When Rmtflt=1, it indicates that a remote fault condition has been detected. This bit is set to 1 if Reg5 bit 13=1. This bit will remain set until read. 1 Auto=1 constitutes the ability of RCC611 to perform auto link detection and configuration. It is set to 1 to indicate that the local PHY has the ability to perform auto link detection and configuration. Lnkstat=1 indicates that the link is active. SDO going HIGH sets Lnkstat HIGH and SDO going HIGH to LOW causes Lnkstat to go HIGH to LOW. Lnkstat=0 indicates that the link is not valid. The occurance of a link failure condition will cause Lnkstat=0 and will remain equal to zero until read. It is set to 1 after read and remains set until the next occurence of SDO going HIGH to LOW. 0 1 This bit is set to 0 since jabber detect function is not supported. Extend=1 indicates that the PHY provides extended set of capabilities which may be accessed through the extended register set, Reg2 through Reg6. The Extend bit is set to 1 for RCC611.
Advanced Information
1
11
10THD
--
1 1
10-6 5
Reserved Config
0
1
4
Rmtflt
1
3
Auto
1
2
Lnkstat
1 1
1 0
Jabdet Extend
11
RCC611
PRODUCT SPECIFICATION
Register Definitions (continued)
PHY ID Register (Read Only) - Address 00010 (Register 2)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000 0000 0000 0011
PHY ID Register (Read Only) - Address 00011 (Register 3)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 11 0001 00 0000 (Model) 0000 (Model Rev)
Register 2 and Register 3 provide a 32-bit value which shall constitute a unique identifier for the PHY. Bits 15-0 of Register 2 and Bits 15-10 of Register 3 constitute the manufacturer ID (OUI). Bits 9-4 of Register 3 constitutes the vendor model and is set to zero. Bits 3-0 of Register 3 constitutes the vendor model version and is set to zero.
Advanced Information
Link Advertisement Register (Read/Write) - Address 00100 (Register 4)
15 NP 14 Ack 13 RF 12 11 10 9 A7-A0 8 7 6 5 4 3 2 S4-S0 1 0
Register 4 provides a 16-bit value used by the auto link configuration process. Bit 0 is the first bit to be transmitted followed by Bit 1, Bit 2-Bit 15. Reg 4 Bit 15 Name NP Default 0 Description Next Page (NP) bit is set to 1 to indicate that this node intends to advertise another Link code word. Otherwise, this bit is set to 0. This bit is set through the management interface. The default value is 0. Acknowledge (ACK) field is used by the auto-negotiation algorithm to indicate that a station has successfully received its link partner's code word. If no next page (Reg4 bit15=0), this bit is set to 1 after the station has successfully received at least 3 consecutive and consistent Fast Link Pulse Bursts. If next page is to be sent as indicated by the NP bit, this bit is set to 1 after the node has successfully received at least 3 consecutive and consistent FLP bursts and read the current Link Code Word. When the ACK bit is set to 1, the Link Code Word shall be sent 6 times. Initially on powerup, before the auto-negotiation starts, ACK=0. Remote Fault (RF) is set to 1 to indicate to the link partner the presence of a fault. Otherwise, this bit shall be set to 0. This bit is set to 1 through the management interface. The default value is 0. A7-A0 indicate the technological ability field. This field is used to indicate the supported technologies for each selector field value. The default value is 0. The bit assignments for various technologies are as follows: A0 A1 A2 A3 A4 A5-7 4 4-0 S4-S0 10baseT 10baseT full-duplex 100baseTX 100baseTX full-duplex 100baseT4 Reserved
4
14
Ack
0
4
13
RF
0
4
12-5
A7-A0
0
S4-S0 is the selector field. It indicates the type of message that is being sent. For IEEE802.3, S4-S0=00001.
12
PRODUCT SPECIFICATION
RCC611
Register Definitions (continued)
Link Partner Register (Read Only) - Address 00101 (Register 5)
15 NP 14 Ack 13 RF 12 11 10 9 A7-A0 8 7 6 5 4 3 2 S4-S0 1 0
Register 5 is the link partner's advertised capability register. The fields are same as those of Register 4. Upon successful completion of the auto-negotiation as indicated by Register 1/Bit 5 set to 1, Register 5 has valid information about the advertised ability of the link partner's PHY.
Expansion Register (Read Only) - Address 00110 (Register 6)
15 14 13 12 11 10 Reserved Reg 6 6 6 6 6 6 Bit 15-5 4 3 2 1 0 Name Reserved PDF LPNP NP Able Pg Rcvd LP Able Description Bits 5 through 15 of Register 6 are reserved for future expansion. PDF = 1 indicates a fault has been detected via the Parallel Detection function. Default = 0. LPNP indicates that the link partner supports the Next Page function. NP Able indicates local device is Next Page able. It is set to 1. Pg rcvd bit is a status bit and indicates that 3 identical and consecutive link code words have been received. This bit is auto clear on read. LP Able indicates that the Link Partner is able to participate in the autonegotiation algorithm. 9 8 7 6 5 4 PDF 3 LPNP 2 1 1 0
Advanced Information
Pg Rcvd LP Able
13
RCC611
PRODUCT SPECIFICATION
Register Definitions (continued)
Next Page Register (Read/Write) - Address 00111 (Register 7)
15 NP 14 Ack 13 MP 12 Ack2 11 10 9 8 7 6 5 4 3 2 1 0 M11/U11-M0/U0
This next page register is a control register used to convey information beyond that of the base page. All the bits except Ack are written through the management interface. Reg 7 7 Bit 15 14 Name NP Ack Description It is set to 1 to indicate that this node intends to advertise another next page. Otherwise, this bit is set to 0. The default value is 0. Acknowledge (Ack) field is used by the auto-negotiation algorithm to indicate that a station has successfully received the link partner's next page. If no next page (Register 7, Bit 15=0), this bit is set to 1 after the station has successfully received at least 3 consecutive and consistent Fast Link Pulse Bursts. If next page is to be sent as indicated by the NP bit, this bit is set to 1 after the node has successfully received at least 3 consecutive and consistent FLP bursts and read the current Link Code Word. When the ACK bit is set to 1, the Link Code Word shall be sent 6 times. Initially on powerup, before the auto-negotiation starts, Ack=0. Message Page (MP). This field is used to differentiate the next page to be message page or the unformatted page. If MP=1, the next page is a message page. If MP=0, the message page is unformatted. Any unformatted page shall be preceded by a message page. Acknowledge2 (Ack2). If Ack2=1, the station has the ability to comply with the received next page. If Ack2=0, the station will not comply with the message. This is the 12 bit encoded message or unformatted message depending on MP being 1 or 0 respectively.
Advanced Information
7
13
MP
7
12
Ack2
7
11-0
M11/U11-M0/U0
User Control/Status Register (Read/Write) - Address 10000 (Register 16)
15 14 13 12 11 Rsvd 10 9 8 7 6 5 4 3 2 1 0 Pwrdn1 Reserved Reserved
This register is used for additional control & status which are user specific. The additional functions are as follows: Reg 16 16 16 Bit 11 10-1 Name Reserved Reserved Description Bits 12 through 15 are reserved for future use. Flow Control Enable. This bit is used to enable flow control signalling mechanism inside the chip. Flow Control Symbols. This is a user-assigned symbol pair that is used to communicate the flow control information to the other communicating node. Do not write JK code combination (1100010001) into this set of bits. In this mode, link signalling is enabled during powerdown.
15-12 Reserved
16
0
Pwrdn1
14
PRODUCT SPECIFICATION
RCC611
Absolute Maximum Ratings1
Parameter Storage Temperature Range Junction Temperature Range Lead Temperature Range (soldering, 10 seconds) Positive Power Supply, VCC, ATXVCC, ARXVCC Voltage applied to any TTL inputs Voltage applied to any PECL inputs Voltage applied to any CMOS outputs Voltage applied to any PECL outputs Current from any CMOS outputs Current from any PECL outputs 0 -1 -1 -1 -1 -50 -50 Min -65 -55 Max 150 150 300 6 6 6 6 6 50 50 Unit C C C V V V V V mA mA
Advanced Information
Note: 1. "Absolute maximum ratings" are those beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. If the device is subjected to the limits in the absolute maximum ratings for extended periods, its reliability may be impaired. The tables of Electrical Characteristics provide conditions for actual device operation.
Operating Conditions
Parameter Ta VCC RI Ambient Operating Temperature Positive Supply Voltage (DVCC and AVCC) PECL Differential Load Resistance (Note 1) Min 0 4.75 80 5.0 100 Typ Max 70 5.25 120 Units C V
Note: 1. Differential load resistance of 100 equals 50 to AC ground on each of DOUT, DOUT.
15
RCC611
PRODUCT SPECIFICATION
DC Electrical Characteristics
AVCC, DVCC = 5V5%, GND=0V, unless otherwise indicated. Symbol Vihc Vilc Iinc Ci Vohp Volp Vop Iolp Vihc Vilc Iinc Vcm Vdiff Iip Vohc Volc Iolc Iohc ICC PD Parameter TTL input Voltage HIGH TTL input Voltage LOW TTL Input Current Input Capacitance PECL Output Voltage HIGH PECL Output Voltage LOW PECL Output Voltage amplitude PECL Output Current HIGH TTL input Voltage HIGH TTL input Voltage LOW TTL Input Current Com. Mode Range (DIN,DIN) Diff. Input Voltage (DIN, DIN) PECL Input Current Output Voltage HIGH Output Voltage LOW Output Current LOW Output Current HIGH Power Supply Current Power Dissipation 2.0 0 -1 2 0.2 -1 3.5 0 4 4 120 600 Rdiff=100, VCC=5V Rdiff=100, VCC=5V Vohp-Volp, VCC=5V 3.5 2.6 0.6 Conditions Min 2.0 0 -1 4 3.8 3.0 0.8 8 +5.5 0.8 1 5 5.5 1 VCC 0.5 Typ Max VCC+0.5 0.8 100 10 4.2 3.4 1.0 Units V V A pF V V V mA V V A V V A V V mA mA mA mW
Transmitter Section
Advanced Information
Receiver Section
16
PRODUCT SPECIFICATION
RCC611
AC Electrical Characteristics
AVCC, DVCC = 5V5%, GND = 0V, unless otherwise indicated Symbol Tt1 Tch Tcl tids tidh tr, tf ttj tdj fcc D n tacq tri, tfi tj tod Tr1 Trh Tmh Tml tims timh tom Parameter TCLK Period TCLK Pulse Width HIGH TCLK Pulse Width LOW DIN0-DIN7,TXEN,TXERR to TCLK setup time TCLK to DIN0-3, TXEN,TXERR hold time DOUT, DOUT rise and fall times DOUT, DOUT total pk-pk jitter DOUT, DOUT pk-pk duty cycle distortion Input Data Rate Variation Input Data Transition Density to Acquire and Maintain Lock Maximum run length of consective 1's or 0's before loss of lock Loop Acquisition Time for 10E-12 BER DIN, DIN input rise and fall time DIN, DIN input peak to peak jitter tolerance RCLK to DO0-DO3, RXDV valid RCLK period RCLK pulse width HIGH MDC pulse width HIGH MDC pulse width LOW MDIO to MDC setup MDIO to MDC hold MDC to MDIO 40 0.35Tr1 0.4Tr1 200 200 5 5 15 0.45Tr1 0.1 60 1000 1 0.075T 10 10% to 90% points 15 15 4 4 2 1.4 500 1000 Conditions Min. Typ. 40 Max. Units ns ns ns ns ns ns
Transmitter Section
Advanced Information
ns ps ppm ppm bits bits ns ns ns ns ns ns ns ns ns ns
Receiver Section
Management Section
Note: 1. Test conditions (unless otherwise indicated:) PECL Input rise and fall times < 1ns, RL = 100 (differential), RL = 50 (singleended). TTL Input rise and fall times < 15ns. Transition density 0.1.
17
RCC611
PRODUCT SPECIFICATION
TIming Diagrams
tr1 to 2tr1
RCLK
Dn-1p DO0-3
Dnp
D0
65-611-08
Figure 5. Receiver Timing--New Alignment
Advanced Information
TXEN
Preamble DI0-3
Data
JK DOUT
Preamble
Data
TR
65-611-09
Figure 6. Frame Sequence--Transmit
JK DIN
Preamble
Data
TR
RXDV
Preamble DO0-3
Data
65-611-10
Figure 7. Frame Sequence--Receive
18
PRODUCT SPECIFICATION
RCC611
Timing Diagrams (continued)
TCLK Tcl Tt1 tids tidh Tch
DIN0..3, TXEN, TXERR
90% DOUT, DOUT tf tr 10%
Advanced Information
DOUT, DOUT ttj, tdj
65-611-11
Figure 8. Transmitter Timing
80% DIN, DIN tfi tri 20%
DIN, DIN tj
D0-3, RXDV, ERROR Tr1 Trh Tod
RCLK
65-611-12
Figure 9. Receiver Timing
19
RCC611
PRODUCT SPECIFICATION
Applications Discussion
RJ45 RCC611
4 DI0-3 DOUT DOUT SDI TLP LPEN LOOP DIN DIN
RCC613
TXIP TXIN SDO TLP LPEN LOOP RXOP RXON TXOP TXON 1 2
Fast Ethernet MAC
4 DO0-3
Pulse Transformer
RXIP RXIN 3 6
65-611-13
Advanced Information
Valor PT4171 Figure 10. Typical Application
20
PRODUCT SPECIFICATION
RCC611
Notes:
Advanced Information
21
RCC611
PRODUCT SPECIFICATION
Notes:
Advanced Information
22
PRODUCT SPECIFICATION
RCC611
Mechanical Dimensions
100 Lead MQFP 14x20mm Package--3.9mm Footprint
Symbol A A1 A2 B C D D1 E E1 e L N ND NE
ccc
Inches Min. -- .010 .100 .008 .005 .922 Max. .134 -- .120 .015 .009 .942
Millimeters Min. -- .25 2.55 .22 .13 23.65 Max. 3.40 -- 3.05 .38 .23 24.15
Notes: Notes 1. All dimensions and tolerances conform to ANSI Y14.5M-1982. 2. Controlling dimension is millimeters. 3. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall be .08mm (.003in.) maximum in excess of the "B" dimension. Dambar cannot be located on the lower radius or the foot. 4. "L" is the length of terminal for soldering to a substrate. 5. "B" & "C" includes lead finish thickness.
3, 5 5
.783 .791 .688 .708 .547 .555 .0256 BSC .028 .040 100 30 20 0 -- 7 .005
19.90 20.10 17.65 18.15 13.90 14.10 .65 BSC .73 1.03 100 30 20 0 -- 7 .12
Advanced Information
4
D D1 Datum Plane B Pin 1 Indentifier E e 0.076" (1.95mm) Ref Lead Detail E1 .13 (.005) R Min. L .20 (.008) Min. 0 Min. .13 (.30) R .005 (.012) C
See Lead Detail A A2 B A1 Seating Plane Base Plane -CLead Coplanarity ccc C
23
RCC611
PRODUCT SPECIFICATION
Ordering Information
Product Number RCC611KR Package 100 Lead MQFP
Advanced Information
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonable expected to result in a significant injury of the user.
Fairchild Semiconductor Corporation Americas Customer Response Center Tel:1-888-522-5372 Fairchild Semiconductor Europe Fax: Email: Deutsch Tel: English Tel: Italy Tel: +49 (0) 1 80-530 85 86 europe.support@nsc.com +49 (0) 8 141-35-0 +44 (0) 1 793-85-68-56 +39 (0) 2 57 5631
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
Fairchild Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Center, 5 Canto Rd. Tsimshatsui, Kowloon Hong Kong Tel:+852 2737-7200 Fax:+852 2314-0061
National Semiconductor Japan Ltd. Tel:81-3-5620-6175 Fax:81-3-5620-6179
www.fairchildsemi.com 2/98 0.0m Stock#DS50000611 (c) 1998 Fairchild Semiconductor Corporation
www.fairchildsemi.com
RCC611
100BaseTX Transceiver
Features
* * * * * * * * * * * * * * * 100 Mbps/125 Mbaud data rates Low power 0.6 micron CMOS technology PLL Clock and data recovery Clock synthesizer Auto-negotiation 4b/5b Encode/Decode FDDI TP/PMD scrambling/descrambling Management Interface for control/status Link Pulse Signalling Conforming to MII interface of IEEE 100baseTX Fast Ethernet Standard(P802.3u/D3) Low Power Dissipation--600 mW typical Single power supply: +5V PECL compatible serial data inputs/outputs Support for external 10 Mbps PHY 100 pin PQFP (20mm x 14mm x 2.7 mm)
* * * * *
Bus Extenders Multimedia High Resolution Graphic Displays Fast Ethernet test equipment FDDI Test Equipment
Description
The RCC611 is a monolithic 125 Megabaud CMOS transceiver chip. It integrates a complete phase-locked loop clock and data recovery, a phase locked loop clock synthesizer, a 5:1 Serializer, a 1:5 Deserializer, 4B/5B Encoder, 5B/4B Decoder, auto-negotiation and a management interface for link control and status. It also includes scrambler, descrambler for twisted pair copper applications in compliance with FDDI TP-PMD specifications. In conjunction with RCC613 twisted pair transceiver, the chipset can be used for driving with category 5 unshielded twisted pair cable and Type 1 shielded twisted pair cable. The chip also can be used to directly interface to fiber optic transceiver for FDDI and 100base-FX applications. The chip meets the physical layer interface requirements of the 100 Base-X Fast Ethernet and FDDI standards. The RCC611 chip operates with a single, +5V power supply.
Advanced Information
Applications
* Fast Ethernet Adapter/hub/switch * FDDI Adapter/hub * High Speed Point to Point Links
Block Diagram
NWAYDIS TCLK 100BTFD REPEATER EX10BTFD EX10BTHD SCRMEN 4B5BDIS 4 DI0-DI3 TXEN/DI4 RESET ILSEL TXERR DESCRMB. INITIALIZE 10BTFD 10BTHD MDC MDIO ISOLATE CRS CLSN CLOCK & DATA RECOVERY DATA CLK 2:1 MUX 4B/5B ENCODER HIGH SPEED CLOCK GENERATOR A0-A3 LEDT, LEDR, LEDL LOOP LPEN /5 2 2
SCRAMB
5:1 SERIALIZER
NRZ TO NRZI
PECL DRIVER
DOUT, DOUT TLP
2
2
MGMT. INTERFACE
AUTO NEGOTIATION
DIN, DIN
BYTE ALIGNMENT CIRCUIT 4 5B/4B DECODER 1:5 DESERIALIZER NRZI TO NRZ
RXEN
ERROR DO0-DO3 RXDV/DO4 RCLK SDO
DESCRAMBLER
LINK MONITOR
65-611-01
SDI
Rev. 0.5.3
ADVANCED INFORMATION data sheets provide specification for products not yet complete or characterized. They provide design target information for customer planning purposes.
RCC611
PRODUCT SPECIFICATION
Functional Description
SDO
Transmitter Section
The RCC611 transmitter section includes a phase locked loop synthesizer, 4B/5B encoder, scrambler and 5:1 serializer. The RCC611 accepts a CMOS data nibble (DI0-DI3) and a control bit, TXEN. The data gets strobed on the positive transition of TCLK. The transmitter encodes the data, DI0-DI3 using 4b/5b coding (see Table 1). TXEN is used to denote the transmitter input being active or not. Whenever TXEN=0, IDLE symbol (11111) is encoded and transmitted. When TXEN transitions from 1 to 0, TR byte is sent before transmitting IDLE symbols. The order of transmission of the 4b/5b encoded output (E4..0)is that the most significant bit of the encoded symbol, E4 is transmitted first followed by E3,E2,E1 and E0. When 4B5BDIS is HIGH, the 4b/5b encoder is bypassed. Under that case, TXEN is used as the fifth bit (DI4) of the encoded symbol. The order of transmission of the input when 4B5BDIS is HIGH is DI4 followed by DI3, DI2, DI1 and DI0. The clock generator consists of a frequency multiplying Phase Locked Loop (PLL). The multiplying ratio is 5. The serial output goes through Non-Return-to-Zero (NRZ) to Non-Return-to-Zero Invert on Ones (NRZI) conversion. The NRZ to NRZI converter takes in the serial NRZ stream and puts out a transition for every 1 in the input stream. For zeros, there will be no transition. This will ensure that there is clocking information even when there is a long stream of 1s. The differential NRZI output is enabled to the output pins DOUT, DOUT. The serial Data Stream (DOUT/ DOUT) is transmitted at PECL levels (positive shifted ECL levels, Vth= +3.7 V). The input clock reference for the PLL Clock Generator, TCLK, typically comes from the CMOS protocol layer IC. TXERR=1 is used to force HALT symbol (00100) on the transmit output. When SCRMEN is HIGH, the encoded symbol is scrambled as per FDDI's TP-PMD standard. The scrambler used is a stream cipher scrambler. The scrambler polynomial is 1+x9+x11.
SDI 330 Sec of IDLE (min)
TXEN
IDLE TXDAT
65-611-02
Figure 1.
Advanced Information
The transmitter has the provision to loopback its output to the receiver input, when ILSEL=1. Under that case, a continuous logic LOW state is sent through the DOUT, DOUT pins. There is also one more level of loopback provided through the external RCC613 chip. When control register Reg0 bit 14 is HIGH, LOOP output pin is HIGH and the the serial output, DOUT, DOUT goes through the RCC613 TXIP, TXIN inputs and loops back through the RXOP, RXON outputs back to the DIN, DIN of RCC611.
Table 1. 4B/5B Encoding
Symbol 0 1 2 3 4 5 6 7 8 9 A B C D E F T R J K TXEN 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 DI3-DI0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 xxxx xxxx xxxx xxxx Encoded Output (E4-E0) 11110 01001 10100 10101 01010 01011 01110 01111 10010 10011 10110 10111 11010 11011 11100 11101 01101 00111 11000 10001
Descrambler Initialization
The descrambler initialization timing is shown in the accompanying diagram. On powerup, TXEN=0. RCC611 under that case, if SCRMEN=1, automatically initializes the downstream descrambler by forcing IDLE symbols (11111) which gets scrambled and driven to the medium. Transmitting IDLE continues until TXEN=1.
2
PRODUCT SPECIFICATION
RCC611
Table 1. 4B/5B Encoding (continued)
Symbol I (IDLE) H (HALT) TXEN 0 1 DI3-DI0 xxxx xxxx Encoded Output (E4-E0) 11111 00100
Table 2. 5B/4B Decoding (continued)
Symbol V V Encoded Output 10000 11011 DO3-0 xxxx xxxx ERROR 1 1
Note: 1. All the symbols are encoded as per the state diagram provided in Chapter 28 of IEEE802.3.
Note: 1. All the symbols are decoded as per the state diagram provided in Chapter 28 of IEEE802.3.
Receiver Section Table 2. 5B/4B Decoding
Symbol 0 1 2 3 4 5 6 7 8 9 A B C D E F T R J K I H V V V V V V V V Encoded Output 11110 01001 10100 10101 01010 01011 01110 01111 10010 10011 10110 10111 11010 11011 11100 11101 01101 00111 11000 10001 11111 00100 00000 00001 00010 00011 00101 00110 01000 01100 DO3-0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ERROR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 The recovered encoded data is then converted to 5 parallel data lines via 1:5 De-Serializer. The RCC611 contains a byte alignment circuitry. When the JK symbols are detected in the serial stream, the chip will automatically resynchronize the demultiplexer to byte align with the JK. The data is then decoded into an 4-bit symbol via the 5b/4b decoder as per the 5b/4b Decoding table. The received data is checked during the 5b/4b decoding and violations are flagged by bringing the Error Flag (ERROR) to a level HIGH. The 5b/4b decoder is bypassed for FDDI. The output from the 5b/4b decoder comes out as 4 bits of data, DO0-DO3 and one control bit output, RXDV. When 4B5BDIS is HIGH, the 5b/4b decoder is bypassed and the output come out as DO0-DO4 where DO4 replaces the RXDV signal. The demultiplexed data goes through a descrambler if SCRMEN=1. The descrambler descrambles the data as per the polynomial discussed in the transmit section. CLSN signal is flagged if the chip is transmitting and receiving data as per the IEEE802.3 transmit and receive state diagram in Chapter 24. CRS is flagged if either the chip is transmitting data or receiving data as per the IEEE802.3 transmit and receive state diagram in Chapter 24. Both CLSN and CRS are asynchronous signals. 3 The RCC611 recovers the clock and regenerates the encoded serial data. There is a PECL to CMOS converter for the SDI signal detect PECL input signal. If SDI goes LOW to HIGH, the SDO output goes HIGH after a minimum of 330 microseconds of continuous IDLE symbols to allow for the clock and data recovery and descrambler to synchronize. The RCC611 Receiver section includes a 2 to 1 multiplexer, a complete phase-locked loop clock and data recovery, and decoder. For twisted pair cable applications, the descrambler function is enabled when SCRMEN pin is HIGH.
Advanced Information
The 2 to 1 Mux is used to choose between the differential PECL receive input data (DIN, DIN) or the transmit output for enabling to the clock and data recovery circuit. The choice of the inputs is made by the ILSEL pin. If ILSEL is HIGH, the transmit output is looped back to the input of the receiver. If ILSEL is LOW, the receive input is chosen.
RCC611
PRODUCT SPECIFICATION
Pin Assignments
100 1 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Name DGND DGND DVCC DVCC NC AGND DGND 4B5BDIS DI0 DI1 DI2 DI3 TXEN/DI4 TXERR DGND TCLK DVCC REPEATER SCRMEN MDC MDIO LOOP NC NC DGND Pin 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Name DVCC Pin 51 52 RESET 53 LEDT 54 ISOLATE 55 LEDR 56 LEDL 57 DVCC 58 DGND 59 A0 60 A1 61 A2 62 A3 63 DGND 64 DGND 65 10BTFD 66 10BTHD EX10BTHD 67 EX10BTFD 68 69 CLSN 70 CRS 71 100BTFD 72 TLP 73 DVCC 74 DVCC NWAYDIS 75 Name LPEN RXEN DGND DGND DO3 DO2 DO1 DO0 DVCC DVCC RXDV/DO4 ERROR DGND RCLK SDO AGND DGND DVCC DGND DGND DVCC DVCC DGND DGND DVCC Pin 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Name DVCC NC NC NC NC DIN DIN NC SDI DGND AGND RXAVCC AGND RXAVCC TXAVCC AGND DGND DVCC TXAVCC TXAVCC AGND AGND ILSEL DOUT DOUT
Advanced Information
65-611-03
Pin Descriptions
Pin Name 10BTFD 10BTHD 4B5BDIS A0-A3 Pin Number 40 41 8 34-37 Type CMOS O/P CMOS O/P TTL I/P TTL I/P Description 10BaseT Full Duplex.10BTFD is used to enable or disable a local 10BaseT Full duplex device. 10BaseT Half Duplex. 10BTHD is used to enable or disable a local 10BaseT half duplex physical layer device. 4b/5b disable. This pin is used to disable the 4b/5b encoder and 5b/4b decoder. Address 0-3. A0-A3 pins are used to denote the physical address of the chip for writing or reading of the internal control/ status registers. During reset, if the PHY address are all zeroes (0000) then the MII interface will be tri-stated. Chip ground for Analog circuitry. AGND pins should be connected to the printed circuit board's ground plane at the pins. CMOS O/P Collision. This output is HIGH if the chip is receiving data and at the same time it is transmitting packet data. It is an asynchronous output. CLSN is LOW during Full duplex mode of operation. Carrier Sense. This output is HIGH if the chip is either receiving data or transmitting packet data. It is an asynchronous output. CRS is determined by receive activity during Full duplex mode. Chip ground for digital circuitry. DGND should be connected to the printed circuit board's ground plane at the pins.
AGND CLSN
6, 66, 86, 88, 91, 96, 97 44
CRS
45
CMOS O/P
DGND
1, 2,7,15, 25, 33, 38, 39, 53, 54, 63, 67, 69, 70, 73, 74, 85, 92
4
PRODUCT SPECIFICATION
RCC611
Pin Descriptions (continued)
Pin Name DIN, DIN DO0-DO3 DOUT, DOUT DVCC Pin Number 81, 82 58-55 100, 99 3, 4, 17, 26, 32, 48, 49, 59, 60, 68, 71, 72, 75, 76, 93 9-12 62 TTL I/P CMOS O/P Type PECL I/P CMOS O/P PECL O/P Description Receiver differential input data. Receiver output data. Transmit differential output data. Positive supply for Digital circuitry. The nominal value is 5V 5%. VCC should be bypassed to the ground plane with a 0.1F chip capacitor placed as close to the pin as possible. Transmitter Input data. Error Flag. ERROR goes HIGH to flag 5B/4B decoding violations. It also indicates transition to idle condition from active without end of frame delimiters. 100BaseT Full Duplex. 100BTFD when low is used to activate a LED and indicates that the RCC611 is operating in the 100BaseT Full Duplex mode. 10BaseT Full Duplex. When EX10BTFD is high, it indicates that there is available an external 10BaseT Physical layer device capable of full duplex operation. This input goes directly to Reg1 bit12. 10BaseT Half Duplex. When EX10BTHD is high, it indicates that there is available an external 10BT physical layer device with half duplex capability. This input goes directly to Reg1 bit11. Isolate. ISOLATE is used to indicate that the chip is in the isolate mode. When activated (low), all the MII interfaces will be tristated. Software can be used to override the the ISOLATE bit (Reg0 bit10). Note that the polarity of ISOLATE and Reg0 bit10 are the opposite to each other. See page 10 for more details. LED Link OK. It is used as an active LOW output to indicate that the link is OK as indicated by the FLG signal from the arbitration state machine. LED Receive. It is used as an active LOW output to indicate that the receive is active. It will be LOW if CRS=1. LED Transmit. It is used as an active LOW output to indicate that the transmit is active. It will be LOW if TXEN=1. Loop. LOOP is used to enable the loopback input of RCC613 chip. LOOP is active if the control register Reg0 bit 14 is HIGH . Link Pulse Enable. It provides an enable signal to the RCC613 for the transmit link pulse. Loop Select. ILSEL is used for differential loopback for "onboard" diagnostic of the device. When ILSEL is HIGH, the receiver accepts the serial output data from the transmitter section. Connect to GND or leave open when not used. Management Data Input/Output. MDIO is a bidirectional signal between RCC611 and the station management entity. It is used to transfer control and status information. All the read and write transactions are done synchronously with MDC. Management Data Clock. MDC is sourced by the station management entity to RCC611 as a timing reference for transfer of information on MDIO signal. MDC is an aperiodic signal whose minimum high and low times are 200 ns. 5
DI0-DI3 ERROR
Advanced Information
100BTFD
46
CMOS O/P
EX10BTFD
43
TTL I/P
EX10BTHD
42
TTL I/P
ISOLATE
29
CMOS O/P
LEDL
31
CMOS O/P
LEDR LEDT LOOP LPEN ILSEL
30 28 22 51 98
CMOS O/P CMOS O/P CMOS O/P CMOS O/P TTL I/P
MDIO
21
TTL/CMOS I/ O
MDC
20
TTL I/P
RCC611
PRODUCT SPECIFICATION
Pin Descriptions (continued)
Pin Name NWAYDIS Pin Number 50 Type TTL I/P Description Nway Disable. When NWAYDIS is high, the auto-negotiation state machines are disabled and AUTO bit (Reg0 bit12) is set to 0. Software can be used to override the AUTO bit. see page 10 for more details. For manual setting, see Table 3. Receive Clock. It is the recovered byte clock derived from the byte alignment circuitry. It provides timing to DO0-DO3, RXDV and ERROR. Repeater/Node Mode. When in the Repeater (high) mode as in the Full Duplex mode, CRS output is asserted due to activity from the receiver only. When in the Node (low) mode and not Full Duplex mode, CRS is asserted due to either receive or transmit activity. Reset. RESET is an asynchronous input which when LOW is used to reset the state machines inside the chip. RESET needs to be LOW for at least one byte clock. Receive Enable. When activated (high), it enables the outputs D0-D3, CRS, ERROR, RXDV, CLSN and RCLK. When low these outputs are tri-stated. Positive Supply for Receive Analog Circuitry. The nominal value is 5V5%. RXAVCC should be bypassed to the ground plane with a 0.1F chip capacitor placed as close to the pin as possible. CMOS O/P Receive Data Valid. RXDV when HIGH indicates the receive output data being active. When 4B5BDIS is HIGH, this pin is used as DO4, the fifth data output. Scrambler Enable. Scrmen when HIGH is used to enable the scrambler and descrambler. Signal Detect Input. It is converted to CMOS output level through a PECL to CMOS converter. Signal Detect Output. SDO is the output from the PECL to CMOS converter for the signal detect signal. The signal is asserted 330 microseconds after SDIN goes HIGH. SDO output is made synchronous to RCLK and has the same timing as the DO0-3. Transmit Clock. TCLK is the 25 MHz input reference for the internal high speed bit clock generator. It provides the timing for the input data, DI0..DI3, TXEN and TXERR. Transmit Link Pulse. TLP is HIGH when a link pulse needs to be transmitted. Positive supply for Transmit Analog circuity. The nominal value is 5V 5%. TXAVCC should be bypassed to the ground plane with a 0.1F chip capacitor placed as close to the pin as possible. TTL I/P Transmit Enable . WhenTXEN is HIGH, it indicates that the input data is active. When 4B5BDIS is HIGH, this pin is used as DI4, the fifth data input. Transmit Error. TXERR is used to transmit VIOLATION symbols (00100) on the transmit output.
RCLK
64
CMOS O/P
REPEATER
18
TTL I/P
Advanced Information
RESET
27
TTL I/P
RXEN
52
TTL I/P
RXAVCC
87,89
RXDV/DO4
61
SCRMEN SDI SDO
19 84 65
TTL I/P PECL I/P CMOS O/P
TCLK
16
TTL I/P
TLP TXAVCC
47 90, 94, 95
CMOS O/P
TXEN/DI4
13
TXERR
14
TLL I/P
6
PRODUCT SPECIFICATION
RCC611
Management Interface
Address Control Register Reg0 (Default) 00000 Address Control Register Reg0 (Default) 00000 Address Status Register Reg1 00001 Address Status Register Reg1 00001 Address PHY ID Register Reg2 00010 Address PHY ID Register Reg3 00011 Address Link Advt Register Reg4 00100 Address Link Partner Register Reg5 00101 Address Expansion Register Reg6 00110 Address Next Page Tx Register Reg7 00111 Address User Register Reg16 10000 Bit 15 NP (0) Bit 15 NP Bit 15 NP Bit 15 ............... Bit 10 11 0001 Bit 14 Ack Bit 14 Ack Bit 13 RF Bit 13 RF Bit 4 PDF Bit 13 MP Bit 12 Ack2 Bit 11 Rsvd Bit 15 Reset (0) Bit 7 Cltest (0) Bit 15 0 (T4) Bit 7 0 Bit 14 1 (TXFD) Bit 6 0 Bit 13 1 (TXHD) Bit 5 Config Bit 12 10TFD Bit 4 Rmtfl (latched) Bit 14 Loop (0) Bit 6 Bit 13 Speed (1) Bit 5 Bit 12 Auto (1) Bit 4 Bit 11 Pwrdn (0) Bit 3 Reserved Bit 11 10THD Bit 3 1 (Auto) Bit 10 0 Bit 2 Bit 9 0 Bit 1 Bit 8 0 Bit 0 R/O Bit 10 Isolate (0) Bit 2 Bit 9 Reconf (0) Bit 1 Bit 8 Duplx (0) Bit 0 R/W R/W
Lnkstat 0 1 (latched) (Jabdet) (Extend) R/O
Advanced Information
Bit 15 .................................................................................... Bit 0 0000 0000 0000 0011 Bit 9 .................. Bit 4 00000 (Model) Bit 12 ............... Bit 5 A7...A0 Bit 12 ............... Bit 5 A7...A0 Bit 3 LPNP Bit 2 1 Bit 3 ...... Bit 0 0000 (Model Rev) Bit 4 ...... Bit 0 S4...S0 Bit 4 ...... Bit 0 S4...S0 Bit 1 Pg rcvd Bit 0 LP able R/O R/O R/W R/O R/O
Bit 15 ............... Bit 5 Reserved Bit 14 Ack (0)
Bit 11 .............................. Bit 0 M11/U11...M0/U0 Bit 10 ............... Bit 1 Reserved Bit 0 Pwrdn1 R/W R/W
Bit 15 ............... Bit 12 Reserved
65-611-04
Register Description
The management interface provides a simple, two wire, serial inteface (MDIO, MDC) to connect the station management entity to the PHY for control and status gathering. MDC is sourced by the station management entity to the PHY as a timing reference for transfer of information on the MDIO signal. MDC is an aperiodic signal with a minimum high and low times of 200 ns. MDIO is a bidirectional signal between PHY and the station management entity. Control information is driven by the station management entity synchronously to MDC and sampled synchronously by PHY. Status information is driven synchronously by PHY and sampled synchronously by the station management. As shown in the figure, there are a total of 9 sixteen bit registers: Reg0, Reg1, through Reg7 and Reg16. Their functions are detailed in the register definitions section. The default values for the registers where applicable are shown in parenthesis. All the status and control transistions occur synchronous to the local clock, TCLK.
7
RCC611
PRODUCT SPECIFICATION
Idle Read: Idle Write: Idle
SOF 01 01
OpCd PHY Addr 10 AAAAA 01 AAAAA
Reg Addr RRRRR RRRRR
Fill Z0 10
Data DDDDDDDDDDDDDDDD DDDDDDDDDDDDDDDD
Management Frame Structure
Management Frame Structure
The management frame structure is as shown in the figure. In between the frames is an Idle condition. The Idle condition on the two wire interface is a logic one through the internal pullup resistor. The open drain driver for MDIO will be disabled. Prior to initiating any transaction, the station management entity will send a sequence of 32 contiguous logic one bits on MDIO with 32 corresponding cycles on MDC to provide the chip with a pattern that it can use to establish synchronization. The frame begins with an SOF field. SOF is indicated by a 01 pattern. The next field is Opcode. The Opcode for a read transaction is 10 and for a write transaction is 01. Next to Opcode is the PHY Address field. The PHY address is 5 bits. The first bit is the most significant bit of the PHY address. The chip will recognize 00000 as its own address. The next field is the register address. The register address is 5 bits. The register accessed at register address zero (00000) is the Register 0 (Reg0) and so on. Next to the Register address is the Turnaround field. An idle bit time during which no device actively drives the MDIO signal is inserted between the Register address field and the Data field of the frame during a Read transaction in order to avoid contention. During a Read transaction, the chip will drive a zero bit onto MDIO for the bit time following the idle bit and preceding the Data field. During a write transaction, the station management entity will fill this idle time with a one bit followed by a zero bit. The data field is 16 bits. The first data bit transmitted and received is the MSB of the data payload.
The information is encapsulated within a burst of closely separated link integrity test pulses that meet 10baseT transmitter waveform for Link test pulses. This burst of pulses is referred to as a Fast Link Pulse (FLP) burst. The chip issues FLP bursts at powerup. The burst consists of alternating clock/data sequence. To maintain interoperability with existing 10baseT devices, the alogrithm also supports the transmission of 10baseT compliant link integrity test pulses. 10baseT pulse is referred to as the Normal Link Pulse (NLP). A device which fails to respond to the FLP sequence and returns only the NLP indication is treated as a 10baseT compatible device.
Advanced Information
Transmit Function
The FLP burst shall contain the Link Code Word (Reg4). FLP bursts consists of 33 pulse positions. The 17 odd numbered pulse positions are always present and represent clock information. The 16 even numbered positions represent data information. A link pulse present in an even numbered position represents a logic one and a link pulse absent from an even numbered pulse position represents a logic zero. The first pulse is a clock pulse. Clock pulses are evenly spaced apart by 12530 microseconds. The data ONE pulse occurs 62.515 microseconds after the clock pulse. The first bit in consecutive FLP bursts shall occur at 168 msec interval. The pulses are sent through the TLP pin. A link pulse enable signal, LPEN, is also provided for convenience.
Receive Function
The receive function detects NLP sequence. In addition, the receive function shall detect FLP bursts and decode the information contained.
Auto-Negotiation Signalling
The chip has the provision to advertise its mode of operation to the remote end of a link segment and detect corresponding operational modes that the other device may be advertising. The auto-negotiation algorithm is performed out of band using a modified 10baseT link integrity pulse sequence. The algorithm allows the devices at both ends of a link segment to request and acknowledge use of the commom modes of operation that both devices share and to reject the use of operational modes that are not shared by both devices. When more than one common mode exists between the two devices, a mechanism is provided to allow the devices to resolve to a single mode of operation using a predetermined priority resolution table.
Arbitration Function
Arbitration function ensures proper sequencing of the autonegotiation algorithm through the transmit and receive function. The arbitration function enables the transmit function to advertise abilities and upon consistent and consecutive reception of the received link code word, advertises acknowledgement. Upon reception of 4 to 6 link code words with acknowledge bit set, the arbitration function determines the highest common denominator using the priority resolution table. If SDO goes active before autonegotiation is complete, a test window timer will be started and at the expiration of the timer, the arbitration function shall indicate that a valid link has been established.
8
PRODUCT SPECIFICATION
RCC611
Table 3. Manual Setting for Non-Auto-Negotiation
Function Auto-negotiation 100BaseT Full Duplex 100BaseT Half Duplex 10BaseT Full Duplex 10BaseT Half Duplex
IDLE SYNC
AUTO Bit (Reg0 Bit12) 1 0 0 0 0
SOF
Speed Bit (Reg0 Bit13) X 1 1 0 0
Write
Duplex Bit (Reg0 Bit8) X 1 0 1 0
IDLE
MDIO
MDC
Advanced Information
200 ns (min) 32 bit times
200 ns (min) 28 bit times
65-611-05
Figure 2. Management Interface Timing during Write to Registers
IDLE
SYNC
SOF
Write
IDLE
MDIO
MDC
tmh 32 bit times
tml 28 bit times
65-611-06
Figure 3. Management Interface Timing during Read from Registers
MDIO (during write) tims MDC tom MDIO (during read)
65-611-07
timh
Figure 4.
9
RCC611
PRODUCT SPECIFICATION
Register Definitions
Control Register (Read/Write) - Address 00000 (Register 0)
15 Reset 7 Cltest All of the control register bits (0 through 15) are read/write. The functions within the Reg0 are as follows: speed, full/half duplex, Isolate, Automatic speed selection, Loopback, Collision test. The individual bit descriptions and the default values are as follows: 14 Loop 6 13 Speed 5 12 Auto 4 11 Pwrdn 3 Reserved 10 Isolate 2 9 Reconfig 1 8 Duplex 0
Advanced Information
Reg 0
Bit 15
Name Reset
Default Description O Reset=1 resets the PHY, i.e. all the control and status registers are reset to their default states. This function is self-clearing. The default value is zero. Writes to other bits of control register has no effect until the reset process is completed. Loop=1. This bit is used to enable the LOOP output pin HIGH and thereby enable the local loopback of the RCC611 through the RCC613. The default value is zero. This bit is used to manually set the speed of operation. Speed=1 denotes 100 Mbps mode of operation. Speed=0 denotes 10 Mbps mode of operation. This bit is used to manually set the speed of operation. This bit is effective only if Auto (Reg0, bit 12)=0 (ie. manual speed selection). The default value is one. If bit12 (Auto) of Reg0=0, and Speed=0, 10Mbps operation is enabled and determined by Reg 1 bit 12 and bit 11. If bit12 (Auto) of Reg0=0 and Speed=1, 100 Mbps operation is enabled. Auto=1 denotes automatic speed selection. Auto=0 denotes manual speed selection. Auto speed selection enables PHY's auto selection algorithm. The default value=1. Pwrdn=1 shuts off the power to the chip except the portions involving the management transactions. The default value=0. Both Pwrdn & Pwrdn1 cannot be HIGH at the same time. If so, there will not be any power down. The chip isolates its data path from the parallel (MII) interface when Isolate=1. When Isolate=1, the chip will tristate the CMOS outputs: RXCLK, RXDV, ERROR, RXD3..RXD0, CLSN, & CRS. Also, the TTL inputs (DI0..DI3, TXEN, TXERR, TCLK) are ignored. The default value=0. If A(3..0)=0000, the default value=1. This bit is brought out as ISOLATE pin. This can be used to enable or disable an external additional PHY connected to the same controller. Autolink configuration process will be initiated when Reconfig=1. This bit is self-clearing. When auto-configuration is disabled (Auto=0), Duplex=1 sets the chip for full duplex operation. In this mode, CRS signal is determined by receive activity. Duplex=0 sets the chip for half duplex operation. The default value of Duplex=0. When Cltest=1, CLSN is asserted in response to TXEN. The default value of Cltest=0. These bits are reserved for future definition. They are set equal to zero.
0
14
Loop
O
0
13
Speed
I
0
12
Auto
I
0
11
Pwrdn
O
0
10
Isolate
O
0 0
9 8
Reconfig Duplex
O O
0 0
7 6-0
Cltest Reserved
O O
10
PRODUCT SPECIFICATION
RCC611
Register Definitions (continued)
Status Register (Read Only) - Address 00001 (Register 1)
15 0 (T4) 7 0 14 1 (TXFD) 6 0 13 1 (TXHD) 5 Config 12 10TFD 4 Rmtflt 11 10THD 3 1 (Auto) 10 0 2 Lnkstat 9 0 1 0 (Jabdet) 8 0 0 Extend
The status functions are as follows: information about all the modes of operation supported by the local PHY, the status of auto-negotiation, and if auto-negotiation is supported by the local PHY or not. Reg 1 1 1 1 Bit 15 14 13 12 Name T4 TXFD TXHD 10TFD Default 0 1 1 -- Description T4=1 indicates the mode is 100 base T4 capable. T4 is set to 0 for RCC611 TXFD=1 indicates the mode is capable of full duplex transmission at 100 base TX. TXFD is set to 1 for RCC611 TXHD=1 indicates the mode is capable of half duplex transmission at 100 base TX. TXHD is set to 1 for RCC611 10TFD=1 indicates the local PHY has the ability to perform full duplex link transmission and reception using the 10baseT signalling specification. 10TFD=1 if the input pin EX10BTFD is equal to 1. 10THD=1 indicates the local PHY has the ability to perform half duplex link transmission and reception using the 100baseTX signalling specification. 10THD=1 if the input pin EX10BTHD is equal to 1. Bits10-6 are reserved for future definition. These bits are set to zero. When Config=1, it indicates that the auto link configuration has been completed and the Registers Reg4, Reg5 and Reg6 are valid. When Config=0, it indicates that the auto link configuration has not been completed. If control register bit 12 (Auto) =0, Config is set to zero. When Rmtflt=1, it indicates that a remote fault condition has been detected. This bit is set to 1 if Reg5 bit 13=1. This bit will remain set until read. 1 Auto=1 constitutes the ability of RCC611 to perform auto link detection and configuration. It is set to 1 to indicate that the local PHY has the ability to perform auto link detection and configuration. Lnkstat=1 indicates that the link is active. SDO going HIGH sets Lnkstat HIGH and SDO going HIGH to LOW causes Lnkstat to go HIGH to LOW. Lnkstat=0 indicates that the link is not valid. The occurance of a link failure condition will cause Lnkstat=0 and will remain equal to zero until read. It is set to 1 after read and remains set until the next occurence of SDO going HIGH to LOW. 0 1 This bit is set to 0 since jabber detect function is not supported. Extend=1 indicates that the PHY provides extended set of capabilities which may be accessed through the extended register set, Reg2 through Reg6. The Extend bit is set to 1 for RCC611.
Advanced Information
1
11
10THD
--
1 1
10-6 5
Reserved Config
0
1
4
Rmtflt
1
3
Auto
1
2
Lnkstat
1 1
1 0
Jabdet Extend
11
RCC611
PRODUCT SPECIFICATION
Register Definitions (continued)
PHY ID Register (Read Only) - Address 00010 (Register 2)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000 0000 0000 0011
PHY ID Register (Read Only) - Address 00011 (Register 3)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 11 0001 00 0000 (Model) 0000 (Model Rev)
Register 2 and Register 3 provide a 32-bit value which shall constitute a unique identifier for the PHY. Bits 15-0 of Register 2 and Bits 15-10 of Register 3 constitute the manufacturer ID (OUI). Bits 9-4 of Register 3 constitutes the vendor model and is set to zero. Bits 3-0 of Register 3 constitutes the vendor model version and is set to zero.
Advanced Information
Link Advertisement Register (Read/Write) - Address 00100 (Register 4)
15 NP 14 Ack 13 RF 12 11 10 9 A7-A0 8 7 6 5 4 3 2 S4-S0 1 0
Register 4 provides a 16-bit value used by the auto link configuration process. Bit 0 is the first bit to be transmitted followed by Bit 1, Bit 2-Bit 15. Reg 4 Bit 15 Name NP Default 0 Description Next Page (NP) bit is set to 1 to indicate that this node intends to advertise another Link code word. Otherwise, this bit is set to 0. This bit is set through the management interface. The default value is 0. Acknowledge (ACK) field is used by the auto-negotiation algorithm to indicate that a station has successfully received its link partner's code word. If no next page (Reg4 bit15=0), this bit is set to 1 after the station has successfully received at least 3 consecutive and consistent Fast Link Pulse Bursts. If next page is to be sent as indicated by the NP bit, this bit is set to 1 after the node has successfully received at least 3 consecutive and consistent FLP bursts and read the current Link Code Word. When the ACK bit is set to 1, the Link Code Word shall be sent 6 times. Initially on powerup, before the auto-negotiation starts, ACK=0. Remote Fault (RF) is set to 1 to indicate to the link partner the presence of a fault. Otherwise, this bit shall be set to 0. This bit is set to 1 through the management interface. The default value is 0. A7-A0 indicate the technological ability field. This field is used to indicate the supported technologies for each selector field value. The default value is 0. The bit assignments for various technologies are as follows: A0 A1 A2 A3 A4 A5-7 4 4-0 S4-S0 10baseT 10baseT full-duplex 100baseTX 100baseTX full-duplex 100baseT4 Reserved
4
14
Ack
0
4
13
RF
0
4
12-5
A7-A0
0
S4-S0 is the selector field. It indicates the type of message that is being sent. For IEEE802.3, S4-S0=00001.
12
PRODUCT SPECIFICATION
RCC611
Register Definitions (continued)
Link Partner Register (Read Only) - Address 00101 (Register 5)
15 NP 14 Ack 13 RF 12 11 10 9 A7-A0 8 7 6 5 4 3 2 S4-S0 1 0
Register 5 is the link partner's advertised capability register. The fields are same as those of Register 4. Upon successful completion of the auto-negotiation as indicated by Register 1/Bit 5 set to 1, Register 5 has valid information about the advertised ability of the link partner's PHY.
Expansion Register (Read Only) - Address 00110 (Register 6)
15 14 13 12 11 10 Reserved Reg 6 6 6 6 6 6 Bit 15-5 4 3 2 1 0 Name Reserved PDF LPNP NP Able Pg Rcvd LP Able Description Bits 5 through 15 of Register 6 are reserved for future expansion. PDF = 1 indicates a fault has been detected via the Parallel Detection function. Default = 0. LPNP indicates that the link partner supports the Next Page function. NP Able indicates local device is Next Page able. It is set to 1. Pg rcvd bit is a status bit and indicates that 3 identical and consecutive link code words have been received. This bit is auto clear on read. LP Able indicates that the Link Partner is able to participate in the autonegotiation algorithm. 9 8 7 6 5 4 PDF 3 LPNP 2 1 1 0
Advanced Information
Pg Rcvd LP Able
13
RCC611
PRODUCT SPECIFICATION
Register Definitions (continued)
Next Page Register (Read/Write) - Address 00111 (Register 7)
15 NP 14 Ack 13 MP 12 Ack2 11 10 9 8 7 6 5 4 3 2 1 0 M11/U11-M0/U0
This next page register is a control register used to convey information beyond that of the base page. All the bits except Ack are written through the management interface. Reg 7 7 Bit 15 14 Name NP Ack Description It is set to 1 to indicate that this node intends to advertise another next page. Otherwise, this bit is set to 0. The default value is 0. Acknowledge (Ack) field is used by the auto-negotiation algorithm to indicate that a station has successfully received the link partner's next page. If no next page (Register 7, Bit 15=0), this bit is set to 1 after the station has successfully received at least 3 consecutive and consistent Fast Link Pulse Bursts. If next page is to be sent as indicated by the NP bit, this bit is set to 1 after the node has successfully received at least 3 consecutive and consistent FLP bursts and read the current Link Code Word. When the ACK bit is set to 1, the Link Code Word shall be sent 6 times. Initially on powerup, before the auto-negotiation starts, Ack=0. Message Page (MP). This field is used to differentiate the next page to be message page or the unformatted page. If MP=1, the next page is a message page. If MP=0, the message page is unformatted. Any unformatted page shall be preceded by a message page. Acknowledge2 (Ack2). If Ack2=1, the station has the ability to comply with the received next page. If Ack2=0, the station will not comply with the message. This is the 12 bit encoded message or unformatted message depending on MP being 1 or 0 respectively.
Advanced Information
7
13
MP
7
12
Ack2
7
11-0
M11/U11-M0/U0
User Control/Status Register (Read/Write) - Address 10000 (Register 16)
15 14 13 12 11 Rsvd 10 9 8 7 6 5 4 3 2 1 0 Pwrdn1 Reserved Reserved
This register is used for additional control & status which are user specific. The additional functions are as follows: Reg 16 16 16 Bit 11 10-1 Name Reserved Reserved Description Bits 12 through 15 are reserved for future use. Flow Control Enable. This bit is used to enable flow control signalling mechanism inside the chip. Flow Control Symbols. This is a user-assigned symbol pair that is used to communicate the flow control information to the other communicating node. Do not write JK code combination (1100010001) into this set of bits. In this mode, link signalling is enabled during powerdown.
15-12 Reserved
16
0
Pwrdn1
14
PRODUCT SPECIFICATION
RCC611
Absolute Maximum Ratings1
Parameter Storage Temperature Range Junction Temperature Range Lead Temperature Range (soldering, 10 seconds) Positive Power Supply, VCC, ATXVCC, ARXVCC Voltage applied to any TTL inputs Voltage applied to any PECL inputs Voltage applied to any CMOS outputs Voltage applied to any PECL outputs Current from any CMOS outputs Current from any PECL outputs 0 -1 -1 -1 -1 -50 -50 Min -65 -55 Max 150 150 300 6 6 6 6 6 50 50 Unit C C C V V V V V mA mA
Advanced Information
Note: 1. "Absolute maximum ratings" are those beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. If the device is subjected to the limits in the absolute maximum ratings for extended periods, its reliability may be impaired. The tables of Electrical Characteristics provide conditions for actual device operation.
Operating Conditions
Parameter Ta VCC RI Ambient Operating Temperature Positive Supply Voltage (DVCC and AVCC) PECL Differential Load Resistance (Note 1) Min 0 4.75 80 5.0 100 Typ Max 70 5.25 120 Units C V
Note: 1. Differential load resistance of 100 equals 50 to AC ground on each of DOUT, DOUT.
15
RCC611
PRODUCT SPECIFICATION
DC Electrical Characteristics
AVCC, DVCC = 5V5%, GND=0V, unless otherwise indicated. Symbol Vihc Vilc Iinc Ci Vohp Volp Vop Iolp Vihc Vilc Iinc Vcm Vdiff Iip Vohc Volc Iolc Iohc ICC PD Parameter TTL input Voltage HIGH TTL input Voltage LOW TTL Input Current Input Capacitance PECL Output Voltage HIGH PECL Output Voltage LOW PECL Output Voltage amplitude PECL Output Current HIGH TTL input Voltage HIGH TTL input Voltage LOW TTL Input Current Com. Mode Range (DIN,DIN) Diff. Input Voltage (DIN, DIN) PECL Input Current Output Voltage HIGH Output Voltage LOW Output Current LOW Output Current HIGH Power Supply Current Power Dissipation 2.0 0 -1 2 0.2 -1 3.5 0 4 4 120 600 Rdiff=100, VCC=5V Rdiff=100, VCC=5V Vohp-Volp, VCC=5V 3.5 2.6 0.6 Conditions Min 2.0 0 -1 4 3.8 3.0 0.8 8 +5.5 0.8 1 5 5.5 1 VCC 0.5 Typ Max VCC+0.5 0.8 100 10 4.2 3.4 1.0 Units V V A pF V V V mA V V A V V A V V mA mA mA mW
Transmitter Section
Advanced Information
Receiver Section
16
PRODUCT SPECIFICATION
RCC611
AC Electrical Characteristics
AVCC, DVCC = 5V5%, GND = 0V, unless otherwise indicated Symbol Tt1 Tch Tcl tids tidh tr, tf ttj tdj fcc D n tacq tri, tfi tj tod Tr1 Trh Tmh Tml tims timh tom Parameter TCLK Period TCLK Pulse Width HIGH TCLK Pulse Width LOW DIN0-DIN7,TXEN,TXERR to TCLK setup time TCLK to DIN0-3, TXEN,TXERR hold time DOUT, DOUT rise and fall times DOUT, DOUT total pk-pk jitter DOUT, DOUT pk-pk duty cycle distortion Input Data Rate Variation Input Data Transition Density to Acquire and Maintain Lock Maximum run length of consective 1's or 0's before loss of lock Loop Acquisition Time for 10E-12 BER DIN, DIN input rise and fall time DIN, DIN input peak to peak jitter tolerance RCLK to DO0-DO3, RXDV valid RCLK period RCLK pulse width HIGH MDC pulse width HIGH MDC pulse width LOW MDIO to MDC setup MDIO to MDC hold MDC to MDIO 40 0.35Tr1 0.4Tr1 200 200 5 5 15 0.45Tr1 0.1 60 1000 1 0.075T 10 10% to 90% points 15 15 4 4 2 1.4 500 1000 Conditions Min. Typ. 40 Max. Units ns ns ns ns ns ns
Transmitter Section
Advanced Information
ns ps ppm ppm bits bits ns ns ns ns ns ns ns ns ns ns
Receiver Section
Management Section
Note: 1. Test conditions (unless otherwise indicated:) PECL Input rise and fall times < 1ns, RL = 100 (differential), RL = 50 (singleended). TTL Input rise and fall times < 15ns. Transition density 0.1.
17
RCC611
PRODUCT SPECIFICATION
TIming Diagrams
tr1 to 2tr1
RCLK
Dn-1p DO0-3
Dnp
D0
65-611-08
Figure 5. Receiver Timing--New Alignment
Advanced Information
TXEN
Preamble DI0-3
Data
JK DOUT
Preamble
Data
TR
65-611-09
Figure 6. Frame Sequence--Transmit
JK DIN
Preamble
Data
TR
RXDV
Preamble DO0-3
Data
65-611-10
Figure 7. Frame Sequence--Receive
18
PRODUCT SPECIFICATION
RCC611
Timing Diagrams (continued)
TCLK Tcl Tt1 tids tidh Tch
DIN0..3, TXEN, TXERR
90% DOUT, DOUT tf tr 10%
Advanced Information
DOUT, DOUT ttj, tdj
65-611-11
Figure 8. Transmitter Timing
80% DIN, DIN tfi tri 20%
DIN, DIN tj
D0-3, RXDV, ERROR Tr1 Trh Tod
RCLK
65-611-12
Figure 9. Receiver Timing
19
RCC611
PRODUCT SPECIFICATION
Applications Discussion
RJ45 RCC611
4 DI0-3 DOUT DOUT SDI TLP LPEN LOOP DIN DIN
RCC613
TXIP TXIN SDO TLP LPEN LOOP RXOP RXON TXOP TXON 1 2
Fast Ethernet MAC
4 DO0-3
Pulse Transformer
RXIP RXIN 3 6
65-611-13
Advanced Information
Valor PT4171 Figure 10. Typical Application
20
PRODUCT SPECIFICATION
RCC611
Notes:
Advanced Information
21
RCC611
PRODUCT SPECIFICATION
Notes:
Advanced Information
22
PRODUCT SPECIFICATION
RCC611
Mechanical Dimensions
100 Lead MQFP 14x20mm Package--3.9mm Footprint
Symbol A A1 A2 B C D D1 E E1 e L N ND NE
ccc
Inches Min. -- .010 .100 .008 .005 .922 Max. .134 -- .120 .015 .009 .942
Millimeters Min. -- .25 2.55 .22 .13 23.65 Max. 3.40 -- 3.05 .38 .23 24.15
Notes: Notes 1. All dimensions and tolerances conform to ANSI Y14.5M-1982. 2. Controlling dimension is millimeters. 3. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall be .08mm (.003in.) maximum in excess of the "B" dimension. Dambar cannot be located on the lower radius or the foot. 4. "L" is the length of terminal for soldering to a substrate. 5. "B" & "C" includes lead finish thickness.
3, 5 5
.783 .791 .688 .708 .547 .555 .0256 BSC .028 .040 100 30 20 0 -- 7 .005
19.90 20.10 17.65 18.15 13.90 14.10 .65 BSC .73 1.03 100 30 20 0 -- 7 .12
Advanced Information
4
D D1 Datum Plane B Pin 1 Indentifier E e 0.076" (1.95mm) Ref Lead Detail E1 .13 (.005) R Min. L .20 (.008) Min. 0 Min. .13 (.30) R .005 (.012) C
See Lead Detail A A2 B A1 Seating Plane Base Plane -CLead Coplanarity ccc C
23
RCC611
PRODUCT SPECIFICATION
Ordering Information
Product Number RCC611KR Package 100 Lead MQFP
Advanced Information
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonable expected to result in a significant injury of the user.
Fairchild Semiconductor Corporation Americas Customer Response Center Tel:1-888-522-5372 Fairchild Semiconductor Europe Fax: Email: Deutsch Tel: English Tel: Italy Tel: +49 (0) 1 80-530 85 86 europe.support@nsc.com +49 (0) 8 141-35-0 +44 (0) 1 793-85-68-56 +39 (0) 2 57 5631
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
Fairchild Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Center, 5 Canto Rd. Tsimshatsui, Kowloon Hong Kong Tel:+852 2737-7200 Fax:+852 2314-0061
National Semiconductor Japan Ltd. Tel:81-3-5620-6175 Fax:81-3-5620-6179
www.fairchildsemi.com 2/98 0.0m Stock#DS50000611 (c) 1998 Fairchild Semiconductor Corporation
www.fairchildsemi.com
RCC613
125 Mbaud Twisted Pair Transceiver (TPT)
Features
* * * * * * * * * * * Designed for 100BaseTX Fast Ethernet PMD Standard Controlled symmetric transmit output rise/fall time Tristatable transmit output Adjustable transmit amplitude for longer cables DC restoration (Baseline wander compensation) No receive input attenuation required Adaptive line equalization Compatible with RCC611 Fast Ethernet PHY Fast link pulse driving 28 pin PLCC 525mW power dissipation
Description
The RCC613 is a monolithic 125 Megabaud twisted pair transceiver (TPT) designed for IEEE 802.3 Fast Ethernet applications. It implements the Physical Media Dependent (PMD) Layer requirements of the 100baseTX Fast Ethernet standard. It can be used with RCC611 Fast Ethernet PHY to perform the 100baseTX physical layer requirements. The RCC613 Integrates MLT3 encoding, data driving and receiving, link pulse driving, adaptive equalization, base line wander compensation (DC restoration) and MLT3 decoding. It operates with a single +5V supply.
Preliminary Information
Applications
* * * * 100Mbps Fast Ethernet Bus extenders Serial Video Communication Fast Ethernet test equipment
Block Diagram
TLP TXIP, TXIN RXOP, TPMODE LOOP RXON SDO
TXVCC TXGND
2 2 2
2 2 TO 1 MUX 2 MLT3 DECODER LOW PASS FILTER DC RESTORE (Base Line Wander Compensation) PEAK DETECT ADAPTIVE EQUALIZER VARIABLE GAIN DIFFERENTIAL AMPLIFIER CRP CRN CEQ SIGNAL DETECT RXVCC RXGND
MLT3 ENCODER 2
LPEN REXT TXDIS
DRIVER
REF
2 TXOP, TXON
2 RXIP, RXIN
65-613-01
Rev. 0.9.3
PRELIMINARY INFORMATION describes products that are not in full production at the time of printing. Specifications are based on design goals and limited characterization. They may change without notice. Contact Raytheon Electronics for current information.
RCC613
PRODUCT SPECIFICATION
Functional Description
Transmitter Section
The RCC613 transmitter section includes the MLT3 Encoder and Twisted pair driver. The transmitter drives either unshielded or shielded twisted pair cables to implement FDDI TP/PMD standard. The differential PECL data from TXIP, TXIN goes through a MLT3 Encoder. The MLT3 encoder is enabled when the TPMODE pin is LOW. The data is encoded per the following rules: The encoded output takes on one of three possible levels: High, Middle, or Low. Whenever the input signal changes state, the output will also change state. If the output is in the middle state, the state to which it will change to is dependent on the previous state. If the previous state was high(low), then the output will change to a low(high) state from the middle state. If the output is at either a high or a low state, then the next transition will cause the output to change to the middle state. The encoder conforms to the diagram shown in Figure 1.
NRZI
The transition time of the output is closely matched and controlled to reduce radiated emissions and to comply with FCC class B regulations. The transmitter section has a pin LPEN to enable fast link pulses for driving. When LPEN is HIGH and Transmit Link Pulse (TLP) input is HIGH, the outputs TXOP and TXON will be at HIGH of 3 volts.
Receiver Section
The signal from the transformer drives RXIP and RXIN and goes through a differential amplifier stage and then to a peak detect circuitry. The output of the peak detector goes to the signal detect comparator and to a low pass filter to remove the AC components. The low pass filter output then goes to an adaptive equalizer. The equalizer output provides an adaptive gain control for the variable gain differential amplifier to compensate for the cable distortion. The gain depends on the measured peak value of the input. The equalizer filter characteristics can be adjusted by means of an external capacitor connected between CEQ and ground (1000pF is suggested). The variable gain differential amplifier output also goes through the DC restoration and decode circuitry. The purpose of the DC restoration (baseline wander compensation) circuit is to provide DC restoration to the data stream on the occurrence of a long run-length. During those instances, the average DC tends to drift away from the decode circuit's threshold. The DC restoration circuit integrates the decoder output to provide a DC offset to the envelope to center it around the threshold of the decoder circuit. The MLT3 decoder also provides 3-level to 2-level conversion. The decoder conforms to the diagram shown in Figure 1. The decoder output goes through a 2 to 1 multiplexer. The other input to the multiplexer comes from the transmitter inputs TXIP, TXIN. If LOOP signal is HIGH, the transmit input is looped back to RXOP, RXON through the multiplexer. Under this condition, the transmitter output (TXOP, TXON) presents a logic LOW voltage. If LOOP is LOW, the decoder output is enabled and routes the signal to RXOP, RXON. The receive section also includes a signal detect logic. The signal detect logic filters the input signal and if the signal exceeds a specified level, the SDO output will go HIGH.
Preliminary Information
0 MLT3
-1
0
+1
+1
0
-1
0
0
+1
0
Figure 1. MLT3-NRZI Conversion Diagram
When TPMODE pin is HIGH, the MLT3 encoder is bypassed and the data directly goes to the current source driver. The driver output current is controlled by external resistor between REXT and REF pins. The voltage at the output is a function of the load termination across the differential output. If R is the effective load termination and I is the current source, the peak to peak output voltage V = IR. I = 40/REXT(in k) mA, where REXT is the resistor connected between the REXT and REF pins. The TP driver provides a differential 2 V peak to peak swing voltage output across TXOP, TXON through a 100 termination in parallel with two 50 pullup resistor, when REXT = 1K. TXOP,TXON are connected externally to a coupling transformer and then to the twisted pair cable medium. The driver can be tristated by means of a pin TXDIS. When TXDIS is HIGH, the output presents a high impedance. In 2-level mode (TPMODE = HIGH), the output amplitude is half that of 3-level mode.
2
PRODUCT SPECIFICATION
RCC613
Pin Assignments
RXGND RXVCC RXVCC
26
RXIN
RXIP
4
3
2
1
28
CRP TPMODE LOOP TXON TXOP TXVCC TXGND
27
CEQ
CRN
5 6 7 8 9 10 11 12 13 14 15 16 17 18
25 24 23
RXOP RXON RXGND SDO NC LPEN TXGND
RCC613
22 21 20 19
Preliminary Information
REXT
REF
TXDIS
TXIN
TXVCC
TXIP
TLP
65-613-04
Pin Definitions
Pin Name TXVCC Pin Number 10, 17 Pin Type Power Description Transmit Positive Supply. The nominal value is 5V 5%. TXVCC should be bypassed to TXGND with a 0.1F chip capacitor placed as close to the pin as possible. Receive Positive Supply. The nominal value is 5V 5%. RXVCC should be bypassed to RXGND with a 0.1F chip capacitor placed as close to the pin as possible. Transmit Ground. Chip ground for transmit circuitry. TXGND should be connected to the printed circuit board's ground plane through a ferrite bead of value 0.2H to 1H. Receive Ground. Chip ground for digital circuitry. RXGND should be connected to the printed circuit board's ground plane through a ferrite bead of value 0.2H to 1H. Transmit Input Positive, Transmit Input Negative. Differential NRZI Transmit data from the PHY chip. Twisted Pair Encode Mode. When TPMODE is LOW, the transmit output is MLT3 encoded with three levels. When TPMODE is HIGH, the transmit output is NRZI with two levels. Transmit Output Positive, Transmit Output Negative. (MLT3 outputs if TPMODE = 0, NRZI outputs if TPMODE = 1). Transmit differential current driver data outputs. External Resistor. It is connected between REXT and REF to adjust the amplitudes of TXOP,TXON. For MLT3 signals, the peak-to-peak differential voltage of 2V is generated across TXOP, TXON when the effective differential load is 50 and REXT = 1K. Receive Input Positive, Receive Input Negative. (MLT3 inputs if TPMODE = 0, NRZI inputs if TPMODE = 1). Receive differential data inputs. Equalizer Capacitor. A capacitor is connected between CEQ and RXGND to adjust the gain of the adaptive equalizer. 1000 pF is recommended.
RXVCC
26, 28
Power
TXGND
11, 19
Power
RXGND
23,3
Power
TXIP, TXIN TPMODE
15, 16 6
PECL DIFF I/P TTL I/P
TXOP,TXON
9,8
O/P
REXT
12
Analog
RXIP, RXIN
2,1
I/P
CEQ
27
Analog
3
RCC613
PRODUCT SPECIFICATION
Pin Definitions (continued)
Pin Name RXOP, RXON Pin Number 25, 24 Pin Type PECL DIFF O/P Description Receive Output Positive, Receive Output Negative. Differential NRZI receive data to the PHY chip. Do not tie external termination lower than 510 to RXGND. For 50 applications, 50 from the outputs to 3V may be connected. Signal Detect. When SDO is HIGH, it indicates that the receive input is active. Do not tie any external termination resistor to SDO. Transmit Link Pulse. If TLP and LPEN are both HIGH, the transmitter generates a 3V differential across TXOP and TXON. Link Pulse Enable. This pin, when HIGH, is used to enable the link pulse driving. Loop. If LOOP is HIGH, it loops the transmit input data, TXIP, TXIN to the receiver output, RXOP, RXON. If LOOP is LOW, the normal operation occurs. Transmit Disable. If TXDIS is HIGH, the transmitter disables the TXOP, TXON output and presents a high impedance. If TXDIS is LOW, the transmitter enables normal data transmission through RCC613. DC Restoration Capacitor Positive, DC Restoration Capacitor Negative. A capacitor is connected at each of CRP, and CRN to RXGND to provide DC restoration. 1000 pF is recommended. Reference. Provides the reference voltage to set the transmit output amplitude when an external resistor is connected between REF and REXT. It is nominally 2.5 Volts.
SDO
22
PECL O/P
TLP
18
TTL I/P
Preliminary Information
LPEN LOOP
20 7
TTL I/P TTL I/P
TXDIS
14
TTL I/P
CRP, CRN
5, 4
Analog
REF
13
Analog O/P
Absolute Maximum Ratings
(beyond which the device may be damaged)1 Parameter Positive power supply Voltage applied to any PECL/MLT3 outputs Voltage applied to any TTL inputs Voltage applied to any PECL inputs Current from any PECL/MLT3 outputs Operating Temperature Storage Temperature Junction Temperature Lead Soldering (10 seconds) Min. 0 -0.5 -0.5 -0.5 -50 0 -65 -55 Max. 6 VCC VCC VCC +50 70 150 150 300 Units V V V V mA C C C C
Note: 1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded.
4
PRODUCT SPECIFICATION
RCC613
Operating Conditions
Parameter Ta VCC Rutp Rstp Ambient Operating Temperature Positive Supply Voltage (TXVCC and RXVCC) Unshielded Twisted Pair Differential Load Resistance Shielded Twisted Pair Differential Load Resistance Min. 0 4.75 99.8 149.7 5.00 100 150 Typ. Max. 70 5.25 100.2 150.3 Units C V
DC Electrical Characteristics
RXVCC, TXVCC = 5V 5%, RXGND, TXGND = 0V, unless otherwise indicated Parameter Transmitter Section Vihc Vilc Iinc C Vcm Vdiff Iip Vomh Voml Vohs Vols Volp Vdif Vcm Vocm Vodiff Vohs Vols Vonth Vofth ICC PD TTL input Voltage HIGH TTL input Voltage LOW TTL Input Current Input Capacitance Com. Mode Range (TXIP,TXIN) Diff. Input Voltage (TXIP,TXIN) PECL Input Current MLT3 Positive Peak Voltage MLT3 Negative Peak Voltage NRZI Output Voltage HIGH NRZI Output Voltage LOW Link Pulse Output RXIP, RXIN Diff Input Voltage RXIP, RXIN Com. Mode Range RXOP, RXON Com. Mode Range 510 to GND on RXOP, RXON Diff Output Voltage RXOP, RXON SDO Output HIGH SDO Output LOW SDO Turnon threshold SDO Turnoff threshold Power Supply Current Power Dissipation VCC-1.1 VCC-2 350 260 110 525 0.4 2.6 VCC-1.5 1.5 VCC-0.7 VCC-1.4 Diff load R=100 0.2% and 50 on both TXOP, TXON to VCC 3.3 0.4 -20 0 4.2 3.2 4.2 3.2 3 2 3.0 3.7 4.1 2.0 20 2.0 0 VCC 0.8 25 V V A pF V Vpp A V V V V V V V V Vpp V V mV mV mA mW Conditions Min. Typ. Max. Units
Preliminary Information
Receiver Section
Power Section
5
RCC613
PRODUCT SPECIFICATION
AC Electrical Characteristics1
VCC = 5V 5%, GND = 0V, unless otherwise indicated.
RXIP
RXIN Ton SDO Toff
65-613-05
Preliminary Information
Parameter Receiver Section Ton Toff SDO turnon delay @ CEQ = 1000pF SDO turnoff delay @ CEQ = 1000pF
Conditions Diff I/P > 1V Diff I/P < 0.2V
Min
Typ 1 200
Max 1000 350
Units s s
Notes: 1. Test conditions (unless otherwise indicated:) PECL Input rise and fall times 2ns, RL = 100. TTL Input rise and fall times 15ns. Transition density 0.1.
Timing Diagrams
Tf, Tr Ttl Vomh TXIP, TXIN TXOP, TXON (TPMODE = 0) Vomh TXOP, TXON (TPMODE = 0) Voml Ttj, Tdj 90% 10% 90% 10% TXOP, TXON (TPMODE = 1) 90% 10% Tf TXOP, TXON (TPMODE = 1) Tr Voml 90% 10% 90% 10%
Ttj, Tdj
65-613-06
Transmitter Timing
Parameter Tr Tf Tdj Ttj Ttl TXOP, TXON rise time 10% to 90% TXOP, TXON fall time 90% to 10% TXOP, TXON duty cycle distortion (peak-to-peak) Random jitter Transmit latency
Conditions 100 termination
Min
Typ 2.7 2.7 0.3 300 5.0
Max
Units ns ns ns ps ns
6
PRODUCT SPECIFICATION
RCC613
Timing Diagrams (continued)
90% RXOP, RXON 10% RXIP, RXIN Trf Trr
RXOP, RXON Trl
RXOP, RXON
Trdj, Trj
65-613-07
Receiver Timing
Preliminary Information
Parameter Trr Tfr Trdj Trj Trl RXOP, RXON rise time 10% to 90% RXOP, RXON fall time 90% to 10% RXOP, RXON duty cycle distortion (peakto-peak) @ 100m calbe (UTP) RXOP, RXON peak to peak jitter Receive latency
Conditions 510 to GND
Min
Typ 1.5 1.5 0.5 400
Max
Units ns ns ns ps ns
@ 100m UTP
5
Applications Discussion
953, 1%
13 12
+5V
26, 28 3, 23
RJ45
Com.Mode Choke
1
REF LOOP DOUT DOUT 100, 1%
7
REXT RXVCC RXGND
+5V 50, 1%
LOOP TXIP TXIN TPMODE TLP LPEN TXDIS SDO RXOP RXON TXVCC
10, 17
15 16 6 18 20 14 22 25 24
TXOP TXON CRP CRN
9 8
50, 1%
2 5
Fast Ethernet PHY TLP RCC611
LPEN 10BTHD/10BTFD SDI DIN DIN 510 510
RCC613
1000pF
4
1000pF RXIP
2
Com.Mode Choke
3 6
50 RXIN CEQ TXGND
27 11, 19, 1
50 0.01F
+5 1000 pF
Valor PT4171 or PE68509
65-613-08
Notes: 1. For FDDI applications, the receive pins are 7 and 8 instead of 3 and 6 on the RJ45 connector. 2. TXVCC and RXVCC should be connected individually to circuit board's +5 volts through ferrite bead of value 0.2 to 1H H (e.g. FAIR-RITE BEAD #274-3019-446). 3. TXGND and RXGND should be connected individually to circuit board's ground through ferrite bead of value 0.2 to 1H H (e.g. FAIR-RITE BEAD #276-3019-446). The current handling capability should be 100mA. 4. For 50 applications, RXOP, RXON may be connected with 50 to 3V.
7
RCC613
PRODUCT SPECIFICATION
Notes:
Preliminary Information
8
PRODUCT SPECIFICATION
RCC613
Notes:
Preliminary Information
9
RCC613
PRODUCT SPECIFICATION
Notes:
Preliminary Information
10
PRODUCT SPECIFICATION
RCC613
Mechanical Dimensions - 28 Lead PLCC (QA) Package
Symbol A A1 A2 B B1 D/E D1/E1 D3/E3 e J ND/NE N ccc Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. Cavity mismatch = .004 (0.10mm) 2. Cavity frame offset = .002 (0.05mm) excluding leadframe tolerances. 3. Mold protrusions: Parting Line = .006 (0.15mm), Top or Bottom = .001 (0.025mm) 4. Variation in lead position = .005 (0.13mm) 5. Shoulder instrusions & protrusions: Intrusions = .002 (0.05mm), Protrusions = .003 (0.08mm) 6. Package warpage, WARP FACTOR = 2.5 = 7. Ejector pin depth = .010 (0.25mm) maximum. 8. Corner and edge chamfer = 45C. 8 WARP (mils) Package Length (inches)
.165 .180 .090 .120 .020 -- .013 .021 .026 .032 .485 .495 .450 .456 .300 BSC .050 BSC .042 .048 7 28 .004
4.19 4.57 2.29 3.04 .51 -- .33 .53 .66 .81 12.32 12.57 11.43 11.58 7.62 BSC 1.27 BSC 1.07 1.22 7 28 0.10
Preliminary Information
E E1 J
D
D1
D3/E3
B1 e J
A A1 A2 B -C- LEAD COPLANARITY ccc C
11
RCC613
PRODUCT SPECIFICATION
Ordering Information
Product Number RCC613V Package 28 PLCC
Preliminary Information
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonable expected to result in a significant injury of the user.
Fairchild Semiconductor Corporation Americas Customer Response Center Tel:1-888-522-5372 Fairchild Semiconductor Europe Fax: Email: Deutsch Tel: English Tel: Italy Tel: +49 (0) 1 80-530 85 86 europe.support@nsc.com +49 (0) 8 141-35-0 +44 (0) 1 793-85-68-56 +39 (0) 2 57 5631
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
Fairchild Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Center, 5 Canto Rd. Tsimshatsui, Kowloon Hong Kong Tel:+852 2737-7200 Fax:+852 2314-0061
National Semiconductor Japan Ltd. Tel:81-3-5620-6175 Fax:81-3-5620-6179
www.fairchildsemi.com 2/98 0.0m Stock#DS50000613 (c) 1998 Fairchild Semiconductor Corporation
www.fairchildsemi.com
RCC615
125 Mbaud Twisted Pair Transceiver (TPT)
Features
* * * * * * * * Compliant with FDDI TP-PMD standards Controlled symmetric transmit output rise/fall time Tristatable transmit output Adjustable transmit amplitude for longer cables DC Restoration (Baseline wander compensation) No receive input attenuation required Adaptive line equalization Compatible with existing FDDI/Fast Ethernet Physical layer (PHY) chips * 28 pin PLCC * 525mW power dissipation
Description
The RCC615 is a monolithic 125 Megabaud twisted pair transceiver (TPT) designed for IEEE 802.3 Fast Ethernet & American National Standard's (ANSI's) Fiber Distributed Data Interface (FDDI) applications. It implements the Physical Media Dependent Layer requirements of the FDDI (TP_PMD) standard. It can be used in a PHY layer solution for FDDI or 100base-TX Fast ethernet. The RCC615 Integrates MLT3 encoding, driving, receiving, adaptive equalization, base line wander compensation (DC restoration) and MLT3 decoding. It operates with a single +5V supply.
Preliminary Information
Applications
* * * * * FDDI 100 Mbps Fast Ethernet Bus Extenders Serial Video Communication Fast Ethernet/FDDI test equipment
Block Diagram
TXIP, TXIN TPMODE LOOP RXOP, RXON SDO
TXVCC TXGND
2 2 2
2 2 TO 1 MUX 2 MLT3 DECODER LOW PASS FILTER DC RESTORE (Base Line Wander Compensation) PEAK DETECT ADAPTIVE EQUALIZER VARIABLE GAIN DIFFERENTIAL AMPLIFIER SIGNAL DETECT
RXVCC RXGND
MLT3 ENCODER 2 REXT TXDIS
DRIVER
CRP CRN CEQ
REF
2 TXOP, TXON
2 RXIP, RXIN
65-615-01
Rev. 0.9.6
PRELIMINARY INFORMATION describes products that are not in full production at the time of printing. Specifications are based on design goals and limited characterization. They may change without notice. Contact Fairchild Semiconductor for current information.
RCC615
PRODUCT SPECIFICATION
Functional Description
Transmitter Section
The RCC615 transmitter section includes the MLT3 Encoder and Twisted pair driver. The transmittter drives either unshielded or shielded twisted pair cables to implement FDDI TP/PMD standard. The differential PECL data from TXIP, TXIN goes through a MLT3 Encoder. The MLT3 encoder is enabled when the TPMODE pin is LOW. The data is encoded per the following rules: The encoded output takes on one of three possible levels: High, Middle, or Low. Whenever the input signal changes state, the output will also change state. If the output is in the middle state, the state to which it will change to is dependent on the previous state. If the previous state was high(low), then the output will change to a low(high) state from the middle state. If the output is at either a high or a low state, then the next transition will cause the output to change to the middle state. The encoder conforms to the diagram shown in Figure 1.
NRZI
The transition time of the output is closely matched and controlled to reduce radiated emissions and to comply with FCC class B regulations.
Receiver Section
The signal from the transformer drives RXIP and RXIN and goes through a differential amplifier stage and then to a peak detect circuitry. The output of the peak detector goes to the signal detect comparator and to a low pass filter to remove the AC components. The low pass filter output then goes to an adaptive equalizer. The equalizer output provides an adaptive gain control for the variable gain differential amplifier to compensate for the cable distortion. The gain depends on the measured peak value of the input. The equalizer filter characteristics can be adjusted by means of an external capacitor connected between CEQ and ground (1000pF is suggested). The variable gain differential amplifier output also goes through the DC restoration and decode circuitry. The purpose of the DC restoration (baseline wander compensation) circuit is to provide DC restoration to the data stream on the occurrence of a long run-length. During those instances, the average DC tends to drift away from the decode circuit's threshold. The DC restoration circuit integrates the decoder output to provide a DC offset to the envelope to center it around the threshold of the decoder circuit. The MLT3 decoder also provides 3-level to 2-level conversion. The decoder conforms to the diagram shown in Figure 1. The decoder output goes through a 2 to 1 multiplexer. The other input to the multiplexer comes from the transmitter inputs TXIP, TXIN. If LOOP signal is HIGH, the transmit input is looped back to RXOP, RXON through the multiplexer. Under this condition, the transmitter output (TXOP, TXON) presents a logic LOW voltage. If LOOP is LOW, the decoder output is enabled and routes the signal to RXOP, RXON. The receive section also includes a signal detect logic. The signal detect logic filters the input signal and if the signal exceeds a specified level, the SDO output will go HIGH.
Preliminary Information
0 MLT3
-1
0
+1
+1
0
-1
0
0
+1
0
Figure 1. MLT3-NRZI Conversion Diagram
When TPMODE pin is high, the MLT3 encoder is bypassed and the data directly goes to the current source driver. The driver output current is controlled by external resistor between REXT and REF pins. The voltage at the output is a function of the load termination across the differential output. If R is the effective load termination and I is the current source, the peak to peak output voltage V = IR. I = 40/REXT(in kW) mA, where REXT is the resistor connected between the REXT and REF pins. The TP driver provides a differential 2 V peak to peak swing voltage output across TXOP, TXON through a 100W termination in parallel with two 50W pullup resistor, when REXT = 1KW. TXOP,TXON are connected externally to a coupling transformer and then to the twisted pair cable medium. The driver can be tristated by means of a pin TXDIS. When TXDIS is HIGH, the output presents a high impedance. In 2-level mode (TPMODE = HIGH), the output amplitude is half that of 3-level mode.
2
PRODUCT SPECIFICATION
RCC615
Pin Assignments
RXGND RXVCC RXVCC
26
RXIN
RXIP
28
CRP TPMODE LOOP TXON TXOP TXVCC TXGND
27
4
3
2
1
CEQ
CRN
5 6 7 8 9 10 11 12 13 14 15 16 17 18
25 24 23
RXOP RXON RXGND SDO NC TXGND TXGND
RCC615
22 21 20 19
Preliminary Information
TXGND
TXDIS
TXIN
TXIP
TXVCC
REXT
REF
65-615-04
Pin Descriptions
Pin Name CEQ Pin Number 27 Pin Type Analog Description Equalizer Capacitor. A capacitor is connected between CEQ and RXGND to adjust the gain of the adaptive equalizer. 1000 pF is recommended. DC Restoration Capacitor Positive, DC Restoration Capacitor Negative. A capacitor is connected at each of CRP, and CRN to RXGND to provide DC restoration. 1000 pF is recommended. Loop. If LOOP is HIGH, it loops the transmit input data, TXIP,TXIN to the receiver output, RXOP,RXON. If LOOP is LOW, the normal operation occurs. Reference. Provides the reference voltage to set the transmit output amplitude when an external resistor is connected between REF and REXT. It is nominally 2.5 Volts. External Resistor. It is connected between REXT and REF to adjust the amplitudes of TXOP, TXON. For MLT3 signals, the peak-to-peak differential voltage of 2V is generated across TXOP, TXON when the effective differential load is 50W and REXT = 1KW. Receive Ground. Chip ground for receive circuity. RXGND should be connected to the printed circuit board's ground plane through a ferrite bead of value 0.2mH to 1mH. Receive Input Positive, Receive Input Negative. (MLT3 inputs if TPMODE = 0, NRZI inputs if TPMODE = 1). Receive differential data inputs. Receive Output Positive, Receive Output Negative. Differential NRZI receive data to the PHY chip. Do not tie external termination below 510W to RXGND. For 50W applications, 50W from the outputs to 3V may be connected. Receive Positive Supply. The nominal value is 5V 5%. RXVCC should be bypassed to RXGND with a 0.1mF chip capacitor placed as close to the pin as possible.
CRP, CRN
5, 4
Analog
LOOP
7
TTL I/P
REF
13
Analog O/P
REXT
12
Analog
RXGND
3, 23
Power
RXIP, RXIN
2, 1
I/P
RXOP, RXON
25, 24
PECL DIFF O/P
RXVCC
26, 28
Power
3
RCC615
PRODUCT SPECIFICATION
Pin Descriptions (continued)
Pin Name SDO Pin Number 22 Pin Type PECL O/P Description Signal Detect. When SDO is HIGH, it indicates that the receive input is active. Do not tie any external termination resistor to SDO. Transmit Ground. Chip ground for transmit circuity. TXGND should be connected to the printed circuit board's ground plane through a ferrite bead of value 0.2mH to 1 mH. Twisted Pair Encode Mode. When TPMODE is LOW, the transmit output is MLT3 encoded with three levels. When TPMODE is HIGH, the transmit output is NRZI with two levels. Transmit Disable. If TXDIS is HIGH, the transmitter disables the TXOP, TXON output and presents a high impedance. If TXDIS is LOW, the transmitter enables normal data transmission through RCC615. Transmit Input Positive, Transmit Input Negative. Differential NRZI Transmit data from the PHY chip. Transmit Output Positive, Transmit Output Negative. (MLT3 outputs if TPMODE = 0, NRZI outputs if TPMODE = 1). Transmit differential current driver data outputs. Transmit Positive Supply. The nominal value is 5V 5%. TXVCC should be bypassed to TXGND with a 0.1mF chip capacitor placed as close to the pin as possible.
TXGND
11, 18, 19, 20
Power
TPMODE
6
TTL I/P
TXDIS
14
TTL I/P
Preliminary Information
TXIP,TXIN TXOP,TXON
15,16 9,8
PECL DIFF I/P O/P
TXVCC
10,17
Power
Absolute Maximum Ratings
(beyond which the device may be damaged)1 Parameter Positive power supply Voltage applied to any PECL/MLT3 outputs Voltage applied to any TTL inputs Voltage applied to any PECL inputs Current from any PECL/MLT3 outputs Operating Temperature Storage Temperature Junction Temperature Lead Soldering (10 seconds) Min. 0 -0.5 -0.5 -0.5 -50 0 -65 -55 Max. 6 VCC VCC VCC +50 70 150 150 300 Units V V V V mA C C C C
Notes: 1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded.
4
PRODUCT SPECIFICATION
RCC615
Operating Conditions
Parameter Ta VCC Rutp Rstp Ambient Operating Temperature Positive Supply Voltage (TXVCC and RXVCC) Unshielded Twisted Pair Differential Load Resistance Shielded Twisted Pair Differential Load Resistance Min. 0 4.75 99.8 149.7 5.00 100 150 Typ. Max. 70 5.25 100.2 150.3 Units C V W W
DC Electrical Characteristics
RXVCC, TXVCC = 5V 5%, RXGND, TXGND = 0V, unless otherwise indicated Parameter Transmitter Section Vihc Vilc Iinc C Vcm Vdiff Iip Vomh Voml Vohn Voln Vdif Vcm Vocm Vodiff Vohp Volp Vonth Vofth ICC PD TTL input Voltage HIGH TTL input Voltage LOW TTL Input Current Input Capacitance Com. Mode Range (TXIP, TXIN) Diff. Input Voltage (TXIP, TXIN) PECL Input Current MLT3 Positive Peak Voltage MLT3 Negative Peak Voltage NRZI Output Voltage HIGH NRZI Output Voltage LOW RXIP, RXIN Diff Input Voltage RXIP, RXIN Com. Mode Range RXOP, RXON Com. Mode Range 510W to GND on RXOP, RXON Diff Output Voltage RXOP, RXON SDO Output HIGH SDO Output LOW SDO Turnon threshold SDO Turnoff threshold Power Supply Current Power Dissipation VCC-1.1 VCC-2 350 260 110 525 0.4 2.6 VCC-1.5 1.5 VCC-0.7 VCC-1.4 Diff load R = 100W 0.2% and 50W on both TXOP, TXON to VCC 3.3 0.4 -20 0 4.2 3.2 4.2 3.2 2 3.0 3.7 4.1 2.0 20 2.0 0 VCC 0.8 25 V V mA pF V Vpp mA V V V V V V V Vpp V V mV mV mA mW Conditions Min. Typ. Max. Units
Preliminary Information
Receiver Section
Power Section
5
RCC615
PRODUCT SPECIFICATION
AC Electrical Characteristics1
VCC = 5V 5%, GND = 0V, unless otherwise indicated
RXIP
RXIN Ton SDO Toff
65-615-05
Preliminary Information
Parameter Receiver Section Ton Toff SDO turnon delay @ CEQ = 1000pF SDO turnoff delay @ CEQ = 1000pF
Conditions Diff I/P > 1V Diff I/P <0.2V
Min.
Typ. 1 200
Max. 1000 350
Units ms ms
Note: 1. Test conditions (unless otherwise indicated:) PECL Input rise and fall times 2ns, RL = 100W. TTL Input rise and fall times 15ns. Transition density 0.1.
Timing Diagrams
Tf, Tr Ttl Vomh TXIP, TXIN TXOP, TXON (TPMODE = 0) Vomh TXOP, TXON (TPMODE = 0) Voml Ttj, Tdj 90% 10% 90% 10% TXOP, TXON (TPMODE = 1) 90% 10% Tf TXOP, TXON (TPMODE = 1) Tr Voml 90% 10% 90% 10%
Ttj, Tdj
65-615-06
Transmitter Timing
Parameter Tr Tf Tdj Ttj Ttl 6 TXOP, TXON rise time 10% to 90% TXOP, TXON fall time TXOP, TXON duty cycle distortion (peak-to-peak) Random jitter Transmit latency
Conditions 100W termination
Min.
Typ. 2.7 2.7 0.3 300 5.0
Max.
Units ns ns ns ps ns
PRODUCT SPECIFICATION
RCC615
Timing Diagrams (continued)
90% RXOP, RXON 10% RXIP, RXIN Trf Trr
RXOP, RXON Trl
RXOP, RXON
Trdj, Trj
65-615-07
Receiver Timing
Preliminary Information
Parameter Trr Tfr Trdj Trj Trl RXOP, RXON rise time RXOP, RXON fall time RXOP, RXON duty cycle distortion (peakto-peak) @ 100m calbe (UTP) RXOP,RXON peak to peak jitter Receive latency
Conditions 10% to 90% 90% to 10%
Min.
Typ. 1.5 1,5 0.5 400
Max.
Units ns ns ns ps ns
@ 100m UTP
5
Applications Discussion
9531/2, 1%
13 12
+5V
26, 28 3, 23
RJ45 1
Com.Mode Choke
1
REF LOOP TX+ TX1001/2, 1%
7
REXT RXVCC RXGND
+5V 501/2, 1%
LOOP TXIP TXIN TPMODE
15 16 6
TXOP TXON CRP CRN
9 8
501/2, 1%
2 5
Fast Ethernet PHY
TXDIS SDI RX+ RX510 510
14 22 25 24
RCC615
TXDIS SDO RXOP RXON TXVCC
10, 17
1000pF
4
1000pF RXIP
2
Com.Mode Choke
3 6
501/2 RXIN CEQ TXGND
27 11, 18, 19, 20 1
501/2 0.01F
+5 1000 pF
Valor PT4171 or PE68509
65-615-08
Notes: 1. For FDDI applications, the receive pins are 7 and 8 instead of 3 and 6 on the RJ45 connector. 2. TXVCC and RXVCC should be connected individually to circuit board's +5 volts through ferrite bead of value 0.2mH to 1mH (e.g. FAIR-RITE BEAD #274-3019-446). 3. TXGND and RXGND should be connected individually to circuit board's ground through ferrite bead of value 0.2mH to 1mH (e.g. FAIR-RITE BEAD #276-3019-446). The current handling capability should be 100mA. 4. For 50W applications, RXOP, RXON may be connected with 50W to 3V.
7
RCC615
PRODUCT SPECIFICATION
Notes:
Preliminary Information
8
PRODUCT SPECIFICATION
RCC615
Notes:
Preliminary Information
9
RCC615
PRODUCT SPECIFICATION
Notes:
Preliminary Information
10
PRODUCT SPECIFICATION
RCC615
Mechanical Dimensions - 28 Lead PLCC (QA) Package
Symbol A A1 A2 B B1 D/E D1/E1 D3/E3 e J ND/NE N ccc Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. Cavity mismatch = .004 (0.10mm) 2. Cavity frame offset = .002 (0.05mm) excluding leadframe tolerances. 3. Mold protrusions: Parting Line = .006 (0.15mm), Top or Bottom = .001 (0.025mm) 4. Variation in lead position = .005 (0.13mm) 5. Shoulder instrusions & protrusions: Intrusions = .002 (0.05mm), Protrusions = .003 (0.08mm) 6. Package warpage, WARP FACTOR = 2.5 = 7. Ejector pin depth = .010 (0.25mm) maximum. 8. Corner and edge chamfer = 45C. 8 WARP (mils) Package Length (inches)
.165 .180 .090 .120 .020 -- .013 .021 .026 .032 .485 .495 .450 .456 .300 BSC .050 BSC .042 .048 7 28 .004
4.19 4.57 2.29 3.04 .51 -- .33 .53 .66 .81 12.32 12.57 11.43 11.58 7.62 BSC 1.27 BSC 1.07 1.22 7 28 0.10
Preliminary Information
E E1 J
D
D1
D3/E3
B1 e J
A A1 A2 B -C- LEAD COPLANARITY ccc C
11
RCC615
PRODUCT SPECIFICATION
Ordering Information
Product Number RCC615V Package 28 PLCC
Preliminary Information
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS50000615 O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RCC700A
Fibre Channel Transceiver
240 to 330 Megabaud Features
* * * * * * * * * * * 240 to 330 Megabaud data rates Compliant with Fibre Channel standard Submicron CMOS technology PLL clock and data recovery Clock synthesizer Selectable 8 bit/10 bit encode, 10 bit/8 bit decode Parity generate/check Low power dissipation: 600 mW typ. at 250 Megabaud Byte sync on K28.1, K28.5 or K28.7 Single power supply: +5V CMOS/TTL compatible parallel data inputs/outputs * PECL compatible serial data inputs/outputs * Available in 64-pin PQFP, 68 pin PLCC
Applications
* * * * * Fibre Channel Transceiver High-speed Fiber Optics or Copper links High-resolution graphic display terminal LAN Switching Video data transmission
Description
The RCC700A is a monolithic transmitter/receiver IC integrating a complete phase-locked loop clock recovery and data retiming/regeneration subsystem, a phase-locked loop clock synthesizer, a 10:1 mux, a 1:10 demux, an 8-bit/10-bit encoder, and an 10-bit/8-bit decoder. It operates with a single +5V power supply. The RCC700A provides a complete physical interface in compliance with the Fibre Channel Physical Layer Standard (FC-PH) specifications at 265.625 Megabaud (Mbaud). 8 bit/10 bit encoder and 10 bit/8 bit decoder can be disabled through an external pin.
Block Diagram
RST TBC ETX CSEL DI0-DI7, KIN/DI8, PIN/DI9 PE/POLSEL DOL PLL Clock Generator
Transmitter
10:1 Time Division MUX DOUT, DOUT
8b/10b Encoder
Parity Check
LSEL SYNCEN RBC BSYNC Byte Alignment Circuit
Receiver
Clock & Data Recovery
2:1 MUX
DIN, DIN
DO0-DO7, KOUT/DO8, POUT/DO9
Parity Gen
10b/8b Decoder
1:10 Time Division Demux
PECL to CMOS Converter
SDIN
EF
SDOUT
65-700A-01
Rev. 1.0.0
RCC700A
PRODUCT SPECIFICATION
Functional Description
Transmitter Section
The RCC700A transmitter section includes a phase-locked loop synthesizer, an 8-bit/10-bit encoder, an input parity checker and a 10:1 multiplexer. The RCC700A accepts a CMOS/TTL data byte (DI0-DI7) along with the K character indicator (KIN) and parity bit (PIN) for CSEL = 0. For CSEL = 1, KIN and PIN become DI8 and DI9, respectively. The Parity Check circuitry calculates the odd parity of the input data byte and compares it with PIN. If the calculated parity differs from PIN, the transmitter flags the error by bringing the parity error bit, PE to a HIGH level. For example, for DI0-DI7=00000101, PIN should be 1. If PIN is not equal to 1, PE=1. The RCC700A transmitter section encodes the CMOS/TTL input data bye (DI0-DI7) into a 10-bit word using IBM's 8-bit/10-bit coding (see Table 2). The encoder is disabled if CSEL = 1, and enabled if CSEL = 0. The encoded word is then converted to a serial high speed data stream (DOUT/DOUT) at 240 to 330 Mbaud via a 10:1 time division mux. The serial data stream (DOUT/DOUT) is transmitted at PECL levels (positive shifted ECL levels, Vth = +3.4V). The RCC700A features a Data Output Low function (DOL) that can force the data output (DOUT, DOUT) to logic LOW for protection of the fiber optic module transmitter diode. DOL is controlled by the Protocol IC or the fiber optic transmitter module. The RCC700A also incorporates an Error Transmit input (ETX). The RCC700A sends a violating code when ETX is brought to a logic HIGH. If ETX stays HIGH for more than one byte clock cycle, the transmitter will send error bytes of alternate running disparities in order to maintain the DC balance of the line (100111 1011 or 011000 0100). The 240 to 330 MHz clock used for the serial stream is generated using a PLL clock generator which multiplies the input frequency, 24 to 33 MHz, by a factor of 10. The input clock reference for the PLL clock generator, Transmit Byte Clock (TBC), typically comes from a crystal oscillator or from the system. CSEL = 1, and enabled if CSEL = 0. K Command characters are also detected and indicated by bringing the KOUT pin to a HIGH level. The odd parity of the output 8-bit byte (DO0-DO7) is calculated and available at pin POUT. For example, for DO0-DO7=00000101, POUT should be 1. For CSEL = 1, KOUT and POUT become D08 and D09, respectively. The RCC700A also generates a Receive Byte Clock (RBC) for driving the CMOS protocol layer IC. All the outputs to the protocol layer IC are at CMOS levels. Running disparity and coding is checked during the 10-bit/8bit decoding and violations are flagged by bringing the Error Flag (EF) to a HIGH level. If consecutive bytes have more 1s or more 0s, or if running disparity is different from expected for the received code, or the transmission character is not part of Table 2, EF goes HIGH. If 100111 1011 or 011000 0100 is received, EF=1, KOUT=1, DO0-DO7=00000000. The RCC700A contains a byte synchronization circuitry. When enabled (SYNCEN HIGH), the RCC700A will automatically resynchronize the demultiplexer to byte align with the leading seven bits (00111 11 or 11000 00) of the transmission character, corresponding to reception of K28.1, K28.5 or K28.7. SYNCEN pin gives the protocol layer IC the flexibility to request the RCC700A to align only when required, e.g. at power up or after loss of byte synchronization. The RCC700A also incorporates a PECL to CMOS converter to translate the PECL output signal from an optical receiver module SDIN to a CMOS output signal. This allows for direct interfacing with the CMOS protocol layer circuit. SDIN is active HIGH. Therefore, SDOUT will be at a CMOS level LOW when an optical signal is present at the input of the fiber optics receiver module.
Loopback Test Mode
The RCC700A features an internal differential loopback for on-board diagnostic of the device. When loop select (LSEL) is HIGH, the receiver accepts the output data from the transmitter section (DOUT, DOUT). When LSEL is LOW, i.e., tied to GND, the receiver accepts the incoming input data (DIN, DIN).
Receiver Section
The RCC700A receiver section includes a complete phaselocked loop clock recovery and data retiming/regeneration subsystem, a byte alignment circuit, a 1:10 demultiplexer, an 10-bit/8-bit decoder, a disparity/code violation checker and a parity generator. The RCC700A accepts a differential data stream (DIN/DIN) at 240 to 330 Mbaud, recovers the clock and regenerates the encoded serial data. The recovered encoded data is then converted to 10 parallel data lines via a 1:10 time division demultiplexer and decoded into an 8-bit byte via the 10-bit/8-bit decoder. The decoder is disabled if 2
Use of Table 2 for Encoding/ Decoding
The following information describes how Table 2 can be used for generating valid transmission characters (encoding) and checking the validity of received transmission characters (decoding). The transmission character is labelled "abcdeifghj". The transmission order is a,b,c...j in that order. HGFEDCBA cor-
PRODUCT SPECIFICATION
RCC700A
responds to the data inputs DI7...DI0 in that order. In the table, each valid data byte and special code byte has two columns corresponding to the current value of the running disparity (CURRENT RD- or CURRENT RD+). Running disparity is a binary parameter with either the value + or -. The transmitter calculates the new running disparity based on the contents of the transmitted character. Similarly, the receiver calculates the new running disparity based on the contents of the received character. The first six bits of the character, "abcdei," form one subblock, and "fghj" forms another sub-block for computing running disparity. Running disparity (CURRENT RD+ or CURRENT RD-) at the beginning of the 6-bit sub-block is the running disparity at the end of the last transmission character. Running disparity at the beginning of the 4-bit subblock is the running disparity at the end of the 6-bit subblock. Running disparity at the end of the transmission character is the running disparity at the end of the 4-bit subblock. Running disparity for the sub-block is calculated as follows: 1. Running disparity at the end of any sub-block is positive if the sub-block contains more ones than zeros. It is also positive at the end of the six-bit sub-block if the six-bit sub-block is 000111, and it is positive at the end of the four-bit sub-block if the four-bit sub-block if 0011. Running disparity at the end of any sub-block is negative if the sub-block contains more zeros than ones. It is also negative at the end of the six-bit sub-block if the six-bit sub-block is 111000, and it is negative at the end of the four-bit sub-block if the four-bit sub-block is 1100. If neither of the above two conditions applies, running disparity at the end of the sub-block is the same as at the beginning of the sub-block.
CURRENT RD is used to select the transmission character for the data byte or special code. While decoding the received character, the column corresponding to the current value of the receiver's running disparity shall be searched for the received transmission character. If the received transmission character is found in the proper column, the transmission character is considered valid and the associated data or special code byte decoded. Otherwise, the character is considered invalid and EF pin is held HIGH for that byte. Independent of the transmission character's validity, the received transmission character shall be used to calculate a new value of running disparity. Detection of code violation (EF=HIGH) does not necessarily indicate that the transmission character in which the code violation was detected is in error. Code violation may occur due to the prior error which altered the running disparity of the bit stream but did not result in a detectable error at the transmission character in which it occurred. An example of an error scenario where the error is flagged after it happens is shown below (see Table 1).
Reset Function
For CSEL = 0, during normal operation, the reset input pin, RST, is LOW and is not used. Under total failure of receive PLL to acquire lock, this reset function can be used. When RST goes HIGH for at least 1 byte clock, the chip is reset, i.e. the receive PLL acquires lock to the bit clock derived from the TBC reference byte frequency and then to the incoming data. For CSEL = 1, RST is normally HIGH and is LOW for at least 1 byte clock to reset.
2.
3.
Table 1. Example of Error Scenario
RD Transmitted character stream Transmitted bit stream Bit stream after error Decoded character stream Character D21.1 101010 1001 101010 1011 D21.0 RD + + Character D10.2 010101 0101 010101 0101 D10.2 RD + + Character D23.5 111010 1010 111010 1010 Error RD + + + +
3
RCC700A
PRODUCT SPECIFICATION
Table 2. 8b/10b Encoding
DATA3 BYTE NAME BITS HGF EDCBA1 CURRENT RDabcdei fghj2 CURRENT RD+ abcdei fghj2 DATA3 BYTE NAME BITS HGF EDCBA1 abcdei CURRENT RDfghj2 abcdei CURRENT RD+ fghj2
D0.0 D1.0 D2.0 D3.0 D4.0 D5.0 D6.0 D7.0 D8.0 D9.0 D10.0 D11.0 D12.0 D13.0 D14.0 D15.0 D16.0 D17.0 D18.0 D19.0 D20.0 D21.0 D22.0 D23.0 D24.0 D25.0 D26.0 D27.0 D28.0 D29.0 D30.0 D31.0 D0.1 D1.1 D2.1 D3.1 D4.1 D5.1 D6.1 D7.1 D8.1 D9.1 D10.1 D11.1 D12.1 D13.1 D14.1 D15.1
000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 001 001 001 001 001 001 001 001 001 001 001 001 001 001 001 001
00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111
100111 011101 101101 110001 110101 101001 011001 111000 111001 100101 010101 110100 001101 101100 011100 010111 011011 100011 010011 110010 001011 101010 011010 111010 110011 100110 010110 110110 001110 101110 011110 101011 100111 011101 101101 110001 110101 101001 011001 111000 111001 100101 010101 110100 001101 101100 011100 010111
0100 0100 0100 1011 0100 1011 1011 1011 0100 1011 1011 1011 1011 1011 1011 0100 0100 1011 1011 1011 1011 1011 1011 0100 0100 1011 1011 0100 1011 0100 0100 0100 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001
011000 100010 010010 110001 001010 101001 011001 000111 000110 100101 010101 110100 001101 101100 011100 101000 100100 100011 010011 110010 001011 101010 011010 000101 001100 100110 010110 001001 001110 010001 100001 010100 011000 100010 010010 110001 001010 101001 011001 000111 000110 100101 010101 110100 001101 101100 011100 101000
1011 1011 1011 0100 1011 0100 0100 0100 1011 0100 0100 0100 0100 0100 0100 1011 1011 0100 0100 0100 0100 0100 0100 1011 1011 0100 0100 1011 0100 1011 1011 1011 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001
D16.1 D17.1 D18.1 D19.1 D20.1 D21.1 D22.1 D23.1 D24.1 D25.1 D26.1 D27.1 D28.1 D29.1 D30.1 D31.1 D0.2 D1.2 D2.2 D3.2 D4.2 D5.2 D6.2 D7.2 D8.2 D9.2 D10.2 D11.2 D12.2 D13.2 D14.2 D15.2 D16.2 D17.2 D18.2 D19.2 D20.2 D21.2 D22.2 D23.2 D24.2 D25.2 D26.2 D27.2 D28.2 D29.2 D30.2 D31.3
001 001 001 001 001 001 001 001 001 001 001 001 001 001 001 001 010 010 010 010 010 010 010 010 010 010 010 010 010 010 010 010 010 010 010 010 010 010 010 010 010 010 010 010 010 010 010 010
10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111
011011 100011 010011 110010 001011 101010 011010 111010 110011 100110 010110 110110 001110 101110 011110 101011 100111 011101 101101 110001 110101 101001 011001 111000 111001 100101 010101 110100 001101 101100 011100 010111 011011 100011 010011 110010 001011 101010 011010 111010 110011 100110 010110 110110 001110 101110 011110 101011
1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101
100100 100011 010011 110010 001011 101010 011010 000101 001100 100110 010110 001001 001110 010001 100001 010100 011000 100010 010010 110001 001010 101001 011001 000111 000110 100101 010101 110100 001101 101100 011100 101000 100100 100011 010011 110010 001011 101010 011010 000101 001100 100110 010110 001001 001110 010001 100001 010100
1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 1001 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101 0101
4
PRODUCT SPECIFICATION
RCC700A
Table 2. 8b/10b Encoding (continued)
DATA3 BYTE NAME BITS HGF EDCBA1 CURRENT RDabcdei fghj2 CURRENT RD+ abcdei fghj2 DATA3 BYTE NAME BITS HGF EDCBA1 abcdei CURRENT RDfghj2 abcdei CURRENT RD+ fghj2
D0.3 D1.3 D2.3 D3.3 D4.3 D5.3 D6.3 D7.3 D8.3 D9.3 D10.3 D11.3 D12.3 D13.3 D14.3 D15.3 D16.3 D17.3 D18.3 D19.3 D20.3 D21.3 D22.3 D23.3 D24.3 D25.3 D26.3 D27.3 D28.3 D29.3 D30.3 D31.3 D0.4 D1.4 D2.4 D3.4 D4.4 D5.4 D6.5 D7.5 D8.5 D9.5 D10.4 D11.4 D12.4 D13.4 D14.4 D15.4
011 011 011 011 011 011 011 011 011 011 011 011 011 011 011 011 011 011 011 011 011 011 011 011 011 011 011 011 011 011 011 011 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100
00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111
100111 011101 101101 110001 110101 101001 011001 111000 111001 100101 010101 110100 001101 101100 011100 010111 011011 100011 010011 110010 001011 101010 011010 111010 110011 100110 010110 110110 001110 101110 011110 101011 100111 011101 101101 110001 110101 101001 011001 111000 111001 100101 010101 110100 001101 101100 011100 010111
0011 0011 0011 1100 0011 1100 1100 1100 0011 1100 1100 1100 1100 1100 1100 0011 0011 1100 1100 1100 1100 1100 1100 0011 0011 1100 1100 0011 1100 0011 0011 0011 0010 0010 0010 1101 0010 1101 1101 1101 0010 1101 1101 1101 1101 1101 1101 0010
011000 100010 010010 110001 001010 101001 011001 000111 000110 100101 010101 110100 001101 101100 011100 101000 100100 100011 010011 110010 001011 101010 011010 000101 001100 100110 010110 001001 001110 010001 100001 010100 011000 100010 010010 110001 001010 101001 011001 000111 000110 100101 010101 110100 001101 101100 011100 101000
1100 1100 1100 0011 1100 0011 0011 0011 1100 0011 0011 0011 0011 0011 0011 1100 1100 0011 0011 0011 0011 0011 0011 1100 1100 0011 0011 1100 0011 1100 1100 1100 1101 1101 1101 0010 1101 0010 0010 0010 1101 0010 0010 0010 0010 0010 0010 1101
D16.4 D17.4 D18.4 D19.4 D20.4 D21.4 D22.4 D23.4 D24.4 D25.4 D26.4 D27.4 D28.4 D29.4 D30.4 D31.4 D0.5 D1.5 D2.5 D3.5 D4.5 D5.5 D6.5 D7.5 D8.5 D9.5 D10.5 D11.5 D12.5 D13.5 D14.5 D15.5 D16.5 D17.5 D18.5 D19.5 D20.5 D21.5 D22.5 D23.5 D24.5 D25.5 D26.5 D27.5 D28.5 D29.5 D30.5 D31.5
100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 101 101 101 101 101 101 101 101 101 101 101 101 101 101 101 101 101 101 101 101 101 101 101 101 101 101 101 101 101 101 101 101
10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111
011011 100011 010011 110010 001011 101010 011010 111010 110011 100110 010110 110110 001110 101110 011110 101011 100111 011101 101101 110001 110101 101001 011001 111000 111001 100101 010101 110100 001101 101100 011100 010111 011011 100011 010011 110010 001011 101010 011010 111010 110011 100110 010110 110110 001110 101110 011110 101011
0010 1101 1101 1101 1101 1101 1101 0010 0010 1101 1101 0010 1101 0010 0010 0010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010
100100 100011 010011 110010 001011 101010 011010 000101 001100 100110 010110 001001 001110 010001 100001 010100 011000 100010 010010 110001 001010 101001 011001 000111 000110 100101 010101 110100 001101 101100 011100 101000 100100 100011 010011 110010 001011 101010 011010 000101 001100 100110 010110 001001 001110 010001 100001 010100
1101 0010 0010 0010 0010 0010 0010 1101 1101 0010 0010 1101 0010 1101 1101 1101 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010 1010
Table 2. 8b/10b Encoding (continued)
5
RCC700A
PRODUCT SPECIFICATION
DATA3 BYTE NAME
BITS HGF EDCBA
CURRENT RDabcdei fghj2
CURRENT RD+ abcdei fghj2
DATA3 BYTE NAME
BITS HGF EDCBA
CURRENT RDabcdei fghj2
CURRENT RD+ abcdei fghj2
D0.6 D1.6 D2.6 D3.6 D4.6 D5.6 D6.6 D7.6 D8.6 D9.6 D10.6 D11.6 D12.6 D13.6 D14.6 D15.6 D16.6 D17.6 D18.6 D19.6 D20.6 D21.6 D22.6 D23.6 D24.6 D25.6 D26.6 D27.6 D28.6 D29.6 D30.6 D31.6
DATA4 BYTE NAME
110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110 110
00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111
100111 011101 101101 110001 110101 101001 011001 111000 111001 100101 010101 110100 001101 101100 011100 010111 011011 100011 010011 110010 001011 101010 011010 111010 110011 100110 010110 110110 001110 101110 011110 101011
0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110
011000 100010 010010 110001 001010 101001 011001 000111 000110 100101 010101 110100 001101 101100 011100 101000 100100 100011 010011 110010 001011 101010 011010 000101 001100 100110 010110 001001 001110 010001 100001 010100
0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110 0110
D0.7 D1.7 D2.7 D3.7 D4.7 D5.7 D6.7 D7.7 D8.7 D9.7 D10.7 D11.7 D12.7 D13.7 D14.7 D15.7 D16.7 D17.7 D18.7 D19.7 D20.7 D21.7 D22.7 D23.7 D24.7 D25.7 D26.7 D27.7 D28.7 D29.7 D30.7 D31.7
111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111
00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111
100111 011101 101101 110001 110101 101001 011001 111000 111001 100101 010101 110100 001101 101100 011100 010111 011011 100011 010011 110010 001011 101010 011010 111010 110011 100110 010110 110110 001110 101110 011110 101011
0001 0001 0001 1110 0001 1110 1110 1110 0001 1110 1110 1110 1110 1110 1110 0001 0001 0111 0111 1110 0111 1110 1110 0001 0001 1110 1110 0001 1110 0001 0001 0001
011000 100010 010010 110001 001010 101001 011001 000111 000110 100101 010101 110100 001101 101100 011100 101000 100100 100011 010011 110010 001011 101010 011010 000101 001100 100110 010110 001001 001110 010001 100001 010100
1110 1110 1110 0001 1110 0001 0001 0001 1110 0001 0001 1000 0001 1000 1000 1110 1110 0001 0001 0001 0001 0001 0001 1110 1110 0001 0001 1110 0001 1110 1110 1110
BITS HGF EDCBA1
CURRENT RDabcdei fghj2
CURRENT RD+ abcdei fghj2
K28.0 K28.1 K28.2 K28.3 K28.4 K28.5 K28.6 K28.7 K23.7 K27.7 K29.7 K30.7
000 001 010 011 100 101 110 111 111 111 111 111
11100 11100 11100 11100 11100 11100 11100 11100 10111 11011 11101 11110
001111 001111 001111 001111 001111 001111 001111 001111 111010 110110 101110 011110
0100 1001 0101 0011 0010 1010 0110 1000 1000 1000 1000 1000
110000 110000 110000 110000 110000 110000 110000 110000 000101 001001 010001 100001
1011 0110 1010 1100 1101 0101 1001 0111 0111 0111 0111 0111
Notes: 1. "HGF EDC BA" corresponds to DI7 ...0 in that order 2. a is to be transmitted first, followed by b, c, d ....j in that order 3. Kin=0 4. Kin=1
6
PRODUCT SPECIFICATION
RCC700A
Pin Assignments
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name DO2 DO1 DO0 DVCC DVCC DGND DGND POUT/DO9 KOUT/DO8 EF RBC DGND PE/POLSEL PIN/DI9 KIN/DI8 ETX Pin 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Name DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DGND TBC DVCC RST DGND DVCC DOL DGND Pin 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Name DOUT DOUT LSEL AGND AVCC AVCC AGND AGND AVCC AVCC AGND AVCC AGND SDIN DIN DIN Pin 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Name SDOUT CSEL SYNCEN BSYNC DVCC DGND DVCC DGND DVCC DGND DO7 DO6 DO5 DO4 D03 DGND
1
65-700A-02
1
65-700A-07
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Name DGND DVCC DGND DO7 DO6 DO5 DO4 DO3 DGND DGND DO2 DO1 DO0 DVCC DVCC DGND DGND
Pin 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Name POUT/DO9 KOUT/DO8 EF RBC DGND PE/POLSEL PIN/DI9 KIN/DI8 ETX DGND DI7 DI6 DI5 DI4 DI3 DI2 DI1
Pin 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51
Name DI0 DGND TBC DVCC RST DGND DVCC DOL DGND DOUT DOUT NC LSEL AGND AVCC AVCC AGND
Pin 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
Name AGND AVCC AVCC AGND AVCC AGND SDIN DIN DIN DGND SDOUT CSEL SYNCEN BSYNC DVCC DGND DVCC
Pin Descriptions
Pin Number Name DVCC 64-pin PQFP 68-pin PLCC 4, 5, 27, 30, 53, 55, 57 2, 14, 15, 38, 41, 66, 68 Function Positive supply for digital circuitry. The nominal value is 5V 5%. VCC should be bypassed to the ground plane with a 10,000 pF chip capacitor placed as close to the pin as possible. Positive supply for analog circuitry. The nominal value is 5V 5%. VCC should be bypassed to the ground plane with a 10,000 pF chip capacitor placed as close to the pin as possible.
AVCC
37, 38, 41, 42, 49, 50, 53, 54, 44 56
DGND
6, 7, 12, 25, 1, 3, 9, 10, 16, Chip ground for digital circuitry. DGND should be connected to the 29, 32, 54, 56, 17, 22, 27, 36, printed circuit board's ground plane at the pins. 58, 64 40, 43, 61, 67 36, 39, 40, 43, 48, 51, 52, 55, 45 57 Chip ground for analog circuitry. AGND should be connected to the printed circuit board's ground plane at the pins.
AGND DI0-DI7
24, 23, 22, 21, 35, 34, 33, 32, Transmitter input data (TTL levels). 20, 19, 18, 17 31, 30, 29, 28
7
RCC700A
PRODUCT SPECIFICATION
Pin Descriptions (continued)
Pin Number Name TBC KIN/DI8 PIN/DI9 PE/ POLSEL 64-pin PQFP 68-pin PLCC 26 15 14 13 37 25 24 23 Function Transmit Byte Clock input (TTL level). Input reference frequency for the internal high speed clock generator: 24 to 33 MHz. K character indicator input/Transmitter input data (TTL levels). If CSEL = 0, this pin in KIN. If CSEL = 1, this pin is DI8. Odd parity input /Transmitter input data (TTL levels). If CSEL = 0, this pin in PIN. If CSEL = 1, this pin is DI9. Parity Error indicator output/Polarity Select Input (CMOS/TTL levels). For CSEL = 0, This pin is PE. For CSEL = 1, This pin is POLSEL. PE will stay low when the on-chip calculated odd parity matches the incoming parity PIN. If there is a parity error, the PE flag is raised to a level HIGH. If POLSEL = 0, the receive data output timing specifications are with respect to the positive edge of RBC. If POLSEL = 1, the above specifications are with respect to the negative edge of RBC. Transmitter differential output data (PECL levels). The output is a current mode driver with a nominal current driver of 8 mA. To generate a 0.8 V swing, use a 100W resistor across DOUT, DOUT. Data Output Low control input (TTL level). When HIGH, it forces the output to a logic low state (DOUT = LOW and DOUT = HIGH) to protect the fiber optic source. Connect to GND or leave open when not used. Loop Select input (TTL level). Internal differential loopback for "onboard" diagnostic of the device. When loop select (LSEL) is HIGH, the receiver accepts the output data from the transmitter section (DOUT/DOUT). When LSEL is LOW, i.e. tied to GND, the receiver accepts the incoming input data (DIN/DIN). Connect to GND or leave open when not used. Receiver differential input data (PECL levels). Byte Synchronization Enable input (TTL level). When SYNCEN is HIGH, the RCC700A will automatically resynchronize the demultiplexer to byte align with the received K28.1, K28.5 or K28.7 for both negative and positive running disparities (RD- and RD+). Connect to GND or leave open when not used. Byte Synchronized output flag (CMOS levels). BSYNC goes to a HIGH level for one byte clock when SYNCEN is HIGH and the RCC700A detects and resynchronizes on K28.1, K28.5 or K28.7. Signal Detect input (PECL level). PECL input of the PECL to CMOS converter for the signal detect flag of the fiber optics receiver module. Leave open when not used. Signal Detect Output (CMOS level). CMOS output of the PECL to CMOS converter for the signal detect flag of the fiber optics receiver module. SDOUT is LOW when SDIN is HIGH. Receiver output data/Receive output data (CMOS levels). K character indicator output / Receive Output Data (CMOS level). If CSEL = 0, this pin is KOUT. If CSEL = 1, this pin is DO8. Odd parity output/Receive output data (CMOS level). If CSEL = 0, this pin is POUT. POUT is HIGH when the parity of the DO0...DO7 byte is even. If CSEL = 1, this pin is DO9.
DOUT/ DOUT DOL
33,34
44,45
31
42
LSEL
35
47
DIN/DIN SYNCEN
48, 47 51
60, 59 64
BSYNC
52
65
SDIN
46
58
SDOUT
49
62
DO0-DO7 KOUT/DO8 POUT/DO9
3, 2, 1, 63, 62, 13, 12, 11, 8, 61, 60, 59 7, 6, 5, 4 9 8 19 18
8
PRODUCT SPECIFICATION
RCC700A
Pin Descriptions (continued)
Pin Number Name RBC EF 64-pin PQFP 68-pin PLCC 11 10 21 20 Function Receive Byte Clock output (CMOS level): 24 to 33 MHz. Error Flag output (CMOS level). EF goes HIGH to flag running disparity and coding violations detected during the 10b/8b decoding. Asynchronous reset input (TTL level). For CSEL = 0, this pin is normally LOW, and when HIGH for at least one byte clock, is used to reset all functions of the chip. This is a master reset. For CSEL = 1, this pin is normally HIGH, and when LOW for at least one byte clock, provides reset. Error Transmit input (TTL level). This pin is only applicable of CSEL = 0 and is a No Connect for CSEL = 1. This pin is normally LOW. This pin, when HIGH, is used to force DC balanced alternating violation codes on its serial output. Select input (TTL level). This pin is normally low and enables the 8b/10b encoder/decoder circuitry. When high, the 8b/10b encoder/ decoder is disabled and the following pins are affected: PIN/DI9, KIN/DI8, POUT/DO9, KOUT/DO8, PE/POLSEL, RST, and ETX. No connection.
RST
28
39
ETX
16
26
CSEL
50
63
NC
--
46
Absolute Maximum Ratings1
Parameter Storage temperature range Junction temperature range Lead temperature range (soldering, 10 seconds) Positive power supply, VCC Voltage applied to any TTL inputs Voltage applied to any CMOS inputs Voltage applied to any PECL inputs Voltage applied to any CMOS outputs Voltage applied to any PECL outputs Current from any CMOS outputs Current from any PECL outputs 0 -1 -1 -1 -1 -1 -50 -50 Min -65 -55 Max 150 150 300 6 6 6 6 6 6 50 50 Unit C C C V V V V V V mA mA
Note: 1. "Absolute maximum ratings" are those beyond which the safety of the device cannot be guaranteed. They are not meant to imply the device should be operated at these limits. If the device is subjected to the limits in the absolute maximum ratings for extended periods, its reliability may be impaired. The tables of Electrical Characteristics provide conditions for actual device operation.
9
RCC700A
PRODUCT SPECIFICATION
Recommended Operating Conditions
Symbol TA VCC RI Parameters Ambient operating temperature Positive supply voltage (DVCC and AVCC) PECL differential load resistance1 Min 0 4.75 80 5.0 100 Typ Max 70 5.25 150 Units C V W
Note: 1. Differential load resistance of 100W equals connection of 50W to AC ground on each of DOUT, DOUT.
DC Electrical Characteristics
VCC = 5V 5%, GND = 0V unless otherwise indicated. Symbol VIH VIL IIH IIL CI VOHP VOLP VOP IO Receiver VIH VIL IIH IIL VCM VDIFF IIPH IIPL VOHC VOLC IOLC IOLC ICC PD TTL input voltage HIGH TTL input voltage LOW TTL input HIGH current TTL input LOW current Com. mode range (DIN, DIN) Diff. input voltage (DIN, DIN) PECL input HIGH current PECL input LOW current CMOS output voltage HIGH CMOS output voltage LOW Output current (except RBC) Output current (RBC) Supply Current (266 Mbaud) Power dissipation (266 Mbaud) VIH = VCC -0.88V VIL = VCC - 1.81V IOH= -4.1mA (-8.1mA for RBC) IOL= 4.1 mA (8.1 mA for RBC) Forcing VOH, VOL Forcing VOH, VOL VCC = 5.25V Based on ICC -100 3.5 0 4 8 135 690 150 VCC 0.5 VCC = max, Vin = 2.7V VCC = max, Vin = 0.4V 2.8 0.4 100 2.0 0 VCC +0.5 0.8 100 -100 4.5 V V mA mA V V mA mA V V mA mA mA mW Parameters TTL input voltage HIGH TTL input voltage LOW TTL input HIGH current TTL input LOW current Input capacitance PECL output voltage HIGH PECL ouput voltage LOW PECL output voltage amplitude PECL output current RDIFF = 100W, VCC = 5V RDIFF = 100W, VCC = 5V VOHP - VOLP, VCC = 5V 3.5 2.6 0.6 VCC = max, VIN = 2.7V VCC = max, VIN = 0.4V -1 4 3.8 3.0 0.8 8 Test Conditions Min 2.0 Typ Max VCC +0.5 0.8 100 100 10 4.2 3.4 1.0 Units V V mA mA pF V V V mA
Transmitter
Note: 1. Under both transmit and receive output switching conditions
10
PRODUCT SPECIFICATION
RCC700A
AC Electrical Characteristics1
VCC = 5V 5%, GND = 0V unless otherwise indicated. Symbol T tacq tids6 tidh
6
Parameters TBC Period Acquisition time DIN0..7, KIN, PIN valid to TBC setup TBC - to DIN0..7, KIN, PIN invalid hold Output data rate DOUT, DOUT rise and fall times DOUT, DOUT pk-pk random jitter DOUT, DOUT pk-pk deterministic jitter Input data rate variation Input data transition density to acquire and maintain lock Loop acquisition time for 1E-12 BER Loop capture range DIN, DIN input peak to peak jitter RBC pulsewidth HIGH
Test Conditions 266 Mbaud Note 2
Min
Typ 37.7
Max
Units ns
Transmitter 1 4 4 240 20% to 80% points Note 3 Note 4 220 125 1000 0.25 2500 1000 Note 5 0.4T 266 Mbaud 15 0.5T 0.07T 0.6T 25 bits ppm ns ns ns 330 500 ms ns ns Mbaud ps ps ps ppm
Fout tr, tf trj tdj Receiver fcc D tacq fc tj th tod ,
67
RBC - to DO0..7 KOUT, POUT, BSYNC delay (CSEL = 0, or CSEL = 1, POLSEL = 0) RBC period
T
266 Mbaud
37.7
ns
Notes: 1. Test conditions (unless otherwise indicated): PECL input rise and fall times, 2 ns, RLOAD = 100W across DOUT, DOUT; TTL input rise and fall times 15 ns. Receiver input data rate = 265.625 Mbaud and 1000 ppm; transition density 0.25. 2. Acquisition time is the time to establish lock once the device is powered up to the operating VCC range. 3. Input test pattern K28.7. Jitter measured at 50% amplitude, for a BER of 1E-12 with receiver running asynchronously. 4. Input test pattern K28.5. Jitter measured at 50% amplitude. 5. Guaranteed by design. 6. For CSEL = 0, the input pins are DI0..7, KIN and PIN, and the output pins are DO0..7, KOUT, and POUT. For CSEL = 1, the input pins are DI0..DI9, and the output pins are DO0..9. 7. For CSEL = 1 and POLSEL = 1, the timing specifications are with respect to the negative edge of RBC.
11
RCC700A
PRODUCT SPECIFICATION
Transmitter Timing
T
TBC tids DIN0-7, KIN, PIN 80% 20% tf DOUT, DOUT
65-700A-03
tidh
DOUT, DOUT tr
trj, tdj
Receiver Timing
DIN, DIN tfi DIN, DIN tri 80% 20%
tj
T th
RBC
tod
DOUT0-7, KOUT, POUT, BSYNC
65-700A-04
12
PRODUCT SPECIFICATION
RCC700A
Applications Discussion
+5V
64 63 62 61 60 59 58 57 56 55 54 53 52 52 50 49
82
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
82 2 3 4 130 130 510 7 8 1 100 9
5
6 SC
RCC700A 64 Pin PQFP
Fiber Optic XCVR
SC
Recommended Fiber Optic Transceivers: 1. HP BR-5302 2. Siemens V23806-A7-C2
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
65-700A-05
Interconnection of RCC700A to a Fiber Optic Transceiver
+5V
64 63 62 61 60 59 58 57 56 55 54 53 52 52 50 49
82
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
82
0.1 F
501/2 Coax Connector 501/2 Coax Connector
0.1 F
RCC700A 64 Pin PQFP
130
130
501/2 Coax Connector 100 501/2 Coax Connector
65-700A-06
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Interconnection of RCC700A to a Coax Cable
13
RCC700A
PRODUCT SPECIFICATION
Mechanical Dimensions
64-Lead MQFP Package
Inches Min. A A1 A2 B D/E D1/E1 e L N ND a ccc Max. Millimeters Min. Max. Notes: Notes 1. All dimensions and tolerances conform to ANSI Y14.5M-1982. 2. Dimensions "D1" and "E1" do not include mold protrusion. 3. Pin 1 identifier is optional. 4. Dimension N: number of terminals. 7 2 6 4 5 5. Dimension ND: Number of terminals per package edge. 6. "L" is the length of terminal for soldering to a substrate. 7. "B" includes lead finish thickness.
Symbol
-- .096 .010 -- .077 .083 .007 .011 .510 .530 .390 .398 .020 BSC .031 .040 64 16 0 7 -- .004
-- 2.45 .25 -- 1.95 2.10 .17 .27 12.95 13.45 9.90 10.10 .50 BSC .78 1.03 64 16 0 7 -- 0.10
D D1
e
E E1
PIN 1 IDENTIFIER
C a
L 0.063" Ref (1.60mm)
See Lead Detail A A2 B A1 Seating Plane Base Plane -CLEAD COPLANARITY ccc C
14
RCC700A
PRODUCT SPECIFICATION
Mechanical Dimensions (continued)
68-Lead PLCC Package
Inches Min. A A1 A2 B B1 D/E D1/E1 D3/E3 e J ND/NE N ccc Max. Millimeters Min. Max. Notes: Notes 1. All dimensions and tolerances conform to ANSI Y14.5M-1982 2. Corner and edge chamfer (J) = 45 3. Dimension D1 and E1 do not include mold protrusion. Allowable protrusion is .101" (.25mm)
Symbol
.165 .200 .090 .130 .020 -- .013 .021 .026 .032 .985 .995 .950 .958 .800 BSC .050 BSC .042 17 68 -- .004 .056
4.19 5.08 2.29 3.30 .51 -- .33 .53 .66 .81 25.02 25.27 24.13 24.33 20.32 BSC 1.27 BSC 1.07 17 68 -- 0.10 1.42
3
2
E E1 J
D D1
D3/E3
e A
B1
J
A1 A2 B -CLEAD COPLANARITY ccc C
15
RCC700A
PRODUCT SPECIFICATION
Ordering Information
Part Number RCC700AKA RCC700AQD Package 64 PQFP 68 PLCC
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS5000700A O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
RCXXXX
Offline Battery Charger
Features
* Very high precision * Chemistry independent
Applications
* * * * Offline applications Portable PCs PDAs Cellular telephones
Target Specification
Block Diagram
AC/DC Bridge Rectifier + RS
DCIN
IFB
PWM UC3845 IOUT
Gm
+ -
OPTO MOC8103
- +
- +
BAT VFB
VREF Digital Soft Start I_OUT
Battery Pack
VPROG
CompV
PGND
SGND
CompI CI CV
RI RV
IPROG
IFB
IOUT
8/6/97 Rev. 0.0.0
TARGET SPECIFICATION

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